WO2020038466A1 - 数据预取方法及装置 - Google Patents

数据预取方法及装置 Download PDF

Info

Publication number
WO2020038466A1
WO2020038466A1 PCT/CN2019/102285 CN2019102285W WO2020038466A1 WO 2020038466 A1 WO2020038466 A1 WO 2020038466A1 CN 2019102285 W CN2019102285 W CN 2019102285W WO 2020038466 A1 WO2020038466 A1 WO 2020038466A1
Authority
WO
WIPO (PCT)
Prior art keywords
data
cache
node
prefetch
written
Prior art date
Application number
PCT/CN2019/102285
Other languages
English (en)
French (fr)
Inventor
刘涛
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to CN201980003468.7A priority Critical patent/CN111406251B/zh
Priority to EP19852195.7A priority patent/EP3835959A4/en
Publication of WO2020038466A1 publication Critical patent/WO2020038466A1/zh
Priority to US17/182,401 priority patent/US11669453B2/en

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0813—Multiuser, multiprocessor or multiprocessing cache systems with a network or matrix configuration
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G06F12/0833—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means in combination with broadcast means (e.g. for invalidation or updating)
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/50—Control mechanisms for virtual memory, cache or TLB
    • G06F2212/502—Control mechanisms for virtual memory, cache or TLB using adaptive policy
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/50—Control mechanisms for virtual memory, cache or TLB
    • G06F2212/507—Control mechanisms for virtual memory, cache or TLB using speculative control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/6028—Prefetching based on hints or prefetch instructions

Definitions

  • the present application relates to the field of communications, and in particular, to a data prefetching method and device.
  • a multi-core (including multi-processor) system generally has multiple levels of caches, which are used to store program instructions, process data for program execution, or frequently referenced data in the next-level cache.
  • One or more data in the lower-level cache may have a copy in each cache of the upper level; when the data copy of a certain level changes, in order to ensure the consistency of the same data cached in multiple levels, you can use the cache Consistency mechanism is completed, that is, the cache consistency mechanism can maintain and guarantee the consistency of data in different locations and different caches by propagating data change messages in a multi-core system.
  • each processor core has a local cache and a hardware module that maintains local cache consistency.
  • the hardware module and the local cache are collectively referred to as a cache node, and the processor core is referred to as a compute node.
  • Cache coherence is mainly used in multi-core CPU systems, and data prefetching (that is, preprocessing of instructions) is for one of the CPUs or cores.
  • Data prefetching refers to using the locality of program execution to analyze consecutive adjacent instructions in a CPU core, predicting the instructions that are most likely to be executed at the next moment, so as to obtain the correlation from memory in advance according to the predicted result.
  • the data to be processed is further eliminated by the advancement of data acquisition to eliminate the delay of the data on the transmission path, so as to reduce the overall system processing delay.
  • this method has the following disadvantages: 1. Instruction prediction is limited to the same cache node, and by analyzing the N consecutive instructions of the current cache node, the data required for the next possible instruction to be executed can be predicted.
  • the master node After the execution of the instructions of node 1, the master node can start processing the read data request of cache node 2 (that is, the time elapsed from the receipt of the read data request from the master node to the sending of the first response message in Figure 1a is the blocking time), and The processing of a read data request by a node will cause additional delay, as shown by the gray rectangle in Figure 1a.
  • the embodiments of the present application provide a data prefetching method and device, which are beneficial to improve the accuracy of data prefetching time and the certainty of the prediction result, and reduce the delay of performing data prefetching.
  • an embodiment of the present application provides a data prefetch method.
  • the method is applied to a data prefetch system.
  • the data prefetch system includes a master node and multiple cache nodes.
  • the method includes:
  • the master node receives a write request sent by the cache node 1; wherein the write request carries data to be written, a data prefetch identifier, and a node number of the data prefetch; the master node prefetches data to the node according to the data prefetch identifier
  • the cache node 2 indicated by the ID number sends a first interception message.
  • the first interception message carries a prefetch query identifier, and the prefetch query identifier is used to instruct the cache node 2 to perform a data prefetch to determine whether it needs to write data.
  • the master node receives a first interception response message sent by the cache node 2, the first interception response message includes indication information for indicating whether the cache node 2 needs to perform a data prefetch operation on the data to be written; when the master node When it is determined that the cache node 2 needs to perform a data prefetch operation on the data to be written, the master node sends a response message carrying the data to be written to the cache node 2.
  • the cache node 1 and the cache node 2 are two different ones of the multiple cache nodes. node.
  • the cache node 1 sends a write request to the master node, specifically, the cache node 1 sends a write request to the master node after processing the received data.
  • the data to be written is data obtained after the cache node 1 processes the received data.
  • the first listening response message is sent by the cache node 2 after determining whether to perform a data prefetch operation on the data to be written according to the prefetch query identifier.
  • the master node predicts whether the cache node needs to prefetch data based on one or more historical instructions. Because the prediction method is used, the timing of data prefetching by the cache node is uncertain, and the result of whether the cache node is prefetching data is uncertain.
  • the master node after receiving the write request from cache node 1, the master node sends a listening message to cache node 2 to ask cache node 2 whether data prefetching is needed. If necessary, the master node sends a cache request to cache node 2. send data.
  • this application directly asks the cache node whether data prefetching is needed, and sends data to the cache node if necessary.
  • the method of the present application is beneficial to make the result of data prefetching and the time of prefetching more accurate, and is not limited to one cache node, and reduces the delay.
  • the indication information is a first prefetch result identifier included in the first listening response message, and different values of the first prefetch result identifier are used to indicate whether the cache node 2 needs to write data.
  • Perform a data prefetch operation for example, the value of the first prefetch result identifier is a first preset threshold to indicate that the cache node 2 needs to perform a data prefetch operation on the data to be written; the value of the second prefetch result identifier is Two preset thresholds to indicate that the cache node does not need to perform a data prefetch operation on the data to be written); or, the indication information is whether the first interception response message includes a second prefetch result identifier to indicate whether the cache node 2 needs to be treated Information for writing data to perform a data prefetch operation (for example, the first listening response message includes a second prefetch result identifier to indicate that the cache node 2 needs to perform a data prefetch operation on the data to be written; the first listening response message
  • the data prefetching system further includes multiple computing nodes.
  • the multiple computing nodes correspond to the multiple cache nodes one by one.
  • the computing node corresponding to the cache node 1 is configured to perform a first operation on the received data.
  • Operation the computing node corresponding to the cache node 2 is configured to perform a second operation on the received data, and the second operation is performed with a high probability after the received data is executed.
  • the received data will be performed with a high probability after the first operation is performed.
  • the second operation includes: the cache node 1 may determine that the received data will be with a high probability after the first operation is performed according to the type of the received data. The second operation is performed; or the cache node 1 determines that the received data will be executed with a high probability after the first operation is performed according to the processing flow of the received data; or the cache node 1 is based on the actual hardware resources To determine that the received data will be executed with a high probability after being executed with the first operation. For example, when users purchase cloud resources, they only purchase storage resources. Therefore, after receiving a message, only the message is stored.
  • the received data is the data sent by the computing node corresponding to the cache node 1.
  • the received data is the cache node 1 processing the received data. After getting the data.
  • the cache node 1 knows that the cache node 2 performs the second operation on the write data with a high probability, when the master node receives the write request from the cache node 1, it will directly send a listening request to the cache node 2 and ask the cache node 2 whether A data prefetch operation needs to be performed on the data to be written. If the master node determines that the cache node 2 needs a data prefetch operation on the data to be written, the master node sends the data to be written to the cache node 2. The cache node 2 can obtain data to be written at the first time, thereby improving efficiency.
  • the data prefetch system further includes a storage node
  • the write request further includes a data write address, where the data write address is a storage address in the storage node when the data to be written is written to the storage node
  • the method further includes: if the master node determines that the cache node 2 does not need to perform a data prefetch operation on the data to be written according to the instruction information, the master node caches the data to be written and the data write address into the cache of the master node, wherein, The data write address is the storage address of the data to be written in the storage node.
  • the purpose of the master node to save the data to be written is that when subsequent cache nodes need to read the data to be written, the master node does not need to send data read requests to other cache nodes to request the data to be written.
  • the cache node that writes the data sends the write data, which improves the data read rate.
  • the master node while the master node sends a completion message and a response message to the cache node 1 and the cache node 2, respectively, the master node sends a data update message to the storage node to update the data to be written to the storage node.
  • the data in the space corresponding to the data write address in the storage node can be updated in time, so that subsequent cache nodes read the data write address correspondingly.
  • the data in the space can be guaranteed to be up-to-date.
  • the method further includes: the master node sends a second interception message to the other cache nodes, and the second interception message is used to indicate Other cache nodes delete the original data.
  • the original data is the data corresponding to the data write address before the master node receives the data to be written.
  • the other cache nodes are multiple cache nodes except cache node 1 and cache node 2.
  • the method further includes: sending a completion message to the cache node 1, the completion message is used to inform the cache node 1 that data writing is completed.
  • the instructions of other cache nodes can be executed only after the master node processes the instructions of the current cache node, so the delay is large. In this application, since messages are sent to the cache node 1 and the cache node 2 at the same time, it can be seen that multiple instructions are processed in one instruction cycle, thereby reducing the delay.
  • the "simultaneity" referred to in this application does not mean that there is no 100% time difference, but a relatively small
  • the time difference is used to ensure that two messages are sent at the same time as far as possible, so that the message can be delivered to the opposite end as soon as possible to save time delay.
  • the time difference can be spaced by one or several instruction cycles.
  • the sending order of the two messages is also not limited. For example, the master node sends the response message first and the sending completion message is last; or the master node sends the completion message first and sends the response message after.
  • the data prefetch system is a processor
  • the cache node and the master node include a cache cache and a control circuit in the processor, which implements data prefetch in a processor scenario.
  • the master node and the cache node perform data interaction through a cache bus
  • the master node and the cache node perform data interaction through a cache consistency protocol (such as the MSI protocol and the MSIF protocol) before the protocol.
  • the computing node is a core in a processor, such as an ARM core or an x86 core.
  • the data prefetch system is a cluster computing system
  • the cluster computing system includes multiple processing servers and storage servers
  • the cache node includes a memory controller and a memory (such as a DDR controller and DDR) in the processing server.
  • Storage media the master node includes the processor and memory in the storage server, and implements data prefetching in a cluster computing system scenario.
  • the computing node is a processor of a processing server.
  • an embodiment of the present application provides another data prefetching method.
  • the method is applied to a data prefetching system.
  • the data prefetching system includes multiple cache nodes and a master node.
  • the method includes:
  • the cache node 2 receives the first interception message sent by the master node.
  • the first interception message carries a prefetch query identifier, and the prefetch query identifier is used to instruct the cache node 2 to perform a data prefetch operation to determine whether data to be written is required.
  • the data to be written is the data obtained by the cache node 1 after processing the received data, and the cache node 1 and the cache node 2 are two different nodes among multiple cache nodes; the cache node 2 identifies the prefetch query Determine whether it needs to perform a data prefetch operation on the data to be written; and send a first listening response message to the master node; the first listening response message includes a message indicating whether the cache node 2 needs to perform data prefetching on the data to be written Operation instruction information, if the cache node 2 determines that it needs to perform a data prefetch operation on the data to be written and after sending the first listening response message to the master node, it receives the response message sent by the master node, and the response message carries the data to be written .
  • the method of determining whether to perform a data prefetch operation through a handshake-like method is more beneficial to making the result of data prefetch and the timing of prefetching more accurate than whether to predict the data prefetch method through instructions, and is not limited to one. Cache nodes, while reducing latency.
  • the data prefetching system further includes multiple computing nodes.
  • the multiple computing nodes correspond to the multiple cache nodes one by one.
  • the computing node corresponding to the cache node 1 is configured to perform a first operation on the received data.
  • Operation the computing node corresponding to the cache node 2 is configured to perform a second operation on the received data, and the second operation is performed with a high probability after the received data is executed.
  • the received data will perform the second operation with a high probability after performing the first operation.
  • the cache node 1 may determine that the received data will perform the second operation with a high probability after performing the first operation according to the type of the received data. Operation; or the cache node 1 determines that the received data will perform the second operation with a high probability after performing the first operation according to the processing flow of the received data; or the cache node 1 determines the received data according to the actual hardware resources
  • the second operation is performed with a high probability. For example, when users purchase cloud resources, they only purchase storage resources. Therefore, after receiving a message, only the message is stored.
  • the received data is the data sent by the computing node corresponding to the cache node 1.
  • the received data is the cache node 1 processing the received data. After getting the data.
  • the cache node 1 knows that the cache node 2 performs the second operation on the write data with a high probability, when the master node receives the write request from the cache node 1, it will directly send a listening request to the cache node 2 and ask the cache node 2 whether A data prefetch operation needs to be performed on the data to be written. If the master node determines that the cache node 2 needs a data prefetch operation on the data to be written, the master node sends the data to be written to the cache node 2. The cache node 2 can obtain data to be written at the first time, thereby improving efficiency.
  • the cache node 2 determines whether it needs to perform a data prefetch operation according to the prefetch query identifier, including: if the cache node 2 supports a data prefetch function and needs data to be written; then Cache node 2 determines that it needs to perform a data prefetch operation on the data to be written. If cache node 2 supports the data prefetch function but does not need data to be written, or cache node 2 does not support the data prefetch function, cache node 2 determines its There is no need to perform a data prefetch operation on the data to be written.
  • the indication information is a first prefetch result identifier included in the first listening response message, and different values of the first prefetch result identifier are used to indicate whether the cache node 2 needs to write data.
  • Perform a data prefetch operation for example, the value of the first prefetch result identifier is a first preset threshold to indicate that the cache node 2 needs to perform a data prefetch operation on the data to be written; the value of the second prefetch result identifier is Two preset thresholds to indicate that the cache node does not need to perform a data prefetch operation on the data to be written); or, the indication information is whether the first interception response message includes a second prefetch result identifier to indicate whether the cache node 2 needs to be treated Information for writing data to perform a data prefetch operation (for example, the first listening response message includes a second prefetch result identifier to indicate that the cache node 2 needs to perform a data prefetch operation on the data to be written; the first listening response message
  • the data prefetch system is a processor
  • the cache node and the master node include a cache cache and a control circuit in the processor, which implements data prefetch in a processor scenario.
  • the master node and the cache node perform data interaction through a cache bus
  • the master node and the cache node perform data interaction through a cache consistency protocol (such as the MSI protocol and the MSIF protocol) before the protocol.
  • the computing node is a core in a processor, such as an ARM core or an x86 core.
  • the data prefetch system is a cluster computing system
  • the cluster computing system includes multiple processing servers and storage servers
  • the cache node includes a memory controller and a memory (such as a DDR controller and DDR) in the processing server.
  • Storage media the master node includes the processor and memory in the storage server, and implements data prefetching in a cluster computing system scenario.
  • the computing node is a processor of a processing server.
  • an embodiment of the present application further provides a master node, which is applied to a data prefetch system.
  • the data prefetch system further includes multiple cache nodes.
  • the master node includes:
  • a receiving unit configured to receive a write request sent by the cache node 1; the write request carries data to be written, a data prefetch identifier, and a node number of the data prefetch;
  • a sending unit configured to send a first interception message to the cache node 2 indicated by the data prefetch node number according to the data prefetch identifier, the first interception message carries a prefetch query identifier, and the prefetch query identifier is used to instruct the cache Node 2 performs a step of determining whether it needs to perform a data prefetch operation on the data to be written; wherein, cache node 1 and cache node 2 are two different nodes among a plurality of cache nodes;
  • the receiving unit is further configured to receive a first interception response message sent by the cache node 2; the first interception response message includes indication information used to indicate whether the cache node 2 needs to perform a data prefetch operation on the data to be written;
  • a determining unit configured to determine whether the cache node 2 needs to perform a data prefetch operation on the data to be written according to the instruction information
  • the sending unit is further configured to send a response message carrying the data to be written to the cache node 2 when the determining unit determines that the cache node 2 needs to perform a data prefetch operation on the data to be written according to the instruction information.
  • the cache node 1 sends a write request to the master node, specifically, the cache node 1 sends a write request to the master node after processing the received data.
  • the data to be written is data obtained after the cache node 1 processes the received data.
  • the first listening response message is sent by the cache node 2 after determining whether to perform a data prefetch operation on the data to be written according to the prefetch query identifier.
  • the indication information is a first prefetch result identifier included in the first listening response message, and different values of the first prefetch result identifier are used to indicate whether the cache node 2 needs to write data.
  • Perform a data prefetch operation for example, the value of the first prefetch result identifier is a first preset threshold to indicate that the cache node 2 needs to perform a data prefetch operation on the data to be written; the value of the second prefetch result identifier is Two preset thresholds to indicate that the cache node does not need to perform a data prefetch operation on the data to be written); or, the indication information is whether the first interception response message includes a second prefetch result identifier to indicate whether the cache node 2 needs to be treated Information for writing data to perform a data prefetch operation (for example, the first listening response message includes a second prefetch result identifier to indicate that the cache node 2 needs to perform a data prefetch operation on the data to be written; the first listening response message
  • the data prefetching system further includes multiple computing nodes.
  • the multiple computing nodes correspond to the multiple cache nodes one by one.
  • the computing node corresponding to the cache node 1 is configured to perform a first operation on the received data.
  • Operation the computing node corresponding to the cache node 2 is configured to perform a second operation on the received data, and the second operation is performed with a high probability after the received data is executed.
  • the received data will be performed with a high probability after the first operation is performed.
  • the second operation includes: the cache node 1 may determine that the received data will be with a high probability after the first operation is performed according to the type of the received data. The second operation is performed; or the cache node 1 determines that the received data will be executed with a high probability after the first operation is performed according to the processing flow of the received data; or the cache node 1 is based on the actual hardware resources To determine that the received data will be executed with a high probability after being executed with the first operation. For example, when users purchase cloud resources, they only purchase storage resources. Therefore, after receiving a message, only the message is stored.
  • the data prefetch system further includes a storage node
  • the write request further includes a data write address, where the data write address is a storage address in the storage node when the data to be written is written to the storage node
  • the master node also includes:
  • the cache unit is configured to cache the data to be written and the data write address to the cache of the master node when the determining unit determines that the cache node 2 does not need to perform a data prefetch operation on the data to be written according to the instruction information.
  • the sending unit is further configured to: while sending the first interception message to the cache node 2, send a second interception message to other cache nodes, and the second interception message is used to instruct other cache nodes
  • the node deletes the original data.
  • the original data is the data corresponding to the data write address before the master node receives the data to be written.
  • the other cache nodes are cache nodes other than cache node 1 and cache node 2 among multiple cache nodes. .
  • the sending unit is further configured to send a completion message to the cache node 1 while sending a response message to the cache node 2, and the completion message is used to inform the cache node 1 that data writing is completed.
  • the "simultaneity" referred to in this application does not mean that there is no 100% time difference, but a relatively small
  • the time difference is used to ensure that two messages are sent at the same time as far as possible, so that the message can be delivered to the peer as soon as possible to save time delay.
  • the time difference can be spaced by one or several instruction cycles.
  • the sending order of the two messages is also not limited. For example, the master node sends the response message first and the sending completion message is last; or the master node sends the completion message first and sends the response message after.
  • the data prefetching system further includes a storage node, and the sending unit is further configured to:
  • the data prefetch system is a processor
  • the cache node and the master node include a cache cache in the processor and a control circuit thereof.
  • the master node and the cache node perform data interaction through the cache bus.
  • the cache consistency protocol such as the MSI protocol and the MSIF protocol.
  • the computing node is a core in a processor, such as an ARM core or an x86 core.
  • the data prefetch system is a cluster computing system, and the cluster computing system includes multiple processing servers and storage servers, and the cache node includes a memory controller and a memory (such as a DDR controller and DDR) in the processing server.
  • the cache node includes a memory controller and a memory (such as a DDR controller and DDR) in the processing server.
  • Storage medium the master node includes a processor and a memory in a storage server.
  • the computing node is a processor of a processing server.
  • an embodiment of the present application further provides a cache node, which is applied to a data prefetch system.
  • the data prefetch system further includes a master node and other multiple cache nodes.
  • the cache node includes:
  • a receiving unit configured to receive a first interception message sent by a master node, where the first interception message carries a prefetch query identifier, and the prefetch query identifier is used to instruct a cache node to perform a step of determining whether a data prefetch operation is required;
  • the data to be written is data obtained by the cache node 1 after processing the received data, and the cache node 1 is one of the other multiple cache nodes;
  • a determining unit configured to determine whether it needs to perform a data prefetch operation on the data to be written according to the prefetch query identifier
  • a sending unit configured to send a first interception response message to the master node;
  • the first interception response message includes an instruction for indicating whether the cache node needs to perform a data prefetch operation on the data to be written;
  • the receiving unit is further configured to: if the determining unit determines that the cache node needs to perform a data prefetch operation on the data to be written, and after sending the first listening response message to the master node, receiving the response message sent by the master node, the response message carrying the pending message Into the data.
  • the data prefetching system further includes multiple computing nodes.
  • the multiple computing nodes correspond to the multiple cache nodes one by one.
  • the computing node corresponding to the cache node 1 is configured to perform a first operation on the received data. Operation, the computing node corresponding to the cache node is configured to perform a second operation on the received data, and the second operation is performed with a high probability after the received data is executed.
  • the received data will be performed with a high probability after the first operation is performed.
  • the second operation includes: the cache node 1 may determine that the received data will be performed with a high probability after the first operation is performed according to the type of the received data. The second operation is performed; or the cache node 1 determines that the received data will be executed with a high probability after the first operation is performed according to the processing flow of the received data; or the cache node 1 is based on the actual hardware resources To determine that the received data will be executed with a high probability after being executed with the first operation. For example, when users purchase cloud resources, they only purchase storage resources. Therefore, after receiving a message, only the message is stored.
  • the determining unit is specifically configured to: if the cache node supports a data prefetch function and needs data to be written; then determine that the cache node needs to perform a data prefetch operation on the data to be written; if the cache node supports data The prefetch function does not require data to be written, or the cache node does not support the data prefetch function, then it is determined that the cache node does not need to perform a data prefetch operation on the data to be written.
  • the indication information is a first pre-fetch result identifier included in the first interception response message, and different values of the first pre-fetch result identifier are used to indicate whether the cache node needs to perform data processing.
  • Data prefetch operation for example, the value of the first prefetch result identifier is a first preset threshold to indicate that the cache node needs to perform a data prefetch operation on the data to be written; the value of the second prefetch result identifier is a second prefetch Set a threshold to indicate that the cache node does not need to perform a data prefetch operation on the data to be written); or, the indication information is whether the first listening response message includes a second prefetch result identifier to indicate whether the cache node needs to treat the data to be written Information for performing a data prefetch operation (for example, the first listening response message includes a second prefetch result identifier to indicate that the cache node needs to perform a data prefetch operation on the data to be written; the first listening
  • the data prefetch system is a processor
  • the cache node and the master node include a cache cache in the processor and a control circuit thereof.
  • the master node and the cache node perform data interaction through the cache bus.
  • the cache consistency protocol such as the MSI protocol and the MSIF protocol.
  • the computing node is a core in a processor, such as an ARM core or an x86 core.
  • the data prefetch system is a cluster computing system, and the cluster computing system includes multiple processing servers and storage servers, and the cache node includes a memory controller and a memory (such as a DDR controller and DDR) in the processing server.
  • the cache node includes a memory controller and a memory (such as a DDR controller and DDR) in the processing server.
  • Storage medium the master node includes a processor and a memory in a storage server.
  • the computing node is a processor of a processing server.
  • the master node after the master node receives the write request sent by the cache node 1, it sends a listening message to the cache node 2.
  • the prefetch query identifier in the listening message is used to indicate The cache node 2 performs an operation of determining whether a data prefetch operation needs to be performed on the data to be written in the foregoing write request.
  • the cache node 2 After the cache node 2 determines to the master node whether it needs to perform a data prefetch operation on the data to be written, it sends a listening response message to the master node.
  • the listening response message carries an instruction indicating whether the cache node 2 needs to perform data prefetching. The indication information of the data prefetch operation.
  • the master node sends a response message to the cache node 2 which contains the data to be written.
  • the application scenario of data prefetching is not limited to the same cache node, and the time of data prefetching is determined and reaches the earliest; meanwhile, the accuracy of data prefetching is improved and the data interaction is further reduced. Delay, when multiple cache nodes access the same address, processing delay can be reduced to a single instruction cycle.
  • FIG. 1a is a schematic flowchart of a data prefetching process
  • FIG. 1b is a schematic diagram of a method for implementing cache coherence by combining listening and directories provided in this application;
  • FIG. 2a is a schematic diagram of a topology structure of an application data prefetching method according to an embodiment of the present application
  • 2b is a schematic diagram of a topology structure of another application data prefetching method provided by an embodiment of the present application
  • 2c is a schematic diagram of a topology structure of another application data prefetching method provided by an embodiment of the present application.
  • FIG. 2d is a schematic diagram of a topology structure of another application data prefetching method according to an embodiment of the present application.
  • FIG. 3 is a schematic framework diagram of a data prefetch system provided by an embodiment of the present application.
  • FIG. 4 is a schematic diagram of a logical functional structure of a cache node according to an embodiment of the present application.
  • FIG. 5 is a schematic diagram of a logical functional structure of a master node and a storage node according to an embodiment of the present application
  • FIG. 6 is a schematic flowchart of a data prefetching method according to an embodiment of the present application.
  • FIG. 7 is a schematic diagram of a comparison of technical effects
  • FIG. 8 is a schematic structural diagram of a cache node based on a processor scenario according to an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of a master node and a cache node based on a processor scenario according to an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of a master node and a cache node based on a cluster computing scenario according to an embodiment of the present application;
  • FIG. 11 is a schematic diagram of a multi-core system with a single-stage structure
  • FIG. 12 is a schematic flowchart of a data prefetching method according to an embodiment of the present application.
  • FIG. 13 is a schematic diagram of a multi-core system with a multi-level structure
  • FIG. 14 is a schematic framework diagram of a processor scenario according to an embodiment of the present application.
  • FIG. 15 is a schematic structural diagram of a master node according to an embodiment of the present application.
  • FIG. 16 is a schematic structural diagram of a cache node according to an embodiment of the present application.
  • FIG. 17 is a schematic structural diagram of a data prefetching device according to an embodiment of the present application.
  • Each processor core has a local cache and a hardware module that maintains local cache consistency.
  • This hardware module and local cache are collectively referred to as a cache node, and the processor core is referred to as a compute node.
  • each cache node (cache node 1, cache node 2 in Figure 1b) can broadcast data update requests, and other cache nodes monitor data update requests and determine whether they own the data update request. Corresponding data copy.
  • the interception mechanism has a short time delay, but at the same time, it will also cause bandwidth occupation and scalability problems caused by continuous broadcast data.
  • the directory-based consistency mechanism data shared between multiple cache nodes can be stored in the master node, and the master node can maintain the consistency among many cache nodes by means of directory records.
  • the master node can update or invalidate the entries of the data recorded in other directories on other nodes, so that the system-wide data copy is maintained and managed at a single point, thereby ensuring the consistency of data between cache nodes.
  • This directory mechanism can effectively improve the problems caused by broadcasting in the listening mechanism, but because any cache node updates data, it needs to go through the directory centrally and obtain update permissions one by one, resulting in a large access delay.
  • the listening / directory combination mechanism is generally used, such as modified, owned, exclusive, shared, invalid, MOESI or modified, exclusive, and shared. , Invalid, forwarding (modified, exclusive, shared, invalid, forwarding, MESIF), etc., combined with Figure 1b to explain the principle of the listening / directory combination mechanism.
  • Cache node 1 cache node 2 and the master node in FIG. 1b may belong to the same CPU.
  • the master node is a cache consistency maintenance node, and is directly connected to a double data rate (DDR) storage medium.
  • DDR double data rate
  • the cache node 1 When the cache node 1 initiates reading data corresponding to a certain DDR memory address, the cache node 1 first sends a data read request to the master node; after the master node receives the data read request sent by the cache node 1, the The master node broadcasts a listening message to other cache nodes ( Figure 1b is for convenience and illustration, it is only shown to send to cache node 2, in fact, it will also send listening messages to other cache nodes). This listening message is used to determine the other cache nodes. Whether the data corresponding to the address of the DDR memory is stored locally; each cache node sends a listening response message to the master node after receiving the interception message and performs corresponding processing.
  • the interception response message carries data corresponding to the address of the DDR memory; if the cache node 2 does not locally store data corresponding to the address of the DDR memory, the interception response The message does not carry data corresponding to the address of the DDR memory.
  • the master node After receiving the listening response messages from all other cache nodes, the master node sends response messages to the above cache node 1. After the master node obtains the data corresponding to the address of the DDR memory, the response message carries the data corresponding to the DDR memory address, and the master node updates the corresponding data to the DDR memory synchronously as needed. If the master node receives data from other cache nodes to read the same address during this process, it will execute this read request before responding to the read requests from other cache nodes.
  • DDR memories are collectively referred to as DDR1, DDR2, DDR3, DDR4 and other memories.
  • the data prefetching method provided in the embodiment of the present application is applicable to communication between any two or more computing circuits that have cache capabilities and support cache coherency.
  • the computing circuits include, but are not limited to, a CPU and a graphics processing unit. (GPU), digital signal processor (DSP), field programmable gate array (field programmable gate array, FPGA) and so on.
  • the embodiments of the present application can be carried in any cache consistency protocol for extension (such as MOESI protocol, MESIF protocol, etc.), and is not limited to the physical interface form and interconnection topology, that is, the method can directly cope with the existing cache consistency.
  • the protocol is enhanced, and the cache coherence mechanism containing the key elements of this application can also be redefined.
  • it can be carried in any form of physical interface such as peripheral component interconnect (external interconnect, express, PCIe) architecture, Ethernet, etc. Above, and there are no restrictions on interconnect topology.
  • a direct interconnection structure is shown, and two computing units with cache capabilities are directly interconnected; or as shown in Fig. 2b, a ring / mesh interconnection structure, three computing units with cache capabilities are connected end to end to form a ring network; Or, as shown in Fig. 2c, a fully interconnected structure is shown, and four computing units with cache capabilities are connected to each other; or as shown in Fig. 2d, any interconnect topology is used, and any computing unit with cache capabilities is connected arbitrarily.
  • FIG. 3 is a schematic diagram of a frame of a data prefetch system provided by an embodiment of the present application.
  • the data prefetch system includes multiple computing nodes, multiple cache nodes, a master node, and a storage node.
  • the computing node is connected to the cache node, and multiple computing nodes correspond to the multiple cache nodes one-to-one, multiple cache nodes are connected to the master node, and the master node is connected to the storage node.
  • the data interaction between multiple cache nodes is realized through the master node.
  • any cache node C in the cache node may receive data from other cache nodes, or receive data sent by a computing node corresponding to the cache node C, and then perform processing. After the processing is completed, a write request is sent to the master node.
  • This application is not limited to which and which node the cache node C receives data from.
  • the master node is used to maintain the cache consistency of multiple cache nodes. For example, when any cache node of multiple cache nodes obtains data from its corresponding computing node or from other cache nodes, after processing the data to generate new data, it will send the new data to the master node; for example, when any cache node A in the cache node needs to read data, the cache node A sends a data read request to the master node, and the master node obtains data required by the cache node A from its local or other cache nodes.
  • the master node is a management center for data of multiple cache nodes.
  • the master node can be regarded as the lower-level cache of multiple cache nodes.
  • each of the plurality of cache nodes includes a plurality of input interfaces 401, a plurality of output interfaces 406, a receiving circuit 402, a processing logic circuit 404, and a cache circuit. 403 ⁇ ⁇ ⁇ 405.
  • the input interface 401 is all coupled to the internal receiving circuit 402, and the output interface 406 is all coupled to the internal transmitting circuit 405, and is used to request read data from or write data to the master node, or respond to the read data request of the master node.
  • the input interface 401 and the output interface 406 are used to realize the connection between the cache nodes before and after the level, and then realize different topological structures, as shown in Figures 2a-2d.
  • the cache circuit 403 can be used to store volatile data, instructions, and data copies in frequently accessed storage nodes, etc.
  • the cache circuit 403 can be fully or partially embedded in the processing logic circuit 404 to more quickly access data.
  • the cache circuit 403 may be a volatile, non-volatile memory.
  • the processing logic circuit 404 is configured to process the received data and determine whether it is necessary to prefetch data generated by other cache nodes.
  • the processing logic circuit 404 is the core of the cache node.
  • multiple cache nodes can form multiple cache levels, such as level 2 cache, level 3 cache, and level 4 cache.
  • the master node includes a plurality of input interfaces 501, a plurality of output interfaces 508, a receiving circuit 502, a processing logic circuit 504, a buffer circuit 503, and a transmitting circuit 507.
  • the storage node includes a storage controller 505 and a storage circuit 506.
  • the input interface 501 is all coupled to the internal receiving circuit 502 and the output interface 508 is all coupled to the internal transmitting circuit 507 for requesting data from an external cache node or responding to a data request from the external cache node.
  • the cache circuit 503 can be used to store volatile data, instructions, data copies in the frequently accessed storage circuit 506, and the like.
  • the cache circuit 503 may be a volatile, non-volatile memory.
  • the processing logic circuit 504 is used to process transactions related to cache consistency and maintain data consistency between cache nodes, and is also the main body for performing data prefetching.
  • the storage controller 505 and the storage circuit 506 are used to store program instructions and process data during program execution.
  • the storage controller 505 is used to control and manage the data flow into and out of the storage circuit 506.
  • the storage controller The function of 505 can also be implemented by the processing logic circuit 504 to achieve faster access to the storage circuit 506. Therefore, the storage controller 505 in FIG. 5 is indicated by a dashed box.
  • the storage circuit 506 may use volatile memory and non-volatile memory, non-volatile memory may be used for non-volatile storage of data, and volatile memory may be generally used for storing process data during program execution.
  • the first thing to explain here is that multiple cache nodes need to share the cache. It is inevitable that multiple cache nodes may operate on the same cache address. When a cache node finishes operating the cache address, the cache address is modified. For the data in the corresponding storage space, other cache nodes may not get the expected data when fetching data from the cache address. In order to ensure consistency, a master node is required to maintain data consistency to ensure that the data obtained by other cache nodes are all expected data.
  • FIG. 6 is a schematic flowchart of a data prefetching method according to an embodiment of the present application. The method is applied to a data prefetch system, which includes a master node and multiple cache nodes.
  • the method includes:
  • the master node receives a write request sent by the cache node 1 after processing the received data.
  • the processing performed by the cache node on the received data includes decapsulating the received data to obtain data to be written, and then mapping the data to be written to a payload that satisfies the transmission protocol between the cache nodes. Then fill the protocol header and rate adaptation to get the write request.
  • the cache node 1 can receive data of other cache nodes; or the data prefetching system further includes multiple computing nodes, and the multiple computing nodes are connected to the multiple cache nodes one by one, for example, the cache node 1 can be connected to one computing node. Nodes correspond.
  • the cache node 1 can receive the data sent by the computing node corresponding to the cache node 1, and then process it. After the processing is completed, a write request is sent to the master node; this application does not limit the specific type of the cache node 1. And which node receives the data.
  • the write request carries data to be written, a data prefetch identifier, and a node number for data prefetch.
  • the node number of the data prefetch is used to indicate the cache node 2.
  • Cache node 1 and cache node 2 are two different nodes among the multiple cache nodes described above.
  • the master node After the master node obtains the data prefetch identifier and the data prefetch node number from the write request, it sends a first interception message to the cache node 2 indicated by the data prefetch node number according to the data prefetch identifier.
  • a listening message carries a prefetch query identifier.
  • the prefetch query identifier is used to instruct the cache node 2 to perform a step of determining whether it needs to perform a data prefetch operation on the data to be written.
  • the data prefetching system further includes multiple computing nodes, and the multiple computing nodes correspond to the multiple cache nodes one by one.
  • the computing node 1 corresponding to the cache node 1 is configured to execute the first step on the received data.
  • the computing node 2 corresponding to the cache node 2 is configured to perform a second operation on the received data, and the second operation is performed with a high probability after the received data is executed.
  • the specific value of the “high probability” is not limited in this application, and those skilled in the art can define it by combining the requirements of actual products.
  • those skilled in the art can understand that in the present application, after the data is performed the first operation, if the second operation is performed again, the prefetch operation of the cache node 2 will bring benefits; otherwise, if Will not be performed the second operation, then will increase the cost of processing (including longer processing time, increase processing power), therefore, those skilled in the art can determine a reasonable "probability" according to the actual application scenario, can It is understood that the greater the "probability" is, the greater the benefit will be. For example, the large probability can be greater than 80% or more than 90%.
  • the "received data will be executed with a high probability after the first operation is performed" may be determined by a prior business model.
  • product personnel can specify the processing capabilities of each hardware (such as a computing node).
  • designing computing node 1 has a 90% probability that it will receive voice data for processing. Then transfer to compute node 2;
  • the second operation will be performed, which is suitable for using the solution of the present application.
  • the “received data will be executed with a high probability after the first operation is performed” may not be a pre-defined model, but may be implemented during processing. Wherein, the received data will be performed with a high probability after the first operation is performed.
  • the second operation includes: the cache node 1 may determine that the received data will be with a high probability after the first operation is performed according to the type of the received data. The second operation is performed (such as performing operations on the received data, including integer operations and decimal operations.
  • the integer operation is performed on the data after receiving the data (that is, the first operation) ( That is, the second operation)); or the cache node 1 determines that the received data will be executed with a high probability after the first operation is performed according to the processing flow of the received data; or the cache node 1 according to the actual hardware Resources or user services (such as what functions users can use, what hardware they use, etc.) to determine that the received data will be executed with a high probability after the first operation is performed, such as when the user purchases a cloud resource and purchases a storage resource , So after receiving the message (that is, the first operation), the message is stored (that is, the second operation); or, the cache node 1 obtains the The proportion of data that has been written to the master node by the cache node 2 is regarded as the probability that the data to be written to the master node will be read again by the cache node 2. When the probability is greater than a certain threshold, Cache node 1 sets the prefetch identifier and specifies the
  • the cache node 1 Before the cache node 1 sends a write request to the master node 1, the cache node 1 will determine whether the received data will be received with a high probability according to the type of data received, known business processing flow, and / or hardware resources. The next user to use (such as the compute node corresponding to cache node 2). Therefore, the write request sent by the cache node 1 to the master node carries the node number indicating the data prefetch of the cache node 2.
  • the computing node corresponding to cache node 1 performs a first operation on the received data
  • the computing node corresponding to cache node 2 performs a second operation on the received data.
  • the cache node 1 Before the cache node 1 sends a write request to the master node, it is determined that the received data will be executed with a high probability after the first operation is performed according to the type of data received, known business processing flow, and / or hardware resources. Two operations, so the cache node 1 will carry the node number indicating the data prefetch of the cache node 2 in the write request sent to the master node.
  • the master node After receiving the write request sent by the cache node 1, the master node broadcasts a listening message to the cache node 2 and other cache nodes. Since the write request carries the node number for data prefetching, and the cache node indicated by the data prefetch node number is cache node 2, the interception message sent to cache node 2 carries the prefetch query identifier. The prefetch query identifier is used to instruct the cache node 2 to perform a step of determining whether a data prefetch operation is required for data to be written. For distinguishing, the listening message sent to other cache nodes is referred to as the second listening message, and the listening message sent to the cache node 2 is the first listening message.
  • the other cache nodes are cache nodes other than cache node 1 and cache node 2 among the plurality of cache nodes.
  • the second listening message sent by the master node to other cache nodes is used to instruct other cache nodes to delete the original data stored in its cache circuit.
  • the original data is the data corresponding to the data write address before the master node receives the data to be written.
  • the advantage of this processing is that, for example, before the cache node 1 sends a write request to the master node, some cache nodes have obtained the data corresponding to the data write address for use by the compute node corresponding to the cache node.
  • the master node receives the write request sent by the cache node 1, the data corresponding to the data write address changes at this time.
  • the master node sends a second listening message to these cache nodes to instruct the cache nodes to delete the data write. Data corresponding to the incoming address.
  • cache nodes After the master node finishes processing the data to be written in the write request sent by the cache node 1, other cache nodes may send a data read request to the master node to request the latest data corresponding to the data write address (i.e. data input). This can make these cache nodes obtain the same data for the same storage address.
  • the cache node 2 after the cache node 2 receives the first listening message, the cache node 2 first determines whether it has a data prefetch function, and if it is determined that it has a data prefetch function, the cache node 2 then continues to determine its Whether data needs to be written. If it is determined that data to be written is required, the cache node 2 determines that it needs to perform data prefetch operation.
  • the cache node 2 determines that it does not need to perform a data prefetch operation on the data to be written; if it determines that the cache node 2 does not have a data prefetch function, it determines that the cache node 2 does not need to perform a data prefetch operation on the data to be written.
  • the master node receives a first interception response message sent by the cache node 2.
  • the first interception response message includes indication information used to indicate whether the cache node 2 needs to perform a data prefetch operation on the data to be written.
  • the first listening response message has two functions, one is to respond to the first listening message, and the other is to indicate whether the cache node 2 needs to perform a data prefetch operation on the data to be written; if it indicates that the cache node 2 needs to Performing a data prefetch operation on the data to be written, the second function of the first listening response message can be regarded as the cache node 2 requesting the master node to obtain the data to be written.
  • the listening response message of the present application has more functions for indicating whether the cache node 2 performs a data prefetch operation on the data to be written.
  • the first interception response message is specifically used to respond to the first interception message and request to obtain the data to be written
  • the first interception response message is specifically used to respond to the first interception message.
  • the indication information is a first prefetch result identifier included in the first listening response message, and different values of the first prefetch result identifier are used to indicate whether the cache node 2 needs to write data.
  • Perform data prefetch operations For example, the value of the first prefetch result identifier is a first preset threshold (such as true or 1) to indicate that the cache node 2 needs to perform a data prefetch operation on the data to be written; the value of the first prefetch result identifier is Two preset thresholds (such as false or 0) to indicate that the cache node does not need to perform a data prefetch operation on the data to be written.
  • the indication information is information about whether the first interception response message includes a second prefetch result identifier to indicate whether the cache node 2 needs to perform a data prefetch operation on the data to be written.
  • the first listening response message includes a second prefetch result identifier to indicate that the cache node 2 needs to perform a data prefetch operation on the data to be written; the first listening response message does not include a second prefetch result identifier to indicate the cache Node 2 does not need to perform a data prefetch operation on the data to be written.
  • the value of the second prefetch result identifier may be the same or different each time.
  • prefetch identifier may be the same field in different messages, that is, in different messages.
  • the same field is used to indicate different meanings.
  • the master node saves the data to be written and the data write address to its cache.
  • the cache circuit of the master node stores a correspondence table between data and storage addresses, and the data storage address is the address in the storage node. Specifically, the master node traverses the correspondence table between the data and the storage address. If it is determined that the data write address of the data to be written is stored in the correspondence table between the data and the storage address, the data corresponding to the data write address is updated to Data to be written. If it is determined that the correspondence table between the data and the storage address does not hold the data write address of the data to be written, the data to be written and the data write address are stored in the correspondence table between the data and the storage address.
  • the master node sends a response message carrying the data to be written to the cache node 2.
  • the response message carries data to be written. If the first listening response message is used to indicate that the cache node 2 needs to perform a data prefetch operation on the data to be written, the first listening response message can be regarded as the cache node 2 requesting the master node to obtain the data to be written. At the same time, the response message here is also used to respond to the first interception message, that is, it has the function for responding to the first interception message mentioned in step 603 above.
  • the master node stores a correspondence table between data and storage addresses.
  • the correspondence table includes data and corresponding storage addresses.
  • the storage addresses are addresses in the storage nodes.
  • the data prefetch system further includes a storage node, and the foregoing write request further includes a data write address, where the data write address is a storage address of the data to be written in the storage node; the method further includes:
  • the master node saves the data to be written and the data write address to the cache of the master node. If the cache of the master node does not have enough space to store the data to be written and / or the data write address, the master node sends a data update message to the storage node to update the data to be written to the data write address in the storage node Corresponding storage space.
  • the data update message carries data to be written and a data write address.
  • the master node when other cache nodes need to repeatedly read the data to be written in a period of time, that is, the data to be written is hot data, in order to facilitate the acquisition of the data to be written, the master node temporarily changes the data to be written.
  • the written data is stored in a correspondence table between the data and the storage address, and the master node can directly obtain the data to be written from the correspondence table.
  • the data to be written is cold data at this time.
  • the master node writes the data to be written to A storage space corresponding to the data write address in the storage node.
  • the master node when multiple cache nodes send a request to the master node to read data stored in the storage space corresponding to the same address A in the storage node, the master node first traverses its stored data and its storage address The corresponding relationship table determines whether the data corresponding to address A is cached in the master node. If the data corresponding to address A is stored in the master node, the data is sent to multiple cache nodes at the same time; if the master node does not cache the data corresponding to address A, Data, the master node obtains the data corresponding to the address A from the storage node and sends the data to the multiple cache nodes at the same time.
  • the cache circuit of the master node stores a correspondence table between data and storage addresses.
  • the data storage address is the address in the storage node.
  • the master node maintains data consistency of multiple cache nodes through the correspondence table.
  • a completion message is sent to the cache node 1, and the completion message is used to respond to the write request.
  • the completion message is used to inform the cache node 1 that the master node has finished writing data to be written.
  • the "simultaneity" referred to in this application does not mean that there is no 100% time difference, but a relatively small
  • the time difference is used to ensure that two messages are sent at the same time as far as possible, so that the message can be delivered to the peer as soon as possible to save time delay.
  • the time difference can be spaced by one or several instruction cycles.
  • the sending order of the two messages is also not limited. For example, the master node sends the response message first and the sending completion message is last; or the master node sends the completion message first and sends the response message after.
  • FIG. 7A is a schematic diagram of data prefetching in the prior art. From this figure, it can be known that the disadvantages of the prior art are: the timing of data prefetching is uncertain, and whether data prefetching is required. There are uncertainties and delays in the results.
  • Figure b in FIG. 7 is a schematic diagram of data prefetching after using the data prefetching method of the present application. As can be seen from the figure, the data prefetching time is determined. As shown in FIG.
  • the master node receives After receiving the write request sent by the cache node 1, by sending a listening message to the cache node 2, the prefetch query identifier in the listening message is used to instruct the cache node 2 to perform determination to determine whether to write to the write request in the above write request. Enter data to perform data prefetch operations.
  • the cache node 2 determines to the master node whether it needs to perform a data prefetch operation on the data to be written, it sends a listening response message to the master node.
  • the listening response message carries an instruction indicating whether the cache node 2 needs to perform data prefetching. The indication information of the data prefetch operation.
  • the master node sends a response message to the cache node 2 which contains the data to be written.
  • the application scenario of data prefetching is not limited to the same cache node, and the time of data prefetching is determined and reaches the earliest; meanwhile, the accuracy of data prefetching is improved and the data interaction is further reduced. Delay, when multiple cache nodes access the same address, processing delay can be reduced to a single instruction cycle.
  • the data prefetching system is a processor, and multiple computing nodes are cores in the processor.
  • the cache node and the master node include a cache in the processor and its control circuit.
  • the storage node may be a DDR storage medium.
  • the master node and the cache node perform data interaction through the cache bus. Before the master node and the cache node perform the cache consistency protocol (such as Modified, Shared, Invalid (MSI) protocol or modify, share, invalid, Forwarding (Modified, Shared, Invalid, Forwarding, MSIF protocol) for data interaction.
  • the cache consistency protocol such as Modified, Shared, Invalid (MSI) protocol or modify, share, invalid, Forwarding (Modified, Shared, Invalid, Forwarding, MSIF protocol
  • this embodiment specifically introduces the foregoing solution based on a processor scenario.
  • cache nodes including caches and their control circuits
  • the cache circuit includes a plurality of input / output interfaces 801, a transceiver 802, a cache control circuit 804, and a high-speed storage medium 803.
  • the input / output interface 801 is directly coupled to the transceiver 802, and the transceiver 802 is connected to the cache control circuit 804.
  • the multiple input / output interfaces 801 are equivalent to the input interface 401 and the output interface 406 in FIG.
  • the cache control circuit 804 is equivalent to the processing logic circuit 404 in FIG. 4.
  • the cache control circuit 804 is connected to the high-speed storage medium 803.
  • the high-speed storage medium 803 is equivalent to the cache circuit 403 in FIG. 4.
  • the high-speed storage medium 803 may be static and random. Access memory (static random-access memory, SRAM).
  • each of the multiple cache nodes includes a high-speed storage medium, or the multiple cache nodes share a high-speed storage medium, and the high-speed storage medium is logically divided into multiple caches. Circuit so that each of the plurality of cache nodes has a cache circuit for use.
  • the master node (including the cache and its control circuit) can also be viewed as a cache circuit.
  • the cache circuit includes a plurality of input / output interfaces 901, a transceiver 902, a cache control circuit 904, and a high-speed storage medium 903.
  • the input / output interface 901 is directly coupled to the transceiver 902, and the transceiver 902 is connected to the cache control circuit 904.
  • the plurality of input / output interfaces 901 correspond to the input interface 501 and the output interface 506 in FIG. 5, and the transceiver 902 corresponds to the transmission circuit 507 and the reception circuit 502 in FIG. 5.
  • the cache control circuit 904 is equivalent to the processing logic circuit 504 in FIG. 5.
  • the cache control circuit 904 is connected to the high-speed storage medium 903.
  • the high-speed storage medium 903 is equivalent to the cache circuit 503 in FIG. 5.
  • the high-speed storage medium 903 may be static and random. Access memory (static random-access memory, SRAM).
  • the storage node includes a storage control circuit 906 and an off-chip storage medium 905.
  • the storage control circuit 906 is equivalent to the storage controller 505 in FIG. 5.
  • the off-chip storage medium 905 is equivalent to the storage circuit 506 in FIG.
  • the medium 905 refers to an external storage medium of the processor, and may be a synchronous dynamic random access memory (SDRAM), for example, specifically, DDR SDRAM (also referred to as "DDR" or "DDR memory” in this application). It should be noted that the memory access speed of SRAM is the fastest, and the memory access speed of SDRAM is slower than that of SRAM.
  • SDRAM synchronous dynamic random access memory
  • the storage control circuit 906 in the storage node may be embedded in the cache control circuit 904 in the master node.
  • the storage nodes all include an off-chip storage medium, or the multiple storage nodes share one off-chip storage medium, and the off-chip storage medium is logically divided into multiple virtual storage circuits (such as Different storage areas in off-chip storage media), so that each of the multiple storage nodes has a virtual storage circuit for use.
  • a processor runs one or more virtual machines (referred to as "virtual machine groups" in this application).
  • virtual machine groups referred to as "virtual machine groups” in this application.
  • these virtual machines are used to perform tasks, they are also called “Mission Machine”.
  • Each virtual machine can share physical memory.
  • the hardware may be a stand-alone system based on a processor, but the memory in this stand-alone system will be shared.
  • Each virtual machine group has its own private memory. At the same time, there is sharing between virtual machine groups. Of memory.
  • the processor can perform video decoding operations. After the processor receives the code stream from the cloud, virtual unit 1 running on the processor is used to receive packets, virtual unit 2 is used to decompress, and the virtual unit 3 is used for decoding, and virtual group 4 is used for back-end storage. Therefore, the business process for video decoding on this processor is: receiving messages, decompressing, decoding, and storing.
  • the cache node 1 can determine that the virtual machine group 1 needs to transmit the message to the virtual machine group 2 after receiving the message according to the business process (that is, the cache node 1 determines that the next user of the processed data is the cache node 2 or the cache node 1 processed data will be used by the cache node 2 with a high probability) for decompression.
  • the core corresponding to cache node 1 is used to run virtual machine group 1, and the core corresponding to cache node 2 is used to run virtual machine group 4.
  • virtual machine group 1 After virtual machine group 1 has received the network, it needs to store the received message, and knows the ability of virtual machine since 4 (for example, it has only storage capacity), it means that there is a high probability that the message will be sent to the virtual machine group for storage. 4.
  • this embodiment discloses another data prefetch system.
  • the data prefetch system is a cluster computing system
  • the cluster computing system includes multiple processing servers and storage servers
  • the data The cache nodes of the prefetch system include a memory controller and a memory in the processing server, such as a DDR storage medium and a DDR controller in the processing server.
  • the master node includes a processor and a memory in a storage server.
  • the storage node is a circuit composed of a storage controller and a storage medium in the storage server, such as a circuit composed of a solid state disk (SSD) controller and an SSD storage medium. Data exchange is performed between the master node and the computing node through an infinite bandwidth (IB) bus.
  • IB infinite bandwidth
  • the cluster computing system includes a processing server 1, a processing server 2, and a storage server.
  • the processing server 1 includes a computing node 1 and a cache node 1.
  • the computing node 1 includes M cores, M caches, a ring bus controller 1, a memory interface 1, an IB interface 1, and other interfaces 1.
  • M is an integer greater than or equal to 1.
  • Each of the M caches includes a cache medium and its control circuit, such as a cache medium and a cache control circuit.
  • the M cores are connected to the M caches in a one-to-one correspondence.
  • the M caches are also connected to the ring bus controller 1, and the memory interface 1, the IB interface 1, and other interfaces 1 are connected to the ring bus controller 1.
  • the cache node 1 includes a memory controller 1 and a memory 1.
  • the cache node 1 implements data interaction with the computing node 1 through its memory controller 1 and the memory interface 1 in the computing node 1.
  • the core in the processing server 1 may be an ARM core or an x86 core.
  • the processing server 2 and the processing server 1 have the same functional entities or logical circuits, and the connection relationship between these functional entities or logical circuits is the same as the connection relationship between the functional entities or logical circuits in the processing server 1. It will not be described here.
  • the processing server 2 includes a compute node 2 and a cache node 2.
  • the processing server 2 includes N cores and N caches, and the N cores are in one-to-one correspondence with the N caches.
  • the N caches are circuits composed of a cache medium and its controller. N is an integer greater than or equal to 1, and N is the same as or different from M.
  • the core in the processing server 2 may be an ARM core or an x86 core.
  • the storage server may include a main node and a storage node, where the main node includes a processor and a memory (memory 3 shown in FIG. 10); the storage node includes a storage controller and a storage medium.
  • the storage controller and the storage medium if the storage medium is a mechanical hard disk storage medium, the storage controller is a mechanical hard disk storage controller; if the storage medium is an SSD storage medium, the storage controller is an SSD controller; if the storage medium is Is flash, the storage controller is a flash controller.
  • the processor in the master node is connected to the IB interface 1 in the computing node 1 through the IB bus. Since the IB interface 1 is connected to the memory controller 1 of the cache node 1 through the ring bus controller 1 and the memory interface 1, the master node can be implemented Data interaction with cache node 1.
  • the master node is also connected to the IB interface 2 of the compute node 2 of the processing server 2 through the IB bus. Since both the IB interface 2 and the memory interface 2 are connected to the ring bus controller 2, and the memory interface 2 is connected to the memory controller in the cache node 2 2 are connected, so the data interaction between the master node and the cache node 2 can be realized.
  • the memory controller 1 of the cache node 1 receives the data transmitted by the computing node 1 through the memory interface 1, the memory controller 1 processes the data. After the data processing is completed, the memory controller 1 passes the memory interface 1 and the ring The bus controller 1 and the IB interface send a write request to the master node based on the IB bus.
  • the write request carries data to be written, a data prefetch identifier, a data prefetch node number, and a data write address.
  • the data to be written is After processing the data, the cache node indicated by the data prefetch node number is cache node 2, and the data write address is the storage address of the data to be written in the storage medium of the storage node.
  • the master node After receiving the write request from cache node 1, the master node obtains the data to be written, the data prefetch node number, the data prefetch identifier, and the data write address from the write request, and forwards the data indicated by the data prefetch node number.
  • the cache node 2 sends a first interception message, and the first interception message carries a prefetch query identifier.
  • the processor in the master node sends the first interception message to the ring bus controller 2 in the processing server 2 through the IB interface 2 of the processing server 2 through the IB bus.
  • the memory controller 2 of the cache node 2 sends a first listening message.
  • the processor in the master node After the processor in the master node receives the first interception response message sent by the memory controller 2 of the cache node 2, it determines whether the cache node 2 needs to perform a data prefetch operation based on the first interception response message. If it is determined that the cache node 2 needs to perform a data prefetch operation on the data to be written, the master node sends a response message to the cache node 2 and the response message carries the data to be written.
  • the path that the master node sends a response message to the cache node 2 is the same as the path that the master node sends the first listening message to the cache node 2.
  • the processor in the master node saves the data to be written and the data write address to the memory 3. If the memory 3 of the master node does not have enough storage space to store the data to be written and / or the data write address, the data to be written is saved or updated to the storage space corresponding to the data write address in the storage medium of the storage node.
  • the processor of the master node sends a completion message to the memory controller 1 of the cache node 1 through the IB interface 1, the ring bus controller 1, and the memory interface 1 based on the IB bus, and the completion message is used to inform the cache node 1 that the data writing is completed .
  • both the memory 1 in the cache node 1 and the memory 2 in the cache node 2 may be DDR storage media. If the memory 1 in the cache node 1 and the memory 2 in the cache node 2 are DDR storage media, the memory controller 1 and the memory controller 2 are DDR controllers, and the memory interface 1 and the memory interface 2 are DDR interfaces.
  • the master node is a data or database management node shared by all cache nodes (including cache node 1 in processing server 1 and cache node 2 in processing server 2).
  • the database includes the shared data.
  • the other interfaces 1 in the processing server 1 include a PCIE interface or an Ethernet interface
  • the other interfaces 2 of the processing server 2 include a PCIE interface or an Ethernet interface.
  • Cache node 1 of processing server 1 implements data interaction with the master node through the PCIE interface or Ethernet interface (that is, it may not use the IB interface)
  • cache node 2 of processing server 2 implements data with the master node through PCIE interface or Ethernet interface. Interaction (that is, without using the IB interface), thereby realizing the management of the shared data or database of the cache node 1 in the server 1 and the cache node 2 in the processing server 2.
  • the database includes the shared data.
  • the master node after the master node receives the write request from the cache node 1, it sends a first listening message to the cache node 2. When it is determined that the cache node 2 needs to When the data to be written performs a data prefetch operation, the master node sends the data to be written to the cache node 2.
  • the data prefetching scenario is not limited to one cache node, and the problem of uncertainty in the timing of initiating data prefetching and the prediction result is solved, and the delay is reduced.
  • FIG. 11 is a schematic diagram of a data prefetch system with a single stage structure.
  • the data prefetching system includes two levels of caches, which are an S-1 level cache and an S level cache.
  • the level S-1 cache is composed of M1 cache nodes
  • the level S cache is composed of the interconnection network and N1 master nodes.
  • M1, N1, and S are all integers greater than or equal to 1.
  • the master node can be logically and physically understood as the next level cache node of the cache node.
  • each master node When there are multiple master nodes, the memory to which each master node belongs is uniformly addressed, that is, multiple master nodes can be logically understood as Distributed master nodes, and each master node manages cache coherency between cache nodes.
  • the interconnection network is used to provide interconnection for communication between M1 cache nodes and N1 master nodes. It should be noted that the single level mentioned here means that there is only one level cache node in FIG. 11, that is, the S-1 level cache.
  • the lower-level cache may be the master node of the upper-level cache.
  • the master node is a level 3 cache
  • the master node is a level 4 cache
  • the cache node is a cache in a multi-core CPU chip
  • the master node is a management node of the cache bus in the multi-core CPU chip.
  • the multi-core mentioned here can be in one CPU, or across CPUs, or across CPUs and accelerators.
  • FIG. 12 is a schematic flowchart of a data reading method according to an embodiment of the present application. As shown in Figure 12, the method includes:
  • the cache node C1 sends a data read request to the target master node, and the data read request is used to request to read the target data.
  • the cache node C1 is one of the M1 cache nodes included in the S-1 cache, and the target master node is one of the N1 master nodes included in the S cache.
  • the data read request carries a data read address.
  • the data read address is an address in a storage node, and the latest data stored in the storage space corresponding to the address is the target data.
  • M1 cache nodes there is a connection relationship between M1 cache nodes and N1 master nodes, so when a cache node needs to read data, it can directly send a data read request to the master node that has a connection relationship with it.
  • the target master node determines whether target data is cached in its local cache circuit.
  • the target master node executes step S1203; when it is determined that the target data is not cached in its local cache circuit, the target master node executes step S1204.
  • a local memory circuit of the target master node stores a correspondence table between data and a storage address.
  • the target master node first traverses the correspondence table between the data and the storage address according to the data read address to determine whether the target data is stored in the correspondence table; if the target data is stored in the correspondence table, the target master node is determined
  • the local cache circuit caches the target data, and the target master node executes step S1203; if the target data is not stored in the correspondence table, it is determined that the target data is not cached in the local cache circuit of the target master node, and the target The master node executes step S1204.
  • the target master node sends a first completion message to the cache node C1.
  • the first completion message carries the target data, and the first completion message instructs the cache node C1 to set the target data to a shared state.
  • the purpose of instructing the above-mentioned cache node C1 to set the target data to a shared state is to enable a cache node located on the same CPU as the cache node C1 or a cache node of the same system to directly obtain the target data without sending to the master node Data read request.
  • the target master node sends a listening message to other cache nodes.
  • the interception message is used to instruct the other cache nodes to query whether the target data is cached locally.
  • the other cache nodes are cache nodes other than the cache node C1 among the M1 cache nodes included in the S-1 level cache.
  • Each of the other cache nodes sends a response message to the target master node.
  • the response message sent by the cache node C2 to the target master node carries the target data; if none of the other cache nodes cache the target data , Each of the other cache nodes sends a response message to the target master node to inform the target master node that it has not cached the target data.
  • S1206 The target master node determines whether the target data is cached in other cache nodes.
  • the target master node executes step S1207; when it is determined that the other cache nodes do not cache the target data, the target master node executes step S1208.
  • S1207 The target master node sends a completion message to the cache node C1.
  • the completion message carries the target data, and the completion message is used to request the cache node C1 to set the target data to a shared state, and correspond to the data read address in the correspondence table of the storage address.
  • the data is updated to the above target data.
  • the target data is stored in the storage space corresponding to the data read address in the storage node.
  • the second completion message carries data corresponding to the data read address of the target master node, and the target master node may obtain data corresponding to the data read address according to a correspondence table between the data and the storage address.
  • next-level cache ie, the S + 1 level cache
  • the target master node sends a data read request to the S + 1 level cache to request to obtain the target data.
  • the S level cache may be a cache node, and the S + 1 level cache may be a master node.
  • the master node in the S + 1 level cache When the master node in the S + 1 level cache receives the data read request, it first judges whether it stores the target data locally. If the target data is not stored locally, the interception message is broadcast to the cache node maintained by it to request the target data. If the master node in the S + 1 level cache receives the target data sent by the cache node it maintains, it sends a response message carrying the target data to the target master node.
  • the target master node receives the response message sent by the S + 1 level cache, and forwards the response message to the cache node C1.
  • the target master node if the response message carries the target data, the target master node simultaneously adds the target data and data read address to the data and storage address corresponding to the local storage circuit of the target master node according to requirements. Relationship table.
  • an embodiment of the present application provides a processor.
  • FIG. 14 it is a schematic diagram of a hardware framework of the processor.
  • the processor includes: multiple CPU cores, multiple cache nodes, and a master node, where M is an integer greater than 1.
  • the cache node and the master node include a cache and a control circuit in the processor.
  • the master node is used to maintain data consistency of multiple cache nodes, and the master node manages the storage nodes at the same time.
  • the cache node and the CPU core, the cache node and the cache node, the cache node and the master node perform data interaction through the cache bus.
  • the processor may further include a storage medium (such as DDR) having a lower speed than the cache.
  • these low-speed storage media may also be located outside the processor as an off-chip storage medium. For example, It is located on the storage node in FIG. 14, where the storage node and the processor are not on a chip.
  • the multiple cache nodes can be divided into a first-level cache, a second-level cache, and a third-level cache.
  • the first-level cache includes M cache nodes, which are in one-to-one correspondence with the M CPU cores.
  • the second-level cache includes N cache nodes.
  • the N cache nodes can be used to maintain the cache nodes in the first-level cache. Cache consistency, so the cache node in the second-level cache can be regarded as the master node of the cache node in the first-level cache, and N is an integer less than M.
  • one cache node in the second-level cache can maintain the cache consistency of two cache nodes in the first-level cache.
  • cache node 20 can be regarded as the master node of cache node 10 and cache node 11.
  • the node 21 can be regarded as the master node of the cache node 12 and the cache node 13.
  • one cache node in the second-level cache may also maintain the cache consistency of other numbers of cache nodes in the first-level cache. Other values may be 3, 4, 5, and so on, and this application is not limited thereto.
  • the third-level cache includes t cache nodes, which can be used to maintain the cache consistency of the cache nodes in the second-level cache. Therefore, the cache nodes in the third-level cache can be regarded as the master nodes of the second-level cache nodes. t is an integer less than n. As shown in FIG. 14, one cache node in the third-level cache can maintain the cache consistency of two cache nodes in the second-level cache. For example, the cache node 30 can be regarded as the master node of the cache node 20 and the cache node 21. Of course, one cache node in the second-level cache may also maintain the cache consistency of other numbers of cache nodes in the first-level cache. Other values may be 3, 4, 5, and so on, and this application is not limited thereto.
  • the master node in FIG. 14 is the management center of the cache bus of multiple cache nodes, and is used to maintain cache consistency of multiple cache nodes (including cache nodes in the first-level cache, the second-level cache, and the third-level cache).
  • the master node also includes a controller for controlling and managing the storage medium.
  • the master node can also be understood as the next-level cache of the third-level cache (ie, the fourth-level cache).
  • the master node in FIG. 14 can be understood as a fifth-level cache.
  • the input interface is a logical or physical interface
  • the output interface is a logical or physical interface.
  • the input interface / output interface of the cache node in the primary cache is used to connect the CPU core shown in FIG. 14 with the cache node in the secondary cache, and the input interface / output interface of the cache node in the secondary cache is used to connect as shown in FIG. 14
  • the cache node in the first-level cache and the cache node in the third-level cache are shown; the input interface / output interface of the cache node in the third-level cache is used to connect the cache node and the master node in the second-level cache shown in FIG. 14 .
  • the input interface of the cache node is all coupled to its internal receiving circuit, which is used to receive data or messages sent by the CPU core, other cache nodes and the master node; the output interface of the cache node is all coupled to its internal sending circuit, which is used to the CPU core.
  • Other cache nodes and master nodes send data or messages.
  • the cache node 10 corresponding to the CPU core0 sends a data read request to its master node (that is, the cache node 20), and the cache node 20 is a cache node. 10 and the master node of cache node 11.
  • the cache node 20 After receiving the data read request, the cache node 20 first determines whether data D is stored in its local cache circuit; if data D is stored in the cache circuit of the cache node 20, the cache node 20 directly sends data D to the cache node 10; If data D is not stored in the cache circuit of the cache node 20, the cache node 20 broadcasts a listening message to the cache nodes (ie, the cache node 10 and the cache node 11) maintained by the cache node 20, and the intercept message is used to request data D; cache The node 11 sends a listening response message to the cache node 20.
  • the cache nodes ie, the cache node 10 and the cache node 11
  • the interception response message sent by the cache node 11 to the cache node 20 carries the data D.
  • the cache node 20 After receiving the interception response message of the cache node 11, the cache node 20 sends the interception response message to the cache node. 10 sends a response message, the response message carrying data D.
  • the cache node 20 If the local cache circuit of the cache node 11 does not store the data D, after the cache node 20 receives the listening response message of the cache node 11, it forwards the data read request to the subordinate node of the cache node 20 (that is, the cache node 30).
  • the cache node 30 is a master node of the cache node 20 and the cache node 21.
  • the cache node 30 After receiving the data read request, the cache node 30 determines whether its local cache circuit stores data D; if data D is stored, the cache node 30 sends a response message carrying the data D to the cache node 20; if the local cache of the cache node 30 The circuit does not store the data D, and then broadcasts a listening message to the cache nodes (ie, the cache node 20 and the cache node 21) maintained by the circuit for requesting the data D.
  • the cache nodes ie, the cache node 20 and the cache node 21
  • the cache node 21 After receiving the listening message from the cache node 30, the cache node 21 determines whether its local cache circuit stores data D. If the cache node 21 determines that its local cache circuit stores data D, it sends a data carrying D to the cache node 30. Listening response message; if the cache node 21 determines that it does not store data D locally, it broadcasts a listening message to the cache nodes (ie, cache node 12 and cache node 13) that it maintains to request data D; cache node 21 Receive the listening response message sent by the cache node it maintains; if the listening response message carries data D, the cache node 21 sends a response message carrying data D to the cache node 30; if the listening response received by the cache node 21 The message does not carry data D, the cache node 21 determines that the data D is not stored in the cache circuit of the cache node it maintains, and sends a response message to the cache node 30 to notify that the data D is not obtained.
  • the cache node 21 determines that the
  • the cache node 30 If the cache node 30 obtains the data D, it sends a response message carrying the data D to the cache node 20; if the cache node 30 does not obtain the data D, it sends a response message to the cache node 20 notifying that the data D is not obtained; if the cache node 20 When the data D is acquired, a response message carrying the data D is sent to the cache node 10; if the cache node 20 does not acquire the data D, a response message for notifying that the data D is not obtained is sent to the cache node 10.
  • the cache node 10, the cache node 11, the cache node 12, and the cache node 13 can be regarded as the S-1 level cache in FIG. 11 or FIG. 13, and the cache node 20 and the cache node 21 can be regarded as FIG. 11 or FIG.
  • cache node 20 can be regarded as the master node of cache node 10 and cache node 11
  • cache node 21 can be regarded as the master node of cache node 12 and cache node 13.
  • the cache node 30 can be regarded as the S + 1 level cache in FIG. 10, and the cache node 30 is the master node of the cache node 20 and the cache node 21.
  • cluster computing system shown in FIG. 10 can read data according to this method, which will not be described here.
  • an embodiment of the present application provides a data prefetch system.
  • the data prefetch system includes a master node and multiple cache nodes.
  • the multiple cache nodes include cache node 1 and cache node 2.
  • the cache node 1, the cache node 2, and the master node For specific steps performed by the cache node 1, the cache node 2, and the master node, reference may be made to the related description of the embodiment shown in FIG. 6, and details are not described herein again.
  • an embodiment of the present application provides a master node.
  • FIG. 15 it is a schematic structural diagram of the master node.
  • the master node is applied to a data prefetch system, and the data prefetch system further includes multiple cache nodes.
  • the master node 1500 includes:
  • the receiving unit 1501 is configured to receive a write request sent by the cache node 1 after processing the received data.
  • the write request carries data to be written, a data prefetch identifier, and a node number for data prefetch.
  • the write data is data obtained after the cache node 1 processes the received data;
  • the sending unit 1502 is configured to send a first interception message to the cache node 2 indicated by the data prefetch node number according to the data prefetch identifier, where the first interception message carries a prefetch query identifier, and the prefetch query identifier is used to indicate
  • the cache node 2 performs a step of determining whether it needs to perform a data pre-fetch operation on the data to be written; wherein the cache node 1 and the cache node 2 are two different nodes among multiple cache nodes;
  • the receiving unit 1501 is further configured to receive a first interception response message sent by the cache node 2.
  • the first interception response message includes indication information for indicating whether the cache node 2 needs to perform a data prefetch operation on the data to be written, where ,
  • the first listening response message is sent by the cache node 2 after determining whether to perform a data prefetch operation on the data to be written according to the prefetch query identifier;
  • a determining unit 1503 configured to determine whether the cache node 2 needs to perform a data prefetch operation on the data to be written according to the instruction information
  • the sending unit 1502 is further configured to send a response message carrying the data to be written to the cache node 2 if the determining unit 1503 determines that the cache node 2 needs to perform a data prefetch operation on the data to be written according to the instruction information.
  • the indication information is a first prefetch result identifier included in the first listening response message, and different values of the first prefetch result identifier are used to indicate whether the cache node 2 needs to write data.
  • Perform a data prefetch operation for example, the value of the first prefetch result identifier is a first preset threshold to indicate that the cache node 2 needs to perform a data prefetch operation on the data to be written; the value of the first prefetch result identifier is Two preset thresholds to indicate that the cache node 2 does not need to perform a data prefetch operation on the data to be written); or, the indication information is whether the first interception response message includes a second prefetch result identifier to indicate whether the cache node 2 requires Information for performing a data prefetch operation on the data to be written (for example, the first listening response message includes a second prefetch result identifier to indicate that the cache node 2 needs to perform a data prefetch operation on the data to be written; in the first listening
  • the data prefetching system further includes multiple computing nodes, and the multiple computing nodes correspond to the multiple cache nodes one-to-one;
  • the computing node corresponding to cache node 1 is used to perform the first operation on the received data, and the computing node corresponding to cache node 2 is used to perform the second operation on the received data; the received data is executed after the first operation is performed The second operation will be performed with a high probability.
  • the data prefetch system further includes a storage node
  • the write request further includes a data write address, where the data write address is a storage address in the storage node when the data to be written is written to the storage node
  • the master node also includes:
  • the cache unit 1504 is configured to cache the data to be written and the data write address to the cache of the master node when the determining unit 1503 determines that the cache node 2 does not need to perform a data prefetch operation on the data to be written according to the instruction information.
  • the sending unit 1502 is further configured to: while sending the first listening message to the cache node 2, send a second listening message to other cache nodes, and the second listening message is used to indicate other
  • the cache node deletes the original data.
  • the original data is the data corresponding to the data write address before the master node receives the data to be written.
  • the other cache nodes are caches other than cache node 1 and cache node 2 among multiple cache nodes. node.
  • the sending unit 1502 is further configured to send a completion message to the cache node 1 while sending a response message to the cache node 2, and the completion message is used to notify the cache node 1 that data writing is completed.
  • the "simultaneity" referred to in this application does not mean that there is no 100% time difference, but a relatively small
  • the time difference is used to ensure that two messages are sent at the same time as far as possible, so that the message can be delivered to the peer as soon as possible to save time delay.
  • the time difference can be spaced by one or several instruction cycles.
  • the sending order of the two messages is also not limited. For example, the master node sends the response message first and the sending completion message is last; or the master node sends the completion message first and sends the response message after.
  • the data prefetch system further includes a storage node
  • the sending unit 1502 is further configured to:
  • the data prefetch system is a processor
  • the cache node and the master node include a cache cache in the processor and a control circuit thereof.
  • the master node and the cache node perform data interaction through the cache bus.
  • the cache consistency protocol such as the MSI protocol and the MSIF protocol.
  • the computing node is a core in a processor, such as an ARM core or an x86 core.
  • the data prefetch system is a cluster computing system, and the cluster computing system includes multiple processing servers and storage servers, and the cache node includes a memory controller and a memory (such as a DDR controller and DDR) in the processing server.
  • the cache node includes a memory controller and a memory (such as a DDR controller and DDR) in the processing server.
  • Storage medium the master node includes a processor and a memory in a storage server.
  • the computing node is a processor of a processing server.
  • the receiving unit 1501 is configured to execute the relevant content of step S601 in the embodiment shown in FIG. 6, and the sending unit 1502 is configured to execute the relevant content of steps S602 and S604 in the embodiment shown in FIG. 6.
  • the receiving unit 1501 and determine The unit 1503 is configured to execute related content of step S603 in the embodiment shown in FIG. 6.
  • the locations of the receiving unit 1501 and the sending unit 1502 correspond to the input / output interface 901 and the transceiver 902 in FIG. 9, and the locations of the determining unit 1503 correspond to the cache control circuit 904 and the cache unit 1504 in FIG. 9.
  • the location corresponds to the high-speed storage medium 903 in FIG. 9.
  • the functions of the receiving unit 1501 and the transmitting unit 1502 may be implemented by the input / output interface 901 and the transceiver 902 in FIG. 9, and the functions of the determining unit 1503 may be implemented by the cache control circuit 904 in FIG. 9, and the cache unit 1504
  • the functions can be implemented by the high-speed storage medium 903 in FIG. 9.
  • this application is not limited to this.
  • an embodiment of the present application provides a cache node.
  • FIG. 16 it is a schematic structural diagram of the cache node.
  • the cache node is applied to a data prefetch system.
  • the data prefetch system further includes a master node and other cache nodes.
  • the cache node 1600 includes:
  • the receiving unit 1601 is configured to receive a first interception message sent by the master node.
  • the first interception message carries a prefetch query identifier, and the prefetch query identifier is used to instruct the cache node to determine whether data prefetching is required for data to be written. Operation steps; wherein the data to be written is data obtained after the cache node 1 processes the received data, and the cache node 1 is one of other cache nodes;
  • a determining unit 1602 configured to determine whether the cache node needs to perform a data prefetch operation on the data to be written according to the prefetch query identifier
  • a sending unit 1603 is configured to send a first interception response message to the master node; the first interception response message includes an instruction for indicating whether the cache node needs to perform a data prefetch operation on the data to be written;
  • the receiving unit 1601 is further configured to receive a response message sent by the master node after the determining unit 1602 determines that the cache node 2 needs to perform a data prefetch operation on the data to be written and sends a first listening response message to the master node. Carry data to be written.
  • the data prefetching system further includes multiple computing nodes, and the multiple computing nodes correspond to the multiple cache nodes one-to-one;
  • the computing node corresponding to cache node 1 is used to perform the first operation on the received data, and the computing node corresponding to cache node is used to perform the second operation on the received data; the received data will be executed after the first operation is performed.
  • the second operation is performed with a high probability.
  • the determining unit 1602 is specifically configured to: if the cache node supports a data prefetch function and needs data to be written; then determine that the cache node needs to perform a data prefetch operation on the data to be written; if the cache node supports The data prefetch function does not require data to be written, or the cache node does not support the data prefetch function, then it is determined that the cache node does not need to perform a data prefetch operation on the data to be written.
  • the indication information is a first pre-fetch result identifier included in the first interception response message, and different values of the first pre-fetch result identifier are used to indicate whether the cache node needs to perform data processing.
  • Data prefetch operation for example, the value of the first prefetch result identifier is a first preset threshold to indicate that the cache node needs to perform a data prefetch operation on the data to be written; the value of the first prefetch result identifier is a second prefetch Set a threshold to indicate that the cache node does not need to perform a data prefetch operation on the data to be written); or, the indication information is whether the first listening response message includes a second prefetch result identifier to indicate whether the cache node needs to treat the data to be written Perform a data prefetch operation (for example, the second listening response message includes a second prefetch result identifier to indicate that the cache node needs to perform a data prefetch operation on the data to be written; the second listening response message
  • the data prefetch system is a processor
  • the cache node and the master node include a cache cache in the processor and a control circuit thereof.
  • the master node and the cache node perform data interaction through the cache bus.
  • the cache consistency protocol such as the MSI protocol and the MSIF protocol.
  • the computing node is a core in a processor, such as an ARM core or an x86 core.
  • the data prefetch system is a cluster computing system, and the cluster computing system includes multiple processing servers and storage servers, and the cache node includes a memory controller and a memory (such as a DDR controller and DDR) in the processing server.
  • the cache node includes a memory controller and a memory (such as a DDR controller and DDR) in the processing server.
  • Storage medium the master node includes a processor and a memory in a storage server.
  • the computing node is a processor of a processing server.
  • receiving unit 1601, the determining unit 1602, and the sending unit 1603 are configured to execute related content in the embodiment shown in FIG. 6.
  • the positions of the receiving unit 1601 and the transmitting unit 1602 correspond to the input / output interface 801 and the transceiver 802 in FIG. 8, and the positions of the determining unit 1602 correspond to the cache control circuit 804 in FIG. 8.
  • the functions of the receiving unit 1601 and the transmitting unit 1603 may be implemented by the input / output interface 801 and the transceiver 802 in FIG. 8, and the functions of the determining unit 1602 may be implemented by the cache control circuit 804 in FIG. 8.
  • this application is not limited to this.
  • FIG. 17 is a schematic structural diagram of a device according to an embodiment of the present application.
  • the device 1700 includes at least one processor 1701, at least one memory 1702, and at least one communication interface 1703.
  • the processor 1701, the memory 1702, and the communication interface 1703 are connected through the communication bus and complete communication with each other.
  • the processor 1701 may be a general-purpose central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits for controlling the execution of the above solutions.
  • CPU central processing unit
  • ASIC application-specific integrated circuit
  • the communication interface 1703 is used to communicate with other devices or communication networks, such as Ethernet, wireless access network (RAN), wireless local area network (WLAN), and the like.
  • Ethernet wireless access network
  • WLAN wireless local area network
  • the memory 1702 may be a read-only memory (ROM) or other type of static storage device that can store static information and instructions, a random access memory (RAM) or other type that can store information and instructions
  • the dynamic storage device can also be Electrically Erasable Programmable Read-Only Memory (EEPROM), Compact Disc (Read-Only Memory, CD-ROM) or other optical disk storage, optical disk storage (Including compact discs, laser discs, optical discs, digital versatile discs, Blu-ray discs, etc.), magnetic disk storage media or other magnetic storage devices, or can be used to carry or store desired program code in the form of instructions or data structures and can be used by a computer Any other media accessed, but not limited to this.
  • the memory may exist independently and be connected to the processor through a bus. The memory can also be integrated with the processor.
  • the memory 1702 is configured to store application program code for executing the foregoing solutions, and the processor 1701 controls execution.
  • the processor 1701 is configured to execute application program code stored in the memory 1702.
  • the code stored in the memory 1702 can execute the data prefetching method provided above.
  • the cache node 2 receives the first interception message sent by the master node.
  • the first interception message carries a prefetch query identifier.
  • the prefetch query identifier is used for Instruct the cache node 2 to perform the steps of determining whether data prefetching is required for the data to be written; the data to be written is data obtained after the cache node 1 processes the received data, and there are multiple cache nodes 1 and 2 Two different nodes in the cache node; the cache node 2 determines whether it needs to perform a data prefetch operation based on the prefetch query identifier; and sends a first interception response message to the master node; the first interception response
  • the message includes instructions for indicating whether the cache node 2 needs to perform a data prefetch operation on the data to be written.
  • the cache node 2 determines that it needs to perform a data prefetch operation on the data to be written, and sends a first listening response to the master node After the message, the response message sent by the master node is received, and the response message carries data to be written; or,
  • the code stored in the memory 1702 can perform another data prefetching method provided above, which specifically includes: the master node receives a write request sent by the cache node 1 after processing the received data; wherein the write request carries The data to be written, the data prefetch identifier, and the node number of the data prefetch; the master node sends a first interception message to the cache node 2 indicated by the data prefetch node number according to the data prefetch identifier, and the first interception message carries A prefetch query identifier is used to instruct the cache node 2 to perform a step of determining whether it needs to perform a data prefetch operation on the data to be written; the master node receives the first listening response message sent by the cache node 2, the The first listening response message includes indication information used to indicate whether the cache node 2 needs to perform a data prefetch operation on the data to be written, wherein the first listening response message is that the cache node 2 determines whether it needs to be written based on the prefetch
  • Caching node 2 to the node sends a response message carrying the data to be written, and the buffer cache node 1 and node 2 is a plurality of cache nodes in two different nodes.
  • the disclosed apparatus and method may be implemented in other ways.
  • the device embodiments described above are only schematic.
  • the division of the modules or units is only a logical function division.
  • multiple units or components may be divided.
  • the combination can either be integrated into another device, or some features can be ignored or not implemented.
  • the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, which may be electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may be one physical unit or multiple physical units, which may be located in one place, or may be distributed to multiple different places. . Some or all of the units may be selected according to actual needs to achieve the objective of the solution of this embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, or each of the units may exist separately physically, or two or more units may be integrated into one unit.
  • the above integrated unit may be implemented in the form of hardware or in the form of software functional unit.
  • the methods provided in the embodiments of the present application may be implemented in whole or in part by software, hardware, firmware, or any combination thereof.
  • software When implemented in software, it may be implemented in whole or in part in the form of a computer program product.
  • the computer program product includes one or more computer instructions.
  • the computer When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions according to the embodiments of the present application are generated.
  • the computer may be a general-purpose computer, a special-purpose computer, a computer network, a network device, a terminal, or another programmable device.
  • the computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be from a website site, computer, server, or data center Transmission by wire (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) to another website site, computer, server, or data center.
  • the computer-readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server, a data center, and the like that includes one or more available medium integration.
  • the available medium may be a magnetic medium (for example, a floppy disk, a hard disk, a magnetic tape), an optical medium (for example, a digital video disc (DVD)), or a semiconductor medium (for example, an SSD).

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

本申请公开了一种数据预取方法，包括：主节点接收缓存节点1在将接收到的数据处理完后发送的写入请求；主节点执行确定缓存节点2是否需要对待写入数据进行数据预取操作的动作；当确定缓存节点2需要对待写入数据进行数据预取操作时，所述主节点向缓存节点2发送待写入数据。采用本申请实施例有利于提高进行数据预取时刻的准确性和确定性，并降低了进行数据预取的时延。

Description

数据预取方法及装置
本申请要求于2019年03月29日提交中国专利局、申请号为201910259338.1、申请名称为“数据预取方法及装置”的中国专利申请以及于2018年8月24日提交专利局、申请号为201810974252.2的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及通信领域，尤其涉及一种数据预取方法及装置。
背景技术
多核(包括多处理器)系统内一般具有多个层级的缓存，用于存储诸如程序指令、程序执行的过程数据或者下一层级缓存中被频繁引用的数据等。下级缓存中的一个或多个数据在上一层级的各个缓存都有可能存在副本；当某一层的数据副本发生改变时，为了保证多个层级中缓存的同一数据的一致性，可通过缓存一致性机制来完成，即缓存一致性机制可通过在多核系统中传播数据变更消息来维护和保证不同位置、不同缓存中数据的一致性。
其中，每个处理器内核都有本地缓存以及维护本地缓存一致性的硬件模块，将该硬件模块和本地缓存统称为缓存节点，将处理器内核称为计算节点。
缓存一致性主要用于多核CPU系统中，而数据预取(也即指令的预处理)是针对其中的某个CPU或核而言的。数据预取是指利用程序执行的局部性，对某个CPU核中连续的相邻指令进行分析，预测在接下来的时刻极有可能执行的指令，从而根据预测的结果提前从内存中获取相关的待处理的数据，进而通过数据获取的提前量来消除数据在传输路径上的时延，以达到降低整体系统处理时延的目的。但是该方式具有以下缺点：1、指令预测仅局限于同一个缓存节点内，而且通过对当前缓存节点的连续N个指令的分析，才能预测接下来可能的待执行指令所需的数据，存在发起数据预取时刻的不确定性；2、预取结果存在不确定性：尽管通常需要预判多个指令有可能提升预测结果的准确性，但仍然无法达到100％；3、时延大：对于多缓存节点协同的时候，只有在某个缓存节点处理完指令并更新了数据后，其他缓存节点才可能通过指令预取得到正确数据。如图1a所示，缓存节点1产生新的数据后需要将该数据写入主节点，向主节点发送写数据请求；缓存节点2要想获得缓存节点1生产的数据，必须等到主节点将缓存节点1的指令执行完毕后，主节点才能开始处理缓存节点2的读数据请求(即图1a中从主节点收到读数据请求到发出第一响应消息所经过的时间为阻塞时间)，并且主节点处理读数据请求会产生额外延时，如图1a中的灰色长方形所表示的时间。
发明内容
本申请实施例提供一种数据预取方法及装置，有利于提高进行数据预取时刻的准确性和预测结果的确定性，并降低了进行数据预取的时延。
第一方面，本申请实施例提供一种数据预取方法，该方法应用于数据预取系统，该数据预取系统包括主节点和多个缓存节点，该方法包括：
主节点接收缓存节点1发送的写入请求；其中，该写入请求中携带待写入数据、数据预取标识、数据预取的节点号；主节点根据数据预取标识向数据预取的节点号指示的缓存节点2发送第一侦听消息，该第一侦听消息携带有预取询问标识，该预取询问标识用于指示缓存节点2执行确定其是否需要对待写入数据进行数据预取操作的步骤；主节点接收缓存节点2发送的第一侦听响应消息，该第一侦听响应消息包括用于指示缓存节点2是否需要对待写入数据进行数据预取操作的指示信息；当主节点确定缓存节点2需要对待写入数据进行数据预取操作时，主节点向缓存节点2发送携带待写入数据的响应消息，缓存节点1和缓存节点2为多个缓存节点中的两个不同的节点。
在此需要说明的是，缓存节点1向主节点发送写入请求，具体是缓存节点1在将接收到的数据处理完后向主节点发送写入请求。其中，待写入数据为缓存节点1将接收到的数据处理完后得到的数据。
其中，第一侦听响应消息为缓存节点2根据预取询问标识确定是否需要对待写入数据进行数据预取操作后发送的。
在现有技术中，主节点根据历史一个或多个指令预测缓存节点是否需要对数据进行预取。由于是采用预测的方式，因此导致缓存节点进行数据预取的时刻不确定和缓存节点是否进行数据预取的结果不确定。而在本申请中，主节点接收到缓存节点1的写入请求后，就向缓存节点2发送侦听消息，以询问缓存节点2是否需要进行数据预取，如果需要则主节点向缓存节点2发送数据。相对于现有技术中通过指令预测缓存节点是否需要进行数据预取的方式，本申请是通过直接询问缓存节点是否需要对数据进行预取，如果需要则向缓存节点发送数据。本申请的方式有利于使得是否进行数据预取的结果及预取时刻更加精确，并且不局限于一个缓存节点内，同时降低了时延。
在一种可能的实施例中，指示信息为第一侦听响应消息中包括的第一预取结果标识，该第一预取结果标识的不同值用于指示缓存节点2是否需要对待写入数据进行数据预取操作(例如第一预取结果标识的取值为第一预设阈值，以指示缓存节点2需要对待写入数据进行数据预取操作；第二预取结果标识的取值为第二预设阈值，以指示缓存节点不需要对待写入数据进行数据预取操作)；或者，指示信息为第一侦听响应消息中是否包括第二预取结果标识来表示缓存节点2是否需要对待写入数据进行数据预取操作的信息(例如第一侦听响应消息包括第二预取结果标识，以指示缓存节点2需要对待写入数据进行数据预取操作；第一侦听响应消息中未包括第二预取结果标识，以指示缓存节点2不需要对待写入数据进行数据预取操作)。通过指示信息告知主节点缓存节点2是否需要对待写入数据进行数据预取操作这种方式，相对于通过指令预测是否需要进行数据预取这种方式会更加精确，不会产生误差。
在一种可能的实施例中，数据预取系统还包括多个计算节点，多个计算节点与多个缓存节点一一对应，缓存节点1对应的计算节点用于对接收到的数据执行第一操作，缓存节点2对应的计算节点用于对接收到的数据执行第二操作，该接收到的数据在被执行完第一操作后会大概率地被执行第二操作。
其中，接收到的数据在被执行第一操作后会大概率地被执行第二操作包括：缓存节点1可根据接收到数据的类型确定接收到的数据在被执行第一操作后会大概率地被执行第二 操作；或者缓存节点1根据对接收到的数据的处理流程确定接收到的数据在被执行第一操作后会大概率地被执行第二操作；或者缓存节点1根据实际的硬件资源来确定接收到的数据在被执行第一操作后会大概率地被执行第二操作。比如用户购买云资源时只购买了存储资源，因此在接收到报文后只对报文进行存储。
需要说明的是，对于缓存节点1来说，接收到的数据为缓存节点1对应的计算节点发送的数据；对于缓存节点2来说，接收到的数据为缓存节点1将接收到的数据处理完后得到的数据。
由于缓存节点1知道缓存节点2大概率地对待写入数据进行第二操作，因此当主节点接收到缓存节点1的写入请求后，会直接向缓存节点2发送侦听请求，询问缓存节点2是否需要对待写入数据进行数据预取操作，若主节点确定缓存节点2需要对待写入数据进行数据预取操作，则主节点向缓存节点2发送待写入数据。缓存节点2能在第一时间得到待写入数据，进而提高了效率。
在一种可能的实施例中，数据预取系统还包括存储节点，写入请求还包括数据写入地址，数据写入地址为待写入数据写入存储节点时在存储节点中的存储地址；该方法还包括：若主节点根据指示信息确定缓存节点2不需要对待写入数据进行数据预取操作，则主节点将待写入数据和数据写入地址缓存至主节点的缓存中，其中，数据写入地址为待写入数据在存储节点中的存储地址。主节点保存待写入数据的目的是在后续缓存节点需要读取待写入数据时，主节点不需要向其他缓存节点发送数据读取请求以请求获取待写入数据，可以直接向需要该待写入数据的缓存节点发送该写入数据，提高了数据读取速率。
在一个可能的实施例中，在主节点向缓存节点1和缓存节点2分别发送完成消息和响应消息的同时，主节点向存储节点发送数据更新消息，以将待写入数据更新至存储节点中数据写入地址对应的存储空间中，在可以节省主节点的存储空间的同时，能够及时更新存储节点中数据写入地址对应的空间中的数据，使得后续缓存节点在读取数据写入地址对应的空间中的数据时，可以保证获得数据都是最新的。
在一种可能的实施例中，主节点向缓存节点2发送第一侦听消息的同时，该方法还包括：主节点向其他缓存节点发送第二侦听消息，第二侦听消息用于指示其他缓存节点删除原数据，原数据为在主节点接收到待写入数据之前数据写入地址对应的数据；其中，其他缓存节点为多个缓存节点中除了缓存节点1和缓存节点2之外的缓存节点。主节点向其他缓存节点发送用于指示其他缓存节点删除原数据的第二侦听消息的目的是为了其他缓存节点在进行后续的操作时使用的数据是最新的，进而保证后续操作的正确性。
在一种可能的实施例中，在主节点向缓存节点2发送响应消息的同时，该方法还包括：向缓存节点1发送完成消息，完成消息用于告知缓存节点1数据写入完成。现有技术中只有当主节点处理完当前缓存节点的指令后，才能执行其他缓存节点的指令，因此时延大。而在本申请中，由于同时向缓存节点1和缓存节点2发送消息，可以看出在一个指令周期内处理多个指令，因此降低了时延。
需要说明的是，本领域技术人员可以理解，由于硬件所限，通常不可能实现100％的同时，因此，本申请所说的“同时”并非指100％没有时间差，而是一个相对很小的时间差，用于保证两个消息发送尽量同时，从而可以尽快将消息传递给对端，以节省时延，具体的， 该时间差可以间隔一个或若干个指令周期。此外，两个消息的发送顺序也不限定，比如主节点发送响应消息在前，发送完成消息在后；或者主节点发送完成消息在前，发送响应消息在后。
在一种可能的实施例中，数据预取系统为处理器，缓存节点以及主节点包括处理器中的高速缓存cache及其控制电路，实现了处理器场景下的数据预取。其中，主节点和缓存节点之间通过cache总线进行数据交互，在协议上主节点和缓存节点之前通过cache一致性协议(比如MSI协议、MSIF协议)进行数据交互。
进一步地，计算节点为处理器中的核(core)，比如ARM核或x86核。
在一种可能的实施例中，数据预取系统为集群计算系统，且集群计算系统包括多台处理服务器和存储服务器，缓存节点包括处理服务器中的内存控制器以及内存(比如DDR控制器及DDR存储介质)，主节点包括存储服务器中的处理器以及内存，实现了集群计算系统场景下的数据预取。
进一步地，计算节点为处理服务器的处理器。
第二方面，本申请实施例提供另一种数据预取方法，该方法应用于数据预取系统，该数据预取系统包括多个缓存节点和主节点，该方法包括：
缓存节点2接收主节点发送的第一侦听消息，第一侦听消息携带有预取询问标识，预取询问标识用于指示缓存节点2执行确定是否需要对待写入数据进行数据预取操作的步骤；待写入数据为缓存节点1将接收到的数据处理完后得到的数据，缓存节点1和缓存节点2为多个缓存节点中的两个不同的节点；缓存节点2根据预取询问标识确定其是否需要对待写入数据进行数据预取操作；并向主节点发送第一侦听响应消息；该第一侦听响应消息包括用于指示缓存节点2是否需要对待写入数据进行数据预取操作的指示信息，若缓存节点2确定其需要对待写入数据进行数据预取操作且在向主节点发送第一侦听响应消息后，接收主节点发送的响应消息，响应消息携带有待写入数据。通过类似握手的方式确定是否进行数据预取操作的方式，相对于通过指令预测是否需要进行数据预取方式，有利于使得是否进行数据预取的结果及预取时刻更加精确，并且不局限于一个缓存节点内，同时降低了时延。
在一种可能的实施例中，数据预取系统还包括多个计算节点，多个计算节点与多个缓存节点一一对应，缓存节点1对应的计算节点用于对接收到的数据执行第一操作，缓存节点2对应的计算节点用于对接收到的数据执行第二操作，该接收到的数据在被执行完第一操作后会大概率地被执行第二操作。
其中，接收到的数据在执行第一操作后会大概率地执行第二操作包括：缓存节点1可根据接收到数据的类型确定接收到的数据在执行第一操作后会大概率地执行第二操作；或者缓存节点1根据对接收到的数据的处理流程确定接收到的数据在执行第一操作后会大概率地执行第二操作；或者缓存节点1根据实际的硬件资源来确定接收到的数据在执行第一操作后会大概率地执行第二操作。比如用户购买云资源时只购买了存储资源，因此在接收到报文后只对报文进行存储。
需要说明的是，对于缓存节点1来说，接收到的数据为缓存节点1对应的计算节点发送的数据；对于缓存节点2来说，接收到的数据为缓存节点1将接收到的数据处理完后得 到的数据。
由于缓存节点1知道缓存节点2大概率地对待写入数据进行第二操作，因此当主节点接收到缓存节点1的写入请求后，会直接向缓存节点2发送侦听请求，询问缓存节点2是否需要对待写入数据进行数据预取操作，若主节点确定缓存节点2需要对待写入数据进行数据预取操作，则主节点向缓存节点2发送待写入数据。缓存节点2能在第一时间得到待写入数据，进而提高了效率。
在一种可能的实施例中，缓存节点2根据预取询问标识确定其是否需要对待写入数据进行数据预取操作，包括：若缓存节点2支持数据预取功能且需要待写入数据；则缓存节点2确定其需要对待写入数据进行数据预取操作；若缓存节点2支持数据预取功能但不需要待写入数据，或者缓存节点2不支持数据预取功能，则缓存节点2确定其不需要对待写入数据进行数据预取操作。
在一种可能的实施例中，指示信息为第一侦听响应消息中包括的第一预取结果标识，该第一预取结果标识的不同值用于指示缓存节点2是否需要对待写入数据进行数据预取操作(例如第一预取结果标识的取值为第一预设阈值，以指示缓存节点2需要对待写入数据进行数据预取操作；第二预取结果标识的取值为第二预设阈值，以指示缓存节点不需要对待写入数据进行数据预取操作)；或者，指示信息为第一侦听响应消息中是否包括第二预取结果标识来表示缓存节点2是否需要对待写入数据进行数据预取操作的信息(例如第一侦听响应消息包括第二预取结果标识，以指示缓存节点2需要对待写入数据进行数据预取操作；第一侦听响应消息中未包括第二预取结果标识，以指示缓存节点2不需要对待写入数据进行数据预取操作)。
在一种可能的实施例中，数据预取系统为处理器，缓存节点以及主节点包括处理器中的高速缓存cache及其控制电路，实现了处理器场景下的数据预取。其中，主节点和缓存节点之间通过cache总线进行数据交互，在协议上主节点和缓存节点之前通过cache一致性协议(比如MSI协议、MSIF协议)进行数据交互。
进一步地，计算节点为处理器中的核(core)，比如ARM核或x86核。
在一种可能的实施例中，数据预取系统为集群计算系统，且集群计算系统包括多台处理服务器和存储服务器，缓存节点包括处理服务器中的内存控制器以及内存(比如DDR控制器及DDR存储介质)，主节点包括存储服务器中的处理器以及内存，实现了集群计算系统场景下的数据预取。
进一步地，计算节点为处理服务器的处理器。
第三方面，本申请实施例还提供一种主节点，该主节点应用于数据预取系统，该数据预取系统还包括多个缓存节点；主节点包括：
接收单元，用于接收缓存节点1发送的写入请求；其中，写入请求中携带待写入数据、数据预取标识、数据预取的节点号；
发送单元，用于根据数据预取标识向数据预取的节点号指示的缓存节点2发送第一侦听消息，该第一侦听消息携带有预取询问标识，预取询问标识用于指示缓存节点2执行确定其是否需要对待写入数据进行数据预取操作的步骤；其中，缓存节点1和缓存节点2为多个缓存节点中的两个不同的节点；
接收单元，还用于接收缓存节点2发送的第一侦听响应消息；该第一侦听响应消息包括用于指示缓存节点2是否需要对待写入数据进行数据预取操作的指示信息；
确定单元，用于根据指示信息确定缓存节点2是否需要对待写入数据是否进行数据预取操作；
发送单元，还用于当确定单元根据指示信息确定缓存节点2需要对待写入数据进行数据预取操作时，向缓存节点2发送携带待写入数据的响应消息。
在此需要说明的是，缓存节点1向主节点发送写入请求，具体是缓存节点1在将接收到的数据处理完后向主节点发送写入请求。待写入数据为缓存节点1将接收到的数据处理完后得到的数据。
其中，第一侦听响应消息为缓存节点2根据预取询问标识确定是否需要对待写入数据进行数据预取操作后发送的。
在一种可能的实施例中，指示信息为第一侦听响应消息中包括的第一预取结果标识，该第一预取结果标识的不同值用于指示缓存节点2是否需要对待写入数据进行数据预取操作(例如第一预取结果标识的取值为第一预设阈值，以指示缓存节点2需要对待写入数据进行数据预取操作；第二预取结果标识的取值为第二预设阈值，以指示缓存节点不需要对待写入数据进行数据预取操作)；或者，指示信息为第一侦听响应消息中是否包括第二预取结果标识来表示缓存节点2是否需要对待写入数据进行数据预取操作的信息(例如第一侦听响应消息包括第二预取结果标识，以指示缓存节点2需要对待写入数据进行数据预取操作；第一侦听响应消息中未包括第二预取结果标识，以指示缓存节点2不需要对待写入数据进行数据预取操作)。
在一种可能的实施例中，数据预取系统还包括多个计算节点，多个计算节点与多个缓存节点一一对应，缓存节点1对应的计算节点用于对接收到的数据执行第一操作，缓存节点2对应的计算节点用于对接收到的数据执行第二操作，该接收到的数据在被执行完第一操作后会大概率地被执行第二操作。
其中，接收到的数据在被执行第一操作后会大概率地被执行第二操作包括：缓存节点1可根据接收到数据的类型确定接收到的数据在被执行第一操作后会大概率地被执行第二操作；或者缓存节点1根据对接收到的数据的处理流程确定接收到的数据在被执行第一操作后会大概率地被执行第二操作；或者缓存节点1根据实际的硬件资源来确定接收到的数据在被执行第一操作后会大概率地被执行第二操作。比如用户购买云资源时只购买了存储资源，因此在接收到报文后只对报文进行存储。
在一种可能的实施例中，数据预取系统还包括存储节点，写入请求还包括数据写入地址，数据写入地址为待写入数据写入存储节点时在存储节点中的存储地址；主节点还包括：
缓存单元，用于当确定单元根据指示信息确定缓存节点2不需要对待写入数据进行数据预取操作时，将待写入数据和数据写入地址缓存至主节点的缓存中。
在一种可能的实施例中，发送单元还用于：在向缓存节点2发送第一侦听消息的同时，向其他缓存节点发送第二侦听消息，第二侦听消息用于指示其他缓存节点删除原数据，原数据为在主节点接收到待写入数据之前数据写入地址对应的数据；其中，其他缓存节点为多个缓存节点中除了缓存节点1和缓存节点2之外的缓存节点。
在一种可能的实施例中，发送单元，还用于在向缓存节点2发送响应消息的同时，向缓存节点1发送完成消息，该完成消息用于告知缓存节点1数据写入完成。
需要说明的是，本领域技术人员可以理解，由于硬件所限，通常不可能实现100％的同时，因此，本申请所说的“同时”并非指100％没有时间差，而是一个相对很小的时间差，用于保证两个消息发送尽量同时，从而可以尽快将消息传递给对端，以节省时延，具体的，该时间差可以间隔一个或若干个指令周期。此外，两个消息的发送顺序也不限定，比如主节点发送响应消息在前，发送完成消息在后；或者主节点发送完成消息在前，发送响应消息在后。
在一个可行的实施例中，数据预取系统还包括存储节点，发送单元还用于：
向存储节点发送数据更新消息，以将待写入数据更新至存储节点中数据写入地址对应的存储空间中；其中，该数据更新消息携带有所述待写入数据。
在一种可能的实施例中，数据预取系统为处理器，缓存节点以及主节点包括处理器中的高速缓存cache及其控制电路。主节点和缓存节点之间通过cache总线进行数据交互，在协议上主节点和缓存节点之前通过cache一致性协议(比如MSI协议、MSIF协议)进行数据交互。
进一步地，计算节点为处理器中的核(core)，比如ARM核或x86核。
在一种可能的实施例中，数据预取系统为集群计算系统，且集群计算系统包括多台处理服务器和存储服务器，缓存节点包括处理服务器中的内存控制器以及内存(比如DDR控制器及DDR存储介质)，主节点包括存储服务器中的处理器以及内存。
进一步地，计算节点为处理服务器的处理器。
第四方面，本申请实施例还提供一种缓存节点，该缓存节点应用于数据预取系统，该数据预取系统还包括主节点和其他多个缓存节点，该缓存节点包括：
接收单元，用于接收主节点发送的第一侦听消息，第一侦听消息携带有预取询问标识，预取询问标识用于指示缓存节点执行确定是否需要对进行数据预取操作的步骤；待写入数据为缓存节点1将接收到的数据处理完后得到的数据，缓存节点1为其他多个缓存节点中的一个；
确定单元，用于根据预取询问标识确定其是否需要对待写入数据进行数据预取操作；
发送单元，用于向主节点发送第一侦听响应消息；该第一侦听响应消息包括用于指示缓存节点是否需要对待写入数据进行数据预取操作；
接收单元，还用于若确定单元确定缓存节点需要对待写入数据进行数据预取操作且在向主节点发送第一侦听响应消息后，接收主节点发送的响应消息，该响应消息携带有待写入数据。
在一种可能的实施例中，数据预取系统还包括多个计算节点，多个计算节点与多个缓存节点一一对应，缓存节点1对应的计算节点用于对接收到的数据执行第一操作，缓存节点对应的计算节点用于对接收到的数据执行第二操作，该接收到的数据在被执行完第一操作后会大概率地被执行第二操作。
其中，接收到的数据在被执行第一操作后会大概率被地执行第二操作包括：缓存节点1可根据接收到数据的类型确定接收到的数据在被执行第一操作后会大概率地被执行第二 操作；或者缓存节点1根据对接收到的数据的处理流程确定接收到的数据在被执行第一操作后会大概率地被执行第二操作；或者缓存节点1根据实际的硬件资源来确定接收到的数据在被执行第一操作后会大概率地被执行第二操作。比如用户购买云资源时只购买了存储资源，因此在接收到报文后只对报文进行存储。
在一种可能的实施例中，确定单元具体用于：若缓存节点支持数据预取功能且需要待写入数据；则确定缓存节点需要对待写入数据进行数据预取操作；若缓存节点支持数据预取功能但不需要待写入数据，或者缓存节点不支持数据预取功能，则确定缓存节点不需要对待写入数据进行数据预取操作。
在一种可能的实施例中，指示信息为第一侦听响应消息中包括的第一预取结果标识，该第一预取结果标识的不同值用于指示缓存节点是否需要对待写入数据进行数据预取操作(例如第一预取结果标识的取值为第一预设阈值，以指示缓存节点需要对待写入数据进行数据预取操作；第二预取结果标识的取值为第二预设阈值，以指示缓存节点不需要对待写入数据进行数据预取操作)；或者，指示信息为第一侦听响应消息中是否包括第二预取结果标识来表示缓存节点是否需要对待写入数据进行数据预取操作的信息(例如第一侦听响应消息包括第二预取结果标识，以指示缓存节点需要对待写入数据进行数据预取操作；第一侦听响应消息中未包括第二预取结果标识，以指示缓存节点不需要对待写入数据进行数据预取操作)。
在一种可能的实施例中，数据预取系统为处理器，缓存节点以及主节点包括处理器中的高速缓存cache及其控制电路。主节点和缓存节点之间通过cache总线进行数据交互，在协议上主节点和缓存节点之前通过cache一致性协议(比如MSI协议、MSIF协议)进行数据交互。
进一步地，计算节点为处理器中的核(core)，比如ARM核或x86核。
在一种可能的实施例中，数据预取系统为集群计算系统，且集群计算系统包括多台处理服务器和存储服务器，缓存节点包括处理服务器中的内存控制器以及内存(比如DDR控制器及DDR存储介质)，主节点包括存储服务器中的处理器以及内存。
进一步地，计算节点为处理服务器的处理器。
可以看出，在本申请实施例的方案中，主节点接收到缓存节点1发送的写入请求后，通过向缓存节点2发送侦听消息，该侦听消息中的预取询问标识用于指示缓存节点2执行确定是否需要对上述写入请求中的待写入数据进行数据预取操作的操作。缓存节点2向主节点确定其是否需要对待写入数据进行数据预取操作后，向主节点发送侦听响应消息，该侦听响应消息中携带用于指示缓存节点2是否需要对待写入数据进行数据预取操作的指示信息；若根据指示信息确定缓存节点2需要对待写入数据进行数据预取操作，则主节点向缓存节点2发送响应消息，该响应消息携带有上述待写入数据。采用本申请实施例，将数据预取的应用场景扩展到不局限于同一个缓存节点内且进行数据预取时刻是确定的，并达到最早；同时提升数据预取的准确度和进一步降低数据交互时延，当多个缓存节点访问相同地址时，可将处理时延压缩到单个指令周期。
附图说明
图1a为一种数据预取的流程示意图；
图1b为本申请提供的一种侦听和目录相结合实现缓存一致性的方法示意图；
图2a为本申请实施例提供的一种应用数据预取方法的拓扑结构示意图；
图2b为本申请实施例提供的另一种应用数据预取方法的拓扑结构示意图；
图2c为本申请实施例提供的另一种应用数据预取方法的拓扑结构示意图；
图2d为本申请实施例提供的另一种应用数据预取方法的拓扑结构示意图；
图3本申请实施例提供的一种数据预取系统的框架示意图；
图4为本申请实施例提供的一种缓存节点的逻辑功能结构示意图；
图5为本申请实施例提供的一种主节点和存储节点的逻辑功能结构示意图；
图6为本申请实施例提供的一种数据预取方法的流程示意图；
图7为技术效果对比示意图；
图8为本申请实施例提供的一种基于处理器场景的缓存节点的结构示意图；
图9为本申请实施例提供的一种基于处理器场景的主节点和缓存节点的结构示意图；
图10为本申请实施例提供的一种基于集群计算场景的主节点和缓存节点的结构示意图；
图11为一种单级结构的多核系统示意图；
图12为本申请实施例提供的一种数据预取方法的流程示意图；
图13为一种多级结构的多核系统示意图；
图14为本申请实施例提供的一种处理器场景的框架示意图；
图15为本申请实施例提供的一种主节点的结构示意图；
图16为本申请实施例提供的一种缓存节点的结构示意图；
图17为本申请实施例提供的一种数据预取设备的结构示意图。
具体实施方式
下面结合附图对本申请的实施例进行描述。
首先在此介绍现有技术中缓存一致性机制的相关原理。
每个处理器内核都有本地缓存以及维护本地缓存一致性的硬件模块，将该硬件模块和本地缓存统称为缓存节点，将处理器内核称为计算节点。
缓存一致性机制有两种，一种是基于侦听(snoop)的一致性，另一种是基于目录的一致性。在基于侦听的缓存一致性机制中，每个缓存节点(图1b的缓存节点1、缓存节点2)都可以广播数据更新请求，其他缓存节点监控数据更新请求并确定自己是否拥有该数据更新请求对应的数据副本。该侦听机制时延较短，但同时也会带来由于连续性广播数据所造成的带宽占用和可扩展性问题。在基于目录的一致性机制中，多个缓存节点之间共享的数据可以存储在主节点中，主节点可通过目录记录的方式保持众多缓存节点之间的一致性。当一个缓存节点中的数据更新时，主节点可以更新或无效目录中记录的该数据在其他节点的条目，实现全系统的数据副本在单点维护和管理，从而保证各缓存节点间的数据一致性，该目录机制可有效改善侦听机制中广播带来的问题，但由于任何缓存节点更新数据都需要集中的经过目录并一一获得更新许可，导致了较大的访问时延。
为获得以上两种机制的优点，目前一般采用侦听/目录相结合的机制，如修改，拥有，独占，共享，无效(modified,owned,exclusive,shared,invalid,MOESI)或修改，独占，共 享，无效，转发(modified,exclusive,shared,invalid,forwarding,MESIF)等，结合图1b对侦听/目录相结合的机制原理进行说明。
图1b中的缓存节点1、缓存节点2和主节点可以属于同一个CPU。主节点为缓存一致性维护节点，并与双倍数据速率(double data rate，DDR)存储介质直接相连。
当缓存节点1发起对某个DDR存储器的地址对应的数据进行读取时，首先缓存节点1向主节点发送数据读取请求；在主节点接收到缓存节点1发送的数据读取请求后，该主节点广播侦听消息到其他缓存节点(图1b为示意方便，仅示出向缓存节点2发送，实际上也会向其他缓存节点发送侦听消息)，该侦听消息用于确定其他缓存节点的本地是否存储有上述DDR存储器的地址对应的数据；各缓存节点收到侦听消息后进行对应的处理后向主节点发送侦听响应消息，以缓存节点2为例，若缓存节点2的本地存储有该DDR存储器的地址对应的数据，则上述侦听响应消息中携带有DDR存储器的地址对应的数据；若上述缓存节点2的本地未存储上述DDR存储器的地址对应的数据，则上述侦听响应消息不携带DDR存储器的地址对应的数据。主节点收到所有的其他缓存节点的侦听响应消息后，向上述缓存节点1发送响应消息。若主节点获取上述DDR存储器的地址对应的数据后，上述响应消息携带上述DDR存储器地址对应的数据，且主节点根据需要同步向DDR存储器更新对应的数据。如果在这个过程中主节点收到来自其他缓存节点对相同地址的数据进行读取，则先执行完本次读取请求后再响应其他缓存节点的读取请求。
需要指出的是，上述DDR存储器是DDR1、DDR2、DDR3、DDR4等存储器的统称。
本申请实施例提供的数据预取方法适用于任意两个或多个具有缓存能力并且支持缓存一致性的计算电路之间的通信，计算电路包括但不限定于CPU、图形处理单元(graphics processing unit，GPU)、数字信号处理器(digital signal processor，DSP)、现场可编程门阵列(field programmable gate array，FPGA)等。
本申请实施例可承载在任何缓存一致性协议之中进行扩展(如MOESI协议，MESIF)协议等)，不限于物理接口形式和互连拓扑结构，即该方法可直接对现有的缓存一致性协议进行增强，也可以重新定义包含本申请关键要素的缓存一致性机制，同时可承载在如外部设备快速互联通道(peripheral component interconnect express，PCIe)架构、以太网(Ethernet)等任意形态的物理接口之上，且无互连拓扑结构限制。
如图2a示意直接互连结构，两个具有缓存能力的计算单元直接互连；或如图2b示意环状/网状互连结构，三个具有缓存能力的计算单元首尾相连组成环状网络；或如图2c示意全互连结构，四个具有缓存能力的计算单元两两相互连接；或如图2d示意任意互连拓扑，任意个具有缓存能力的计算单元之间任意连接。
参见图3，图3为本申请实施例提供的一种数据预取系统的框架示意图。如图3所述，该数据预取系统包括多个计算节点、多个缓存节点、主节点和存储节点。
其中，计算节点与缓存节点相连接，且多个计算节点与多个缓存节点一一对应，多个缓存节点与主节点相连接，主节点与存储节点相连接。多个缓存节点间的数据交互是通过主节点实现的。
其中，缓存节点中任一个缓存节点C可以接收其他缓存节点的数据，或者接收缓存节点C对应的计算节点发送的数据，然后进行处理，处理完成后向主节点发送写入请求。本申请并不限定缓存节点C具体从哪种以及哪个节点接收数据。
主节点用于维护多个缓存节点的缓存一致性。比如当多个缓存节点中任一个缓存节点从其对应的计算节点或者从其他缓存节点得到数据，对该数据进行处理产生新的数据后，都会将该新的数据发送至主节点；再比如当缓存节点中的任一个缓存节点A需要读取数据时，该缓存节点A会向主节点发送数据读取请求，主节点在从其本地或者其他缓存节点中获取缓存节点A所需的数据。换句话说，主节点为多个缓存节点的数据的管理中心。
需要说明的是，主节点可以看成多个缓存节点的下级缓存。
具体地，如图4所示，从逻辑功能上划分，上述多个缓存节点中的每个缓存节点包括多个输入接口401、多个输出接口406、接收电路402、处理逻辑电路404、缓存电路403和发送电路405。
其中，输入接口401全部耦合到内部接收电路402，输出接口406全部耦合到内部发送电路405，用于向主节点请求读取数据或者写入数据，或响应主节点的读取数据请求。输入接口401和输出接口406用于实现前后级缓存节点之间的连接，进而实现不同的拓扑结构，如图2a-图2d所示。
缓存电路403可用于存储易失性数据、指令、频繁访问的存储节点中的数据副本等，其中缓存电路403可全部或部分的嵌入到处理逻辑电路404内部，以便更快速的存取数据。缓存电路403可以为易失性、非易失性存储器。
处理逻辑电路404用于对接收到的数据进行处理，并且判断是否需要预取其他缓存节点产生的数据，处理逻辑电路404为缓存节点的核心。
需要说明的是，多个缓存节点可以组成多个缓存级别，如2级缓存、3级缓存和4级缓存等。
具体地，如图5所示，从逻辑功能上划分，主节点包括多个输入接口501、多个输出接口508、接收电路502、处理逻辑电路504、缓存电路503和发送电路507。存储节点包括存储控制器505、存储电路506。
其中，输入接口501全部耦合到内部接收电路502，输出接口508全部耦合到内部发送电路507，用于向外部缓存节点请求数据，或响应外部缓存节点的数据请求。
缓存电路503可用于存储易失性数据、指令、频繁访问的存储电路506中的数据副本等。缓存电路503可以为易失性、非易失性存储器。
处理逻辑电路504用于处理缓存一致性相关的事务和维护缓存节点间数据一致性，也是执行数据预取的主体。
存储控制器505和存储电路506用于存储程序指令以及程序执行期间的过程数据，其中存储控制器505用于控制和管理流入和流出存储电路506的数据流，在一个实施例中，存储控制器505的功能也可以由处理逻辑电路504实现，以达到更快速访问存储电路506的目的，因此图5中存储控制器505是以虚线框表示的。一般而言，存储电路506可使用易失性存储器和非易失性存储器，非易失性存储器可用于数据的非易失性存储，易失性存储器通常可用于存储程序执行期间的过程数据。
首先需要在此说明的是，多个缓存节点要共享缓存，不可避免多个缓存节点可能会对同一个缓存地址进行操作，当某一个缓存节点对该缓存地址操作完后，修改了该缓存地址对应的存储空间里面的数据，其他缓存节点从该缓存地址取数据时会取不到预期的数据。为了保证一致性，需要有主节点来维护数据的一致性，以保证其他缓存节点取到的数据都是预期的数据。
实施例一
参见图6，图6为本申请实施例提供的一种数据预取方法的流程示意图。该方法应用于数据预取系统，该数据预取系统包括主节点和多个缓存节点。
如图6所示，该方法包括：
S601、主节点接收到缓存节点1在将接收到的数据处理完后发送的写入请求。
需要说明的是，缓存节点对接收到的数据进行的处理包括对接收到的数据进行解封装，得到待写入数据，然后将待写入数据映射到满足缓存节点间传输协议的净荷上，然后填充该协议的报头和速率适配，得到写入请求。
其中，缓存节点1可以接收其他缓存节点的数据；或者上述数据预取系统还包括多个计算节点，该多个计算节点分别与多个缓存节点一一连接，例如，缓存节点1可以与一个计算节点对应，此时，缓存节点1可以接收缓存节点1所对应的计算节点发送的数据，然后进行处理，处理完成后向主节点发送写入请求；本申请并不限定缓存节点1具体从哪种以及哪个节点接收数据。
写入请求携带有待写入数据、数据预取标识、数据预取的节点号。其中，数据预取的节点号用于指示缓存节点2。缓存节点1和缓存节点2为上述多个缓存节点中的两个不同的节点。
S602、主节点从写入请求中获取数据预取标识和数据预取节点号后，根据该数据预取标识向数据预取的节点号所指示的缓存节点2发送第一侦听消息，该第一侦听消息携带有预取询问标识。
其中，预取询问标识用于指示缓存节点2执行确定其是否需要对待写入数据进行数据预取操作的步骤。
在一种可能的实施例中，数据预取系统还包括多个计算节点，多个计算节点与多个缓存节点一一对应，缓存节点1对应的计算节点1用于对接收到的数据执行第一操作，缓存节点2对应的计算节点2用于对接收到的数据执行第二操作，该接收到的数据在被执行完第一操作后会大概率地被执行第二操作。其中，本申请中，“大概率”具体的值并不限定，本领域技术人员可以结合实际产品的需求来定义。具体的，本领域技术人员可以理解，本申请中，数据在被执行完第一操作后，如果会再被执行第二操作，那么缓存节点2的预取操作就会带来收益；否则，如果不会被执行第二操作，那么会白白增加处理的成本(包括处理时间会更长，增加处理功耗)，因此，本领域技术人员可以根据实际应用场景来确定一个合理的“概率”，可以理解，在“概率”越大的情况下，带来的收益也会越大，例如，大概率可以为大于80％以上，或者90％以上。
其中，“接收到的数据在被执行第一操作后会大概率地被执行第二操作”可以是通过事 先的业务模型来确定。例如，产品人员在设计一种业务模型时，可规定各硬件(如计算节点)的处理能力，例如，设计计算节点1有90％的可能性会接收到语音数据进行处理，处理完后肯定会再转给计算节点2；另外计算节点1有10％的可能性会用于处理其他数据，但处理完后不再转给计算节点2。在这种情况下，数据被执行第一操作后，会有90％的可能性被执行第二操作，就适合使用本申请的方案。
在另一实施例中，“接收到的数据在被执行第一操作后会大概率地被执行第二操作”也可以不是预先定义的模型，而是通过在处理过程中来实现。其中，接收到的数据在被执行第一操作后会大概率地被执行第二操作包括：缓存节点1可根据接收到数据的类型确定接收到的数据在被执行第一操作后会大概率地被执行第二操作(比如说对接收到的数据进行运算，包括整数运算和小数运算，若接收到数据的类型为整数，则在接收数据(即第一操作)后对该数据进行整数运算(即第二操作))；或者缓存节点1根据对接收到的数据的处理流程确定接收到的数据在被执行第一操作后会大概率地被执行第二操作；或者缓存节点1根据实际的硬件资源或用户服务(如用户能够使用哪些功能、使用哪些硬件等)来确定接收到的数据在被执行第一操作后会大概率地被执行第二操作，比如用户购买云资源时购买了存储资源，因此在接收报文(即第一操作)后会对报文进行存储(即第二操作)；或者，缓存节点1根据历史统计数据得到在自己曾经写入主节点的数据中，被缓存节点2读取的比例，将其作为当前待写入主节点的数据会被缓存节点2再次读取的概率；当这个概率大于某个阈值时，缓存节点1在发往主节点的写入请求中，设置预取标识并指定预取节点号为缓存节点2。
需要说明的是，缓存节点1在向主节点1发送写入请求之前，缓存节点1会根据接收到数据的类型、已知的业务处理流程和/或硬件资源确定接收到数据的大概率地被使用的下一任使用者(比如缓存节点2对应的计算节点)。因此缓存节点1在向主节点发送的写入请求中会携带指示缓存节点2的数据预取的节点号。
比如缓存节点1对应的计算节点对接收到的数据执行第一操作，缓存节点2对应的计算节点对接收到的数据执行第二操作。缓存节点1在向主节点发送写入请求之前，根据接收到数据的类型、已知的业务处理流程和/或硬件资源确定接收到的数据在被执行第一操作后会大概率地被执行第二操作，因此缓存节点1在向主节点发送的写入请求中会携带指示缓存节点2的数据预取的节点号。
在此需要说明的是，主节点接收到缓存节点1发送的写入请求后，向缓存节点2和其他缓存节点广播侦听消息。由于写入请求中携带有数据预取的节点号，且该数据预取节点号所指示的缓存节点为缓存节点2，因此在向缓存节点2发送的侦听消息中携带预取询问标识，该预取询问标识用于指示缓存节点2执行确定是否需要对待写入数据进行数据预取操作的步骤。为了区分，将向其他缓存节点发送的侦听消息称为第二侦听消息，将向缓存节点2发送的侦听消息为第一侦听消息。
其中，其他缓存节点为多个缓存节点中除了缓存节点1和缓存节点2之外的缓存节点。
主节点向其他缓存节点发送的第二侦听消息用于指示其他缓存节点删除其缓存电路中存储的原数据，原数据为主节点接收到待写入数据之前数据写入地址对应的数据。
这样处理的好处是，比如在缓存节点1向主节点发送写入请求之前，部分缓存节点已 获取了数据写入地址对应的数据，以供缓存节点对应的计算节点使用。当主节点接收到缓存节点1发送的写入请求后，此时数据写入地址对应的数据发生变化。对于已获取的数据写入地址对应的数据的缓存节点来说，其获取的数据不是预期需要的，因此主节点会向这些缓存节点发送第二侦听消息，以指示这些缓存节点删除该数据写入地址对应的数据。在主节点完成对缓存节点1发送的写入请求中的待写入数据处理后，其他缓存节点可以向主节点发送数据读取请求，以请求获取数据写入地址对应的最新的数据(即待写入数据)。这样可以使得这些缓存节点对同一存储地址获取的数据是一致的。
在一个可能的实施例中，缓存节点2接收到第一侦听消息后，缓存节点2先确定其是否具有数据预取功能，若确定其具有数据预取功能，则缓存节点2再继续确定其是否需要待写入数据，若确定需要待写入数据，则缓存节点2确定其需要对待写入数据进行数据预取操作；若确定缓存节点2具有数据预取功能，但不需要待写入数据，则缓存节点2确定其不需要对待写入数据进行数据预取操作；若确定缓存节点2不具有数据预取功能，则确定缓存节点2不需要对待写入数据进行数据预取操作。
S603、主节点接收缓存节点2发送的第一侦听响应消息，该第一侦听响应消息包括用于指示缓存节点2是否需要对待写入数据进行数据预取操作的指示信息。
其中，第一侦听响应消息有两个功能，一是用于响应第一侦听消息，二是用于指示缓存节点2是否需要对待写入数据进行数据预取操作；若指示缓存节点2需要对待写入数据进行数据预取操作，则第一侦听响应消息的第二个功能可以看成缓存节点2向主节点请求获取待写入数据。
本申请的侦听响应消息与传统的侦听响应消息相比，多了用于指示缓存节点2是否对待写入数据进行数据预取操作的功能。
需要说明的是，当指示信息用于指示缓存节点2需要对待写入数据进行数据预取操作时，该第一侦听响应消息具体是用于响应第一侦听消息和请求获取待写入数据；当指示信息用于指示缓存节点2不需要对待写入数据进行数据预操作时，该第一侦听响应消息具体是用于响应第一侦听消息。
在一种可能的实施例中，指示信息为第一侦听响应消息中包括的第一预取结果标识，该第一预取结果标识的不同值用于指示缓存节点2是否需要对待写入数据进行数据预取操作。例如第一预取结果标识的取值为第一预设阈值(比如true或1)，以指示缓存节点2需要对待写入数据进行数据预取操作；第一预取结果标识的取值为第二预设阈值(比如false或0)，以指示缓存节点不需要对待写入数据进行数据预取操作。
在一种可能的实施例中，指示信息为第一侦听响应消息中是否包括第二预取结果标识来表示缓存节点2是否需要对待写入数据进行数据预取操作的信息。例如第一侦听响应消息包括第二预取结果标识，以指示缓存节点2需要对待写入数据进行数据预取操作；第一侦听响应消息中未包括第二预取结果标识，以指示缓存节点2不需要对待写入数据进行数据预取操作。需要解释说明的是，第二预取结果标识每次的取值可以相同，也可以不相同。
需要说明的是，上述数据预取标识、预取询问标识、第一预取结果标识和第二预取结果标识中的部分或者全部可以是不同消息中的同一字段，也即不同的消息中的同一个字段用来表示不同的含义。
在一个实施例中，若确定缓存节点2不需要对待写入数据进行数据预取操作，则主节点将待写入数据及数据写入地址保存至其缓存中。
需要说明的是，主节点的缓存电路中保存有数据与存储地址的对应关系表，数据存储地址为存储节点中的地址。具体地，主节点遍历数据与存储地址的对应关系表，若确定该数据与存储地址的对应关系表中保存有待写入数据的数据写入地址，则将该数据写入地址对应的数据更新为待写入数据。若确定数据与存储地址的对应关系表未保存待写入数据的数据写入地址，则将待写入数据及数据写入地址保存至数据与存储地址的对应关系表中。
S604、当根据指示信息确定缓存节点2需要对待写入数据进行数据预取操作时，主节点向缓存节点2发送携带待写入数据的响应消息。
其中，响应消息携带有待写入数据。若第一侦听响应消息用于指示缓存节点2需要对待写入数据进行数据预取操作时，则第一侦听响应消息可以看成缓存节点2向主节点请求获取待写入数据。同时，这里的响应消息也用于对第一侦听消息进行响应，即具有前述603步骤中提到的用于响应第一侦听消息的功能。
需要说明的是，主节点存储有数据与存储地址的对应关系表，该对应关系表包括数据及对应的存储地址，该存储地址为存储节点中的地址。
在一个可能的实施例中，数据预取系统还包括存储节点，上述写入请求还包括数据写入地址，数据写入地址为待写入数据在存储节点中的存储地址；该方法还包括：
若根据指示信息确定缓存节点2不需要对待写入数据进行数据预取操作，则主节点将待写入数据及数据写入地址保存至主节点的缓存中。若主节点的缓存没有足够的空间来存储待写入数据和/或数据写入地址，则该主节点向存储节点发送数据更新消息，以将待写入数据更新至存储节点中数据写入地址对应的存储空间中。该数据更新消息中携带有待写入数据和数据写入地址。
若在存储节点中数据写入地址对应的存储空间中已存储有数据，将该数据删除并将待写入数据保存到数据写入地址对应的存储空间中；若数据写入地址对应的存储空间未存储数据，则直接将待写入数据存储至数据写入地址对应的存储空间中。
需要说明的是，当其他缓存节点在一段时间内需要反复读取上述待写入数据时，即上述待写入数据为热数据，为了方便其获取待写入数据，上述主节点暂时将该待写入数据存储至数据与存储地址的对应关系表中，主节点可以直接从该对应关系表中获取该待写入数据。当在一段时间内其他缓存节点不需要反复读取上述待写入数据，此时上述待写入数据已是冷数据，为了节省主节点的存储空间，主节点将上述待写入数据写入到上述存储节点中上述数据写入地址对应的存储空间。
在一个可能的实施例中，当多个缓存节点向主节点发送对存储节点中同一地址A对应的存储空间存储的数据进行读取的请求时，主节点首先遍历其存储的数据及其存储地址的对应关系表，确定主节点中是否缓存地址A对应的数据，若主节点中存储有地址A对应的数据，则将该数据同时发送到多个缓存节点；若主节点未缓存地址A对应的数据，则主节点从上述存储节点中获取地址A对应的数据，并将该数据同时发送至上述多个缓存节点。
需要说明的是，主节点的缓存电路中保存有数据与存储地址的对应关系表。数据存储地址为存储节点中的地址。主节点通过该对应关系表来维护多个缓存节点的数据一致性。
在一个可能的实施例中，在主节点向缓存节点2发送响应消息的同时，向缓存节点1发送完成消息，该完成消息用于响应写入请求。换句话说，该完成消息用于告知缓存节点1主节点已完成对待写入数据的写入。
需要说明的是，本领域技术人员可以理解，由于硬件所限，通常不可能实现100％的同时，因此，本申请所说的“同时”并非指100％没有时间差，而是一个相对很小的时间差，用于保证两个消息发送尽量同时，从而可以尽快将消息传递给对端，以节省时延，具体的，该时间差可以间隔一个或若干个指令周期。此外，两个消息的发送顺序也不限定，比如主节点发送响应消息在前，发送完成消息在后；或者主节点发送完成消息在前，发送响应消息在后。
采用本申请的数据预取的方法的有益效果可参见图7。如图7所示，图7中的a图为现有技术中数据预取的示意图，从该图可知现有技术的缺点有：进行数据预取时刻的不确定、是否需要进行数据预取的结果存在不确定性和时延大。图7中的b图为采用本申请的数据预取的方法后的数据预取示意图，从该图可知，数据预取时刻是确定的，如图7所示，本申请方案中：主节点接收到缓存节点1发送的写入请求后，通过向缓存节点2发送侦听消息，该侦听消息中的预取询问标识用于指示缓存节点2执行确定是否需要对上述写入请求中的待写入数据进行数据预取操作的操作。缓存节点2向主节点确定其是否需要对待写入数据进行数据预取操作后，向主节点发送侦听响应消息，该侦听响应消息中携带用于指示缓存节点2是否需要对待写入数据进行数据预取操作的指示信息；若根据指示信息确定缓存节点2需要对待写入数据进行数据预取操作，则主节点向缓存节点2发送响应消息，该响应消息携带有上述待写入数据。采用本申请实施例，将数据预取的应用场景扩展到不局限于同一个缓存节点内且进行数据预取时刻是确定的，并达到最早；同时提升数据预取的准确度和进一步降低数据交互时延，当多个缓存节点访问相同地址时，可将处理时延压缩到单个指令周期。
在一个可能的实施例中，上述数据预取系统为处理器，多个计算节点为处理器中的核(core)，缓存节点以及主节点包括处理器中的高速缓存(cache)及其控制电路，存储节点可以为DDR存储介质。主节点和缓存节点之间通过cache总线进行数据交互，在协议上主节点和缓存节点之前通过cache一致性协议(比如修改、共享、无效(Modified Shared Invalid，MSI)协议或修改、共享、无效、转发(Modified Shared Invalid forwarding，MSIF协议))进行数据交互。
实施例二
基于以上实施例，本实施例基于处理器场景对上述方案进行具体介绍。在处理器的场景下，缓存节点(包括cache及其控制电路)可以看成cache电路。如图8所示，该cache电路包括多个输入/输出接口801、收发器802、cache控制电路804、高速存储介质803。其中，输入/输出接口801直接与收发器802耦合，该收发器802与cache控制电路804相连接，多个输入/输出接口801相当于图4中的输入接口401和输出接口406，收发器802相当于图4中的发送电路405和接收电路402。cache控制电路804相当于图4中的处理逻辑电路404，cache控制电路804与高速存储介质803相连接，高速存储介质803相当于图4中的缓存电路403，该高速存储介质803可以为静态随机存取存储器(static random-access  memory，SRAM)。
在一个可能的实施例中，上述多个缓存节点中的每个缓存节点包括一个高速存储介质，或者上述多个缓存节点共用一个高速存储介质，该高速存储介质从逻辑上被划分成多个缓存电路，以使多个缓存节点中的每个缓存节点有一个缓存电路供使用。
在处理器的场景下，主节点(包括cache及其控制电路)也可以看成cache电路。如图9所示，该cache电路包括多个输入/输出接口901、收发器902、cache控制电路904、高速存储介质903。其中，输入/输出接口901直接与收发器902耦合，该收发器902与cache控制电路904相连接。多个输入/输出接口901相当于图5中的输入接口501和输出接口506，收发器902相当于图5中的发送电路507和接收电路502。cache控制电路904相当于图5中的处理逻辑电路504，cache控制电路904与高速存储介质903相连接，高速存储介质903相当于图5中的缓存电路503，该高速存储介质903可以为静态随机存取存储器(static random-access memory，SRAM)。
存储节点包括存储控制电路906及片外存储介质905，该存储控制电路906相当于图5中的存储控制器505，该片外存储介质905相当于图5中的存储电路506，该片外存储介质905是指处理器的外部存储介质，可以为同步动态随机存储器(synchronous dynamic random access memory，SDRAM)，例如，具体可以是DDR SDRAM(本申请中也简称“DDR”或者“DDR存储器”)。需要说明的是，SRAM的访存速度最快，SDRAM的访存速度慢于SRAM的访存速度。
在一个可能的示例中，存储节点中存储控制电路906可以嵌入在主节点中的cache控制电路904中。
在一个可能的实施例中，上述存储节点都包括一个片外存储介质，或者上述多个存储节点共用一个片外存储介质，该片外存储介质从逻辑上被划分为多个虚拟存储电路(如片外存储介质中的不同存储区域)，以使多个存储节点中的每个存储节点均有一个虚拟存储电路供使用。
对于处理器场景，在一个具体的实施例中，处理器上运行有一个或多个虚拟机(本申请中称“虚拟机组”)，此外，由于这些虚拟机用于执行任务，因此，也称“任务机”。各个虚拟机可以共用物理内存，在硬件上可能会是基于处理器的单机系统，但这个单机系统中的内存会被共享，每个虚拟机组有自己的私有内存，同时，虚拟机组之间有共享的内存。
在一种应用场景中，该处理器可以进行视频解码操作，处理器从云端收到码流后，处理器上运行的虚拟机组1用于接收报文，虚拟机组2用于解压缩，虚拟机组3用于解码，虚拟机组4用于后端存储。因此对于视频解码在该处理器上的业务流程为：接收报文、解压缩、解码和存储。
比如缓存节点1对应的core用于运行虚拟机组1，缓存节点2对应的core用于运行虚拟机组2。因此缓存节点1可根据业务流程确定虚拟机组1接收报文后需要将该报文传输至虚拟机组2(即缓存节点1确定其处理完的数据的下一任使用者为缓存节点2或者说缓存节点1处理完的数据会大概率地被缓存节点2使用)，以进行解压缩。
再比如，缓存节点1对应的core用于运行虚拟机组1，缓存节点2对应的core用于运行虚拟机组4。虚拟机组1做了网络接收后，需要对接收到报文进行存储，且知道虚拟机 自4的能力(比如仅具有存储能力)，则说明大概率会把报文发送给用于存储的虚拟机组4。
实施例三
基于上述各实施例，本实施例公开了另一种数据预取系统，在本实施例中，数据预取系统为集群计算系统，且该集群计算系统包括多台处理服务器和存储服务器时，数据预取系统的缓存节点包括处理服务器中的内存控制器以及内存，比如处理服务器中的DDR存储介质及DDR控制器。主节点包括存储服务器中的处理器及内存，存储节点为存储服务器中存储控制器和存储介质组成的电路，比如由固态硬盘(solid state disk，SSD)控制器和SSD存储介质组成的电路。主节点与计算节点之间通过无限带宽(infiniband，IB)总线进行数据交互。
如图10所示，集群计算系统包括处理服务器1、处理服务器2和存储服务器。处理服务器1包括计算节点1以及缓存节点1。其中，计算节点1包括M个core、M个高速缓存、环形总线控制器1、内存接口1、IB接口1和其他接口1；其中，M为大于或者等于1的整数。M个高速缓存中的每个高速缓存包括高速缓存介质及其控制电路，比如cache介质及cache控制电路。M个core与M个高速缓存一一对应连接，M个高速缓存还均与环形总线控制器1连接，内存接口1、IB接口1和其他接口1均与环形总线控制器1连接。缓存节点1包括内存控制器1和内存1。缓存节点1通过其内存控制器1与计算节点1中的内存接口1实现与计算节点1之间的数据交互。
可选地，处理服务器1中的core可以为ARM核或者x86核。
需要说明的是，处理服务器2与处理服务器1具有相同的功能实体或者逻辑电路，这些功能实体或逻辑电路之间的连接关系与处理服务器1中的功能实体或逻辑电路之间的连接关系相同，在此不再叙述。换句话说，处理服务器2包括计算节点2和缓存节点2。处理服务器2包括N个core和N个高速缓存，N个core与N个高速缓存一一对应连接。N个高速缓存为由高速缓存介质及其控制器组成的电路。N为大于或者等于1的整数，N与M相同或者不同。
可选地，处理服务器2中的core可以为ARM核或者x86核。
存储服务器可以包括主节点以及存储节点，其中，主节点包括处理器及内存(图10中所示的内存3)；存储节点包括存储控制器和存储介质。其中，对于存储控制器和存储介质，若存储介质为机械硬盘存储介质，则存储控制器为机械硬盘存储控制器；若存储介质为SSD存储介质，则存储控制器为SSD控制器；若存储介质为闪存(flash)，则存储控制器为闪存控制器。
主节点中的处理器通过IB总线与计算节点1中的IB接口1连接，由于IB接口1通过环形总线控制器1和内存接口1与缓存节点1的内存控制器1连接，因此可实现主节点和缓存节点1之间的数据交互。主节点还通过IB总线与处理服务器2的计算节点2的IB接口2连接，由于IB接口2和内存接口2均与环形总线控制器2连接，且内存接口2与缓存节点2中的内存控制器2相连接，因此可实现主节点与缓存节点2之间的数据交互。
具体地，缓存节点1的内存控制器1接收到计算节点1通过内存接口1传输的数据后，该内存控制器1对该数据进行处理，数据处理完后内存控制器1通过内存接口1、环形总 线控制器1和IB接口基于IB总线向主节点发送写入请求，该写入请求携带有待写入数据、数据预取标识、数据预取节点号和数据写入地址；其中待写入数据为处理完后的数据，数据预取节点号所指示的缓存节点为缓存节点2，数据写入地址为待写入数据在存储节点的存储介质中的存储地址。
主节点接收到缓存节点1的写入请求后，从写入请求中获取待写入数据、数据预取节点号，数据预取标识和数据写入地址，并向数据预取节点号所指示的缓存节点2发送第一侦听消息，该第一侦听消息携带有预取询问标识。具体地，主节点中的处理器通过IB总线经处理服务器2的IB接口2将第一侦听消息发送至处理服务器2中的环形总线控制器2，该环形总线控制器2通过内存接口2向缓存节点2的内存控制器2发送第一侦听消息。
主节点中的处理器接收缓存节点2的内存控制器2发送的第一侦听响应消息后，根据该第一侦听响应消息确定缓存节点2需要对待写入数据是否进行数据预取操作。若确定缓存节点2需要对待写入数据进行数据预取操作，则主节点向缓存节点2发送响应消息，该响应消息携带有待写入数据。其中，主节点向缓存节点2发送响应消息的路径与主节点向缓存节点2发送第一侦听消息的路径相同。若确定缓存节点2不需要对待写入数据进行数据预取操作，则主节点中的处理器将待写入数据及数据写入地址保存到内存3中。如果主节点的内存3没有足够的存储空间存储待写入数据和/或数据写入地址，则将待写入数据保存或者更新至存储节点的存储介质中数据写入地址对应的存储空间中。
同时，主节点的处理器基于IB总线通过IB接口1、环形总线控制器1和内存接口1向缓存节点1的内存控制器1发送完成消息，该完成消息用于告知缓存节点1数据写入完成。
需要说明的是，缓存节点1中的内存1和缓存节点2中的内存2均可以为DDR存储介质。若缓存节点1中的内存1和缓存节点2中的内存2为DDR存储介质，则内存控制器1和内存控制器2为DDR控制器，内存接口1和内存接口2为DDR接口。
需要说明的是，主节点为所有缓存节点(包括处理服务器1中的缓存节点1和处理服务器2中的缓存节点2)共享的数据或数据库的管理节点。其中，该数据库包括该共享的数据。
在一种可能的实施例中，处理服务器1中的其他接口1包括PCIE接口或以太网接口，处理服务器2的其他接口2包括PCIE接口或以太网接口。处理服务器1的缓存节点1通过PCIE接口或以太网接口实现与主节点进行数据交互(即可以不通过IB接口)，处理服务器2的缓存节点2通过PCIE接口或以太网接口实现与主节点进行数据交互(即可以不通过IB接口)，进而实现对服务器1中的缓存节点1和处理服务器2中的缓存节点2的共享的数据或数据库的管理。其中，该数据库包括该共享的数据。
可以看出，在本申请实施例的方案中，主节点接收到缓存节点1的写入请求后，就向缓存节点2发送第一侦听消息，当确定缓存节点2需要对写入请求中的待写入数据进行数据预取操作时，主节点向缓存节点2发送待写入数据。采用本申请实施例使得数据预取场景未局限于一个缓存节点内，并解决了发起数据预取时刻和预测结果存在不确定性的问题，同时降低了时延。
实施例四
基于上述各实施例，本申请对另一种数据预取系统及数据预取方法进行介绍。参见图11，图11为一种单级结构的数据预取系统示意图。如图11所示，该数据预取系统包括两级缓存，分别为第S-1级缓存和第S级缓存。第S-1级缓存由M1个缓存节点组成，第S级缓存由互连网络和N1个主节点组成，其中，M1、N1和S均为大于或者等于1的整数。主节点在逻辑上和物理上可理解为缓存节点的下一级缓存节点，当存在多个主节点时，各主节点所属的内存进行统一编址，即多个主节点在逻辑上可理解为分布式主节点，同时各主节点管理着缓存节点之间的缓存一致性。互连网络用于为M1个缓存节点和N1个主节点之间的通信提供互连。需要说明的是，这里所说的单级是指在图11中只有一级缓存节点，即S-1级缓存。
需要说明的是，下级缓存可为上级缓存的主节点。例如在多核CPU芯片内，若缓存节点为一级缓存/二级缓存，则主节点为三级缓存，若缓存节点为三级缓存，则主节点为四级缓存，以此类推。缓存节点为多核CPU芯片内的cache，主节点为多核CPU芯片中cache总线的管理节点。这里所说的多核可以是一个CPU中的，还可以是跨CPU的，还可以是跨CPU和加速器的。
参见图12，图12为本申请实施例提供的一种数据读取方法的流程示意图。如图12所示，该方法包括：
S1201、缓存节点C1向目标主节点发送数据读取请求，该数据读取请求用于请求读取目标数据。
其中，上述缓存节点C1为第S-1级缓存包括的M1个缓存节点中的一个，目标主节点为第S级缓存包括的N1个主节点中的一个。上述数据读取请求携带数据读取地址，该数据读取地址为存储节点中的地址，该地址对应的存储空间存储的最新数据即为上述目标数据。
需要说明的是，M1个缓存节点与N1个主节点存在连接关系，因此缓存节点需要读取数据时，可以直接向与其具有连接关系的主节点发送数据读取请求。
S1202、目标主节点判断在其本地的缓存电路中是否缓存有目标数据。
其中，当确定在其本地的缓存电路中缓存有上述目标数据时，上述目标主节点执行步骤S1203；当在确定其本地的缓存电路中未缓存上述目标数据时，上述目标主节点执行步骤S1204。
具体地，目标主节点本地的缓存电路中存储有数据与存储地址的对应关系表。目标主节点先根据数据读取地址遍历上述数据与存储地址对应关系表，确定该对应关系表中是否存储有上述目标数据；若上述对应关系表中存储有上述目标数据，即确定上述目标主节点本地的缓存电路中缓存上述目标数据，上述目标主节点执行步骤S1203；若上述对应关系表中未存储有上述目标数据，即确定上述目标主节点本地的缓存电路中未缓存上述目标数据，上述目标主节点执行步骤S1204。
S1203、目标主节点向缓存节点C1发送第一完成消息。
其中，上述第一完成消息携带有上述目标数据，且该第一完成消息并指示上述缓存节点C1将该目标数据设置为共享状态。
需要说明的是，指示上述缓存节点C1将目标数据设置为共享状态的目的为了使与缓存节点C1位于同一CPU的缓存节点或同一系统的缓存节点能够直接获取该目标数据，而不用向主节点发送数据读取请求。
S1204、目标主节点向其他缓存节点发送侦听消息。
其中，上述侦听消息用于指示上述其他缓存节点查询其本地是否缓存有上述目标数据。
需要指出的是，上述其他缓存节点为在上述第S-1级缓存包括的M1个缓存节点中除了上述缓存节点C1之外的缓存节点。
S1205、其他缓存节点中的每个缓存节点向目标主节点发送响应消息。
具体地，若上述其他缓存节点中的一个缓存节点C2缓存有上述目标数据，则该缓存节点C2向目标主节点发送的响应消息携带有上述目标数据；若上述其他缓存节点均未缓存上述目标数据，上述其他缓存节点中的每个缓存节点向目标主节点发送用于告知上述目标主节点其未缓存上述目标数据的响应消息。
S1206、目标主节点判断其他缓存节点中是否缓存目标数据。
其中，当确定上述其他缓存节点缓存有上述目标数据时，上述目标主节点执行步骤S1207；当确定上述其他缓存节点未缓存上述目标数据时，上述目标主节点执行步骤S1208。
S1207、目标主节点向缓存节点C1发送完成消息。
其中，上述完成消息中携带有上述目标数据，且该完成消息用于请求上述缓存节点C1将上述目标数据设置为共享状态，并将上述数据与存储地址的对应关系表中的数据读取地址对应的数据更新为上述目标数据。
在一个可能的实施例中，若上述目标主节点的缓存电路没有充足的存储空间来存储目标数据时，则将该目标数据存储至上述存储节点中数据读取地址对应的存储空间中。
S1208、若第S级缓存包括的N1个主节点为末端节点，则目标主节点向缓存节点C1发送第二完成消息。
其中，上述第二完成消息携带有上述目标主节点的与数据读取地址对应的数据，其中，目标主节点可以根据数据与存储地址之间的对应关系表来获取数据读取地址对应的数据。
进一步地，若存在下一级缓存(即第S+1级缓存)，如图13所示的多级结构，则当上述目标主节点从上述M1个缓存节点(即第S-1级缓存)中未获取目标数据时，目标主节点向上述第S+1级缓存发送数据读取请求，以请求获取上述目标数据。
需要说明的是，若存在第S+1级缓存时，则第S级缓存可以为缓存节点，第S+1级缓存可以为主节点。
第S+1级缓存中的主节点接收到上述数据读取请求时，先判断其本地是否存储目标数据。若本地未存储目标数据，则向其所维护的缓存节点广播侦听消息，以请求获取目标数据。若第S+1级缓存中的主节点接收到其所维护的缓存节点发送的目标数据后，向上述目标主节点发送携带目标数据的响应消息。
上述目标主节点接收上述第S+1级缓存发送的响应消息，并将该响应消息转发至上述缓存节点C1。
在一个可能的实施例中，若上述响应消息携带有上述目标数据，则目标主节点同时根据需求将该目标数据及数据读取地址添加到上述目标主节点本地存储电路的数据及存储地 址对应的关系表中。
实施例五
基于上述各实施例，本申请实施例提供了一种处理器，如图14所示，为该处理器的硬件框架示意图。该处理器包括：多个CPU核(core)、多个缓存节点以及主节点，M为大于1的整数。其中上述缓存节点以及主节点包括处理器中的高速缓存(cache)及其控制电路，主节点用于维护多个缓存节点的数据一致性，主节点同时管理存储节点。缓存节点与CPU核之间、缓存节点与缓存节点之间、缓存节点和主节点通过cache总线进行数据交互。
可选地，处理器还可以包括相比于cache速度较低的存储介质(如DDR)，在实际中，这些速度较低的存储介质还可以位于处理器外，作为片外存储介质，例如，位于图14中的存储节点上，其中，该存储节点与处理器不在一个芯片上。
其中，上述多个缓存节点可以划分为一级缓存、二级缓存和三级缓存。
一级缓存包括M个缓存节点，该M个缓存节点与M个CPU核一一对应连接，二级缓存包括N个缓存节点，该N个缓存节点可以用于维护一级缓存中的缓存节点的缓存一致性，因此二级缓存中的缓存节点可以看成一级缓存中缓存节点主节点，N为小于M的整数。如图14所示，二级缓存中的1个缓存节点可以维护一级缓存中的2个缓存节点的缓存一致性，比如缓存节点20可以看成缓存节点10和缓存节点11的主节点，缓存节点21可以看成缓存节点12和缓存节点13的主节点。当然二级缓存中的1个缓存节点也可以维护一级缓存中的其他数量的缓存节点的缓存一致性，其他值可以为3,4,5等等，本申请不限定于此。
三级缓存包括t个缓存节点，该t个缓存节点可以用于维护二级缓存中缓存节点的缓存一致性，因此三级缓存中的缓存节点可以看成二级缓存中缓存节点的主节点，t为小于n的整数。如图14所示，三级缓存中的1个缓存节点可以维护二级缓存中的2个缓存节点的缓存一致性，比如缓存节点30可以看成缓存节点20和缓存节点21的主节点。当然二级缓存中的1个缓存节点也可以维护一级缓存中的其他数量的缓存节点的缓存一致性，其他值可以为3,4,5等等，本申请不限定于此。
图14中的主节点为多个缓存节点的cache总线的管理中心，用于维护多个缓存节点(包括一级缓存、二级缓存和三级缓存中的缓存节点)的缓存一致性。该主节点还包括控制器，用于控制管理存储介质。主节点还可以理解为三级缓存的下一级缓存(即四级缓存)。
若缓存节点被划为一级缓存、二级缓存、三级缓存和四级缓存，则图14中的主节点可理解为五级缓存。
其中，对于图14中缓存节点，输入接口为逻辑或物理接口；输出接口为逻辑或物理接口。一级缓存中缓存节点的输入接口/输出接口用于连接如图14所示的CPU核与二级缓存中的缓存节点，二级缓存中缓存节点的输入接口/输出接口用于连接如图14所示的一级缓存中的缓存节点和三级缓存中的缓存节点；三级缓存中的缓存节点的输入接口/输出接口用于连接如图14所示二级缓存中的缓存节点和主节点。同时缓存节点的输入接口全部耦合到其内部接收电路，用于接收CPU核、其他缓存节点和主节点发送的数据或者消息；缓存节点的输出接口全部耦合到其内部发送电路，用于向CPU核、其他缓存节点和主节点发送数据或者消息。
在一个具体的实施例中，如图14所示，若CPU core0需要数据D，CPU core0对应的缓存节点10向其主节点(即缓存节点20)发送数据读取请求，缓存节点20为缓存节点10和缓存节点11的主节点。缓存节点20接收到数据读取请求后，首先确定其本地缓存电路中是否存储有数据D；若缓存节点20的缓存电路中存储有数据D，则缓存节点20直接向缓存节点10发送数据D；若缓存节点20的缓存电路中未存储数据D，则缓存节点20向其维护的缓存节点(即缓存节点10和缓存节点11)广播侦听消息，该侦听消息用于请求获取数据D；缓存节点11向缓存节点20发送侦听响应消息。
若缓存节点11的本地缓存电路存储有数据D，则缓存节点11向缓存节点20发送的侦听响应消息携带有数据D，缓存节点20接收到缓存节点11的侦听响应消息后，向缓存节点10发送响应消息，该响应消息中携带有数据D。
若缓存节点11的本地缓存电路未存储有数据D，在缓存节点20接收到缓存节点11的侦听响应消息后，向缓存节点20的下级节点(即缓存节点30)转发数据读取请求。缓存节点30为缓存节点20和缓存节点21的主节点。缓存节点30接收到数据读取请求后，确定其本地缓存电路是否存储有数据D；若存储有数据D，缓存节点30向缓存节点20发送携带数据D的响应消息；若缓存节点30的本地缓存电路未存储数据D，则向其所维护的缓存节点(即缓存节点20和缓存节点21)广播侦听消息，用于请求数据D。
缓存节点21接收到缓存节点30的侦听消息后，确定其本地的缓存电路是否存储有数据D；若缓存节点21确定其本地缓存电路存储有数据D，则向缓存节点30发送携带数据D的侦听响应消息；若缓存节点21确定其本地未存储数据D，则向其所维护的缓存节点(即缓存节点12和缓存节点13)广播侦听消息，用于请求获取数据D；缓存节点21接收其所维护的缓存节点发送的侦听响应消息；若该侦听响应消息中携带数据D，缓存节点21向缓存节点30发送携带数据D的响应消息；若缓存节点21接收到的侦听响应消息未携带数据D，则缓存节点21确定其所维护的缓存节点的缓存电路中未存储数据D，向缓存节点30发送用于告知未获取数据D的响应消息。
若缓存节点30获取数据D，向缓存节点20发送携带数据D的响应消息；若缓存节点30未获取数据D，则向缓存节点20发送用于告知未获取数据D的响应消息；若缓存节点20获取数据D，向缓存节点10发送携带数据D的响应消息；若缓存节点20未获取数据D，则向缓存节点10发送用于告知未获取数据D的响应消息。
需要说明的是，缓存节点10、缓存节点11、缓存节点12和缓存节点13可以看成图11或图13中的S-1级缓存，缓存节点20和缓存节点21可以看成图11或图13中的S级缓存，缓存节点20可以看成缓存节点10和缓存节点11的主节点，缓存节点21可以看成缓存节点12和缓存节点13的主节点。缓存节点30可以看成图10中的S+1级缓存，缓存节点30为缓存节点20和缓存节点21的主节点。
需要说明的是，图10所示的集群计算系统可以按照该方法进行数据的读取，在此不再叙述。
在一个可能的实施例中，本申请实施例提供一种数据预取系统，该数据预取系统包括主节点和多个缓存节点。其中，多个缓存节点包括缓存节点1和缓存节点2。缓存节点1、缓存节点2和主节点所执行的具体步骤可参见图6所示实施例的相关描述，在此不再叙述。
实施例六
基于上述各实施例，本申请实施例提供了一种主节点，如图15所示，为该主节点的结构示意图。该主节点应用于数据预取系统，该数据预取系统还包括多个缓存节点。如图15所示，该主节点1500包括：
接收单元1501，用于接收缓存节点1在将接收到的数据处理完后发送的写入请求；其中，写入请求中携带待写入数据、数据预取标识、数据预取的节点号；待写入数据为缓存节点1将接收到的数据处理完得到的数据；
发送单元1502，用于根据数据预取标识向数据预取的节点号指示的缓存节点2发送第一侦听消息，该第一侦听消息携带有预取询问标识，预取询问标识用于指示缓存节点2执行确定其是否需要对待写入数据进行数据预取操作的步骤；其中，缓存节点1和缓存节点2为多个缓存节点中的两个不同的节点；
接收单元1501，还用于接收缓存节点2发送的第一侦听响应消息；该第一侦听响应消息包括用于指示缓存节点2是否需要对待写入数据进行数据预取操作的指示信息，其中，第一侦听响应消息为缓存节点2根据预取询问标识确定是否需要对待写入数据进行数据预取操作后发送的；
确定单元1503，用于根据指示信息确定缓存节点2是否需要对待写入数据进行数据预取操作；
发送单元1502，还用于若确定单元1503根据指示信息确定缓存节点2需要对待写入数据进行数据预取操作，则向缓存节点2发送携带待写入数据的响应消息。
在一种可能的实施例中，指示信息为第一侦听响应消息中包括的第一预取结果标识，该第一预取结果标识的不同值用于指示缓存节点2是否需要对待写入数据进行数据预取操作(例如第一预取结果标识的取值为第一预设阈值，以指示缓存节点2需要对待写入数据进行数据预取操作；第一预取结果标识的取值为第二预设阈值，以指示缓存节点2不需要对待写入数据进行数据预取操作)；或者，指示信息为第一侦听响应消息中是否包括第二预取结果标识来表示缓存节点2是否需要对待写入数据进行数据预取操作的信息(例如第一侦听响应消息包括第二预取结果标识，以指示缓存节点2需要对待写入数据进行数据预取操作；第一侦听响应消息中未包括第二预取结果标识，以指示缓存节点2不需要对待写入数据进行数据预取操作)。
在一种可能的实施例中，数据预取系统还包括多个计算节点，该多个计算节点与多个缓存节点一一对应；
缓存节点1对应的计算节点用于对接收到的数据执行第一操作，缓存节点2对应的计算节点用于对接收到的数据执行第二操作；接收到的数据在被执行完第一操作后会大概率地被执行第二操作。
在一种可能的实施例中，数据预取系统还包括存储节点，写入请求还包括数据写入地址，数据写入地址为待写入数据写入存储节点时在存储节点中的存储地址；主节点还包括：
缓存单元1504，用于当确定单元1503根据指示信息确定缓存节点2不需要对待写入数据进行数据预取操作时，将待写入数据和数据写入地址缓存至主节点的缓存中。
在一种可能的实施例中，发送单元1502还用于：在向缓存节点2发送第一侦听消息的同时，向其他缓存节点发送第二侦听消息，第二侦听消息用于指示其他缓存节点删除原数据，原数据为在主节点接收到待写入数据之前数据写入地址对应的数据；其中，其他缓存节点为多个缓存节点中除了缓存节点1和缓存节点2之外的缓存节点。
在一种可能的实施例中，发送单元1502，还用于在向缓存节点2发送响应消息的同时，向缓存节点1发送完成消息，该完成消息用于告知缓存节点1数据写入完成。
需要说明的是，本领域技术人员可以理解，由于硬件所限，通常不可能实现100％的同时，因此，本申请所说的“同时”并非指100％没有时间差，而是一个相对很小的时间差，用于保证两个消息发送尽量同时，从而可以尽快将消息传递给对端，以节省时延，具体的，该时间差可以间隔一个或若干个指令周期。此外，两个消息的发送顺序也不限定，比如主节点发送响应消息在前，发送完成消息在后；或者主节点发送完成消息在前，发送响应消息在后。
在一个可行实施例中，数据预取系统还包括存储节点，发送单元1502还用于：
向存储节点发送数据更新消息，以将待写入数据更新至存储节点中数据写入地址对应的存储空间中；其中，数据更新消息携带有待写入数据。
在一种可能的实施例中，数据预取系统为处理器，缓存节点以及主节点包括处理器中的高速缓存cache及其控制电路。主节点和缓存节点之间通过cache总线进行数据交互，在协议上主节点和缓存节点之前通过cache一致性协议(比如MSI协议、MSIF协议)进行数据交互。
进一步地，计算节点为处理器中的核(core)，比如ARM核或x86核。
在一种可能的实施例中，数据预取系统为集群计算系统，且集群计算系统包括多台处理服务器和存储服务器，缓存节点包括处理服务器中的内存控制器以及内存(比如DDR控制器及DDR存储介质)，主节点包括存储服务器中的处理器以及内存。
进一步地，计算节点为处理服务器的处理器。
需要说明的是，接收单元1501用于执行图6所示实施例的步骤S601的相关内容，发送单元1502用于执行图6所示实施例的步骤S602和S604的相关内容，接收单元1501和确定单元1503用于执行图6所示实施例的步骤S603的相关内容。
作为一个示例，该接收单元1501和发送单元1502的位置对应于图9中的输入/输出接口901和收发器902，确定单元1503的位置对应于图9中的cache控制电路904，缓存单元1504的位置对应于图9中的高速存储介质903。换言之，接收单元1501和发送单元1502的功能可以由图9中的输入/输出接口901和收发器902来实现，确定单元1503的功能可以由图9中的cache控制电路904来实现，缓存单元1504的功能可以由图9中的高速存储介质903来实现。当然本申请不限于此。
实施例七
基于上述各实施例，本申请实施例提供了一种缓存节点，如图16所示，为该缓存节点的结构示意图。该缓存节点应用于数据预取系统，该数据预取系统还包括主节点和其他多个缓存节点。如图16所示，该缓存节点1600包括：
接收单元1601，用于接收主节点发送的第一侦听消息，第一侦听消息携带有预取询问标识，预取询问标识用于指示缓存节点执行确定是否需要对待写入数据进行数据预取操作的步骤；其中，该待写入数据为缓存节点1将接收到的数据处理完后得到的数据，缓存节点1为其他多个缓存节点中的一个；
确定单元1602，用于根据预取询问标识确定缓存节点是否需要对待写入数据进行数据预取操作；
发送单元1603，用于向主节点发送第一侦听响应消息；该第一侦听响应消息包括用于指示缓存节点是否需要对待写入数据进行数据预取操作；
接收单元1601，还用于若确定单元1602确定缓存节点2需要对待写入数据进行数据预取操作且在向主节点发送第一侦听响应消息后，接收主节点发送的响应消息，该响应消息携带有待写入数据。
在一种可能的实施例中，数据预取系统还包括多个计算节点，该多个计算节点与多个缓存节点一一对应；
缓存节点1对应的计算节点用于对接收到的数据执行第一操作，缓存节点对应的计算节点用于对接收到的数据执行第二操作；接收到的数据在被执行完第一操作后会大概率地被执行第二操作。
在一种可能的实施例中，确定单元1602具体用于：若缓存节点支持数据预取功能且需要待写入数据；则确定缓存节点需要对待写入数据进行数据预取操作；若缓存节点支持数据预取功能但不需要待写入数据，或者缓存节点不支持数据预取功能，则确定缓存节点不需要对待写入数据进行数据预取操作。
在一种可能的实施例中，指示信息为第一侦听响应消息中包括的第一预取结果标识，该第一预取结果标识的不同值用于指示缓存节点是否需要对待写入数据进行数据预取操作(例如第一预取结果标识的取值为第一预设阈值，以指示缓存节点需要对待写入数据进行数据预取操作；第一预取结果标识的取值为第二预设阈值，以指示缓存节点不需要对待写入数据进行数据预取操作)；或者，指示信息为第一侦听响应消息中是否包括第二预取结果标识来表示缓存节点是否需要对待写入数据进行数据预取操作(例如第二侦听响应消息包括第二预取结果标识，以指示缓存节点需要对待写入数据进行数据预取操作；第二侦听响应消息中未包括第二预取结果标识，以指示缓存节点不需要对待写入数据进行数据预取操作)。
在一种可能的实施例中，数据预取系统为处理器，缓存节点以及主节点包括处理器中的高速缓存cache及其控制电路。主节点和缓存节点之间通过cache总线进行数据交互，在协议上主节点和缓存节点之前通过cache一致性协议(比如MSI协议、MSIF协议)进行数据交互。
进一步地，计算节点为处理器中的核(core)，比如ARM核或x86核。
在一种可能的实施例中，数据预取系统为集群计算系统，且集群计算系统包括多台处理服务器和存储服务器，缓存节点包括处理服务器中的内存控制器以及内存(比如DDR控制器及DDR存储介质)，主节点包括存储服务器中的处理器以及内存。
进一步地，计算节点为处理服务器的处理器。
需要说明的是，接收单元1601、确定单元1602和发送单元1603用于执行图6所示实施例的相关内容。
作为一个示例，该接收单元1601和发送单元1602的位置对应于图8中的输入/输出接口801和收发器802，确定单元1602的位置对应于图8中的cache控制电路804。换言之，接收单元1601和发送单元1603的功能可以由图8中的输入/输出接口801和收发器802来实现，确定单元1602的功能可以由图8中的cache控制电路804来实现。当然本申请不限于此。
实施例八
基于上述各实施例，本实施例提供了一种设备。参见图17，图17为本申请实施例提供的一种设备的结构示意图。该设备1700包括至少一个处理器1701，至少一个存储器1702以及至少一个通信接口1703。所述处理器1701、所述存储器1702和所述通信接口1703通过所述通信总线连接并完成相互间的通信。
处理器1701可以是通用中央处理器(CPU)，微处理器，特定应用集成电路(application-specific integrated circuit，ASIC)，或一个或多个用于控制以上方案执行的集成电路。
通信接口1703，用于与其他设备或通信网络通信，如以太网，无线接入网(RAN)，无线局域网(Wireless Local Area Networks，WLAN)等。
存储器1702可以是只读存储器(read-only memory，ROM)或可存储静态信息和指令的其他类型的静态存储设备，随机存取存储器(random access memory，RAM)或者可存储信息和指令的其他类型的动态存储设备，也可以是电可擦可编程只读存储器(Electrically Erasable Programmable Read-Only Memory，EEPROM)、只读光盘(Compact Disc Read-Only Memory，CD-ROM)或其他光盘存储、光碟存储(包括压缩光碟、激光碟、光碟、数字通用光碟、蓝光光碟等)、磁盘存储介质或者其他磁存储设备、或者能够用于携带或存储具有指令或数据结构形式的期望的程序代码并能够由计算机存取的任何其他介质，但不限于此。存储器可以是独立存在，通过总线与处理器相连接。存储器也可以和处理器集成在一起。
其中，存储器1702用于存储执行以上方案的应用程序代码，并由处理器1701来控制执行。处理器1701用于执行存储器1702中存储的应用程序代码。
存储器1702存储的代码可执行以上提供一种数据预取方法，具体包括缓存节点2接收主节点发送的第一侦听消息，第一侦听消息携带有预取询问标识，预取询问标识用于指示缓存节点2执行确定是否需要对待写入数据进行数据预取操作的步骤；待写入数据为缓存节点1将接收到的数据处理完后得到的数据，缓存节点1和缓存节点2为多个缓存节点中的两个不同的节点；缓存节点2根据预取询问标识确定其是否需要对待写入数据进行数据预取操作；并向主节点发送第一侦听响应消息；该第一侦听响应消息包括用于指示缓存节点2是否需要对待写入数据进行数据预取操作的指示信息，若缓存节点2确定其需要对待写入数据进行数据预取操作且在向主节点发送第一侦听响应消息后，接收主节点发送的响应消息，响应消息携带有待写入数据；或者，
存储器1702存储的代码可执行以上提供的另一种数据预取方法，具体包括：主节点接收缓存节点1在将接收到的数据处理完后发送的写入请求；其中，该写入请求中携带待写 入数据、数据预取标识、数据预取的节点号；主节点根据数据预取标识向数据预取的节点号指示的缓存节点2发送第一侦听消息，该第一侦听消息携带有预取询问标识，该预取询问标识用于指示缓存节点2执行确定其是否需要对待写入数据进行数据预取操作的步骤；主节点接收缓存节点2发送的第一侦听响应消息，该第一侦听响应消息包括用于指示缓存节点2是否需要对待写入数据进行数据预取操作的指示信息，其中，第一侦听响应消息为缓存节点2根据预取询问标识确定是否需要对待写入数据进行数据预取操作后发送的；当主节点确定缓存节点2需要对待写入数据进行数据预取操作时，主节点向缓存节点2发送携带待写入数据的响应消息，缓存节点1和缓存节点2为多个缓存节点中的两个不同的节点。
通过以上的实施方式的描述，所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，仅以上述各功能模块的划分进行举例说明，实际应用中，可以根据需要而将上述功能分配由不同的功能模块完成，即将装置的内部结构划分成不同的功能模块，以完成以上描述的全部或者部分功能。
在本申请所提供的几个实施例中，应该理解到，所揭露的装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述模块或单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个装置，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是一个物理单元或多个物理单元，既可以位于一个地方，或者也可以分布到多个不同地方。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
本申请实施例提供的方法中，可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。当使用软件实现时，可以全部或部分地以计算机程序产品的形式实现。所述计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行所述计算机程序指令时，全部或部分地产生按照本申请实施例所述的流程或功能。所述计算机可以是通用计算机、专用计算机、计算机网络、网络设备、终端或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一个计算机可读存储介质传输，例如，所述计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如同轴电缆、光纤、数字用户线(digital subscriber line，DSL))或无线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。所述计算机可读存储介质可以是计算机可以存取的任何可用介质或者是包含一个或多个可用介质集成的服务器、数据中心等数据存储设备。所述可用介质可以是磁性介质(例如，软盘、硬盘、磁带)、光介质(例如，数字视频光盘(digital video disc，DVD))、或者半导体介质(例如，SSD)等。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何在本申请揭露的技术范围内的变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (32)

  1. 一种数据预取方法，其特征在于，所述方法应用于数据预取系统，该数据预取系统包括主节点和多个缓存节点，所述方法包括：
    所述主节点接收缓存节点1发送的写入请求；其中，所述写入请求中携带待写入数据、数据预取标识、数据预取的节点号；
    所述主节点根据所述数据预取标识向所述数据预取的节点号指示的缓存节点2发送第一侦听消息，所述第一侦听消息携带有预取询问标识，所述预取询问标识用于指示所述缓存节点2执行确定是否需要对所述待写入数据进行数据预取操作的步骤；
    所述主节点接收所述缓存节点2发送的第一侦听响应消息，所述第一侦听响应消息包括用于指示所述缓存节点2是否需要对所述待写入数据进行数据预取操作的指示信息；
    当所述主节点根据所述指示信息确定所述缓存节点2需要对所述待写入数据进行数据预取操作时，所述主节点向所述缓存节点2发送携带所述待写入数据的响应消息；
    其中，所述缓存节点1和所述缓存节点2为所述多个缓存节点中的两个不同的节点。
  2. 根据权利要求1所述的方法，其特征在于：
    所述指示信息为第一侦听响应消息中包括的第一预取结果标识，所述第一预取结果标识的不同值用于指示所述缓存节点2是否需要对所述待写入数据进行数据预取操作；
    或者，
    所述指示信息为通过第一侦听响应消息中是否包括第二预取结果标识来表示所述缓存节点2是否需要对所述待写入数据进行数据预取操作的信息。
  3. 根据权利要求1或2所述的方法，其特征在于，所述数据预取系统还包括多个计算节点，所述多个计算节点与所述多个缓存节点一一对应；
    所述缓存节点1对应的计算节点用于对接收到的数据执行第一操作，所述缓存节点2对应的计算节点用于对所述接收到的数据执行第二操作；所述接收到的数据在被执行完所述第一操作后会大概率地被执行所述第二操作。
  4. 根据权利要求1-3任一项所述的方法，其特征在于，所述数据预取系统还包括存储节点，所述写入请求还包括数据写入地址，所述数据写入地址为所述待写入数据写入所述存储节点时在所述存储节点中的存储地址；所述方法还包括：
    当所述主节点根据所述指示信息确定所述缓存节点2不需要对所述待写入数据进行数据预取操作时，所述主节点将所述待写入数据和数据写入地址缓存至所述主节点的缓存中。
  5. 根据权利要求1-4任一项所述的方法，其特征在于，所述主节点向缓存节点2发送第一侦听消息的同时，所述方法还包括：
    所述主节点向其他缓存节点发送第二侦听消息，所述第二侦听消息用于指示所述其他缓存节点删除原数据，所述原数据为在所述主节点接收到所述待写入数据之前所述数据写 入地址对应的数据；
    其中，所述其他缓存节点为所述多个缓存节点中除了所述缓存节点1和缓存节点2之外的缓存节点。
  6. 根据权利要求1-5任一项所述的方法，其特征在于，在所述主节点向所述缓存节点2发送响应消息的同时，所述方法还包括：
    向所述缓存节点1发送完成消息，所述完成消息用于告知所述缓存节点1数据写入完成。
  7. 根据权利要求1-6任一项所述的方法，其特征在于，所述数据预取系统还包括存储节点，所述方法还包括：
    所述主节点向所述存储节点发送数据更新消息，以将所述待写入数据更新至所述存储节点中数据写入地址对应的存储空间中；
    其中，所述数据更新消息携带有所述待写入数据。
  8. 根据权利要求1-7任一项所述的方法，其特征在于，所述第一侦听响应消息为所述缓存节点2根据所述预取询问标识确定是否需要对所述待写入数据进行数据预取操作后发送的。
  9. 根据权利要求1-8任一项所述的方法，其特征在于，所述数据预取系统为处理器，所述缓存节点以及所述主节点包括所述处理器中的高速缓存cache及cache控制电路。
  10. 根据权利要求1-8任一项所述的方法，其特征在于，所述数据预取系统为集群计算系统，所述集群计算系统包括多台处理服务器和存储服务器，所述缓存节点包括所述处理服务器中的内存控制器以及内存，所述主节点包括所述存储服务器中的处理器以及内存。
  11. 一种数据预取方法，其特征在于，所述方法应用于数据预取系统，所述数据预取系统包括主节点和多个缓存节点，所述方法包括：
    缓存节点2接收所述主节点发送的第一侦听消息，所述第一侦听消息携带有预取询问标识，所述预取询问标识用于指示所述缓存节点2执行确定是否需要对待写入数据进行数据预取操作的步骤；所述待写入数据为缓存节点1将接收到的数据处理完后得到的数据，所述缓存节点1和缓存节点2为所述多个缓存节点中的两个不同的节点；
    所述缓存节点2根据所述预取询问标识确定其是否需要对所述待写入数据进行数据预取操作；
    所述缓存节点2向所述主节点发送第一侦听响应消息；所述第一侦听响应消息包括用于指示所述缓存节点2是否需要对所述待写入数据进行数据预取操作的指示信息；
    若所述缓存节点2确定其需要对所述待写入数据进行数据预取操作且在向所述主节点发送所述第一侦听响应消息后，接收所述主节点发送的响应消息，所述响应消息携带有所 述待写入数据。
  12. 根据权利要求11所述的方法，其特征在于，所述数据预取系统还包括多个计算节点，所述多个计算节点与所述多个缓存节点一一对应；
    所述缓存节点1对应的计算节点用于对接收到的数据执行第一操作，所述缓存节点2对应的计算节点用于对所述接收到的数据执行第二操作；所述接收到的数据在被执行完所述第一操作后会大概率地被执行所述第二操作。
  13. 根据权利要求11或12所述的方法，其特征在于，所述缓存节点2根据预取询问标识确定其是否需要对所述待写入数据进行数据预取操作，包括：
    若所述缓存节点2支持数据预取功能且需要所述待写入数据；则所述缓存节点2确定其需要对所述待写入数据进行数据预取操作；
    若所述缓存节点2支持数据预取功能且不需要所述待写入数据，或者所述缓存节点2不支持数据预取功能，则所述缓存节点2确定其不需要对所述待写入数据进行数据预取操作。
  14. 根据权利要求11-13任一项所述的方法，其特征在于，
    所述指示信息为第一侦听响应消息中包括的第一预取结果标识，所述第一预取结果标识的不同值用于指示所述缓存节点2是否需要对所述待写入数据进行数据预取操作；
    或者，
    所述指示信息为通过第一侦听响应消息中是否包括第二预取结果标识来表示所述缓存节点2是否需要对所述待写入数据进行数据预取操作的信息。
  15. 根据权利要求11-14任一项所述的方法，其特征在于，所述数据预取系统为处理器，所述缓存节点以及所述主节点包括所述处理器中的高速缓存cache及其控制电路。
  16. 根据权利要求11-14任一项所述的方法，其特征在于，所述数据预取系统为集群计算系统，且所述集群计算系统包括多台处理服务器和存储服务器，所述缓存节点包括所述处理服务器中的内存控制器以及内存，所述主节点包括存储服务器中的处理器以及内存。
  17. 一种主节点，其特征在于，所述主节点应用于数据预取系统，该数据预取系统还包括多个缓存节点，所述主节点包括：
    接收单元，用于接收缓存节点1发送的写入请求；其中，所述写入请求中携带待写入数据、数据预取标识、数据预取的节点号；
    发送单元，用于根据所述数据预取标识向所述数据预取的节点号指示的缓存节点2发送第一侦听消息，所述第一侦听消息携带有预取询问标识，所述预取询问标识用于指示所述缓存节点2执行确定其是否需要对所述待写入数据进行数据预取操作的步骤；
    所述接收单元，还用于接收所述缓存节点2发送的第一侦听响应消息；所述第一侦听 响应消息包括用于指示所述缓存节点2是否需要对所述待写入数据进行数据预取操作的指示信息，
    所述发送单元，还用于当确定单元根据所述指示信息确定所述缓存节点2需要对所述待写入数据进行数据预取操作时，向所述缓存节点2发送携带所述待写入数据的响应消息；
    其中，所述缓存节点1和缓存节点2为所述多个缓存节点中的两个不同的节点。
  18. 根据权利要求17所述的主节点，其特征在于，
    所述指示信息为第一侦听响应消息中包括的第一预取结果标识，所述第一预取结果标识的不同值用于指示所述缓存节点2是否需要对所述待写入数据进行数据预取操作；
    或者，
    所述指示信息为通过第一侦听响应消息中是否包括第二预取结果标识来表示所述缓存节点2是否需要对所述待写入数据进行数据预取操作的信息。
  19. 根据权利要求17或18所述的主节点，其特征在于，所述数据预取系统还包括多个计算节点，所述多个计算节点与所述多个缓存节点一一对应；
    所述缓存节点1对应的计算节点用于对接收到的数据执行第一操作，所述缓存节点2对应的计算节点用于对所述接收到的数据执行第二操作；所述接收到的数据在被执行完所述第一操作后会大概率地被执行所述第二操作。
  20. 根据权利要求17-19任一项所述的主节点，其特征在于，所述数据预取系统还包括存储节点，所述写入请求还包括数据写入地址，所述数据写入地址为所述待写入数据写入所述存储节点时在所述存储节点中的存储地址；所述主节点还包括：
    缓存单元，用于当所述确定单元根据所述指示信息确定所述缓存节点2不需要对所述待写入数据进行数据预取操作，将所述待写入数据和数据写入地址缓存至所述主节点的缓存中。
  21. 根据权利要求17-20任一项所述的主节点，其特征在于，所述发送单元还用于：
    在向缓存节点2发送第一侦听消息的同时，向其他缓存节点发送第二侦听消息，所述第二侦听消息用于指示所述其他缓存节点删除原数据，所述原数据为在所述主节点接收到所述待写入数据之前所述数据写入地址对应的数据；
    其中，所述其他缓存节点为所述多个缓存节点中除了所述缓存节点1和缓存节点2之外的缓存节点。
  22. 根据权利要求17-21任一项所述的主节点，其特征在于，所述发送单元，还用于在向所述缓存节点2发送响应消息的同时，向所述缓存节点1发送完成消息，所述完成消息用于告知所述缓存节点1数据写入完成。
  23. 根据权利要求17-22任一项所述的主节点，其特征在于，所述数据预取系统还包括存储节点，所述发送单元还用于：
    向所述存储节点发送数据更新消息，以将所述待写入数据更新至所述存储节点中数据写入地址对应的存储空间中；其中，所述数据更新消息携带有所述待写入数据。
  24. 根据权利要求17-23任一项所述的主节点，其特征在于，所述第一侦听响应消息为所述缓存节点2根据所述预取询问标识确定是否需要对所述待写入数据进行数据预取操作后发送的。
  25. 根据权利要求17-24任一项所述的主节点，其特征在于，所述数据预取系统为处理器，所述缓存节点以及所述主节点包括所述处理器中的高速缓存cache及其控制电路。
  26. 根据权利要求17-24任一项所述的主节点，其特征在于，所述数据预取系统为集群计算系统，且所述集群计算系统包括多台处理服务器和存储服务器，所述缓存节点包括所述处理服务器中的内存控制器以及内存，所述主节点包括存储服务器中的处理器以及内存。
  27. 一种缓存节点，其特征在于，所述缓存节点应用于数据预取系统，所述数据预取系统还包括主节点和其他多个缓存节点，所述缓存节点包括：
    接收单元，用于接收所述主节点发送的第一侦听消息，所述第一侦听消息携带有预取询问标识，所述预取询问标识用于指示所述缓存节点执行确定是否需要对待写入数据进行数据预取操作的步骤；所述待写入数据为缓存节点1将接收到的数据处理完后得到的数据，所述缓存节点1和所述其他多个所述缓存节点中的一个；
    确定单元，用于根据所述预取询问标识确定其是否需要对所述待写入数据进行数据预取操作；
    发送单元，用于向所述主节点发送第一侦听响应消息；所述第一侦听响应消息包括用于指示所述缓存节点是否需要对所述待写入数据进行数据预取操作的指示信息；
    所述接收单元，还用于若所述确定单元确定所述缓存节点需要对所述待写入数据进行数据预取操作且在向所述主节点发送所述第一侦听响应消息后，接收所述主节点发送的响应消息，所述响应消息携带有所述待写入数据。
  28. 根据权利要求27所述的缓存节点，其特征在于，所述数据预取系统还包括多个计算节点，所述多个计算节点与所述多个缓存节点一一对应；
    所述缓存节点1对应的计算节点用于对接收到的数据执行第一操作，所述缓存节点对应的计算节点用于对所述接收到的数据执行第二操作；所述接收到的数据在执行完所述第一操作后会大概率地执行所述第二操作。
  29. 根据权利要求27或28所述的缓存节点，其特征在于，所述确定单元具体用于：
    若所述缓存节点支持数据预取功能且需要所述待写入数据；则确定所述缓存节点需要对所述待写入数据进行数据预取操作；
    若所述缓存节点支持数据预取功能但不需要所述待写入数据，或者所述缓存节点不支持数据预取功能，则确定所述缓存节点不需要对所述待写入数据进行数据预取操作。
  30. 根据权利要求27-29任一项所述的缓存节点，其特征在于，所述指示信息为第一侦听响应消息中包括的第一预取结果标识，所述第一预取结果标识的不同值用于指示所述缓存节点是否需要对所述待写入数据进行数据预取操作；
    或者，
    所述指示信息为通过第一侦听响应消息中是否包括第二预取结果标识来表示所述缓存节点是否需要对所述待写入数据进行数据预取操作的信息。
  31. 根据权利要求27-30任一项所述的缓存节点，其特征在于，所述数据预取系统为处理器，所述缓存节点以及所述主节点包括所述处理器中的高速缓存cache及其控制电路。
  32. 根据权利要求27-30任一项所述的缓存节点，其特征在于，所述数据预取系统为集群计算系统，且所述集群计算系统包括多台处理服务器和存储服务器，所述缓存节点包括所述处理服务器中的内存控制器以及内存，所述主节点包括存储服务器中的处理器以及内存。
PCT/CN2019/102285 2018-08-24 2019-08-23 数据预取方法及装置 WO2020038466A1 (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN201980003468.7A CN111406251B (zh) 2018-08-24 2019-08-23 数据预取方法及装置
EP19852195.7A EP3835959A4 (en) 2018-08-24 2019-08-23 DATA PRE-EXTRACTION PROCESS AND DEVICE
US17/182,401 US11669453B2 (en) 2018-08-24 2021-02-23 Data prefetching method and apparatus

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
CN201810974252 2018-08-24
CN201810974252.2 2018-08-24
CN201910259338.1 2019-03-29
CN201910259338 2019-03-29

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US17/182,401 Continuation US11669453B2 (en) 2018-08-24 2021-02-23 Data prefetching method and apparatus

Publications (1)

Publication Number Publication Date
WO2020038466A1 true WO2020038466A1 (zh) 2020-02-27

Family

ID=69592878

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/102285 WO2020038466A1 (zh) 2018-08-24 2019-08-23 数据预取方法及装置

Country Status (4)

Country Link
US (1) US11669453B2 (zh)
EP (1) EP3835959A4 (zh)
CN (1) CN111406251B (zh)
WO (1) WO2020038466A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113342709B (zh) * 2021-06-04 2023-02-21 海光信息技术股份有限公司 在多处理器系统中访问数据的方法和多处理器系统
CN113852533B (zh) * 2021-09-27 2022-06-07 北京微纳星空科技有限公司 一种多通道数据通信系统、方法及电子设备
CN114153754B (zh) * 2022-02-08 2022-04-29 维塔科技(北京)有限公司 用于计算集群的数据传输方法、装置及存储介质

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1506849A (zh) * 2002-12-12 2004-06-23 国际商业机器公司 能够管理虚拟存储器处理方案的数据处理系统
CN1652091A (zh) * 2004-02-07 2005-08-10 华为技术有限公司 一种在数据存储系统中预取数据的方法
US6954767B1 (en) * 1999-03-31 2005-10-11 Fuji Photo Film Co., Ltd. Server and method for searching for image using image prefetch, designating database and storage devices for searching, and setting retrieval and processing parameters for search
CN101082861A (zh) * 2006-03-31 2007-12-05 英特尔公司 自适应预取

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5848254A (en) * 1996-07-01 1998-12-08 Sun Microsystems, Inc. Multiprocessing system using an access to a second memory space to initiate software controlled data prefetch into a first address space
US7124252B1 (en) * 2000-08-21 2006-10-17 Intel Corporation Method and apparatus for pipelining ordered input/output transactions to coherent memory in a distributed memory, cache coherent, multi-processor system
US6654857B2 (en) * 2001-06-21 2003-11-25 International Business Machines Corporation Non-uniform memory access (NUMA) computer system having distributed global coherency management
US6760817B2 (en) * 2001-06-21 2004-07-06 International Business Machines Corporation Method and system for prefetching utilizing memory initiated prefetch write operations
US7155572B2 (en) * 2003-01-27 2006-12-26 Advanced Micro Devices, Inc. Method and apparatus for injecting write data into a cache
US7360027B2 (en) * 2004-10-15 2008-04-15 Intel Corporation Method and apparatus for initiating CPU data prefetches by an external agent
US7395375B2 (en) * 2004-11-08 2008-07-01 International Business Machines Corporation Prefetch miss indicator for cache coherence directory misses on external caches
ES2723781T3 (es) * 2011-08-03 2019-09-02 Amadeus Sas Método y sistema para mantener consistencia fuerte de contenidos replicados distribuidos en un sistema de cliente/servidor
CN103635887B (zh) * 2013-09-23 2015-07-08 华为技术有限公司 缓存数据的方法和存储系统
US9710533B2 (en) * 2015-06-04 2017-07-18 Codership Oy Efficient buffer pool page pre-fetching for database clusters
US10389839B2 (en) * 2016-06-01 2019-08-20 Intel Corporation Method and apparatus for generating data prefetches specifying various sizes to prefetch data from a remote computing node
US10452551B2 (en) * 2016-12-12 2019-10-22 Intel Corporation Programmable memory prefetcher for prefetching multiple cache lines based on data in a prefetch engine control register
US11314648B2 (en) * 2017-02-08 2022-04-26 Arm Limited Data processing
US10802969B2 (en) * 2019-02-04 2020-10-13 Arm Limited Interconnect and method of operation of such an interconnect

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6954767B1 (en) * 1999-03-31 2005-10-11 Fuji Photo Film Co., Ltd. Server and method for searching for image using image prefetch, designating database and storage devices for searching, and setting retrieval and processing parameters for search
CN1506849A (zh) * 2002-12-12 2004-06-23 国际商业机器公司 能够管理虚拟存储器处理方案的数据处理系统
CN1652091A (zh) * 2004-02-07 2005-08-10 华为技术有限公司 一种在数据存储系统中预取数据的方法
CN101082861A (zh) * 2006-03-31 2007-12-05 英特尔公司 自适应预取

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3835959A4

Also Published As

Publication number Publication date
CN111406251B (zh) 2023-12-08
US20210224189A1 (en) 2021-07-22
EP3835959A4 (en) 2021-11-10
EP3835959A1 (en) 2021-06-16
US11669453B2 (en) 2023-06-06
CN111406251A (zh) 2020-07-10

Similar Documents

Publication Publication Date Title
TWI416322B (zh) 最佳化以目錄為基礎的一致性協定中之同時存取
CN109313644B (zh) 数据库代理所用的系统和方法
US9235529B2 (en) Using broadcast-based TLB sharing to reduce address-translation latency in a shared-memory system with optical interconnect
US11669453B2 (en) Data prefetching method and apparatus
US9009446B2 (en) Using broadcast-based TLB sharing to reduce address-translation latency in a shared-memory system with electrical interconnect
US7788452B2 (en) Method and apparatus for tracking cached addresses for maintaining cache coherency in a computer system having multiple caches
US20060143406A1 (en) Predictive early write-back of owned cache blocks in a shared memory computer system
JP2000112910A (ja) 非一様メモリ・アクセス・コンピュ―タ・システム及びその操作方法
CN114153754B (zh) 用于计算集群的数据传输方法、装置及存储介质
KR102581572B1 (ko) 허브 디바이스 및 그의 작동방법
US8635411B2 (en) Data processing apparatus and method for managing coherency of cached data
US11483260B2 (en) Data processing network with flow compaction for streaming data transfer
WO2021213209A1 (zh) 数据处理方法及装置、异构系统
US8510513B2 (en) Network load reducing method and node structure for multiprocessor system with distributed memory
US10255184B2 (en) Memory access architecture with coherence
US10917198B2 (en) Transfer protocol in a data processing network
US10503648B2 (en) Cache to cache data transfer acceleration techniques
WO2018077123A1 (zh) 内存访问方法及多处理器系统
US8732351B1 (en) System and method for packet splitting
US11874783B2 (en) Coherent block read fulfillment
US11947418B2 (en) Remote access array
KR20110070772A (ko) 분산 메모리를 가지는 다중 프로세서 시스템을 위한 네트워크 부하 감소 방법 및 노드의 구조
JP2017146786A (ja) 演算処理装置、制御装置、情報処理装置及び情報処理装置の制御方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19852195

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

ENP Entry into the national phase

Ref document number: 2019852195

Country of ref document: EP

Effective date: 20210311