WO2020035975A1 - Numerical control device - Google Patents

Numerical control device Download PDF

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Publication number
WO2020035975A1
WO2020035975A1 PCT/JP2019/016864 JP2019016864W WO2020035975A1 WO 2020035975 A1 WO2020035975 A1 WO 2020035975A1 JP 2019016864 W JP2019016864 W JP 2019016864W WO 2020035975 A1 WO2020035975 A1 WO 2020035975A1
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WIPO (PCT)
Prior art keywords
processing
sub
pattern
core processor
processes
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PCT/JP2019/016864
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French (fr)
Japanese (ja)
Inventor
健二 西脇
剛志 津田
Original Assignee
三菱電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to DE112019004142.8T priority Critical patent/DE112019004142T5/en
Priority to CN201980053039.0A priority patent/CN112567304B/en
Priority to JP2020537368A priority patent/JP6877649B2/en
Publication of WO2020035975A1 publication Critical patent/WO2020035975A1/en

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/18—Numerical control [NC], i.e. automatically operating machines, in particular machine tools, e.g. in a manufacturing environment, so as to execute positioning, movement or co-ordinated operations by means of programme data in numerical form
    • G05B19/4155—Numerical control [NC], i.e. automatically operating machines, in particular machine tools, e.g. in a manufacturing environment, so as to execute positioning, movement or co-ordinated operations by means of programme data in numerical form characterised by programme execution, i.e. part programme or machine function execution, e.g. selection of a programme
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5061—Partitioning or combining of resources
    • G06F9/5066—Algorithms for mapping a plurality of inter-dependent sub-tasks onto a plurality of physical CPUs
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/30—Nc systems
    • G05B2219/35—Nc in input of data, input till input file format
    • G05B2219/35382—Distribution

Definitions

  • the present invention relates to a numerical control device for controlling a machine tool.
  • the numerical control device that controls the machine tool reads the machining program, calculates the command position per unit time on the tool path based on the machining program, and accelerates / decelerates the machine tool to operate smoothly.
  • the processing and the axis control processing for instructing the motor of each axis of the machine tool are executed.
  • the numerical controller performs HMI processing for displaying information for operating the numerical controller and displaying operation results, I / O control processing for controlling input / output signals, and processing for network communication and bus communication. Execute communication processing.
  • HMI is an abbreviation for “Human ⁇ Machine ⁇ Interface”.
  • I / O is an abbreviation for “Input / Output”.
  • a numerical control device having a plurality of core processors has been proposed (for example, see Patent Document 1).
  • a conventional numerical controller divides a process to be executed into a plurality of sub-processes, and distributes the plurality of sub-processes to allocate to a plurality of core processors. As a result, the conventional numerical control device executes the increasing process within a predetermined time.
  • the processing performed by the numerical controller can be divided into a plurality of sub-processings
  • the plurality of sub-processings may include a plurality of sub-processings in which the order of execution is not permitted.
  • a certain process can be divided into a sub-process A, a sub-process B and a sub-process C.
  • the sub-process B is a process using the result of the sub-process A
  • the sub-process C is a process using the result of the sub-process B. It may be a process to be used.
  • sub-process A, sub-process B, and sub-process C must be executed in the order of sub-process A, sub-process B, and sub-process C.
  • sub-process A is allocated to the first core processor
  • sub-process B is allocated to the second core processor
  • sub-process C is allocated to the third core processor.
  • the sub-process A, the sub-process B, and the sub-process C must be executed in the order of the sub-process A, the sub-process B, and the sub-process C. C cannot be executed in parallel.
  • the present invention has been made in view of the above, and when a process to be executed is divided into a plurality of sub-processes, a plurality of sub-processes which are not allowed to change the order of execution among the plurality of sub-processes It is an object of the present invention to obtain a numerical controller that executes the above processing without changing the order of execution, and executes the above processing in a processing time shorter than the processing time when one core processor executes the above processing. .
  • the present invention is a numerical controller that controls a machine tool, and includes a multi-core processor including a plurality of core processors, and a pattern determination unit.
  • the pattern determination unit may include: resource information including information indicating the number of core processors included in the multi-core processor; machine configuration information on hardware configuring the machine tool; and software executed by the multi-core processor.
  • the processing time when the multi-core processor executes the processing is the plurality of core processors And selecting a processing pattern that is shorter than the processing time when one of the core processors executes the processing, and determines the selected processing pattern as a processing pattern when the plurality of core processors execute the processing.
  • the present invention further includes an assignment unit that distributes a plurality of sub-processes constituting the process and allocates the sub-processes to the plurality of core processors according to the processing pattern determined by the pattern determination unit.
  • Each of the plurality of processing patterns is a processing pattern for executing a plurality of sub-processes of the plurality of sub-processes, the order of execution of which is not allowed to be changed, without changing the order of execution.
  • the core processor can execute the above processing in a processing time shorter than the processing time when one core processor executes the above processing.
  • FIG. 1 shows a configuration of a numerical control device according to a first embodiment.
  • FIG. 4 is a diagram illustrating processing executed by the numerical control device according to the first embodiment;
  • FIG. 4 is a diagram for explaining an operation when the numerical controller according to the first embodiment assigns sub-processes to a plurality of core processors The figure which shows the example at the time of performing a machining program analysis process beyond a predetermined cycle time when one core processor performs a several sub process.
  • FIG. 9 is a diagram illustrating an example of a case where an interpolation process is performed beyond a predetermined cycle time when one core processor performs a plurality of sub-processes;
  • FIG. 4 is a diagram illustrating processing executed by the numerical control device according to the first embodiment
  • FIG. 4 is a diagram for explaining an operation when the numerical controller according to the first embodiment assigns sub-processes to a plurality of core processors
  • the figure which shows the example at the time of performing a machining program analysis process beyond a predetermined
  • FIG. 6 is a diagram showing a first example of a processing pattern in which processing is distributed and assigned to a plurality of core processors to execute processing in the numerical control device according to the first embodiment
  • FIG. 9 is a diagram illustrating a second example of a processing pattern in which processing is distributed and assigned to a plurality of core processors to execute processing in the numerical control device according to the first embodiment
  • FIG. 9 is a diagram showing a third example of a processing pattern in which processing is distributed in the numerical control device according to the first embodiment and the processing is executed by being allocated to a plurality of core processors
  • FIG. 4 is a diagram illustrating processing times and execution cycles of a plurality of sub-processes executed by the numerical control device according to the first embodiment
  • 5 is a flowchart showing an example of the procedure of the operation of the pattern determining unit of the numerical control device according to the first embodiment
  • FIG. 3 is a diagram illustrating a configuration of a numerical control device according to a second embodiment.
  • FIG. 9 is a diagram showing a first example of a processing pattern in which processing is executed in the numerical control device according to the second embodiment and another numerical control device.
  • FIG. 9 is a diagram showing a second example of a processing pattern in which processing is performed in the numerical control device according to the second embodiment and another numerical control device.
  • FIG. 3 is a diagram showing a configuration of a numerical control device according to a third embodiment.
  • FIG. 14 is a diagram illustrating a second example of the processing pattern when the number of core processors included in the multi-core processor included in the numerical control device according to the third embodiment is smaller than the number of axes of the control target;
  • the figure showing the 3rd example of the processing pattern when the number of core processors included in the multi-core processor which the numerical control device concerning a 3rd embodiment has is smaller than the number of axes of a control subject.
  • FIG. 2 is a diagram illustrating a processor in a case where some or all of the functions of a pattern determination unit and an assignment unit included in the numerical control device according to the first embodiment are implemented by the processor;
  • FIG. 3 is a diagram illustrating a processing circuit when a part or all of a pattern determining unit and an allocating unit included in the numerical control device according to the first embodiment are realized by the processing circuit;
  • FIG. 1 is a diagram illustrating a configuration of a numerical control device 1 according to the first embodiment.
  • the numerical control device 1 is a device for controlling a machine tool, and has a multi-core processor 2.
  • the multi-core processor 2 includes a first core processor 21, a second core processor 22, a third core processor 23, and a fourth core processor 24.
  • the first core processor 21, the second core processor 22, the third core processor 23, and the fourth core processor 24 are examples of a plurality of core processors.
  • the numerical control device 1 further includes a storage unit 3.
  • An example of the storage unit 3 is a semiconductor memory.
  • a part of the storage unit 3 is a nonvolatile memory.
  • the storage unit 3 stores resource information including information indicating the number of core processors included in the multi-core processor 2.
  • the storage unit 3 further stores machine configuration information relating to hardware configuring the machine tool.
  • the storage unit 3 further stores software configuration information indicating the configuration of the software when the process executed by the multi-core processor 2 is executed using software.
  • the software configuration information is information indicating a plurality of processing blocks executed inside the numerical controller 1 and the execution cycle and execution time of each of the plurality of processing blocks.
  • the processing block is a processing function.
  • the storage unit 3 further stores processing pattern information indicating a plurality of processing patterns.
  • Each of the plurality of processing patterns is a processing pattern for performing, without changing the order of execution, a plurality of sub-processes of the plurality of sub-processes constituting the above-mentioned process, the change of the order of execution of which is not permitted. .
  • the numerical control device 1 determines, based on the resource information, the machine configuration information, and the software configuration information, a processing time when the multi-core processor 2 executes the above processing from among a plurality of processing patterns indicated by the processing pattern information. It further includes a pattern determination unit 4 that selects a processing pattern that is shorter than a processing time when one of the plurality of core processors executes the above processing. The pattern determination unit 4 determines the selected processing pattern as a processing pattern when a plurality of core processors execute the above processing.
  • the resource information, the machine configuration information, the software configuration information, and the processing pattern information are information stored in the storage unit 3.
  • the pattern determination unit 4 performs processing that minimizes the processing time when the multi-core processor 2 executes the above processing from among a plurality of processing patterns.
  • a pattern is selected, and the selected processing pattern is determined as a processing pattern when a plurality of core processors execute the above processing.
  • the pattern determination unit 4 measures in advance the processing time of each of the plurality of sub-processes, and uses the measured processing time to execute the above-described processing from the multi-core processor 2 among the plurality of processing patterns. Then, the processing pattern that minimizes the processing time is selected, and the selected processing pattern is determined as the processing pattern when the plurality of core processors execute the above processing.
  • the numerical control device 1 further includes an assignment unit 5 that distributes a plurality of sub-processes constituting the above process and allocates the sub-processes to a plurality of core processors according to the processing pattern determined by the pattern determination unit 4.
  • Each of the first core processor 21, the second core processor 22, the third core processor 23, and the fourth core processor 24 executes the sub-process assigned by the assigning unit 5.
  • the numerical control device 1 is connected to the motor control amplifier 11.
  • the motor control amplifier 11 is connected to the plurality of motors 12 and controls each of the plurality of motors 12.
  • Each of the plurality of motors 12 is a part of a machine tool.
  • FIG. 1 shows only one motor 12 for the sake of simplicity.
  • Each of the plurality of motors 12 rotates the axis of the control target. That is, the motor control amplifier 11 controls the rotation of each axis of the plurality of control objects.
  • the numerical controller 1 is also connected to a display 13 having a function of displaying the result of the calculation executed by the numerical controller 1.
  • the display 13 may have a data input device.
  • the data input device may have a keyboard.
  • the numerical controller 1 receives one or both of the digital input information and the analog input information from the machine tool, and transmits the one or both of the digital output information and the analog output information to the machine tool. Is also connected.
  • the “input / output device 14” may be described as the “I / O device 14”.
  • the “input / output device 14” is described as the “I / O device 14”.
  • the numerical controller 1 is also connected to a network device 15 that connects the numerical controller 1 to a communication network.
  • FIG. 2 is a diagram illustrating a process executed by the numerical controller 1 according to the first embodiment.
  • FIG. 2 also shows a motor control amplifier 11, a display 13, an I / O device 14, and a network device 15.
  • the numerical control device 1 reads the machining program 31 and executes a machining program reading process 32 for reading a G code described in the machining program 31.
  • the machining program 31 includes a plurality of command statements.
  • the numerical control device 1 may read a command sentence for each line, or may read command sentences for a plurality of lines at a time.
  • the numerical controller 1 executes a machining program analysis process 33 for analyzing the read machining program 31.
  • the machining program 31 includes a function code including a movement command called a G code and a synchronization command between systems.
  • the machining program 31 also describes, for example, coordinate positions for determining the tip position of the tool.
  • the numerical control device 1 calculates a coordinate position to finally instruct the motor 12 based on the movement command, the synchronization command, and the coordinate position of the tool in the machining program analysis processing 33.
  • the numerical control device 1 specifies the read coordinate position in the machining program analysis process 33 for the designated tool. Calculate the correction position moved by the diameter correction of the tool with the number. In the machining program analysis processing 33, the numerical control device 1 performs coordinate conversion on the tip position of the tool, which is the correction position, and calculates the control position of the motor 12. The numerical controller 1 calculates a control position for each of the plurality of motors 12.
  • the numerical controller 1 executes an interpolation process 34 for calculating an interpolation position by adding a movement amount corresponding to the feed speed at regular intervals to the control position of the motor 12 calculated in the machining program analysis process 33. I do.
  • the interpolation processing 34 in the interpolation processing 34, in addition to calculating the interpolation position, when performing the processing of multiple systems, the numerical controller 1 executes the synchronization processing for one system and another system.
  • the synchronization process is a waiting process that checks the status of another system and determines whether the next interpolation process may be performed for one system.
  • the synchronous processing indicates the movement amount of the axis of the other system when the movement amount commanded in the machining program 31 is obtained by adding the movement amount of the axis of one system and the movement amount of the axis of the other system. This is a process of acquiring information, determining the movement amount of one system axis, and calculating an interpolation position.
  • the numerical control device 1 executes, for example, a moving average filter process or a process for making the acceleration constant with respect to the interpolation position obtained in the interpolation process 34 so that the speed of the control object becomes smooth.
  • An acceleration / deceleration process 35 for calculating a command position for the motor 12 is executed.
  • the numerical controller 1 executes an axis control process 36 for setting the command position to the motor 12 calculated in the acceleration / deceleration process 35 to a command to the motor 12.
  • the motor control amplifier 11 controls the motor 12 based on a command. For example, the motor control amplifier 11 controls a current value flowing through the motor 12.
  • the numerical controller 1 also executes an HMI process 37 for displaying data inside the numerical controller 1 on the display 13.
  • the data includes data obtained by a calculation performed inside the numerical controller 1.
  • the HMI process 37 includes a process for receiving an input from a user. In the HMI process 37, the responsiveness to the user increases as soon as the process is executed.
  • the numerical controller 1 also executes an I / O control process 38 including output of data to the machine tool and ladder processing for receiving a signal from the machine tool.
  • the numerical controller 1 executes the I / O control processing 38 via the I / O device 14.
  • the numerical controller 1 also executes a communication process 39 for transmitting and receiving data to and from an object outside the numerical controller 1 via the network device 15. Machines outside the numerical control device 1 do not include machine tools.
  • the processing program reading processing 32, the processing program analysis processing 33, the interpolation processing 34, the acceleration / deceleration processing 35, the axis control processing 36, the HMI processing 37, the I / O control processing 38, and the communication processing 39 are processing executed by the multi-core processor 2. It is.
  • Each of the machining program reading process 32, the machining program analysis process 33, the interpolation process 34, the acceleration / deceleration process 35, the axis control process 36, the HMI process 37, the I / O control process 38, and the communication process 39 is an example of a sub process. .
  • FIG. 3 is a diagram for explaining an operation when the numerical controller 1 according to the first embodiment assigns sub-processes to a plurality of core processors.
  • one example of the sub-process is one of the plurality of processes described with reference to FIG.
  • the storage unit 3 stores processing pattern information 41 indicating a processing pattern for specifying how to divide the processing executed by the multi-core processor 2 and when to execute each sub-processing.
  • the processing pattern information 41 indicates a plurality of processing patterns. Processing pattern information 41 indicating a plurality of processing patterns is prepared in advance.
  • the storage unit 3 further stores resource information 42 including information indicating the number of core processors constituting the multi-core processor 2 included in the numerical controller 1.
  • the resource information 42 includes information indicating the number of usable arithmetic devices included in other numerical control devices or calculation devices connected to the numerical control device 1 via a communication network or a communication bus. You may.
  • An example of an arithmetic device is a processor.
  • the storage unit 3 further stores machine configuration information 43 relating to hardware constituting the machine tool.
  • the machine configuration information 43 includes information indicating the number of axes included in the machine tool, information indicating the number of systems, information indicating a machine type, and I / O connected to the numerical controller 1. Part or all of the information indicating the number of devices is included.
  • the information indicating the machine type is, for example, information indicating that the machine tool is a lathe or a machining center.
  • the storage unit 3 further stores software configuration information 44 indicating the configuration of the software when the processing executed by the multi-core processor 2 is executed using software.
  • the software configuration information 44 is information indicating a plurality of processing blocks executed inside the numerical control device 1 and an execution cycle and an execution time of each of the plurality of processing blocks.
  • the processing block is a processing function.
  • the pattern determination unit 4 determines, based on the resource information 42, the machine configuration information 43, and the software configuration information 44, a processing time when the multi-core processor 2 executes a process from a plurality of processing patterns indicated by the processing pattern information 41. Determines a processing pattern that is shorter than the processing time when one of the plurality of core processors executes the above processing. For example, based on the resource information 42, the machine configuration information 43, and the software configuration information 44, the pattern determination unit 4 determines the shortest processing time when the multi-core processor 2 executes the above processing from among a plurality of processing patterns. Is selected, and the selected processing pattern is determined as a processing pattern when a plurality of core processors execute the above processing.
  • the allocating unit 5 distributes a plurality of sub-processes in accordance with the processing pattern determined by the pattern determining unit 4, and allocates the first core processor 21, the second core processor 22, and the third core processor of the multi-core processor 2. Assigned to the processor 23 and the fourth core processor 24.
  • the first embodiment there is one command system in a machining program, and a case where a machining program described with a relatively short line segment length is executed, and a multi-axis multi-system control in which there are two or more command systems in a machining program.
  • a processing pattern is determined and a plurality of sub-processes are distributed and assigned to each of a plurality of core processors will be described.
  • FIG. 4 is a diagram showing an example of a case where a single core processor executes a plurality of sub-processes and executes a machining program analysis process over a predetermined period of time.
  • FIG. 4 shows an example of processing when a command to create a free-form surface is given in a machining program in which the number of axes to be controlled and the number of systems are relatively small, but are described with relatively short line segment lengths.
  • processing program reading processing and processing program analysis processing, which must be performed in real time, exceeds a predetermined cycle time. Processing that must be performed in real time is processing that must be completed within a certain processing time.
  • FIG. 5 is a diagram illustrating an example of a case where one core processor executes a plurality of sub-processes and performs an interpolation process beyond a predetermined cycle time.
  • FIG. 5 is a diagram illustrating an example in which the number of axes to be controlled and the number of systems are relatively large, but the machining program reading process and the machining program analysis process do not need to be completed within a certain processing time.
  • FIG. 5 shows that, for example, when the numerical controller 1 controls 16 axes by four systems, the total time of the axis control processing, acceleration / deceleration processing, and interpolation processing that must be performed in real time exceeds a predetermined cycle time. Is shown.
  • the predetermined cycle time is extended to reduce the demand for control responsiveness.
  • FIG. 6 is a diagram illustrating a first example of a processing pattern in which processing is distributed in the numerical control device 1 according to the first embodiment and the processing is executed by being allocated to a plurality of core processors.
  • FIG. 6 shows one of the plurality of processing patterns.
  • a plurality of processes for the axis to be controlled and a plurality of processes for the system are divided.
  • the plurality of sub-processes are distributed, and each of the plurality of sub-processes is assigned to one of the plurality of core processors.
  • system process a plurality of sub-processes for a system may be described as “system process”.
  • the first core processor executes the common processing of the axis control processing and executes the axis control processing for each axis from the first axis to the fourth axis. It indicates that In the processing pattern shown in FIG. 6, the second core processor executes the axis control processing for each axis from the fifth axis to the eighth axis, and the third core processor executes the axis control processing for each axis from the ninth axis to the twelfth axis. It is further shown that the fourth core processor executes the axis control processing of each axis from the thirteenth axis to the sixteenth axis.
  • the number of axes assigned to each core processor is the same. However, based on the control processing time for each of the plurality of axes, the number of axes allocated to the core processors may be different for each core processor so that the processing time in each core processor is equal.
  • the processing pattern shown in FIG. 6 further indicates that the first core processor executes the common processing of the system processing and also executes the processing of the first system.
  • the second core processor executes the processing for the second system
  • the third core processor executes the processing for the third system
  • the fourth core processor executes the processing for the fourth system. It further illustrates performing.
  • the number of systems assigned to each core processor is the same. However, when the numerical controller 1 executes the processing of four or more systems, based on the processing time of each of the plurality of systems, the number of systems assigned to the core processors is equalized so that the processing time in each core processor is equal. The number may be different for each core processor.
  • FIG. 7 is a diagram illustrating a second example of a processing pattern in which the processing is distributed in the numerical control device 1 according to the first embodiment and the processing is executed by being allocated to a plurality of core processors.
  • FIG. 7 also shows one of the plurality of processing patterns.
  • the processing pattern shown in FIG. 7 indicates that the first core processor executes common processing of the axis control processing and executes processing for each axis from the first axis to the eighth axis. I have.
  • the processing pattern shown in FIG. 7 further indicates that the first core processor executes the system processing for the first system and executes the system processing for the second system.
  • the processing pattern shown in FIG. 7 indicates that the second core processor executes processing for each axis from the ninth axis to the sixteenth axis, executes system processing for the third system, and executes processing for the fourth system. Executing the system processing for The processing pattern shown in FIG. 7 further indicates that the third core processor executes the I / O control processing, the HMI processing, and the communication processing. The I / O control processing, the HMI processing, and the communication processing need not be executed in real time. The processing pattern shown in FIG. 7 further indicates that the fourth core processor executes another task process and another function process. The different task process and the different function process are sub-processes not shown in FIG.
  • the processing pattern shown in FIG. 7 allocates half of the resources to axis processing and system processing.
  • Resource means a plurality of core processors. However, the number of core processors allocated to axis processing and system processing may be changed. Processing patterns are prepared corresponding to the number of core processors to which axis processing and system processing are assigned.
  • FIG. 8 is a diagram illustrating a third example of a processing pattern in which processing is distributed in the numerical control device 1 according to the first embodiment, and the processing is executed by being allocated to a plurality of core processors.
  • FIG. 8 also shows one of the plurality of processing patterns.
  • the processing pattern shown in FIG. 8 is a processing pattern in which sub-processing of one task is assigned to one core processor and executed.
  • the processing pattern shown in FIG. 8 indicates that the first core processor executes the axis control process and the acceleration / deceleration process, and the second core processor executes the interpolation process.
  • the processing pattern shown in FIG. 8 further indicates that the third core processor executes the processing program reading processing and the processing program analysis processing, and the fourth core processor executes the I / O control processing, the HMI processing, and the communication processing. ing.
  • the number of core processors to which sub-processes that need to be executed in real time such as the axis control process, the acceleration / deceleration process, and the interpolation process, may be changed.
  • the processing pattern is prepared corresponding to the number of core processors to which sub-processes that need to be executed in real time are allocated.
  • the processing pattern shown in FIG. 8 is a processing pattern in which a plurality of sub-processes that can be calculated independently are executed in parallel. Furthermore, the processing pattern shown in FIG. 8 is a processing pattern in which the execution order of the sub-processing of each task does not change in one cycle.
  • the pattern determination unit 4 selects one processing pattern for distributing the processing load from a plurality of processing patterns.
  • the pattern determining unit 4 determines a processing pattern that specifies a sub-process executed by each of the plurality of core processors. Specifically, based on the number of core processors included in the multi-core processor 2 included in the resource information, the pattern determination unit 4 causes the number of core processors to execute sub-processing from a plurality of processing patterns. Select multiple processing patterns.
  • the pattern determining unit 4 selects a processing pattern in which four core processors will execute processing. When the number of core processors is 8, the pattern determination unit 4 selects a processing pattern in which the eight core processors execute processing.
  • FIG. 9 is a diagram showing the processing time and execution cycle of each of a plurality of sub-processes executed by the numerical controller 1 according to the first embodiment.
  • the processing time is measured in advance for each processing function and processing task indicating the content of the sub-processing.
  • FIG. 9 shows a common processing time t1 that is a time required for common processing and a processing time t2 per unit processing.
  • An example of the processing time t2 per unit processing is the processing time per axis or per system.
  • the processing time t2 is the processing time for reading one processing program.
  • the processing time t2 is the processing time when analyzing one machining program.
  • FIG. 9 also shows the processing time and execution cycle for the sub-process A, the sub-process B, and the sub-process C not shown in FIG. The execution cycle in FIG. 9 is indicated by a multiple of the unit cycle.
  • the overhead time when the multi-core processor executes processing is time t3.
  • the processing time t_k depending on the number of systems is expressed by the following equation (1), and depends on the number of axes.
  • the processing time t_j is expressed by the following equation (2).
  • t_k t1_k + t2_k ⁇ n + t3_k
  • t_j t1_j + t2_j ⁇ m + t3_j (2)
  • the suffix _k represents time dependent on the number of systems
  • the suffix _j represents time dependent on the number of axes.
  • the processing time of each processing function and processing task may be measured in advance by a numerical control device different from the numerical control device 1.
  • the processing time of each processing function and processing task has a software configuration in which the numerical controller 1 has a measuring means for measuring the processing time, and the measuring means measures the processing time of each processing when the numerical controller 1 starts up.
  • the information may include a processing time table.
  • the pattern determining unit 4 may have a function of a measuring unit.
  • FIG. 10 is a flowchart illustrating an example of an operation procedure of the pattern determining unit 4 included in the numerical controller 1 according to the first embodiment.
  • the pattern determination unit 4 acquires information indicating the number of core processors constituting the multi-core processor 2 from the resource information.
  • the pattern determining unit 4 extracts processing patterns corresponding to the number indicated by the information acquired in step S1. Examples of the extracted processing patterns are the processing patterns shown in FIGS.
  • step S3 the pattern determination unit 4 calculates the processing time of each task for one of the processing patterns extracted in step S2 based on the machine configuration information and the software configuration information, and determines the execution period in the processing pattern. The processing time is calculated.
  • step S4 the pattern determination unit 4 determines whether or not the processing times of all the processing patterns extracted in step S2 have been calculated. If the pattern determination unit 4 determines that the processing times of all the extracted processing patterns have not been calculated (No in step S4), the pattern determination unit 4 performs the operation of step S3.
  • step S4 If the pattern determination unit 4 determines that the processing times of all the extracted processing patterns have been calculated (Yes in step S4), the multi-core processor 2 executes the processing from among the extracted processing patterns in step S5. A processing pattern in which the processing time when performing the above processing is shorter than the processing time when one of the plurality of core processors executes the above processing is selected. In step S5, the pattern determination unit 4 determines a processing pattern to be executed by the multi-core processor 2 by making a selection.
  • the pattern determination unit 4 sets the predetermined cycle to two cycles To calculate the processing time required for the execution cycle.
  • the processing pattern shown in FIG. 6 since the number of axis control processing and interpolation processing is smaller than the number of core processors, even when the processing is distributed, idle time occurs in which the core processor does not perform processing.
  • the idle time is shorter than in the processing pattern shown in FIG. 6, and the processing time is shorter than the processing time in the processing pattern shown in FIG.
  • the processing time balance of the axis control processing, the acceleration / deceleration processing, the interpolation processing, the processing program reading processing, and the processing program analysis processing is better than the processing time balance in the processing patterns shown in FIGS. Also, the processing time is relatively short.
  • the pattern determination unit 4 selects the processing pattern shown in FIG. 8 having the shortest processing time among the three processing patterns shown in FIGS.
  • the allocating unit 5 allocates the axis control processing and the acceleration / deceleration processing to the first core processor and allocates the interpolation processing to the second core processor based on the processing pattern determined by the pattern determining unit 4.
  • the allocating unit 5 allocates the processing program reading processing and the processing program analysis processing to the third core processor, and allocates the I / O control processing, the HMI processing, and the communication processing to the fourth core processor.
  • the pattern determination unit 4 sets the execution cycle to two predetermined cycles. Calculate the processing time required for.
  • four-axis control processing can be assigned to each core processor, and one system of interpolation processing can be assigned to each core processor. Therefore, the processing pattern shown in FIG. 6 can make the processing time relatively short.
  • the number of core processors that need to execute processing in real time is two. For this reason, in the processing pattern shown in FIG. 6, the axis control processing and the interpolation processing which were executed by the four core processors are performed. In the processing pattern shown in FIG. 7, the processing is executed by the two core processors.
  • the processing time in the processing pattern shown in FIG. 7 is longer than the processing time in the processing pattern shown in FIG.
  • the processing pattern shown in FIG. 8 is a pattern in which the axis control processing and the interpolation processing, which are increased in proportion to the number of systems and the number of axes, are assigned to the first core processor and the second core processor.
  • the processing time is longer than the processing time in the processing pattern shown in FIG. 6 and shorter than the processing time in the processing pattern shown in FIG.
  • the pattern determination unit 4 selects the processing pattern shown in FIG. 6 which has the shortest processing time among the three processing patterns shown in FIGS.
  • the allocating unit 5 allocates the common processing and the processing of the first axis and the first system to the first core processor based on the processing pattern selected by the pattern determining unit 4.
  • the allocating unit 5 allocates the second axis and the second system to the second core processor, allocates the third axis and the third system to the third core processor, and allocates the fourth axis and the fourth system to the second core processor. Assign to a 4-core processor.
  • the numerical control device 1 is executed by the multi-core processor 2 from a plurality of processing patterns indicated by the processing pattern information based on the resource information, the machine configuration information, and the software configuration information.
  • a processing pattern in which the processing time is shorter than the processing time when one of the plurality of core processors executes the above processing is selected.
  • the numerical controller 1 determines the selected processing pattern as a processing pattern when a plurality of core processors execute the above processing.
  • the numerical controller 1 selects a processing pattern that minimizes the processing time of the multi-core processor 2 from a plurality of processing patterns based on the resource information, the machine configuration information, and the software configuration information.
  • the numerical controller 1 determines the selected processing pattern as a processing pattern when a plurality of core processors execute the above processing.
  • the numerical controller 1 distributes a plurality of sub-processes constituting the above process and allocates them to a plurality of core processors according to the determined process pattern.
  • Each of the plurality of processing patterns is a processing pattern for performing, without changing the order, a plurality of sub-processes of the plurality of sub-processes constituting the above-described process, the order of which is not allowed to be changed.
  • the numerical controller 1 changes the order of the plurality of sub-processes in which the change of the execution order among the plurality of sub-processes is not permitted. Can be performed without any
  • the numerical controller 1 can execute the above processing in a processing time shorter than the processing time when one core processor executes the above processing.
  • FIG. 11 is a diagram illustrating a configuration of a numerical controller 1A according to the second embodiment.
  • the numerical control device 1A includes a multi-core processor 2A including a first core processor 21, a second core processor 22, and a third core processor 23, a storage unit 3A, and a pattern determination unit 4.
  • Each of the first core processor 21, the second core processor 22, the third core processor 23, and the pattern determining unit 4 is a component described in the first embodiment.
  • the storage unit 3A stores processing pattern information, resource information, machine configuration information, and software configuration information, similarly to the storage unit 3 of the first embodiment.
  • the numerical control device 1A is connected to another numerical control device 1B via the communication network 16.
  • the other numerical controller 1B is the same device as the numerical controller 1A.
  • the numerical control device 1A further includes an allocating unit 5A that allocates a part of the plurality of sub-processes to another numerical control device 1B and allocates the rest of the plurality of sub-processes to the numerical control device 1A.
  • the allocating unit 5A causes the other numerical control device 1B to execute the part while the multicore processor 2A of the numerical control device 1A executes the remaining portion.
  • the other numerical control device 1B does not include the pattern determination unit 4 and the assignment unit 5A.
  • the number of command systems of the machining program is two or more, the number of control axes is 32, and the multi-axis multi-system control in which the number of control systems is eight is performed.
  • the numerical controller 1A selects one processing pattern and distributes the processing to a plurality of core processors constituting the multi-core processor 2A and another numerical controller 1B. explain.
  • FIG. 12 is a diagram illustrating a first example of a processing pattern in which processing is performed in the numerical controller 1A according to the second embodiment and another numerical controller 1B.
  • the processing pattern shown in FIG. 12 is such that the first core processor of the numerical controller 1A performs I / O control processing, axis control processing for each axis from the first axis to the 16th axis, and 16th to 16th axes. This shows that the acceleration and deceleration processing for each axis up to the axis is executed.
  • the processing pattern shown in FIG. 12 further indicates that the second core processor of the numerical controller 1A executes the HMI processing and the interpolation processing for each of 1 to 4 systems.
  • the processing pattern shown in FIG. 12 further indicates that the third core processor of the numerical controller 1A executes the communication processing, the processing program reading processing, and the processing program analysis processing.
  • the processing pattern shown in FIG. 12 is such that the first core processor of the other numerical controller 1B performs I / O control processing, axis control processing for each of the 17th to 32nd axes, and It also shows that the acceleration and deceleration processing for each axis up to the 32nd axis is executed.
  • the processing pattern shown in FIG. 12 further indicates that the second core processor of the other numerical controller 1B executes the HMI processing and the interpolation processing for each of the five to eight systems.
  • the processing pattern shown in FIG. 12 further indicates that the third core processor of the other numerical control device 1B executes a communication process, a machining program reading process, and a machining program analysis process.
  • the number of axes and the number of systems of processing executed in the numerical controller 1A are the same as the number of axes and the number of systems of processing executed in the other numerical controllers 1B.
  • the number of axes and the number of systems of processing executed in the numerical controller 1A may be different from the number of axes and the number of systems of processing executed in another numerical controller 1B.
  • a processing pattern is prepared in which the numerical control device 1A performs interpolation processing of one system and two systems having a relatively large processing load, and performs interpolation processing of three to eight systems in another numerical control device 1B. Is also good. Similarly, a processing pattern in which the number of axes for processing executed in the numerical controller 1A and the number of axes for processing executed in the other numerical controllers 1B are different may be prepared.
  • FIG. 13 is a diagram illustrating a second example of a processing pattern in which the numerical controller 1A according to the second embodiment and the other numerical controller 1B perform processing.
  • the processing pattern shown in FIG. 13 indicates that the first core processor of the numerical control device 1A executes the I / O control processing and the interpolation processing.
  • the processing pattern shown in FIG. 13 further indicates that the second core processor of the numerical controller 1A executes the HMI processing and the interpolation processing.
  • the processing pattern shown in FIG. 13 further indicates that the third core processor of the numerical controller 1A executes communication processing, processing program reading processing, and processing program analysis processing.
  • the processing pattern shown in FIG. 13 further indicates that the first core processor of the other numerical controller 1B executes the I / O control processing, the axis control processing, and the acceleration / deceleration processing.
  • the processing pattern shown in FIG. 13 further indicates that the second core processor of the other numerical control device 1B executes the HMI processing, the axis control processing, and the acceleration / deceleration processing.
  • the processing pattern shown in FIG. 13 further indicates that the third core processor of the other numerical controller 1B executes the communication processing, the axis control processing, and the acceleration / deceleration processing.
  • the machining program reading process and the machining program analysis process may not be executed by the numerical controller 1A, but may be executed by another numerical controller 1B.
  • the numerical controller 1A is connected to another numerical controller 1B via the communication network 16.
  • one or both of the HMI process and the communication process may be executed in one of the numerical controller 1A and the other numerical controller 1B.
  • the pattern determining unit 4 selects one processing pattern from among the plurality of processing patterns indicated by the processing pattern information in order to distribute the processing load.
  • the resource information includes information indicating that the number of arithmetic devices is two: the numerical control device 1A and the other numerical control device 1B.
  • the resource information includes information indicating that each of the numerical controller 1A and the other numerical controller 1B has three core processors.
  • the pattern determination unit 4 first specifies the number of core processors included in all the arithmetic devices based on the resource information, and determines the number of core processors among the plurality of processing patterns based on the specified number. Narrow down the corresponding processing pattern. When the processing pattern cannot be narrowed down based on the resource information, that is, when the assumed number of resources does not exist, the pattern determination unit 4 determines that the number of core processors smaller than the number of core processors included in all the arithmetic devices is Selects a processing pattern that will execute the processing.
  • the pattern determination unit 4 determines whether the number of core processors included in all the arithmetic devices is five. Select a processing pattern.
  • the pattern determination unit 4 selects a processing pattern based on the number of core processors, and selects a processing pattern having the shortest processing time from among them. However, the pattern determination unit 4 does not have to select a processing pattern based on the number of core processors. For example, the pattern determination unit 4 may calculate the processing time of each of a plurality of processing patterns regardless of the number of core processors, and select the processing pattern with the shortest processing time.
  • the processing time of each processing function and processing task is measured in advance in each of the plurality of processing units, and the time required for communication processing is further included in real time.
  • the processing times of the axis control processing, acceleration / deceleration processing, and interpolation processing that need to be executed are calculated.
  • the pattern determination unit 4 selects a processing pattern having the shortest processing time based on the calculation result.
  • the allocating unit 5A allocates a plurality of sub-processes to the numerical control device 1A and another numerical control device 1B, and causes the core processors included in the numerical control device 1A and the other numerical control devices 1B to execute the allocated sub-processes. .
  • the numerical controller 1A distributes a plurality of sub-processes constituting the above-described processing according to the determined processing pattern, and distributes the plurality of cores included in the numerical controller 1A and the other numerical controller 1B. Assign to processor. Therefore, the numerical control device 1A can execute the above processing in a shorter time than the processing time when one of the plurality of core processors executes the above processing. In addition, the numerical controller 1A can perform control of a larger number of axes than before and control of a larger number of systems than before.
  • the other numerical controller 1B does not have the allocating unit 5A.
  • another numerical controller 1B may include the allocating unit 5A.
  • the numerical controller 1A outputs information indicating the processing pattern determined by the pattern determining unit 4 included in the numerical controller 1A to another numerical controller 1B, and the allocating unit 5A included in the other numerical controller 1B outputs Based on the processing pattern, the sub-processing to be executed in the processing pattern may be distributed and assigned to a plurality of core processors included in another numerical controller 1B.
  • the other numerical control device 1B may be replaced by a computing device having a plurality of core processors.
  • FIG. 14 is a diagram illustrating a configuration of a numerical control device 50 according to the third embodiment.
  • the numerical control device 50 is a device that controls a machine tool, and has the multi-core processor 2.
  • the multi-core processor 2 includes a first core processor 21, a second core processor 22, a third core processor 23, and a fourth core processor 24.
  • the first core processor 21, the second core processor 22, the third core processor 23, and the fourth core processor 24 are examples of a plurality of core processors.
  • the numerical controller 50 divides the processing executed by the multi-core processor 2 and, when the number of the plurality of primary sub-processes obtained by performing the division is larger than the number of the plurality of core processors, There is further provided a dividing unit 51 that divides the processing into a part and a remainder, and divides the part to obtain a plurality of secondary sub-processes.
  • the numerical control device 50 further includes an assignment unit 52 that distributes the remainder of the plurality of primary sub-processes obtained by the dividing unit 51 and the plurality of secondary sub-processes and assigns them to a plurality of core processors.
  • the allocating unit 52 holds the execution order for each of the plurality of secondary sub-processes.
  • the allocating unit 52 performs the second primary sub-process between the first secondary sub-process and the second secondary sub-process obtained by dividing the first primary sub-process.
  • the third secondary sub-process obtained by the division is interrupted.
  • the allocating unit 52 allocates the first secondary sub-process, the third secondary sub-process, and the second secondary sub-process to one of the plurality of core processors in this order.
  • the allocating unit 52 divides the second primary sub-process between the fourth secondary sub-process and the fifth secondary sub-process obtained by dividing the third primary sub-process. Then, the sixth secondary sub-process obtained by performing the above-mentioned process is interrupted. The allocating unit 52 allocates the fourth secondary sub-process, the sixth secondary sub-process, and the fifth secondary sub-process to another one of the plurality of core processors in this order.
  • the numerical control device 50 further includes a storage unit 53.
  • An example of the storage unit 53 is a semiconductor memory. Part of the storage unit 53 is a nonvolatile memory.
  • FIG. 15 is a diagram illustrating a first example of a processing pattern in a case where the number of core processors included in the multi-core processor 2 included in the numerical controller 50 according to the third embodiment is smaller than the number of axes of a control target. .
  • the number of core processors included in the multi-core processor is four and the number of axes of the control target is five.
  • the axis control processing of the first axis and the fifth axis is assigned to the first core processor, the axis control processing of the second axis is assigned to the second core processor, and the axis control processing of the third axis is performed.
  • This is a processing pattern in which the axis control processing of the fourth axis is allocated to the third core processor and the axis control processing of the fourth axis is allocated to the fourth core processor.
  • the axis control processing includes common processing for each axis from the first axis to the fifth axis.
  • the interpolation process also includes a common process for each of the first to fifth axes.
  • the processing pattern shown in FIG. 15 is a processing pattern for executing an interpolation process after the execution of the axis control process.
  • the second core processor, the third core processor, and the fourth core processor are idle. Time occurs. Free time is wasted time.
  • FIG. 16 is a diagram illustrating a second example of the processing pattern when the number of core processors included in the multi-core processor 2 included in the numerical control device 50 according to the third embodiment is smaller than the number of axes of the control target. .
  • the processing of each axis other than the common processing in the axis control processing has high processing independence. Therefore, the processing of each axis can be assigned to one core processor and executed.
  • FIG. 16 shows that the axis control process of the fifth axis, which is one example of the plurality of primary sub-processes, is divided into four secondary sub-processes from a secondary sub-process A to a secondary sub-process D. This shows that three secondary sub-processes from sub-processes B to D cannot be executed.
  • FIG. 17 is a diagram illustrating a third example of the processing pattern when the number of core processors included in the multi-core processor 2 included in the numerical controller 50 according to the third embodiment is smaller than the number of axes of the control target. .
  • the axis control processing of the first axis is assigned to the first core processor
  • the axis control processing of the second axis is assigned to the second core processor
  • the axis control of the third axis is performed.
  • the processing is assigned to the third core processor
  • the axis control processing of the fourth axis is assigned to the fourth core processor.
  • the axis control processing for each of the first axis, the second axis, and the third axis is executed after the secondary sub-processing A and the secondary sub-processing A are executed. It is divided into the next sub-process B.
  • the axis control processing for the fifth axis is a secondary sub-processing A, a secondary sub-processing B executed after the execution of the secondary sub-processing A, and a secondary sub-processing B Is performed, and a secondary sub-process C is executed after the secondary sub-process C is executed, and a secondary sub-process D is executed after the secondary sub-process C is executed.
  • the secondary sub-processing A for the first axis is executed by the first core processor
  • the secondary sub-processing A for the fifth axis is assigned to the first core processor and Executed by the core processor.
  • the secondary sub-process B for the first axis is executed by the first core processor.
  • the secondary sub-processing B for the fifth axis is assigned to the second core processor and Executed by the core processor.
  • the secondary sub-process B for the fifth axis is executed, the secondary sub-process B for the second axis is executed by the second core processor.
  • the secondary sub-process C for the fifth axis is assigned to the third core processor and executed by the third core processor.
  • the secondary sub-process B for the third axis is executed by the third core processor.
  • the secondary sub-process D for the fifth axis is assigned to the fourth core processor and executed by the fourth core processor.
  • the axis control processing which is the primary sub-processing for each of the first, second, and third axes, is the secondary sub-processing A and the secondary sub-processing.
  • A is divided into a secondary sub-process B executed after A is executed.
  • one secondary sub-process for the fifth axis is allocated between the secondary sub-process A and the secondary sub-process B. .
  • the processing pattern illustrated in FIG. 17 is a processing pattern in which a plurality of secondary sub-processes of which the order of execution is not allowed to be changed among the plurality of secondary sub-processes is executed without changing the order of execution. . That is, in the processing pattern shown in FIG. 17, the order of execution is maintained.
  • the data obtained by executing each of the secondary sub-processes is stored in the storage unit 53. Therefore, in the processing pattern shown in FIG. 17, the plurality of secondary sub-processes for each axis from the first axis to the fifth axis are performed by using the data stored in the storage unit 53. It is executed in order from the top of the primary sub-process constituted by the sub-process.
  • the numerical control device 50 divides the processing executed by the multi-core processor 2 and sets the number of primary sub-processes obtained by performing the division to a plurality of core processors. If the number is larger than the number, a part of the plurality of primary sub-processes is divided to obtain a plurality of secondary sub-processes.
  • the numerical controller 50 distributes the remaining primary sub-processes other than a part of the plurality of obtained primary sub-processes and the plurality of secondary sub-processes and allocates them to the plurality of core processors.
  • the numerical controller 50 keeps the execution order for each of the plurality of secondary sub-processes.
  • the numerical controller 50 divides the second primary sub-process between the first secondary sub-process and the second secondary sub-process obtained by dividing the first primary sub-process. A third secondary sub-process obtained by this is interrupted. The numerical controller 50 allocates the first secondary sub-process, the third secondary sub-process, and the second secondary sub-process to one of the core processors in this order.
  • the numerical controller 50 divides the second primary sub-process between the fourth secondary sub-process and the fifth secondary sub-process obtained by dividing the third primary sub-process. A sixth secondary sub-process obtained as a result is interrupted. The numerical controller 50 allocates the fourth secondary sub-process, the sixth secondary sub-process, and the fifth secondary sub-process to another one of the plurality of core processors in this order.
  • the numerical controller 50 when the number of the plurality of primary sub-processes obtained by performing the division is larger than the number of the plurality of core processors, the numerical controller 50 has the following effects. That is, the numerical control device 50 can execute the processing executed by the multi-core processor 2 in a processing time shorter than the processing time when one core processor executes the processing, without making the idle time as much as possible. .
  • FIG. 18 is a diagram illustrating the processor 81 in a case where some or all of the functions of the pattern determination unit 4 and the assignment unit 5 included in the numerical control device 1 according to the first embodiment are realized by the processor 81. That is, a part or all of the functions of the pattern determining unit 4 and the allocating unit 5 may be realized by the processor 81 that executes the program stored in the memory 82.
  • the processor 81 is a CPU (Central Processing Unit), a processing device, an arithmetic device, a microprocessor, or a DSP (Digital Signal Processor).
  • FIG. 18 also shows the memory 82.
  • the processor 81 When some or all of the functions of the pattern determination unit 4 and the assignment unit 5 are realized by the processor 81, the part or all of the functions are performed by the processor 81 and software, firmware, or a combination of software and firmware. Is achieved.
  • Software or firmware is described as a program and stored in the memory 82.
  • the processor 81 realizes a part or all of the functions of the pattern determination unit 4 and the assignment unit 5 by reading and executing the program stored in the memory 82.
  • the numerical controller 1 When a part or all of the functions of the pattern determining unit 4 and the allocating unit 5 are realized by the processor 81, the numerical controller 1 performs the steps executed by the part or all of the pattern determining unit 4 and the allocating unit 5 as a result.
  • the memory 82 is, for example, a non-volatile memory such as a RAM (Random Access Memory), a ROM (Read Only Memory), a flash memory, an EPROM (Erasable Programmable Read Only Memory), and an EEPROM (registered trademark) (Electrically Erasable Programmable Read-Only Memory).
  • a non-volatile memory such as a RAM (Random Access Memory), a ROM (Read Only Memory), a flash memory, an EPROM (Erasable Programmable Read Only Memory), and an EEPROM (registered trademark) (Electrically Erasable Programmable Read-Only Memory).
  • EEPROM Electrically Erasable Programmable Read-Only Memory
  • it is a volatile semiconductor memory, a magnetic disk, a flexible disk, an optical disk, a compact disk, a mini disk, a DVD (Digital Versatile Disk), or the like.
  • FIG. 19 is a diagram illustrating the processing circuit 91 when a part or all of the pattern determining unit 4 and the allocating unit 5 included in the numerical control device 1 according to the first embodiment are realized by the processing circuit 91. That is, a part or all of the pattern determination unit 4 and the assignment unit 5 may be realized by the processing circuit 91.
  • the processing circuit 91 is dedicated hardware.
  • the processing circuit 91 is, for example, a single circuit, a composite circuit, a programmed processor, a parallel programmed processor, an ASIC (Application Specific Integrated Circuit), an FPGA (Field-Programmable Gate Array), or a combination thereof. It is.
  • Part of the pattern determination unit 4 and the assignment unit 5 may be dedicated hardware separate from the rest.
  • a part of the plurality of functions may be realized by software or firmware, and the rest of the plurality of functions may be realized by dedicated hardware.
  • the plurality of functions of the pattern determination unit 4 and the assignment unit 5 can be realized by hardware, software, firmware, or a combination thereof.
  • a part or all of the functions of the pattern determining unit 4 and the allocating unit 5A of the numerical control device 1A according to the second embodiment may be realized by a processor having a function equivalent to the processor 81 described above.
  • the numerical control device 1A according to the second embodiment stores the processor and a program that results in execution of steps executed by some or all of the pattern determination unit 4 and the assignment unit 5A.
  • a memory for performing The memory is a memory having the same function as the memory 82 described above.
  • a part or all of the pattern determining unit 4 and the allocating unit 5A included in the numerical control device 1A according to the second embodiment may be realized by a processing circuit having a function equivalent to that of the processing circuit 91.
  • a part or all of the functions of the dividing unit 51 and the allocating unit 52 included in the numerical control device 50 according to the third embodiment may be realized by a processor having the same function as the processor 81 described above.
  • the numerical control device 50 according to the third embodiment stores the processor and a program that results in execution of steps executed by some or all of the dividing unit 51 and the allocating unit 52.
  • a memory for The memory is a memory having the same function as the memory 82 described above.
  • Part or all of the dividing unit 51 and the allocating unit 52 included in the numerical control device 50 according to the third embodiment may be realized by a processing circuit having a function equivalent to the processing circuit 91 described above.
  • 1,50 numerical control unit 2 multi-core processor, 3,53 storage unit, 4 pattern determination unit, 5,52 allocation unit, 11 motor control amplifier, 12 motor, 13 display, 14 input / output device, 15 network device, 21 First core processor, 22 second core processor, 23 third core processor, 24 fourth core processor, 31 machining program, 32 machining program reading process, 33 machining program analysis process, 34 interpolation process, 35 acceleration / deceleration process, 36 axis Control processing, 37 HMI processing, 38 I / O control processing, 39 communication processing, 41 processing pattern information, 42 resource information, 43 machine configuration information, 44 software configuration information, 51 division unit, 81 processor, 82 memory, 91 processing circuit .

Abstract

A numerical control device (1) comprises: a multicore processor (2); a pattern determination unit (4) which determines, from among a plurality of processing patterns, a processing pattern that allows the multicore processor (2) to perform a process in a shorter time than a single core processor; and an allocation unit (5) which distributes and allocates a plurality of subprocesses constituting the process to a plurality of core processors in accordance with the determined processing pattern. The plurality of subprocesses include a plurality of subprocesses, the execution order of which is not allowed to be changed, and the processing pattern is such that these subprocesses are performed without changing the execution order thereof.

Description

数値制御装置Numerical control unit
　本発明は、工作機械を制御する数値制御装置に関する。 The present invention relates to a numerical control device for controlling a machine tool.
　工作機械を制御する数値制御装置は、加工プログラムを読込み、加工プログラムをもとに、工具径路上の単位時間毎の指令位置を計算する補間処理と、工作機械を滑らかに動作させるための加減速処理と、工作機械の各軸のモータへ指令するための軸制御処理とを実行する。数値制御装置は、数値制御装置を操作するための情報の表示及び操作結果の表示を行うＨＭＩ処理と、入出力信号の制御を行うＩ／Ｏ制御処理と、ネットワーク通信及びバス通信の処理を行う通信処理とを実行する。“ＨＭＩ”は、“Human　Machine　Interface”の略語である。“Ｉ／Ｏ”は、“Input/Output”の略語である。 The numerical control device that controls the machine tool reads the machining program, calculates the command position per unit time on the tool path based on the machining program, and accelerates / decelerates the machine tool to operate smoothly. The processing and the axis control processing for instructing the motor of each axis of the machine tool are executed. The numerical controller performs HMI processing for displaying information for operating the numerical controller and displaying operation results, I / O control processing for controlling input / output signals, and processing for network communication and bus communication. Execute communication processing. “HMI” is an abbreviation for “Human \ Machine \ Interface”. “I / O” is an abbreviation for “Input / Output”.
　近年、工作機械の構成が複雑になってきていたり、モータによって回転させられる軸の個数及び軸のグループである系統数が増加してきているので、数値制御装置が実行する処理が増加してきている。数値制御装置が実行する処理は、あらかじめ決められた時間以内に実行されなければならない。 In recent years, as the configuration of a machine tool has become more complicated, and the number of shafts rotated by a motor and the number of systems as a group of shafts have increased, the number of processes executed by a numerical controller has increased. The processing executed by the numerical controller must be executed within a predetermined time.
　従来、複数のコアプロセッサを有する数値制御装置が提案されている（例えば、特許文献１参照）。従来の数値制御装置は、実行される処理を複数のサブ処理に分割し、複数のサブ処理を分散させて複数のコアプロセッサに割り当てる。これにより、従来の数値制御装置は、増加してきている処理をあらかじめ決められた時間以内に実行する。 Conventionally, a numerical control device having a plurality of core processors has been proposed (for example, see Patent Document 1). A conventional numerical controller divides a process to be executed into a plurality of sub-processes, and distributes the plurality of sub-processes to allocate to a plurality of core processors. As a result, the conventional numerical control device executes the increasing process within a predetermined time.
特許第６１５１６６９号公報Japanese Patent No. 6151669
　数値制御装置によって実行される処理を複数のサブ処理に分割することはできるが、複数のサブ処理のなかには実行される順序の変更が許可されない複数のサブ処理が含まれる場合がある。例えば、ある処理をサブ処理Ａ、サブ処理Ｂ及びサブ処理Ｃに分割することができるが、サブ処理Ｂはサブ処理Ａの結果を利用する処理であり、サブ処理Ｃはサブ処理Ｂの結果を利用する処理である場合がある。この場合、サブ処理Ａ、サブ処理Ｂ及びサブ処理Ｃは、サブ処理Ａ、サブ処理Ｂ、サブ処理Ｃの順に実行されなければならない。 (4) Although the processing performed by the numerical controller can be divided into a plurality of sub-processings, the plurality of sub-processings may include a plurality of sub-processings in which the order of execution is not permitted. For example, a certain process can be divided into a sub-process A, a sub-process B and a sub-process C. The sub-process B is a process using the result of the sub-process A, and the sub-process C is a process using the result of the sub-process B. It may be a process to be used. In this case, sub-process A, sub-process B, and sub-process C must be executed in the order of sub-process A, sub-process B, and sub-process C.
　従来の数値制御装置では、サブ処理Ａが第１コアプロセッサに割り当てられ、サブ処理Ｂが第２コアプロセッサに割り当てられ、サブ処理Ｃが第３コアプロセッサに割り当てられる場合がある。この場合、上述の通り、サブ処理Ａ、サブ処理Ｂ及びサブ処理Ｃは、サブ処理Ａ、サブ処理Ｂ、サブ処理Ｃの順に実行されなければならないので、サブ処理Ａ、サブ処理Ｂ及びサブ処理Ｃを並列に実行することはできない。 In the conventional numerical controller, there are cases where sub-process A is allocated to the first core processor, sub-process B is allocated to the second core processor, and sub-process C is allocated to the third core processor. In this case, as described above, the sub-process A, the sub-process B, and the sub-process C must be executed in the order of the sub-process A, the sub-process B, and the sub-process C. C cannot be executed in parallel.
　本発明は、上記に鑑みてなされたものであって、実行される処理が複数のサブ処理に分割された場合に複数のサブ処理のうちの実行される順序の変更が許可されない複数のサブ処理を実行の順序が変更されることなく実行すると共に、ひとつのコアプロセッサが上記の処理を実行する際の処理時間より短い処理時間で上記の処理を実行する数値制御装置を得ることを目的とする。 The present invention has been made in view of the above, and when a process to be executed is divided into a plurality of sub-processes, a plurality of sub-processes which are not allowed to change the order of execution among the plurality of sub-processes It is an object of the present invention to obtain a numerical controller that executes the above processing without changing the order of execution, and executes the above processing in a processing time shorter than the processing time when one core processor executes the above processing. .
　上述した課題を解決し、目的を達成するために、本発明は、工作機械を制御する数値制御装置であって、複数のコアプロセッサを含むマルチコアプロセッサと、パターン決定部とを有する。前記パターン決定部は、前記マルチコアプロセッサに含まれるコアプロセッサの個数を示す情報を含むリソース情報、前記工作機械を構成するハードウェアに関する機械構成情報、及び、前記マルチコアプロセッサによって実行される処理がソフトウェアが用いられて実行される場合の前記ソフトウェアの構成を示すソフトウェア構成情報をもとに、複数の処理パターンのなかから、前記マルチコアプロセッサが前記処理を実行する際の処理時間が、前記複数のコアプロセッサのうちのひとつのコアプロセッサが前記処理を実行する際の処理時間より短くなる処理パターンを選択し、選択された処理パターンを前記複数のコアプロセッサが前記処理を実行する際の処理パターンと決定する。本発明は、前記パターン決定部によって決定された前記処理パターンにしたがって、前記処理を構成する複数のサブ処理を分散させて前記複数のコアプロセッサに割り当てる割り当て部を更に有する。前記複数の処理パターンの各々は、前記複数のサブ処理のうちの実行される順序の変更が許可されない複数のサブ処理を実行の順序が変更されることなく実行させる処理パターンである。 In order to solve the above-described problems and achieve the object, the present invention is a numerical controller that controls a machine tool, and includes a multi-core processor including a plurality of core processors, and a pattern determination unit. The pattern determination unit may include: resource information including information indicating the number of core processors included in the multi-core processor; machine configuration information on hardware configuring the machine tool; and software executed by the multi-core processor. Based on software configuration information indicating the configuration of the software when used and executed, from among a plurality of processing patterns, the processing time when the multi-core processor executes the processing is the plurality of core processors And selecting a processing pattern that is shorter than the processing time when one of the core processors executes the processing, and determines the selected processing pattern as a processing pattern when the plurality of core processors execute the processing. . The present invention further includes an assignment unit that distributes a plurality of sub-processes constituting the process and allocates the sub-processes to the plurality of core processors according to the processing pattern determined by the pattern determination unit. Each of the plurality of processing patterns is a processing pattern for executing a plurality of sub-processes of the plurality of sub-processes, the order of execution of which is not allowed to be changed, without changing the order of execution.
　本発明によれば、実行される処理が複数のサブ処理に分割された場合に複数のサブ処理のうちの実行される順序の変更が許可されない複数のサブ処理を実行の順序が変更されることなく実行すると共に、ひとつのコアプロセッサが上記の処理を実行する際の処理時間より短い処理時間で上記の処理を実行することができるという効果が得られる。 According to the present invention, when a process to be executed is divided into a plurality of sub-processes, the order of execution of a plurality of sub-processes among which a change in the order of execution is not permitted is changed. And the core processor can execute the above processing in a processing time shorter than the processing time when one core processor executes the above processing.
実施の形態１にかかる数値制御装置の構成を示す図FIG. 1 shows a configuration of a numerical control device according to a first embodiment. 実施の形態１にかかる数値制御装置によって実行される処理を示す図FIG. 4 is a diagram illustrating processing executed by the numerical control device according to the first embodiment; 実施の形態１にかかる数値制御装置がサブ処理を複数のコアプロセッサに割り当てる際の動作を説明するための図FIG. 4 is a diagram for explaining an operation when the numerical controller according to the first embodiment assigns sub-processes to a plurality of core processors ひとつのコアプロセッサが複数のサブ処理を実行する場合において加工プログラム解析処理を所定周期時間を超えて実行する場合の例を示す図The figure which shows the example at the time of performing a machining program analysis process beyond a predetermined cycle time when one core processor performs a several sub process. ひとつのコアプロセッサが複数のサブ処理を実行する場合において補間処理を所定周期時間を超えて実行する場合の例を示す図FIG. 9 is a diagram illustrating an example of a case where an interpolation process is performed beyond a predetermined cycle time when one core processor performs a plurality of sub-processes; 実施の形態１にかかる数値制御装置において処理が分散されて複数のコアプロセッサに割り当てられて処理が実行される処理パターンの第１の例を示す図FIG. 6 is a diagram showing a first example of a processing pattern in which processing is distributed and assigned to a plurality of core processors to execute processing in the numerical control device according to the first embodiment; 実施の形態１にかかる数値制御装置において処理が分散されて複数のコアプロセッサに割り当てられて処理が実行される処理パターンの第２の例を示す図FIG. 9 is a diagram illustrating a second example of a processing pattern in which processing is distributed and assigned to a plurality of core processors to execute processing in the numerical control device according to the first embodiment; 実施の形態１にかかる数値制御装置において処理が分散されて複数のコアプロセッサに割り当てられて処理が実行される処理パターンの第３の例を示す図FIG. 9 is a diagram showing a third example of a processing pattern in which processing is distributed in the numerical control device according to the first embodiment and the processing is executed by being allocated to a plurality of core processors; 実施の形態１にかかる数値制御装置によって実行される複数のサブ処理の各々の処理時間及び実行周期を示す図FIG. 4 is a diagram illustrating processing times and execution cycles of a plurality of sub-processes executed by the numerical control device according to the first embodiment; 実施の形態１にかかる数値制御装置が有するパターン決定部の動作の手順の一例を示すフローチャート5 is a flowchart showing an example of the procedure of the operation of the pattern determining unit of the numerical control device according to the first embodiment 実施の形態２にかかる数値制御装置の構成を示す図FIG. 3 is a diagram illustrating a configuration of a numerical control device according to a second embodiment. 実施の形態２にかかる数値制御装置と他の数値制御装置とにおいて処理が実行される処理パターンの第１の例を示す図FIG. 9 is a diagram showing a first example of a processing pattern in which processing is executed in the numerical control device according to the second embodiment and another numerical control device. 実施の形態２にかかる数値制御装置と他の数値制御装置とにおいて処理が実行される処理パターンの第２の例を示す図FIG. 9 is a diagram showing a second example of a processing pattern in which processing is performed in the numerical control device according to the second embodiment and another numerical control device. 実施の形態３にかかる数値制御装置の構成を示す図FIG. 3 is a diagram showing a configuration of a numerical control device according to a third embodiment. 実施の形態３にかかる数値制御装置が有するマルチコアプロセッサに含まれるコアプロセッサの個数が制御対象物の軸の個数より少ない場合の処理パターンの第１の例を示す図The figure showing the first example of the processing pattern when the number of core processors included in the multi-core processor of the numerical control device according to the third embodiment is smaller than the number of axes of the control target. 実施の形態３にかかる数値制御装置が有するマルチコアプロセッサに含まれるコアプロセッサの個数が制御対象物の軸の個数より少ない場合の処理パターンの第２の例を示す図FIG. 14 is a diagram illustrating a second example of the processing pattern when the number of core processors included in the multi-core processor included in the numerical control device according to the third embodiment is smaller than the number of axes of the control target; 実施の形態３にかかる数値制御装置が有するマルチコアプロセッサに含まれるコアプロセッサの個数が制御対象物の軸の個数より少ない場合の処理パターンの第３の例を示す図The figure showing the 3rd example of the processing pattern when the number of core processors included in the multi-core processor which the numerical control device concerning a 3rd embodiment has is smaller than the number of axes of a control subject. 実施の形態１にかかる数値制御装置が有するパターン決定部及び割り当て部の一部又は全部の機能がプロセッサによって実現される場合のプロセッサを示す図FIG. 2 is a diagram illustrating a processor in a case where some or all of the functions of a pattern determination unit and an assignment unit included in the numerical control device according to the first embodiment are implemented by the processor; 実施の形態１にかかる数値制御装置が有するパターン決定部及び割り当て部の一部又は全部が処理回路によって実現される場合の処理回路を示す図FIG. 3 is a diagram illustrating a processing circuit when a part or all of a pattern determining unit and an allocating unit included in the numerical control device according to the first embodiment are realized by the processing circuit;
　以下に、本発明の実施の形態にかかる数値制御装置を図面に基づいて詳細に説明する。なお、この実施の形態によりこの発明が限定されるものではない。 Hereinafter, a numerical control device according to an embodiment of the present invention will be described in detail with reference to the drawings. The present invention is not limited by the embodiment.
実施の形態１．
　図１は、実施の形態１にかかる数値制御装置１の構成を示す図である。数値制御装置１は、工作機械を制御する装置であって、マルチコアプロセッサ２を有する。マルチコアプロセッサ２は、第１コアプロセッサ２１と、第２コアプロセッサ２２と、第３コアプロセッサ２３と、第４コアプロセッサ２４とを含む。第１コアプロセッサ２１、第２コアプロセッサ２２、第３コアプロセッサ２３及び第４コアプロセッサ２４は、複数のコアプロセッサの一例である。 Embodiment 1 FIG.
FIG. 1 is a diagram illustrating a configuration of a numerical control device 1 according to the first embodiment. The numerical control device 1 is a device for controlling a machine tool, and has a multi-core processor 2. The multi-core processor 2 includes a first core processor 21, a second core processor 22, a third core processor 23, and a fourth core processor 24. The first core processor 21, the second core processor 22, the third core processor 23, and the fourth core processor 24 are examples of a plurality of core processors.
　数値制御装置１は、記憶部３を更に有する。記憶部３の例は、半導体メモリである。例えば、記憶部３の一部は不揮発性メモリである。記憶部３は、マルチコアプロセッサ２に含まれるコアプロセッサの個数を示す情報を含むリソース情報を記憶する。記憶部３は、工作機械を構成するハードウェアに関する機械構成情報を更に記憶する。記憶部３は、マルチコアプロセッサ２によって実行される処理がソフトウェアが用いられて実行される場合の当該ソフトウェアの構成を示すソフトウェア構成情報を更に記憶する。ソフトウェア構成情報は、数値制御装置１の内部で実行される複数の処理ブロックと、当該複数の処理ブロックの各々の実行周期及び実行時間とを示す情報である。処理ブロックは、処理関数である。 The numerical control device 1 further includes a storage unit 3. An example of the storage unit 3 is a semiconductor memory. For example, a part of the storage unit 3 is a nonvolatile memory. The storage unit 3 stores resource information including information indicating the number of core processors included in the multi-core processor 2. The storage unit 3 further stores machine configuration information relating to hardware configuring the machine tool. The storage unit 3 further stores software configuration information indicating the configuration of the software when the process executed by the multi-core processor 2 is executed using software. The software configuration information is information indicating a plurality of processing blocks executed inside the numerical controller 1 and the execution cycle and execution time of each of the plurality of processing blocks. The processing block is a processing function.
　記憶部３は、複数の処理パターンを示す処理パターン情報を更に記憶する。複数の処理パターンの各々は、上記の処理を構成する複数のサブ処理のうちの実行される順序の変更が許可されない複数のサブ処理を実行の順序が変更されることなく実行させる処理パターンである。 The storage unit 3 further stores processing pattern information indicating a plurality of processing patterns. Each of the plurality of processing patterns is a processing pattern for performing, without changing the order of execution, a plurality of sub-processes of the plurality of sub-processes constituting the above-mentioned process, the change of the order of execution of which is not permitted. .
　数値制御装置１は、リソース情報、機械構成情報及びソフトウェア構成情報をもとに、処理パターン情報が示す複数の処理パターンのなかから、マルチコアプロセッサ２が上記の処理を実行する際の処理時間が、複数のコアプロセッサのうちのひとつのコアプロセッサが上記の処理を実行する際の処理時間より短くなる処理パターンを選択するパターン決定部４を更に有する。パターン決定部４は、選択された処理パターンを複数のコアプロセッサが上記の処理を実行する際の処理パターンと決定する。実施の形態１では、リソース情報、機械構成情報、ソフトウェア構成情報及び処理パターン情報は、記憶部３に記憶されている情報である。 The numerical control device 1 determines, based on the resource information, the machine configuration information, and the software configuration information, a processing time when the multi-core processor 2 executes the above processing from among a plurality of processing patterns indicated by the processing pattern information. It further includes a pattern determination unit 4 that selects a processing pattern that is shorter than a processing time when one of the plurality of core processors executes the above processing. The pattern determination unit 4 determines the selected processing pattern as a processing pattern when a plurality of core processors execute the above processing. In the first embodiment, the resource information, the machine configuration information, the software configuration information, and the processing pattern information are information stored in the storage unit 3.
　例えば、パターン決定部４は、リソース情報、機械構成情報及びソフトウェア構成情報をもとに、複数の処理パターンのなかから、マルチコアプロセッサ２が上記の処理を実行する際の処理時間が最短となる処理パターンを選択し、選択された処理パターンを複数のコアプロセッサが上記の処理を実行する際の処理パターンと決定する。 For example, based on the resource information, the machine configuration information, and the software configuration information, the pattern determination unit 4 performs processing that minimizes the processing time when the multi-core processor 2 executes the above processing from among a plurality of processing patterns. A pattern is selected, and the selected processing pattern is determined as a processing pattern when a plurality of core processors execute the above processing.
　例えば、パターン決定部４は、複数のサブ処理の各々の処理時間を事前に計測し、計測された処理時間を利用して、複数の処理パターンのなかから、マルチコアプロセッサ２が上記の処理を実行する際の処理時間が最短となる処理パターンを選択し、選択された処理パターンを複数のコアプロセッサが上記の処理を実行する際の処理パターンと決定する。 For example, the pattern determination unit 4 measures in advance the processing time of each of the plurality of sub-processes, and uses the measured processing time to execute the above-described processing from the multi-core processor 2 among the plurality of processing patterns. Then, the processing pattern that minimizes the processing time is selected, and the selected processing pattern is determined as the processing pattern when the plurality of core processors execute the above processing.
　数値制御装置１は、パターン決定部４によって決定された処理パターンにしたがって、上記の処理を構成する複数のサブ処理を分散させて複数のコアプロセッサに割り当てる割り当て部５を更に有する。第１コアプロセッサ２１、第２コアプロセッサ２２、第３コアプロセッサ２３及び第４コアプロセッサ２４の各々は、割り当て部５によって割り当てられたサブ処理を実行する。 The numerical control device 1 further includes an assignment unit 5 that distributes a plurality of sub-processes constituting the above process and allocates the sub-processes to a plurality of core processors according to the processing pattern determined by the pattern determination unit 4. Each of the first core processor 21, the second core processor 22, the third core processor 23, and the fourth core processor 24 executes the sub-process assigned by the assigning unit 5.
　数値制御装置１は、モータ制御アンプ１１に接続されている。モータ制御アンプ１１は、複数のモータ１２に接続されており、複数のモータ１２の各々を制御する。複数のモータ１２の各々は、工作機械の一部である。図１では、説明を簡単に行うために、ひとつのモータ１２のみが示されている。複数のモータ１２の各々は、制御対象物の軸を回転させる。つまり、モータ制御アンプ１１は、複数の制御対象物の各々の軸の回転を制御する。 The numerical control device 1 is connected to the motor control amplifier 11. The motor control amplifier 11 is connected to the plurality of motors 12 and controls each of the plurality of motors 12. Each of the plurality of motors 12 is a part of a machine tool. FIG. 1 shows only one motor 12 for the sake of simplicity. Each of the plurality of motors 12 rotates the axis of the control target. That is, the motor control amplifier 11 controls the rotation of each axis of the plurality of control objects.
　数値制御装置１は、数値制御装置１によって実行された演算の結果を表示する機能を有する表示器１３にも接続されている。表示器１３は、データ入力装置を有していてもよい。データ入力装置は、キーボードを有していてもよい。数値制御装置１は、デジタルインプット情報とアナログインプット情報との一方又は双方を工作機械から受信すると共に、デジタルアウトプット情報とアナログアウトプット情報との一方又は双方を工作機械に送信する入出力装置１４にも接続されている。以下では、「入出力装置１４」は「Ｉ／Ｏ装置１４」と記載される場合がある。図面では、「入出力装置１４」は「Ｉ／Ｏ装置１４」と記載されている。数値制御装置１は、数値制御装置１を通信ネットワークに接続するネットワーク装置１５にも接続されている。 The numerical controller 1 is also connected to a display 13 having a function of displaying the result of the calculation executed by the numerical controller 1. The display 13 may have a data input device. The data input device may have a keyboard. The numerical controller 1 receives one or both of the digital input information and the analog input information from the machine tool, and transmits the one or both of the digital output information and the analog output information to the machine tool. Is also connected. Hereinafter, the “input / output device 14” may be described as the “I / O device 14”. In the drawings, the “input / output device 14” is described as the “I / O device 14”. The numerical controller 1 is also connected to a network device 15 that connects the numerical controller 1 to a communication network.
　図２は、実施の形態１にかかる数値制御装置１によって実行される処理を示す図である。図２には、モータ制御アンプ１１、表示器１３、Ｉ／Ｏ装置１４及びネットワーク装置１５も示されている。数値制御装置１は、加工プログラム３１を読込んで、加工プログラム３１に記述されているＧコードを読み取る加工プログラム読込み処理３２を実行する。加工プログラム３１は、複数の指令文を含む。数値制御装置１は、加工プログラム読込み処理３２において、１行毎に指令文を読込んでもよいし、１度に複数の行の指令文を読込んでもよい。 FIG. 2 is a diagram illustrating a process executed by the numerical controller 1 according to the first embodiment. FIG. 2 also shows a motor control amplifier 11, a display 13, an I / O device 14, and a network device 15. The numerical control device 1 reads the machining program 31 and executes a machining program reading process 32 for reading a G code described in the machining program 31. The machining program 31 includes a plurality of command statements. In the machining program reading process 32, the numerical control device 1 may read a command sentence for each line, or may read command sentences for a plurality of lines at a time.
　数値制御装置１は、加工プログラム読込み処理３２を実行した後、読込まれた加工プログラム３１を解析する加工プログラム解析処理３３を実行する。加工プログラム３１には、Ｇコードと呼ばれる移動指令と系統間での同期指令とを含む機能コードが含まれている。加工プログラム３１には、例えば工具の先端位置を決める座標位置も記述されている。数値制御装置１は、加工プログラム解析処理３３において、移動指令、同期指令及び工具の座標位置をもとに、モータ１２に対して最終的に指令する座標位置を計算する。 After executing the machining program reading process 32, the numerical controller 1 executes a machining program analysis process 33 for analyzing the read machining program 31. The machining program 31 includes a function code including a movement command called a G code and a synchronization command between systems. The machining program 31 also describes, for example, coordinate positions for determining the tip position of the tool. The numerical control device 1 calculates a coordinate position to finally instruct the motor 12 based on the movement command, the synchronization command, and the coordinate position of the tool in the machining program analysis processing 33.
　例えば、加工プログラム３１に工具の径補正と工具の先端位置を決める座標位置とが記述されている場合、数値制御装置１は、加工プログラム解析処理３３において、読込まれた座標位置を指定された工具番号の工具の径補正分移動させた補正位置を計算する。数値制御装置１は、加工プログラム解析処理３３において、補正位置である工具の先端位置に対して座標変換を行い、モータ１２の制御位置を算出する。数値制御装置１は、複数のモータ１２の各々について制御位置を算出する。 For example, if the machining program 31 describes a tool diameter correction and a coordinate position for determining the tip position of the tool, the numerical control device 1 specifies the read coordinate position in the machining program analysis process 33 for the designated tool. Calculate the correction position moved by the diameter correction of the tool with the number. In the machining program analysis processing 33, the numerical control device 1 performs coordinate conversion on the tip position of the tool, which is the correction position, and calculates the control position of the motor 12. The numerical controller 1 calculates a control position for each of the plurality of motors 12.
　次に、数値制御装置１は、加工プログラム解析処理３３において計算されたモータ１２の制御位置に一定の周期毎に送り速度に対応した移動量を加算して補間位置を計算する補間処理３４を実行する。数値制御装置１は、補間処理３４では、補間位置を計算するだけでなく、多系統の処理を実行する場合にはひとつの系統と他の系統とについて同期処理を実行する。 Next, the numerical controller 1 executes an interpolation process 34 for calculating an interpolation position by adding a movement amount corresponding to the feed speed at regular intervals to the control position of the motor 12 calculated in the machining program analysis process 33. I do. In the interpolation processing 34, in the interpolation processing 34, in addition to calculating the interpolation position, when performing the processing of multiple systems, the numerical controller 1 executes the synchronization processing for one system and another system.
　例えば、同期処理は、他の系統の状態を確認して、ひとつの系統について次の補間処理を行ってよいか否かを判定する待ち合わせ処理である。例えば、同期処理は、ひとつの系統の軸の移動量と他の系統の軸の移動量とを合算して加工プログラム３１において指令された移動量を扱う場合、他系統の軸の移動量を示す情報を取得してひとつの系統の軸の移動量を決めて補間位置を計算する処理である。 {For example, the synchronization process is a waiting process that checks the status of another system and determines whether the next interpolation process may be performed for one system. For example, the synchronous processing indicates the movement amount of the axis of the other system when the movement amount commanded in the machining program 31 is obtained by adding the movement amount of the axis of one system and the movement amount of the axis of the other system. This is a process of acquiring information, determining the movement amount of one system axis, and calculating an interpolation position.
　次に、数値制御装置１は、補間処理３４において得られた補間位置に対して例えば移動平均フィルタ処理又は加速度を一定にする処理を実行し、制御対象物の速度が滑らかになるように、モータ１２への指令位置を計算する加減速処理３５を実行する。 Next, the numerical control device 1 executes, for example, a moving average filter process or a process for making the acceleration constant with respect to the interpolation position obtained in the interpolation process 34 so that the speed of the control object becomes smooth. An acceleration / deceleration process 35 for calculating a command position for the motor 12 is executed.
　次に、数値制御装置１は、加減速処理３５において計算されたモータ１２への指令位置をモータ１２への指令に設定する軸制御処理３６を実行する。モータ制御アンプ１１は、指令をもとにモータ１２を制御する。例えば、モータ制御アンプ１１は、モータ１２に流れる電流値を制御する。 Next, the numerical controller 1 executes an axis control process 36 for setting the command position to the motor 12 calculated in the acceleration / deceleration process 35 to a command to the motor 12. The motor control amplifier 11 controls the motor 12 based on a command. For example, the motor control amplifier 11 controls a current value flowing through the motor 12.
　数値制御装置１は、数値制御装置１の内部のデータを表示器１３に表示させるＨＭＩ処理３７も実行する。当該データは、数値制御装置１の内部で行われた演算によって得られたデータを含む。ＨＭＩ処理３７は、ユーザからの入力を受け付ける処理を含む。ＨＭＩ処理３７では、処理の実行が早ければ早いだけユーザへの応答性が上がる。数値制御装置１は、工作機械へのデータの出力と、工作機械からの信号を受け付けるためのラダー処理とを含むＩ／Ｏ制御処理３８も実行する。数値制御装置１は、Ｉ／Ｏ制御処理３８をＩ／Ｏ装置１４を介して実行する。数値制御装置１は、ネットワーク装置１５を介して数値制御装置１の外部の物とデータの送受信を行う通信処理３９も実行する。数値制御装置１の外部の物には、工作機械は含まれない。 The numerical controller 1 also executes an HMI process 37 for displaying data inside the numerical controller 1 on the display 13. The data includes data obtained by a calculation performed inside the numerical controller 1. The HMI process 37 includes a process for receiving an input from a user. In the HMI process 37, the responsiveness to the user increases as soon as the process is executed. The numerical controller 1 also executes an I / O control process 38 including output of data to the machine tool and ladder processing for receiving a signal from the machine tool. The numerical controller 1 executes the I / O control processing 38 via the I / O device 14. The numerical controller 1 also executes a communication process 39 for transmitting and receiving data to and from an object outside the numerical controller 1 via the network device 15. Machines outside the numerical control device 1 do not include machine tools.
　加工プログラム読込み処理３２、加工プログラム解析処理３３、補間処理３４、加減速処理３５、軸制御処理３６、ＨＭＩ処理３７、Ｉ／Ｏ制御処理３８及び通信処理３９は、マルチコアプロセッサ２によって実行される処理である。加工プログラム読込み処理３２、加工プログラム解析処理３３、補間処理３４、加減速処理３５、軸制御処理３６、ＨＭＩ処理３７、Ｉ／Ｏ制御処理３８及び通信処理３９の各々は、サブ処理の例である。 The processing program reading processing 32, the processing program analysis processing 33, the interpolation processing 34, the acceleration / deceleration processing 35, the axis control processing 36, the HMI processing 37, the I / O control processing 38, and the communication processing 39 are processing executed by the multi-core processor 2. It is. Each of the machining program reading process 32, the machining program analysis process 33, the interpolation process 34, the acceleration / deceleration process 35, the axis control process 36, the HMI process 37, the I / O control process 38, and the communication process 39 is an example of a sub process. .
　図３は、実施の形態１にかかる数値制御装置１がサブ処理を複数のコアプロセッサに割り当てる際の動作を説明するための図である。上述の通り、サブ処理のひとつの例は、図２を用いて説明した複数の処理のひとつである。記憶部３は、マルチコアプロセッサ２によって実行される処理をどのように分割して各サブ処理をどのタイミングで実行するのかを特定する処理パターンを示す処理パターン情報４１を記憶している。処理パターン情報４１は、複数の処理パターンを示す。複数の処理パターンを示す処理パターン情報４１は、あらかじめ用意されている。 FIG. 3 is a diagram for explaining an operation when the numerical controller 1 according to the first embodiment assigns sub-processes to a plurality of core processors. As described above, one example of the sub-process is one of the plurality of processes described with reference to FIG. The storage unit 3 stores processing pattern information 41 indicating a processing pattern for specifying how to divide the processing executed by the multi-core processor 2 and when to execute each sub-processing. The processing pattern information 41 indicates a plurality of processing patterns. Processing pattern information 41 indicating a plurality of processing patterns is prepared in advance.
　記憶部３は、数値制御装置１が有するマルチコアプロセッサ２を構成するコアプロセッサの個数を示す情報を含むリソース情報４２を更に記憶している。リソース情報４２には、通信ネットワーク又は通信バスを介して数値制御装置１に接続されている他の数値制御装置又は計算装置に含まれていて使用可能な演算装置の個数を示す情報が含まれていてもよい。演算装置の例は、プロセッサである。 (4) The storage unit 3 further stores resource information 42 including information indicating the number of core processors constituting the multi-core processor 2 included in the numerical controller 1. The resource information 42 includes information indicating the number of usable arithmetic devices included in other numerical control devices or calculation devices connected to the numerical control device 1 via a communication network or a communication bus. You may. An example of an arithmetic device is a processor.
　記憶部３は、工作機械を構成するハードウェアに関する機械構成情報４３を更に記憶している。例えば、機械構成情報４３には、工作機械に含まれている軸の個数を示す情報と、系統数を示す情報と、機械タイプを示す情報と、数値制御装置１に接続されているＩ／Ｏ装置の個数を示す情報とのうちの一部又は全部が含まれている。機械タイプを示す情報は、例えば工作機械が旋盤又はマシニングセンタであることを示す情報である。 The storage unit 3 further stores machine configuration information 43 relating to hardware constituting the machine tool. For example, the machine configuration information 43 includes information indicating the number of axes included in the machine tool, information indicating the number of systems, information indicating a machine type, and I / O connected to the numerical controller 1. Part or all of the information indicating the number of devices is included. The information indicating the machine type is, for example, information indicating that the machine tool is a lathe or a machining center.
　記憶部３は、マルチコアプロセッサ２によって実行される処理がソフトウェアが用いられて実行される場合の当該ソフトウェアの構成を示すソフトウェア構成情報４４を更に記憶している。例えば、ソフトウェア構成情報４４は、数値制御装置１の内部で実行される複数の処理ブロックと、当該複数の処理ブロックの各々の実行周期及び実行時間とを示す情報である。処理ブロックは、処理関数である。 The storage unit 3 further stores software configuration information 44 indicating the configuration of the software when the processing executed by the multi-core processor 2 is executed using software. For example, the software configuration information 44 is information indicating a plurality of processing blocks executed inside the numerical control device 1 and an execution cycle and an execution time of each of the plurality of processing blocks. The processing block is a processing function.
　パターン決定部４は、リソース情報４２、機械構成情報４３及びソフトウェア構成情報４４をもとに、処理パターン情報４１が示す複数の処理パターンのなかから、マルチコアプロセッサ２が処理を実行する際の処理時間が、複数のコアプロセッサのうちのひとつのコアプロセッサが上記の処理を実行する際の処理時間より短くなる処理パターンを決定する。例えば、パターン決定部４は、リソース情報４２、機械構成情報４３及びソフトウェア構成情報４４をもとに、複数の処理パターンのなかから、マルチコアプロセッサ２が上記の処理を実行する際の処理時間が最短となる処理パターンを選択し、選択された処理パターンを複数のコアプロセッサが上記の処理を実行する際の処理パターンと決定する。 The pattern determination unit 4 determines, based on the resource information 42, the machine configuration information 43, and the software configuration information 44, a processing time when the multi-core processor 2 executes a process from a plurality of processing patterns indicated by the processing pattern information 41. Determines a processing pattern that is shorter than the processing time when one of the plurality of core processors executes the above processing. For example, based on the resource information 42, the machine configuration information 43, and the software configuration information 44, the pattern determination unit 4 determines the shortest processing time when the multi-core processor 2 executes the above processing from among a plurality of processing patterns. Is selected, and the selected processing pattern is determined as a processing pattern when a plurality of core processors execute the above processing.
　割り当て部５は、パターン決定部４によって決定された処理パターンにしたがって、複数のサブ処理を、分散させて、マルチコアプロセッサ２が有する第１コアプロセッサ２１と、第２コアプロセッサ２２と、第３コアプロセッサ２３と、第４コアプロセッサ２４とに割り当てる。 The allocating unit 5 distributes a plurality of sub-processes in accordance with the processing pattern determined by the pattern determining unit 4, and allocates the first core processor 21, the second core processor 22, and the third core processor of the multi-core processor 2. Assigned to the processor 23 and the fourth core processor 24.
　実施の形態１では、加工プログラムにおける指令系統がひとつであり、比較的短い線分長で記載された加工プログラムを実行する場合と、加工プログラムにおける指令系統が二つ以上ある多軸多系統制御を行っている場合とで、処理パターンを決定して複数のサブ処理を分散させて複数のコアプロセッサの各々に割り当てる例を示す。 In the first embodiment, there is one command system in a machining program, and a case where a machining program described with a relatively short line segment length is executed, and a multi-axis multi-system control in which there are two or more command systems in a machining program. An example in which a processing pattern is determined and a plurality of sub-processes are distributed and assigned to each of a plurality of core processors will be described.
　図４は、ひとつのコアプロセッサが複数のサブ処理を実行する場合において加工プログラム解析処理を所定周期時間を超えて実行する場合の例を示す図である。図４は、制御対象の軸の個数及び系統数は比較的少ないが、比較的短い線分長で記載された加工プログラムにおいて自由曲面の作成を指令する場合の処理の例を示している。自由曲面を加工する際、工作機械の動作速度を一定に保つ必要があり、加工プログラムの読込み処理と、加工プログラムの解析処理とを一定の処理時間内に完了する必要がある。つまり、リアルタイム性が求められる。図４は、リアルタイムで行わなければならない処理である軸制御処理、加減速処理、補間処理、加工プログラム読込み処理及び加工プログラム解析処理の合計時間が所定周期時間を超えている様子を示している。リアルタイムで行わなければならない処理は、一定の処理時間内に実行完了しなければいけない処理である。 FIG. 4 is a diagram showing an example of a case where a single core processor executes a plurality of sub-processes and executes a machining program analysis process over a predetermined period of time. FIG. 4 shows an example of processing when a command to create a free-form surface is given in a machining program in which the number of axes to be controlled and the number of systems are relatively small, but are described with relatively short line segment lengths. When processing a free-form surface, it is necessary to keep the operating speed of the machine tool constant, and it is necessary to complete the processing for reading the processing program and the processing for analyzing the processing program within a fixed processing time. That is, real-time properties are required. FIG. 4 shows a state in which the total time of axis control processing, acceleration / deceleration processing, interpolation processing, processing program reading processing, and processing program analysis processing, which must be performed in real time, exceeds a predetermined cycle time. Processing that must be performed in real time is processing that must be completed within a certain processing time.
　図５は、ひとつのコアプロセッサが複数のサブ処理を実行する場合において補間処理を所定周期時間を超えて実行する場合の例を示す図である。図５は、制御対象の軸の個数及び系統数が比較的多いが、加工プログラム読込み処理及び加工プログラム解析処理を一定の処理時間内に完了する必要がない場合の例を示す図である。 FIG. 5 is a diagram illustrating an example of a case where one core processor executes a plurality of sub-processes and performs an interpolation process beyond a predetermined cycle time. FIG. 5 is a diagram illustrating an example in which the number of axes to be controlled and the number of systems are relatively large, but the machining program reading process and the machining program analysis process do not need to be completed within a certain processing time.
　図５は、例えば数値制御装置１が４系統で１６個の軸を制御する場合において、リアルタイムで行われなければならない軸制御処理、加減速処理及び補間処理の合計時間が所定周期時間を超えている様子を示している。リアルタイムで行わなければならない処理が所定周期時間で行われない場合、従来、所定周期時間を延ばし、制御の応答性についての要求を低下させる対応がとられる。又は、従来、リアルタイムで行われなければならない処理の負荷を軽減してリアルタイムで行わなければならない処理を所定周期時間以内で実行することにより、制御の応答性についての要求を保つ対応がとられる。 FIG. 5 shows that, for example, when the numerical controller 1 controls 16 axes by four systems, the total time of the axis control processing, acceleration / deceleration processing, and interpolation processing that must be performed in real time exceeds a predetermined cycle time. Is shown. In the case where processing that must be performed in real time is not performed in a predetermined cycle time, conventionally, the predetermined cycle time is extended to reduce the demand for control responsiveness. Alternatively, conventionally, by reducing the load of the processing that must be performed in real time and executing the processing that must be performed in real time within a predetermined period of time, it is possible to keep the demand for control responsiveness.
　図６は、実施の形態１にかかる数値制御装置１において処理が分散されて複数のコアプロセッサに割り当てられて処理が実行される処理パターンの第１の例を示す図である。図６は、複数の処理パターンのうちのひとつの処理パターンを示している。図６が示す処理パターンでは、制御対象の軸についての複数の処理と、系統についての複数の処理とが分割されている。複数のサブ処理は分散され、複数のサブ処理の各々は複数のコアプロセッサのいずれかに割り当てられている。以下では、系統についての複数のサブ処理は「系統処理」と記載される場合がある。 FIG. 6 is a diagram illustrating a first example of a processing pattern in which processing is distributed in the numerical control device 1 according to the first embodiment and the processing is executed by being allocated to a plurality of core processors. FIG. 6 shows one of the plurality of processing patterns. In the processing pattern shown in FIG. 6, a plurality of processes for the axis to be controlled and a plurality of processes for the system are divided. The plurality of sub-processes are distributed, and each of the plurality of sub-processes is assigned to one of the plurality of core processors. Hereinafter, a plurality of sub-processes for a system may be described as “system process”.
　具体的には、図６が示す処理パターンは、第１コアプロセッサが、軸制御処理のうちの共通処理を実行すると共に、第１軸から第４軸までの各軸についての軸制御処理を実行することを示している。図６が示す処理パターンは、第２コアプロセッサが第５軸から第８軸までの各軸についての軸制御処理を実行し、第３コアプロセッサが第９軸から第１２軸までの各軸についての軸制御処理を実行し、第４コアプロセッサが第１３軸から第１６軸までの各軸についての軸制御処理を実行することを更に示している。 Specifically, in the processing pattern shown in FIG. 6, the first core processor executes the common processing of the axis control processing and executes the axis control processing for each axis from the first axis to the fourth axis. It indicates that In the processing pattern shown in FIG. 6, the second core processor executes the axis control processing for each axis from the fifth axis to the eighth axis, and the third core processor executes the axis control processing for each axis from the ninth axis to the twelfth axis. It is further shown that the fourth core processor executes the axis control processing of each axis from the thirteenth axis to the sixteenth axis.
　図６が示す処理パターンでは、各コアプロセッサに割り当てられる軸の個数は同じである。しかしながら、複数の軸の各々についての制御処理時間をもとに、各コアプロセッサにおける処理時間が均等になるように、コアプロセッサに割り当てる軸の個数をコアプロセッサ毎に異なる個数としてもよい。 で は In the processing pattern shown in FIG. 6, the number of axes assigned to each core processor is the same. However, based on the control processing time for each of the plurality of axes, the number of axes allocated to the core processors may be different for each core processor so that the processing time in each core processor is equal.
　図６が示す処理パターンは、第１コアプロセッサが、系統処理のうちの共通処理を実行すると共に、１系統目についての処理を実行することを更に示している。図６が示す処理パターンは、第２コアプロセッサが２系統目についての処理を実行し、第３コアプロセッサが３系統目についての処理を実行し、第４コアプロセッサが４系統目についての処理を実行することを更に示している。 (6) The processing pattern shown in FIG. 6 further indicates that the first core processor executes the common processing of the system processing and also executes the processing of the first system. In the processing pattern shown in FIG. 6, the second core processor executes the processing for the second system, the third core processor executes the processing for the third system, and the fourth core processor executes the processing for the fourth system. It further illustrates performing.
　図６が示す処理パターンでは、各コアプロセッサに割り当てられる系統の個数は同じである。しかしながら、数値制御装置１が４系統以上の処理を実行する場合、複数の系統の各々についての処理時間をもとに、各コアプロセッサにおける処理時間が均等になるように、コアプロセッサに割り当てる系統の個数をコアプロセッサ毎に異なる個数としてもよい。 で は In the processing pattern shown in FIG. 6, the number of systems assigned to each core processor is the same. However, when the numerical controller 1 executes the processing of four or more systems, based on the processing time of each of the plurality of systems, the number of systems assigned to the core processors is equalized so that the processing time in each core processor is equal. The number may be different for each core processor.
　図７は、実施の形態１にかかる数値制御装置１において処理が分散されて複数のコアプロセッサに割り当てられて処理が実行される処理パターンの第２の例を示す図である。図７も、複数の処理パターンのうちのひとつの処理パターンを示している。図７が示す処理パターンは、第１コアプロセッサが、軸制御処理のうちの共通処理を実行することと、第１軸から第８軸までの各軸についての処理を実行することとを示している。図７が示す処理パターンは、第１コアプロセッサが、１系統目についての系統処理を実行することと、２系統目についての系統処理を実行することとを更に示している。 FIG. 7 is a diagram illustrating a second example of a processing pattern in which the processing is distributed in the numerical control device 1 according to the first embodiment and the processing is executed by being allocated to a plurality of core processors. FIG. 7 also shows one of the plurality of processing patterns. The processing pattern shown in FIG. 7 indicates that the first core processor executes common processing of the axis control processing and executes processing for each axis from the first axis to the eighth axis. I have. The processing pattern shown in FIG. 7 further indicates that the first core processor executes the system processing for the first system and executes the system processing for the second system.
　図７が示す処理パターンは、第２コアプロセッサが、第９軸から第１６軸までの各軸についての処理を実行することと、３系統目についての系統処理を実行することと、４系統目についての系統処理を実行することとを更に示している。図７が示す処理パターンは、第３コアプロセッサが、Ｉ／Ｏ制御処理、ＨＭＩ処理及び通信処理を実行することを更に示している。Ｉ／Ｏ制御処理、ＨＭＩ処理及び通信処理は、リアルタイムに実行されなくてもよい処理である。図７が示す処理パターンは、第４コアプロセッサが、別タスク処理及び別関数処理を実行することを更に示している。別タスク処理及び別関数処理は、図２において示されていないサブ処理である。 The processing pattern shown in FIG. 7 indicates that the second core processor executes processing for each axis from the ninth axis to the sixteenth axis, executes system processing for the third system, and executes processing for the fourth system. Executing the system processing for The processing pattern shown in FIG. 7 further indicates that the third core processor executes the I / O control processing, the HMI processing, and the communication processing. The I / O control processing, the HMI processing, and the communication processing need not be executed in real time. The processing pattern shown in FIG. 7 further indicates that the fourth core processor executes another task process and another function process. The different task process and the different function process are sub-processes not shown in FIG.
　図７が示す処理パターンは、リソースの半分を軸処理及び系統処理に割り当てている。リソースは、複数のコアプロセッサを意味する。しかしながら、軸処理及び系統処理に割り当てられるコアプロセッサの個数は、変更されてもよい。処理パターンは、軸処理及び系統処理が割り当てられるコアプロセッサの個数に対応して用意される。 処理 The processing pattern shown in FIG. 7 allocates half of the resources to axis processing and system processing. Resource means a plurality of core processors. However, the number of core processors allocated to axis processing and system processing may be changed. Processing patterns are prepared corresponding to the number of core processors to which axis processing and system processing are assigned.
　図８は、実施の形態１にかかる数値制御装置１において処理が分散されて複数のコアプロセッサに割り当てられて処理が実行される処理パターンの第３の例を示す図である。図８も、複数の処理パターンのうちのひとつの処理パターンを示している。図８が示す処理パターンは、ひとつのタスクのサブ処理がひとつのコアプロセッサに割り当てられて実行される処理パターンである。 FIG. 8 is a diagram illustrating a third example of a processing pattern in which processing is distributed in the numerical control device 1 according to the first embodiment, and the processing is executed by being allocated to a plurality of core processors. FIG. 8 also shows one of the plurality of processing patterns. The processing pattern shown in FIG. 8 is a processing pattern in which sub-processing of one task is assigned to one core processor and executed.
　図８が示す処理パターンは、第１コアプロセッサが軸制御処理と加減速処理とを実行し、第２コアプロセッサが補間処理を実行することを示している。図８が示す処理パターンは、第３コアプロセッサが加工プログラム読込み処理と加工プログラム解析処理とを実行し、第４コアプロセッサがＩ／Ｏ制御処理、ＨＭＩ処理及び通信処理を実行することを更に示している。軸制御処理、加減速処理及び補間処理といったリアルタイムに実行する必要があるサブ処理が割り当てられるコアプロセッサの個数は変更されてもよい。処理パターンは、リアルタイムに実行する必要があるサブ処理が割り当てられるコアプロセッサの個数に対応して用意される。 8 indicates that the first core processor executes the axis control process and the acceleration / deceleration process, and the second core processor executes the interpolation process. The processing pattern shown in FIG. 8 further indicates that the third core processor executes the processing program reading processing and the processing program analysis processing, and the fourth core processor executes the I / O control processing, the HMI processing, and the communication processing. ing. The number of core processors to which sub-processes that need to be executed in real time, such as the axis control process, the acceleration / deceleration process, and the interpolation process, may be changed. The processing pattern is prepared corresponding to the number of core processors to which sub-processes that need to be executed in real time are allocated.
　図８が示す処理パターンは、独立して計算することができる複数のサブ処理が並列に実行される処理パターンである。更に言うと、図８が示す処理パターンは、ひとつの周期において、各タスクのサブ処理の実行順が変わらない処理パターンである。 処理 The processing pattern shown in FIG. 8 is a processing pattern in which a plurality of sub-processes that can be calculated independently are executed in parallel. Furthermore, the processing pattern shown in FIG. 8 is a processing pattern in which the execution order of the sub-processing of each task does not change in one cycle.
　パターン決定部４は、複数の処理パターンから処理の負荷を分散するための処理パターンをひとつ選択する。パターン決定部４は、複数のコアプロセッサの各々が実行するサブ処理を特定する処理パターンを決定する。具体的には、パターン決定部４は、リソース情報に含まれるマルチコアプロセッサ２を構成するコアプロセッサの個数をもとに、複数の処理パターンから当該個数のコアプロセッサがサブ処理を実行することになる複数の処理パターンを選択する。 The pattern determination unit 4 selects one processing pattern for distributing the processing load from a plurality of processing patterns. The pattern determining unit 4 determines a processing pattern that specifies a sub-process executed by each of the plurality of core processors. Specifically, based on the number of core processors included in the multi-core processor 2 included in the resource information, the pattern determination unit 4 causes the number of core processors to execute sub-processing from a plurality of processing patterns. Select multiple processing patterns.
　実施の形態１では、パターン決定部４は、４個のコアプロセッサが処理を実行することになる処理パターンを選択する。コアプロセッサの個数が８である場合、パターン決定部４は、８個のコアプロセッサが処理を実行することになる処理パターンを選択する。 In the first embodiment, the pattern determining unit 4 selects a processing pattern in which four core processors will execute processing. When the number of core processors is 8, the pattern determination unit 4 selects a processing pattern in which the eight core processors execute processing.
　図９は、実施の形態１にかかる数値制御装置１によって実行される複数のサブ処理の各々の処理時間及び実行周期を示す図である。サブ処理の内容を示す処理関数及び処理タスク毎に、処理時間が予め計測される。図９には、共通の処理が必要な時間である共通処理時間ｔ１と、単位処理当たりの処理時間ｔ２とが示されている。単位処理当たりの処理時間ｔ２の例は、ひとつの軸当たり又はひとつの系統当たりの処理時間である。 FIG. 9 is a diagram showing the processing time and execution cycle of each of a plurality of sub-processes executed by the numerical controller 1 according to the first embodiment. The processing time is measured in advance for each processing function and processing task indicating the content of the sub-processing. FIG. 9 shows a common processing time t1 that is a time required for common processing and a processing time t2 per unit processing. An example of the processing time t2 per unit processing is the processing time per axis or per system.
　図９において、加工プログラム読込み処理については、処理時間ｔ２は、ひとつの加工プログラムを読込む際の処理時間である。加工プログラム解析処理については、処理時間ｔ２は、ひとつの加工プログラムを解析する際の処理時間である。図９には、図２に示されていないサブ処理Ａ、サブ処理Ｂ及びサブ処理Ｃについての処理時間及び実行周期も示されている。図９における実行周期は、単位周期の倍数で示されている。 In FIG. 9, in the processing program reading processing, the processing time t2 is the processing time for reading one processing program. In the machining program analysis processing, the processing time t2 is the processing time when analyzing one machining program. FIG. 9 also shows the processing time and execution cycle for the sub-process A, the sub-process B, and the sub-process C not shown in FIG. The execution cycle in FIG. 9 is indicated by a multiple of the unit cycle.
　マルチコアプロセッサが処理を実行する際のオーバヘッド時間が、時間ｔ３であると仮定する。この場合、機械構成情報に含まれる系統数がｎであり、軸の個数がｍであるとき、系統数に依存する処理時間ｔ_ｋは下記の式（１）で表現され、軸の個数に依存する処理時間ｔ_ｊは下記の式（２）で表現される。
　　ｔ_ｋ=ｔ１_ｋ＋ｔ２_ｋ×ｎ＋ｔ３_ｋ　・・・（１）
　　ｔ_ｊ=ｔ１_ｊ＋ｔ２_ｊ×ｍ＋ｔ３_ｊ　・・・（２）
　添え字_ｋは系統数に依存する時間を表し、添え字_ｊは軸の個数に依存する時間を表している。 It is assumed that the overhead time when the multi-core processor executes processing is time t3. In this case, when the number of systems included in the machine configuration information is n and the number of axes is m, the processing time t_k depending on the number of systems is expressed by the following equation (1), and depends on the number of axes. The processing time t_j is expressed by the following equation (2).
t_k = t1_k + t2_k × n + t3_k (1)
t_j = t1_j + t2_j × m + t3_j (2)
The suffix _k represents time dependent on the number of systems, and the suffix _j represents time dependent on the number of axes.
　各処理関数及び処理タスクの処理時間は、事前に数値制御装置１とは別の数値制御装置で計測されていてもよい。各処理関数及び処理タスクの処理時間は、数値制御装置１が処理時間を計測する計測手段を有していて、計測手段が数値制御装置１の立ち上がり時に各処理の処理時間を計測してソフトウェア構成情報に処理時間テーブルを含めてもよい。パターン決定部４は、計測手段の機能を有していてもよい。 処理 The processing time of each processing function and processing task may be measured in advance by a numerical control device different from the numerical control device 1. The processing time of each processing function and processing task has a software configuration in which the numerical controller 1 has a measuring means for measuring the processing time, and the measuring means measures the processing time of each processing when the numerical controller 1 starts up. The information may include a processing time table. The pattern determining unit 4 may have a function of a measuring unit.
　図１０は、実施の形態１にかかる数値制御装置１が有するパターン決定部４の動作の手順の一例を示すフローチャートである。パターン決定部４は、ステップＳ１において、リソース情報からマルチコアプロセッサ２を構成するコアプロセッサの個数を示す情報を取得する。パターン決定部４は、ステップＳ２において、ステップＳ１において取得された情報が示す個数に対応する処理パターンを抽出する。抽出された処理パターンの例は、図６から図８が示す処理パターンである。 FIG. 10 is a flowchart illustrating an example of an operation procedure of the pattern determining unit 4 included in the numerical controller 1 according to the first embodiment. In step S1, the pattern determination unit 4 acquires information indicating the number of core processors constituting the multi-core processor 2 from the resource information. In step S2, the pattern determining unit 4 extracts processing patterns corresponding to the number indicated by the information acquired in step S1. Examples of the extracted processing patterns are the processing patterns shown in FIGS.
　パターン決定部４は、ステップＳ３において、ステップＳ２において抽出されたひとつの処理パターンについて、機械構成情報とソフトウェア構成情報とをもとに各タスクの処理時間を計算し、当該処理パターンで実行周期にかかる処理時間を計算する。パターン決定部４は、ステップＳ４において、ステップＳ２において抽出されたすべての処理パターンの処理時間が計算されたか否かを判定する。パターン決定部４は、抽出されてすべての処理パターンの処理時間が計算されていないと判定した場合（ステップＳ４でＮｏ）、ステップＳ３の動作を行う。 In step S3, the pattern determination unit 4 calculates the processing time of each task for one of the processing patterns extracted in step S2 based on the machine configuration information and the software configuration information, and determines the execution period in the processing pattern. The processing time is calculated. In step S4, the pattern determination unit 4 determines whether or not the processing times of all the processing patterns extracted in step S2 have been calculated. If the pattern determination unit 4 determines that the processing times of all the extracted processing patterns have not been calculated (No in step S4), the pattern determination unit 4 performs the operation of step S3.
　パターン決定部４は、抽出されたすべての処理パターンの処理時間が計算されたと判定した場合（ステップＳ４でＹｅｓ）、ステップＳ５において、抽出された処理パターンのなかから、マルチコアプロセッサ２が処理を実行する際の処理時間が、複数のコアプロセッサのうちのひとつのコアプロセッサが上記の処理を実行する際の処理時間より短くなる処理パターンを選択する。ステップＳ５において、パターン決定部４は、選択することによってマルチコアプロセッサ２が実行する処理パターンを決定する。 If the pattern determination unit 4 determines that the processing times of all the extracted processing patterns have been calculated (Yes in step S4), the multi-core processor 2 executes the processing from among the extracted processing patterns in step S5. A processing pattern in which the processing time when performing the above processing is shorter than the processing time when one of the plurality of core processors executes the above processing is selected. In step S5, the pattern determination unit 4 determines a processing pattern to be executed by the multi-core processor 2 by making a selection.
　系統数が比較的少なく、比較的短い線分長で記載された加工プログラムで所定周期以内に加工プログラム解析処理も実行する必要がある場合、例えば、パターン決定部４は、所定の周期を２周期として実行周期にかかる処理時間を計算する。図６が示す処理パターンでは、軸制御処理及び補間処理の個数がコアプロセッサの個数より少ないので、処理を分散してもコアプロセッサが処理を行わない空き時間が発生する。 When the number of systems is relatively small and a machining program described with a relatively short line segment length also needs to execute a machining program analysis process within a predetermined cycle, for example, the pattern determination unit 4 sets the predetermined cycle to two cycles To calculate the processing time required for the execution cycle. In the processing pattern shown in FIG. 6, since the number of axis control processing and interpolation processing is smaller than the number of core processors, even when the processing is distributed, idle time occurs in which the core processor does not perform processing.
　図７が示す処理パターンでは、図６が示す処理パターンに比べて空き時間は少なくなり、処理時間は図６が示す処理パターンにおける処理時間より短い。図８が示す処理パターンでは、軸制御処理、加減速処理、補間処理、加工プログラム読込み処理及び加工プログラム解析処理の処理時間のバランスが図６及び図７が示す処理パターンにおける処理時間のバランスよりよく、処理時間も比較的短い。 空 き In the processing pattern shown in FIG. 7, the idle time is shorter than in the processing pattern shown in FIG. 6, and the processing time is shorter than the processing time in the processing pattern shown in FIG. In the processing pattern shown in FIG. 8, the processing time balance of the axis control processing, the acceleration / deceleration processing, the interpolation processing, the processing program reading processing, and the processing program analysis processing is better than the processing time balance in the processing patterns shown in FIGS. Also, the processing time is relatively short.
　パターン決定部４は、図６から図８が示す３個の処理パターンのなかで処理時間が最も短い図８が示す処理パターンを選択する。割り当て部５は、パターン決定部４によって決定された処理パターンをもとに、軸制御処理と加減速処理とを第１コアプロセッサに割り当て、補間処理を第２コアプロセッサに割り当てる。加えて、割り当て部５は、加工プログラム読込み処理と加工プログラム解析処理とを第３コアプロセッサに割り当て、Ｉ／Ｏ制御処理、ＨＭＩ処理及び通信処理を第４コアプロセッサに割り当てる。 The pattern determination unit 4 selects the processing pattern shown in FIG. 8 having the shortest processing time among the three processing patterns shown in FIGS. The allocating unit 5 allocates the axis control processing and the acceleration / deceleration processing to the first core processor and allocates the interpolation processing to the second core processor based on the processing pattern determined by the pattern determining unit 4. In addition, the allocating unit 5 allocates the processing program reading processing and the processing program analysis processing to the third core processor, and allocates the I / O control processing, the HMI processing, and the communication processing to the fourth core processor.
　数値制御装置１が、加工プログラムにおける指令系統が４系統であって軸の個数が１６個である多軸多系統制御を行う場合、例えば、パターン決定部４は、所定周期を２周期として実行周期にかかる処理時間を計算する。図６が示す処理パターンでは、各コアプロセッサに４軸の軸制御処理を割り当てることができると共に、各コアプロセッサに１系統の補間処理を割り当てることができる。そのため、図６が示す処理パターンは、処理時間を比較的短くすることができる。 When the numerical control device 1 performs multi-axis multi-system control in which the number of command systems in the machining program is four and the number of axes is 16, for example, the pattern determination unit 4 sets the execution cycle to two predetermined cycles. Calculate the processing time required for. In the processing pattern shown in FIG. 6, four-axis control processing can be assigned to each core processor, and one system of interpolation processing can be assigned to each core processor. Therefore, the processing pattern shown in FIG. 6 can make the processing time relatively short.
　図７が示す処理パターンでは、リアルタイムで処理を実行する必要があるコアプロセッサの個数が２個である。そのため、図６が示す処理パターンでは４つのコアプロセッサで処理を実行していた軸制御処理、および、補間処理を図７が示す処理パターンでは、２つのコアプロセッサで処理を実行することになるため、図７が示す処理パターンでの処理時間は、図６が示す処理パターンでの処理時間より長くなる。 で は In the processing pattern shown in FIG. 7, the number of core processors that need to execute processing in real time is two. For this reason, in the processing pattern shown in FIG. 6, the axis control processing and the interpolation processing which were executed by the four core processors are performed. In the processing pattern shown in FIG. 7, the processing is executed by the two core processors. The processing time in the processing pattern shown in FIG. 7 is longer than the processing time in the processing pattern shown in FIG.
　図８が示す処理パターンは、系統数及び軸数に比例して大きくなった軸制御処理及び補間処理を第１コアプロセッサ及び第２コアプロセッサに割り当てるパターンである。このケースでは、処理時間は、図６が示す処理パターンでの処理時間よりも長く、図７が示す処理パターンでの処理時間よりも短い。 処理 The processing pattern shown in FIG. 8 is a pattern in which the axis control processing and the interpolation processing, which are increased in proportion to the number of systems and the number of axes, are assigned to the first core processor and the second core processor. In this case, the processing time is longer than the processing time in the processing pattern shown in FIG. 6 and shorter than the processing time in the processing pattern shown in FIG.
　パターン決定部４は、図６から図８が示す３個の処理パターンのなかで処理時間が最も短い図６が示す処理パターンを選択する。割り当て部５は、パターン決定部４によって選択された処理パターンをもとに、共通処理と、第１軸及び１系統目の処理とを第１コアプロセッサに割り当てる。割り当て部５は、第２軸及び２系統目の処理を第２コアプロセッサに割り当て、第３軸及び３系統目の処理を第３コアプロセッサに割り当て、第４軸及び４系統目の処理を第４コアプロセッサに割り当てる。 The pattern determination unit 4 selects the processing pattern shown in FIG. 6 which has the shortest processing time among the three processing patterns shown in FIGS. The allocating unit 5 allocates the common processing and the processing of the first axis and the first system to the first core processor based on the processing pattern selected by the pattern determining unit 4. The allocating unit 5 allocates the second axis and the second system to the second core processor, allocates the third axis and the third system to the third core processor, and allocates the fourth axis and the fourth system to the second core processor. Assign to a 4-core processor.
　上述の通り、実施の形態１にかかる数値制御装置１は、リソース情報、機械構成情報及びソフトウェア構成情報をもとに、処理パターン情報が示す複数の処理パターンのなかから、マルチコアプロセッサ２が実行する処理の時間が、上記の複数のコアプロセッサのうちのひとつのコアプロセッサが上記の処理を実行する場合の処理時間より短くなる処理パターンを選択する。数値制御装置１は、選択された処理パターンを複数のコアプロセッサが上記の処理を実行する際の処理パターンと決定する。 As described above, the numerical control device 1 according to the first embodiment is executed by the multi-core processor 2 from a plurality of processing patterns indicated by the processing pattern information based on the resource information, the machine configuration information, and the software configuration information. A processing pattern in which the processing time is shorter than the processing time when one of the plurality of core processors executes the above processing is selected. The numerical controller 1 determines the selected processing pattern as a processing pattern when a plurality of core processors execute the above processing.
　例えば、数値制御装置１は、リソース情報、機械構成情報及びソフトウェア構成情報をもとに、複数の処理パターンのなかから、マルチコアプロセッサ２が実行する処理の時間が最短となる処理パターンを選択する。数値制御装置１は、選択された処理パターンを複数のコアプロセッサが上記の処理を実行する際の処理パターンと決定する。 {For example, the numerical controller 1 selects a processing pattern that minimizes the processing time of the multi-core processor 2 from a plurality of processing patterns based on the resource information, the machine configuration information, and the software configuration information. The numerical controller 1 determines the selected processing pattern as a processing pattern when a plurality of core processors execute the above processing.
　数値制御装置１は、決定された処理パターンにしたがって、上記の処理を構成する複数のサブ処理を分散させて複数のコアプロセッサに割り当てる。複数の処理パターンの各々は、上記の処理を構成する複数のサブ処理のうちの実行される順序の変更が許可されない複数のサブ処理を順序が変更されることなく実行させる処理パターンである。 (4) The numerical controller 1 distributes a plurality of sub-processes constituting the above process and allocates them to a plurality of core processors according to the determined process pattern. Each of the plurality of processing patterns is a processing pattern for performing, without changing the order, a plurality of sub-processes of the plurality of sub-processes constituting the above-described process, the order of which is not allowed to be changed.
　したがって、数値制御装置１は、実行される処理が複数のサブ処理に分割された場合に複数のサブ処理のうちの実行される順序の変更が許可されない複数のサブ処理を処理の順序が変更されることなく実行することができる。加えて、数値制御装置１は、ひとつのコアプロセッサが上記の処理を実行する際の処理時間より短い処理時間で上記の処理を実行することができる。 Therefore, when the process to be executed is divided into a plurality of sub-processes, the numerical controller 1 changes the order of the plurality of sub-processes in which the change of the execution order among the plurality of sub-processes is not permitted. Can be performed without any In addition, the numerical controller 1 can execute the above processing in a processing time shorter than the processing time when one core processor executes the above processing.
実施の形態２．
　図１１は、実施の形態２にかかる数値制御装置１Ａの構成を示す図である。数値制御装置１Ａは、第１コアプロセッサ２１、第２コアプロセッサ２２及び第３コアプロセッサ２３を含むマルチコアプロセッサ２Ａと、記憶部３Ａと、パターン決定部４とを有する。第１コアプロセッサ２１、第２コアプロセッサ２２及び第３コアプロセッサ２３及びパターン決定部４の各々は、実施の形態１において説明された構成要素である。記憶部３Ａは、実施の形態１の記憶部３と同様に、処理パターン情報、リソース情報、機械構成情報及びソフトウェア構成情報を記憶する。 Embodiment 2 FIG.
FIG. 11 is a diagram illustrating a configuration of a numerical controller 1A according to the second embodiment. The numerical control device 1A includes a multi-core processor 2A including a first core processor 21, a second core processor 22, and a third core processor 23, a storage unit 3A, and a pattern determination unit 4. Each of the first core processor 21, the second core processor 22, the third core processor 23, and the pattern determining unit 4 is a component described in the first embodiment. The storage unit 3A stores processing pattern information, resource information, machine configuration information, and software configuration information, similarly to the storage unit 3 of the first embodiment.
　数値制御装置１Ａは、通信ネットワーク１６を介して他の数値制御装置１Ｂに接続されている。他の数値制御装置１Ｂは、数値制御装置１Ａと同様な装置である。数値制御装置１Ａは、複数のサブ処理の一部を他の数値制御装置１Ｂに割り当てると共に、当該複数のサブ処理の残部を数値制御装置１Ａに割り当てる割り当て部５Ａを更に有する。割り当て部５Ａは、数値制御装置１Ａのマルチコアプロセッサ２Ａが当該残部を実行する期間に、当該一部を他の数値制御装置１Ｂに実行させる。他の数値制御装置１Ｂは、パターン決定部４及び割り当て部５Ａを有していない。 The numerical control device 1A is connected to another numerical control device 1B via the communication network 16. The other numerical controller 1B is the same device as the numerical controller 1A. The numerical control device 1A further includes an allocating unit 5A that allocates a part of the plurality of sub-processes to another numerical control device 1B and allocates the rest of the plurality of sub-processes to the numerical control device 1A. The allocating unit 5A causes the other numerical control device 1B to execute the part while the multicore processor 2A of the numerical control device 1A executes the remaining portion. The other numerical control device 1B does not include the pattern determination unit 4 and the assignment unit 5A.
　実施の形態２では、加工プログラムの指令系統数が２個以上であり、制御軸の個数が３２個であり、制御系統数が８系統である多軸多系統制御が行われる場合を想定する。実施の形態２では、当該場合において、数値制御装置１Ａがひとつの処理パターンを選択して、処理を、マルチコアプロセッサ２Ａを構成する複数のコアプロセッサと、他の数値制御装置１Ｂに分散させる例を説明する。 In the second embodiment, it is assumed that the number of command systems of the machining program is two or more, the number of control axes is 32, and the multi-axis multi-system control in which the number of control systems is eight is performed. In the second embodiment, in this case, an example in which the numerical controller 1A selects one processing pattern and distributes the processing to a plurality of core processors constituting the multi-core processor 2A and another numerical controller 1B. explain.
　図１２は、実施の形態２にかかる数値制御装置１Ａと他の数値制御装置１Ｂとにおいて処理が実行される処理パターンの第１の例を示す図である。図１２が示す処理パターンは、数値制御装置１Ａの第１コアプロセッサが、Ｉ／Ｏ制御処理と、第１軸から第１６軸までの各軸についての軸制御処理と、第１軸から第１６軸までの各軸についての加減速処理とを実行することを示している。 FIG. 12 is a diagram illustrating a first example of a processing pattern in which processing is performed in the numerical controller 1A according to the second embodiment and another numerical controller 1B. The processing pattern shown in FIG. 12 is such that the first core processor of the numerical controller 1A performs I / O control processing, axis control processing for each axis from the first axis to the 16th axis, and 16th to 16th axes. This shows that the acceleration and deceleration processing for each axis up to the axis is executed.
　図１２が示す処理パターンは、数値制御装置１Ａの第２コアプロセッサが、ＨＭＩ処理と、１系統から４系統までの各系統についての補間処理とを実行することを更に示している。図１２が示す処理パターンは、数値制御装置１Ａの第３コアプロセッサが、通信処理と、加工プログラム読込み処理と、加工プログラム解析処理とを実行することを更に示している。 処理 The processing pattern shown in FIG. 12 further indicates that the second core processor of the numerical controller 1A executes the HMI processing and the interpolation processing for each of 1 to 4 systems. The processing pattern shown in FIG. 12 further indicates that the third core processor of the numerical controller 1A executes the communication processing, the processing program reading processing, and the processing program analysis processing.
　図１２が示す処理パターンは、他の数値制御装置１Ｂの第１コアプロセッサが、Ｉ／Ｏ制御処理と、第１７軸から第３２軸までの各軸についての軸制御処理と、第１７軸から第３２軸までの各軸についての加減速処理とを実行することを更に示している。図１２が示す処理パターンは、他の数値制御装置１Ｂの第２コアプロセッサが、ＨＭＩ処理と、５系統から８系統までの各系統についての補間処理とを実行することを更に示している。図１２が示す処理パターンは、他の数値制御装置１Ｂの第３コアプロセッサが、通信処理と、加工プログラム読込み処理と、加工プログラム解析処理とを実行することを更に示している。 The processing pattern shown in FIG. 12 is such that the first core processor of the other numerical controller 1B performs I / O control processing, axis control processing for each of the 17th to 32nd axes, and It also shows that the acceleration and deceleration processing for each axis up to the 32nd axis is executed. The processing pattern shown in FIG. 12 further indicates that the second core processor of the other numerical controller 1B executes the HMI processing and the interpolation processing for each of the five to eight systems. The processing pattern shown in FIG. 12 further indicates that the third core processor of the other numerical control device 1B executes a communication process, a machining program reading process, and a machining program analysis process.
　図１２が示す処理パターンでは、数値制御装置１Ａにおいて実行される処理の軸の個数及び系統数は、他の数値制御装置１Ｂにおいて実行される処理の軸の個数及び系統数と同じである。しかしながら、数値制御装置１Ａにおいて実行される処理の軸の個数及び系統数は、他の数値制御装置１Ｂにおいて実行される処理の軸の個数及び系統数と異なっていてもよい。 In the processing pattern shown in FIG. 12, the number of axes and the number of systems of processing executed in the numerical controller 1A are the same as the number of axes and the number of systems of processing executed in the other numerical controllers 1B. However, the number of axes and the number of systems of processing executed in the numerical controller 1A may be different from the number of axes and the number of systems of processing executed in another numerical controller 1B.
　処理の負荷が比較的大きい１系統及び２系統の補間処理が数値制御装置１Ａにおいて行われ、３系統から８系統までの補間処理が他の数値制御装置１Ｂにおいて実行される処理パターンが用意されてもよい。同様に、数値制御装置１Ａにおいて実行される処理の軸の個数と他の数値制御装置１Ｂにおいて実行される処理の軸の個数とが異なる処理パターンが用意されてもよい。 A processing pattern is prepared in which the numerical control device 1A performs interpolation processing of one system and two systems having a relatively large processing load, and performs interpolation processing of three to eight systems in another numerical control device 1B. Is also good. Similarly, a processing pattern in which the number of axes for processing executed in the numerical controller 1A and the number of axes for processing executed in the other numerical controllers 1B are different may be prepared.
　図１３は、実施の形態２にかかる数値制御装置１Ａと他の数値制御装置１Ｂとにおいて処理が実行される処理パターンの第２の例を示す図である。図１３が示す処理パターンは、数値制御装置１Ａの第１コアプロセッサが、Ｉ／Ｏ制御処理と、補間処理とを実行することを示している。 FIG. 13 is a diagram illustrating a second example of a processing pattern in which the numerical controller 1A according to the second embodiment and the other numerical controller 1B perform processing. The processing pattern shown in FIG. 13 indicates that the first core processor of the numerical control device 1A executes the I / O control processing and the interpolation processing.
　図１３が示す処理パターンは、数値制御装置１Ａの第２コアプロセッサが、ＨＭＩ処理と、補間処理とを実行することを更に示している。図１３が示す処理パターンは、数値制御装置１Ａの第３コアプロセッサが、通信処理と、加工プログラム読込み処理と、加工プログラム解析処理とを実行することを更に示している。 The processing pattern shown in FIG. 13 further indicates that the second core processor of the numerical controller 1A executes the HMI processing and the interpolation processing. The processing pattern shown in FIG. 13 further indicates that the third core processor of the numerical controller 1A executes communication processing, processing program reading processing, and processing program analysis processing.
　図１３が示す処理パターンは、他の数値制御装置１Ｂの第１コアプロセッサが、Ｉ／Ｏ制御処理と、軸制御処理と、加減速処理とを実行することを更に示している。図１３が示す処理パターンは、他の数値制御装置１Ｂの第２コアプロセッサが、ＨＭＩ処理と、軸制御処理と、加減速処理とを実行することを更に示している。図１３が示す処理パターンは、他の数値制御装置１Ｂの第３コアプロセッサが、通信処理と、軸制御処理と、加減速処理とを実行することを更に示している。 (13) The processing pattern shown in FIG. 13 further indicates that the first core processor of the other numerical controller 1B executes the I / O control processing, the axis control processing, and the acceleration / deceleration processing. The processing pattern shown in FIG. 13 further indicates that the second core processor of the other numerical control device 1B executes the HMI processing, the axis control processing, and the acceleration / deceleration processing. The processing pattern shown in FIG. 13 further indicates that the third core processor of the other numerical controller 1B executes the communication processing, the axis control processing, and the acceleration / deceleration processing.
　加工プログラム読込み処理及び加工プログラム解析処理は、数値制御装置１Ａにおいて実行されるのではなく、他の数値制御装置１Ｂにおいて実行されてもよい。上述の通り、数値制御装置１Ａは通信ネットワーク１６を介して他の数値制御装置１Ｂに接続されている。データの通信にかかる処理負荷を軽減するために、ＨＭＩ処理と通信処理との一方又は双方は、数値制御装置１Ａと他の数値制御装置１Ｂとのうちの一方において実行されてもよい。 The machining program reading process and the machining program analysis process may not be executed by the numerical controller 1A, but may be executed by another numerical controller 1B. As described above, the numerical controller 1A is connected to another numerical controller 1B via the communication network 16. In order to reduce the processing load on data communication, one or both of the HMI process and the communication process may be executed in one of the numerical controller 1A and the other numerical controller 1B.
　パターン決定部４は、処理パターン情報が示す複数の処理パターンのなかから、処理の負荷を分散するために、ひとつの処理パターンを選択する。リソース情報は、演算装置の個数が数値制御装置１Ａと他の数値制御装置１Ｂとの２個であることを示す情報を含んでいる。リソース情報は、数値制御装置１Ａ及び他の数値制御装置１Ｂの各々が３個のコアプロセッサを有することを示す情報を含んでいる。 (4) The pattern determining unit 4 selects one processing pattern from among the plurality of processing patterns indicated by the processing pattern information in order to distribute the processing load. The resource information includes information indicating that the number of arithmetic devices is two: the numerical control device 1A and the other numerical control device 1B. The resource information includes information indicating that each of the numerical controller 1A and the other numerical controller 1B has three core processors.
　パターン決定部４は、まず、リソース情報をもとに、すべての演算装置に含まれるコアプロセッサの個数を特定し、特定された個数をもとに、複数の処理パターンのなかで、当該個数に対応する処理パターンを絞り込む。パターン決定部４は、リソース情報をもとに処理パターンを絞り込むことができない場合、つまり想定された個数のリソースが存在しない場合、すべての演算装置に含まれるコアプロセッサの個数より少ない個数のコアプロセッサが処理を実行することになる処理パターンを選択する。 The pattern determination unit 4 first specifies the number of core processors included in all the arithmetic devices based on the resource information, and determines the number of core processors among the plurality of processing patterns based on the specified number. Narrow down the corresponding processing pattern. When the processing pattern cannot be narrowed down based on the resource information, that is, when the assumed number of resources does not exist, the pattern determination unit 4 determines that the number of core processors smaller than the number of core processors included in all the arithmetic devices is Selects a processing pattern that will execute the processing.
　例えばすべての演算装置に含まれるコアプロセッサの個数が６個で、対応する処理パターンが存在しない場合、パターン決定部４は、すべての演算装置に含まれるコアプロセッサの個数が５個である場合の処理パターンを選択する。 For example, when the number of core processors included in all the arithmetic devices is six and there is no corresponding processing pattern, the pattern determination unit 4 determines whether the number of core processors included in all the arithmetic devices is five. Select a processing pattern.
　実施の形態２では、パターン決定部４は、処理パターンをコアプロセッサの個数をもとに選択し、そのなかから処理時間が一番短い処理パターンを選択する。しかしながら、パターン決定部４は、コアプロセッサの個数をもとに処理パターンを選択しなくてもよい。例えば、パターン決定部４は、コアプロセッサの個数を問わず複数の処理パターンの各々の処理時間を計算し、処理時間が一番短い処理パターンを選択してもよい。 In the second embodiment, the pattern determination unit 4 selects a processing pattern based on the number of core processors, and selects a processing pattern having the shortest processing time from among them. However, the pattern determination unit 4 does not have to select a processing pattern based on the number of core processors. For example, the pattern determination unit 4 may calculate the processing time of each of a plurality of processing patterns regardless of the number of core processors, and select the processing pattern with the shortest processing time.
　複数の演算装置が処理を分散して実行する場合においても、複数の演算装置の各々において、各処理関数及び処理タスクの処理時間があらかじめ計測され、更に通信処理にかかる時間も含めて、リアルタイムに実行することが必要な軸制御処理、加減速処理及び補間処理の処理時間が計算される。例えば、パターン決定部４は、計算の結果をもとに、処理時間が一番短い処理パターンを選択する。割り当て部５Ａは、複数のサブ処理を数値制御装置１Ａと他の数値制御装置１Ｂとに割り当てて、割り当てたサブ処理を数値制御装置１Ａ及び他の数値制御装置１Ｂに含まれるコアプロセッサに実行させる。 Even in the case where a plurality of processing units execute processing in a distributed manner, the processing time of each processing function and processing task is measured in advance in each of the plurality of processing units, and the time required for communication processing is further included in real time. The processing times of the axis control processing, acceleration / deceleration processing, and interpolation processing that need to be executed are calculated. For example, the pattern determination unit 4 selects a processing pattern having the shortest processing time based on the calculation result. The allocating unit 5A allocates a plurality of sub-processes to the numerical control device 1A and another numerical control device 1B, and causes the core processors included in the numerical control device 1A and the other numerical control devices 1B to execute the allocated sub-processes. .
　上述の通り、数値制御装置１Ａは、決定された処理パターンにしたがって、上記の処理を構成する複数のサブ処理を分散させて数値制御装置１Ａと他の数値制御装置１Ｂとに含まれる複数のコアプロセッサに割り当てる。したがって、数値制御装置１Ａは、上記の複数のコアプロセッサのうちのひとつのコアプロセッサが上記の処理を実行する場合の処理時間より短い時間で上記の処理を実行することができる。加えて、数値制御装置１Ａは、従来より多い個数の軸の制御と従来より多い系統数の制御とを行うことができる。 As described above, the numerical controller 1A distributes a plurality of sub-processes constituting the above-described processing according to the determined processing pattern, and distributes the plurality of cores included in the numerical controller 1A and the other numerical controller 1B. Assign to processor. Therefore, the numerical control device 1A can execute the above processing in a shorter time than the processing time when one of the plurality of core processors executes the above processing. In addition, the numerical controller 1A can perform control of a larger number of axes than before and control of a larger number of systems than before.
　実施の形態２では、他の数値制御装置１Ｂは割り当て部５Ａを有していない。しかしながら、他の数値制御装置１Ｂは割り当て部５Ａを有していてもよい。数値制御装置１Ａは、数値制御装置１Ａに含まれるパターン決定部４によって決定された処理パターンを示す情報を他の数値制御装置１Ｂに出力し、他の数値制御装置１Ｂに含まれる割り当て部５Ａが、当該処理パターンをもとに、当該処理パターンのなかの実行すべきサブ処理を分散させて他の数値制御装置１Ｂに含まれる複数のコアプロセッサに割り当ててもよい。 In the second embodiment, the other numerical controller 1B does not have the allocating unit 5A. However, another numerical controller 1B may include the allocating unit 5A. The numerical controller 1A outputs information indicating the processing pattern determined by the pattern determining unit 4 included in the numerical controller 1A to another numerical controller 1B, and the allocating unit 5A included in the other numerical controller 1B outputs Based on the processing pattern, the sub-processing to be executed in the processing pattern may be distributed and assigned to a plurality of core processors included in another numerical controller 1B.
　他の数値制御装置１Ｂは、複数のコアプロセッサを有する計算装置に置き換えられてもよい。 The other numerical control device 1B may be replaced by a computing device having a plurality of core processors.
実施の形態３．
　図１４は、実施の形態３にかかる数値制御装置５０の構成を示す図である。数値制御装置５０は、工作機械を制御する装置であって、マルチコアプロセッサ２を有する。マルチコアプロセッサ２は、第１コアプロセッサ２１と、第２コアプロセッサ２２と、第３コアプロセッサ２３と、第４コアプロセッサ２４とを含む。第１コアプロセッサ２１、第２コアプロセッサ２２、第３コアプロセッサ２３及び第４コアプロセッサ２４は、複数のコアプロセッサの一例である。 Embodiment 3 FIG.
FIG. 14 is a diagram illustrating a configuration of a numerical control device 50 according to the third embodiment. The numerical control device 50 is a device that controls a machine tool, and has the multi-core processor 2. The multi-core processor 2 includes a first core processor 21, a second core processor 22, a third core processor 23, and a fourth core processor 24. The first core processor 21, the second core processor 22, the third core processor 23, and the fourth core processor 24 are examples of a plurality of core processors.
　数値制御装置５０は、マルチコアプロセッサ２によって実行される処理を分割し、分割を行うことによって得られた複数の１次サブ処理の個数が複数のコアプロセッサの個数より多い場合、複数の１次サブ処理を一部と残部に分割し、一部を分割して複数の２次サブ処理を得る分割部５１を更に有する。 The numerical controller 50 divides the processing executed by the multi-core processor 2 and, when the number of the plurality of primary sub-processes obtained by performing the division is larger than the number of the plurality of core processors, There is further provided a dividing unit 51 that divides the processing into a part and a remainder, and divides the part to obtain a plurality of secondary sub-processes.
　数値制御装置５０は、分割部５１によって得られた複数の１次サブ処理の残部と、複数の２次サブ処理とを、分散させて複数のコアプロセッサに割り当てる割り当て部５２を更に有する。割り当て部５２は、複数の２次サブ処理の各々についての実行順を保持させる。 The numerical control device 50 further includes an assignment unit 52 that distributes the remainder of the plurality of primary sub-processes obtained by the dividing unit 51 and the plurality of secondary sub-processes and assigns them to a plurality of core processors. The allocating unit 52 holds the execution order for each of the plurality of secondary sub-processes.
　加えて、割り当て部５２は、第１の１次サブ処理を分割することによって得られる第１の２次サブ処理と第２の２次サブ処理との間に、第２の１次サブ処理を分割することによって得られる第３の２次サブ処理を割り込ませる。割り当て部５２は、第１の２次サブ処理、第３の２次サブ処理及び第２の２次サブ処理を、この順に、複数のコアプロセッサのうちのひとつのコアプロセッサに割り当てる。 In addition, the allocating unit 52 performs the second primary sub-process between the first secondary sub-process and the second secondary sub-process obtained by dividing the first primary sub-process. The third secondary sub-process obtained by the division is interrupted. The allocating unit 52 allocates the first secondary sub-process, the third secondary sub-process, and the second secondary sub-process to one of the plurality of core processors in this order.
　さらに、割り当て部５２は、第３の１次サブ処理を分割することによって得られる第４の２次サブ処理と第５の２次サブ処理との間に、第２の１次サブ処理を分割することによって得られる第６の２次サブ処理を割り込ませる。割り当て部５２は、第４の２次サブ処理、第６の２次サブ処理及び第５の２次サブ処理を、この順に、複数のコアプロセッサのうちの別のひとつのコアプロセッサに割り当てる。 Further, the allocating unit 52 divides the second primary sub-process between the fourth secondary sub-process and the fifth secondary sub-process obtained by dividing the third primary sub-process. Then, the sixth secondary sub-process obtained by performing the above-mentioned process is interrupted. The allocating unit 52 allocates the fourth secondary sub-process, the sixth secondary sub-process, and the fifth secondary sub-process to another one of the plurality of core processors in this order.
　数値制御装置５０は、記憶部５３を更に有する。記憶部５３の例は、半導体メモリである。記憶部５３の一部は、不揮発性メモリである。 The numerical control device 50 further includes a storage unit 53. An example of the storage unit 53 is a semiconductor memory. Part of the storage unit 53 is a nonvolatile memory.
　以下に、数値制御装置５０が行う動作について説明する。図１５は、実施の形態３にかかる数値制御装置５０が有するマルチコアプロセッサ２に含まれるコアプロセッサの個数が制御対象物の軸の個数より少ない場合の処理パターンの第１の例を示す図である。実施の形態３では、マルチコアプロセッサに含まれるコアプロセッサの個数が４個であり、制御対象物の軸の個数が５個である場合を想定する。 The operation performed by the numerical controller 50 will be described below. FIG. 15 is a diagram illustrating a first example of a processing pattern in a case where the number of core processors included in the multi-core processor 2 included in the numerical controller 50 according to the third embodiment is smaller than the number of axes of a control target. . In the third embodiment, it is assumed that the number of core processors included in the multi-core processor is four and the number of axes of the control target is five.
　図１５が示す処理パターンは、第１軸及び第５軸の軸制御処理を第１コアプロセッサに割り当て、第２軸の軸制御処理を第２コアプロセッサに割り当て、第３軸の軸制御処理を第３コアプロセッサに割り当て、第４軸の軸制御処理を第４コアプロセッサに割り当てる処理パターンである。軸制御処理は、第１軸から第５軸までの各軸についての共通処理を含む。補間処理も、第１軸から第５軸までの各軸についての共通処理を含む。図１５が示す処理パターンは、軸制御処理が実行された後に補間処理を実行させる処理パターンである。 In the processing pattern shown in FIG. 15, the axis control processing of the first axis and the fifth axis is assigned to the first core processor, the axis control processing of the second axis is assigned to the second core processor, and the axis control processing of the third axis is performed. This is a processing pattern in which the axis control processing of the fourth axis is allocated to the third core processor and the axis control processing of the fourth axis is allocated to the fourth core processor. The axis control processing includes common processing for each axis from the first axis to the fifth axis. The interpolation process also includes a common process for each of the first to fifth axes. The processing pattern shown in FIG. 15 is a processing pattern for executing an interpolation process after the execution of the axis control process.
　図１５が示す処理パターンでは、補間処理における共通処理を実行するために、第５軸の軸制御処理が実行されている間、第２コアプロセッサ、第３コアプロセッサ及び第４コアプロセッサについて、空き時間が発生する。空き時間は、無駄な時間である。 In the processing pattern shown in FIG. 15, in order to execute the common processing in the interpolation processing, while the axis control processing of the fifth axis is being executed, the second core processor, the third core processor, and the fourth core processor are idle. Time occurs. Free time is wasted time.
　図１６は、実施の形態３にかかる数値制御装置５０が有するマルチコアプロセッサ２に含まれるコアプロセッサの個数が制御対象物の軸の個数より少ない場合の処理パターンの第２の例を示す図である。軸制御処理のうちの共通処理以外の各軸の処理は、処理の独立性が高い。そのため、各軸の処理をひとつのコアプロセッサに割り当てて実行させることができる。 FIG. 16 is a diagram illustrating a second example of the processing pattern when the number of core processors included in the multi-core processor 2 included in the numerical control device 50 according to the third embodiment is smaller than the number of axes of the control target. . The processing of each axis other than the common processing in the axis control processing has high processing independence. Therefore, the processing of each axis can be assigned to one core processor and executed.
　しかしながら、ひとつの軸の処理を複数の処理に分割して分割後の複数の処理を並列に実行させようとしても、当該ひとつの軸の前半の処理についての結果を後半の処理で使用することがあるので、上記の分割後の複数の処理を並列に実行させることはできない。図１６は、複数の１次サブ処理のひとつの例である第５軸の軸制御処理が２次サブ処理Ａから２次サブ処理Ｄまでの４個の２次サブ処理に分割され、２次サブ処理ＢからＤまでの３個の２次サブ処理を実行することができない様子を示している。 However, even if the process of one axis is divided into a plurality of processes and a plurality of processes after the division are to be executed in parallel, the result of the first half process of the one axis may be used in the second half process. Therefore, a plurality of processes after the above division cannot be executed in parallel. FIG. 16 shows that the axis control process of the fifth axis, which is one example of the plurality of primary sub-processes, is divided into four secondary sub-processes from a secondary sub-process A to a secondary sub-process D. This shows that three secondary sub-processes from sub-processes B to D cannot be executed.
　図１７は、実施の形態３にかかる数値制御装置５０が有するマルチコアプロセッサ２に含まれるコアプロセッサの個数が制御対象物の軸の個数より少ない場合の処理パターンの第３の例を示す図である。図１７が示す処理パターンでは、第１軸の軸制御処理は第１コアプロセッサに割り当てられており、第２軸の軸制御処理は第２コアプロセッサに割り当てられており、第３軸の軸制御処理は第３コアプロセッサに割り当てられており、第４軸の軸制御処理は第４コアプロセッサに割り当てられている。図１７が示す処理パターンでは、第１軸、第２軸及び第３軸の各軸についての軸制御処理は、２次サブ処理Ａと、２次サブ処理Ａが実行された後に実行される２次サブ処理Ｂとに分割されている。 FIG. 17 is a diagram illustrating a third example of the processing pattern when the number of core processors included in the multi-core processor 2 included in the numerical controller 50 according to the third embodiment is smaller than the number of axes of the control target. . In the processing pattern shown in FIG. 17, the axis control processing of the first axis is assigned to the first core processor, the axis control processing of the second axis is assigned to the second core processor, and the axis control of the third axis is performed. The processing is assigned to the third core processor, and the axis control processing of the fourth axis is assigned to the fourth core processor. In the processing pattern shown in FIG. 17, the axis control processing for each of the first axis, the second axis, and the third axis is executed after the secondary sub-processing A and the secondary sub-processing A are executed. It is divided into the next sub-process B.
　図１７が示す処理パターンでは、第５軸についての軸制御処理は、２次サブ処理Ａと、２次サブ処理Ａが実行された後に実行される２次サブ処理Ｂと、２次サブ処理Ｂが実行された後に実行される２次サブ処理Ｃと、２次サブ処理Ｃが実行された後に実行される２次サブ処理Ｄとの４個の２次サブ処理に分割されている。図１７が示す処理パターンでは、第１軸についての２次サブ処理Ａが第１コアプロセッサによって実行された後に、第５軸についての２次サブ処理Ａが第１コアプロセッサに割り当てられて第１コアプロセッサによって実行される。第５軸についての２次サブ処理Ａが実行された後に、第１軸についての２次サブ処理Ｂが第１コアプロセッサによって実行される。 In the processing pattern shown in FIG. 17, the axis control processing for the fifth axis is a secondary sub-processing A, a secondary sub-processing B executed after the execution of the secondary sub-processing A, and a secondary sub-processing B Is performed, and a secondary sub-process C is executed after the secondary sub-process C is executed, and a secondary sub-process D is executed after the secondary sub-process C is executed. In the processing pattern shown in FIG. 17, after the secondary sub-processing A for the first axis is executed by the first core processor, the secondary sub-processing A for the fifth axis is assigned to the first core processor and Executed by the core processor. After the secondary sub-process A for the fifth axis is executed, the secondary sub-process B for the first axis is executed by the first core processor.
　図１７が示す処理パターンでは、第２軸についての２次サブ処理Ａが第２コアプロセッサによって実行された後に、第５軸についての２次サブ処理Ｂが第２コアプロセッサに割り当てられて第２コアプロセッサによって実行される。第５軸についての２次サブ処理Ｂが実行された後に、第２軸についての２次サブ処理Ｂが第２コアプロセッサによって実行される。 In the processing pattern shown in FIG. 17, after the secondary sub-processing A for the second axis is executed by the second core processor, the secondary sub-processing B for the fifth axis is assigned to the second core processor and Executed by the core processor. After the secondary sub-process B for the fifth axis is executed, the secondary sub-process B for the second axis is executed by the second core processor.
　第３軸についての２次サブ処理Ａが第３コアプロセッサによって実行された後に、第５軸についての２次サブ処理Ｃが第３コアプロセッサに割り当てられて第３コアプロセッサによって実行される。第５軸についての２次サブ処理Ｃが実行された後に、第３軸についての２次サブ処理Ｂが第３コアプロセッサによって実行される。第４軸についての軸制御処理が第４コアプロセッサによって実行された後に、第５軸についての２次サブ処理Ｄが第４コアプロセッサに割り当てられて第４コアプロセッサによって実行される。 後 に After the secondary sub-process A for the third axis is executed by the third core processor, the secondary sub-process C for the fifth axis is assigned to the third core processor and executed by the third core processor. After the secondary sub-process C for the fifth axis is executed, the secondary sub-process B for the third axis is executed by the third core processor. After the axis control process for the fourth axis is executed by the fourth core processor, the secondary sub-process D for the fifth axis is assigned to the fourth core processor and executed by the fourth core processor.
　上述の通り、図１７が示す処理パターンでは、第１軸、第２軸及び第３軸の各軸についての１次サブ処理である軸制御処理は、２次サブ処理Ａと、２次サブ処理Ａが実行された後に実行される２次サブ処理Ｂとに分割されている。第１コアプロセッサ、第２コアプロセッサ及び第３コアプロセッサの各々については、２次サブ処理Ａと２次サブ処理Ｂとの間に第５軸についてのひとつの２次サブ処理が割り当てられている。 As described above, in the processing pattern shown in FIG. 17, the axis control processing, which is the primary sub-processing for each of the first, second, and third axes, is the secondary sub-processing A and the secondary sub-processing. A is divided into a secondary sub-process B executed after A is executed. For each of the first core processor, the second core processor, and the third core processor, one secondary sub-process for the fifth axis is allocated between the secondary sub-process A and the secondary sub-process B. .
　図１７が示す処理パターンでは、第１軸から第５軸までの各軸についての複数の２次サブ処理は、複数の２次サブ処理によって構成される１次サブ処理の先頭から順に実行される。そのため、図１７が示す処理パターンは、複数の２次サブ処理のうちの実行される順序の変更が許可されない複数の２次サブ処理を実行の順序が変更されることなく実行させる処理パターンである。つまり、図１７が示す処理パターンでは、実行の順序が保たれる。 In the processing pattern shown in FIG. 17, the plurality of secondary sub-processes for each of the first to fifth axes are sequentially executed from the top of the primary sub-process formed by the plurality of secondary sub-processes. . Therefore, the processing pattern illustrated in FIG. 17 is a processing pattern in which a plurality of secondary sub-processes of which the order of execution is not allowed to be changed among the plurality of secondary sub-processes is executed without changing the order of execution. . That is, in the processing pattern shown in FIG. 17, the order of execution is maintained.
　更に言うと、各２次サブ処理が実行されることによって得られたデータは、記憶部５３に記憶される。そのため、図１７が示す処理パターンでは、第１軸から第５軸までの各軸についての複数の２次サブ処理は、記憶部５３に記憶されたデータが利用されることによって、複数の２次サブ処理によって構成される１次サブ処理の先頭から順に実行される。 {Furthermore, the data obtained by executing each of the secondary sub-processes is stored in the storage unit 53. Therefore, in the processing pattern shown in FIG. 17, the plurality of secondary sub-processes for each axis from the first axis to the fifth axis are performed by using the data stored in the storage unit 53. It is executed in order from the top of the primary sub-process constituted by the sub-process.
　上述の通り、実施の形態３にかかる数値制御装置５０は、マルチコアプロセッサ２によって実行される処理を分割し、分割を行うことによって得られた複数の１次サブ処理の個数が複数のコアプロセッサの個数より多い場合、複数の１次サブ処理の一部を分割して複数の２次サブ処理を得る。 As described above, the numerical control device 50 according to the third embodiment divides the processing executed by the multi-core processor 2 and sets the number of primary sub-processes obtained by performing the division to a plurality of core processors. If the number is larger than the number, a part of the plurality of primary sub-processes is divided to obtain a plurality of secondary sub-processes.
　数値制御装置５０は、得られた複数の１次サブ処理のうちの一部以外である残部の１次サブ処理と、複数の２次サブ処理とを、分散させて複数のコアプロセッサに割り当てる。数値制御装置５０は、複数の２次サブ処理の各々についての実行順を保持させる。 The numerical controller 50 distributes the remaining primary sub-processes other than a part of the plurality of obtained primary sub-processes and the plurality of secondary sub-processes and allocates them to the plurality of core processors. The numerical controller 50 keeps the execution order for each of the plurality of secondary sub-processes.
　数値制御装置５０は、第１の１次サブ処理を分割することによって得られる第１の２次サブ処理と第２の２次サブ処理との間に、第２の１次サブ処理を分割することによって得られる第３の２次サブ処理を割り込ませる。数値制御装置５０は、第１の２次サブ処理、第３の２次サブ処理及び第２の２次サブ処理を、この順に、複数のコアプロセッサのうちのひとつのコアプロセッサに割り当てる。 The numerical controller 50 divides the second primary sub-process between the first secondary sub-process and the second secondary sub-process obtained by dividing the first primary sub-process. A third secondary sub-process obtained by this is interrupted. The numerical controller 50 allocates the first secondary sub-process, the third secondary sub-process, and the second secondary sub-process to one of the core processors in this order.
　数値制御装置５０は、第３の１次サブ処理を分割することによって得られる第４の２次サブ処理と第５の２次サブ処理との間に、第２の１次サブ処理を分割することによって得られる第６の２次サブ処理を割り込ませる。数値制御装置５０は、第４の２次サブ処理、第６の２次サブ処理及び第５の２次サブ処理を、この順に、複数のコアプロセッサのうちの別のひとつのコアプロセッサに割り当てる。 The numerical controller 50 divides the second primary sub-process between the fourth secondary sub-process and the fifth secondary sub-process obtained by dividing the third primary sub-process. A sixth secondary sub-process obtained as a result is interrupted. The numerical controller 50 allocates the fourth secondary sub-process, the sixth secondary sub-process, and the fifth secondary sub-process to another one of the plurality of core processors in this order.
　したがって、数値制御装置５０は、分割を行うことによって得られた複数の１次サブ処理の個数が複数のコアプロセッサの個数より多い場合、以下の効果を得る。すなわち、数値制御装置５０は、空き時間をできるだけ作ることなく、マルチコアプロセッサ２によって実行される処理を、ひとつのコアプロセッサが当該処理を実行する場合の処理時間より短い処理時間で実行することができる。 Therefore, when the number of the plurality of primary sub-processes obtained by performing the division is larger than the number of the plurality of core processors, the numerical controller 50 has the following effects. That is, the numerical control device 50 can execute the processing executed by the multi-core processor 2 in a processing time shorter than the processing time when one core processor executes the processing, without making the idle time as much as possible. .
　図１８は、実施の形態１にかかる数値制御装置１が有するパターン決定部４及び割り当て部５の一部又は全部の機能がプロセッサ８１によって実現される場合のプロセッサ８１を示す図である。つまり、パターン決定部４及び割り当て部５の一部又は全部の機能は、メモリ８２に格納されるプログラムを実行するプロセッサ８１によって実現されてもよい。プロセッサ８１は、ＣＰＵ（Central　Processing　Unit）、処理装置、演算装置、マイクロプロセッサ、又はＤＳＰ（Digital　Signal　Processor）である。図１８には、メモリ８２も示されている。 FIG. 18 is a diagram illustrating the processor 81 in a case where some or all of the functions of the pattern determination unit 4 and the assignment unit 5 included in the numerical control device 1 according to the first embodiment are realized by the processor 81. That is, a part or all of the functions of the pattern determining unit 4 and the allocating unit 5 may be realized by the processor 81 that executes the program stored in the memory 82. The processor 81 is a CPU (Central Processing Unit), a processing device, an arithmetic device, a microprocessor, or a DSP (Digital Signal Processor). FIG. 18 also shows the memory 82.
　パターン決定部４及び割り当て部５の一部又は全部の機能がプロセッサ８１によって実現される場合、当該一部又は全部の機能は、プロセッサ８１と、ソフトウェア、ファームウェア、又は、ソフトウェア及びファームウェアとの組み合わせにより実現される。ソフトウェア又はファームウェアはプログラムとして記述され、メモリ８２に格納される。プロセッサ８１は、メモリ８２に記憶されたプログラムを読み出して実行することにより、パターン決定部４及び割り当て部５の一部又は全部の機能を実現する。 When some or all of the functions of the pattern determination unit 4 and the assignment unit 5 are realized by the processor 81, the part or all of the functions are performed by the processor 81 and software, firmware, or a combination of software and firmware. Is achieved. Software or firmware is described as a program and stored in the memory 82. The processor 81 realizes a part or all of the functions of the pattern determination unit 4 and the assignment unit 5 by reading and executing the program stored in the memory 82.
　パターン決定部４及び割り当て部５の一部又は全部の機能がプロセッサ８１によって実現される場合、数値制御装置１は、パターン決定部４及び割り当て部５の一部又は全部によって実行されるステップが結果的に実行されることになるプログラムを格納するためのメモリ８２を有する。メモリ８２に格納されるプログラムは、パターン決定部４及び割り当て部５の一部又は全部が実行する手順又は方法をコンピュータに実行させるものであるともいえる。 When a part or all of the functions of the pattern determining unit 4 and the allocating unit 5 are realized by the processor 81, the numerical controller 1 performs the steps executed by the part or all of the pattern determining unit 4 and the allocating unit 5 as a result. And a memory 82 for storing a program to be executed. It can be said that the program stored in the memory 82 causes a computer to execute a procedure or a method executed by a part or all of the pattern determination unit 4 and the assignment unit 5.
　メモリ８２は、例えば、ＲＡＭ（Random　Access　Memory）、ＲＯＭ（Read　Only　Memory）、フラッシュメモリ、ＥＰＲＯＭ（Erasable　Programmable　Read　Only　Memory）、ＥＥＰＲＯＭ（登録商標）（Electrically　Erasable　Programmable　Read-Only　Memory）等の不揮発性もしくは揮発性の半導体メモリ、磁気ディスク、フレキシブルディスク、光ディスク、コンパクトディスク、ミニディスク又はＤＶＤ（Digital　Versatile　Disk）等である。 The memory 82 is, for example, a non-volatile memory such as a RAM (Random Access Memory), a ROM (Read Only Memory), a flash memory, an EPROM (Erasable Programmable Read Only Memory), and an EEPROM (registered trademark) (Electrically Erasable Programmable Read-Only Memory). Alternatively, it is a volatile semiconductor memory, a magnetic disk, a flexible disk, an optical disk, a compact disk, a mini disk, a DVD (Digital Versatile Disk), or the like.
　図１９は、実施の形態１にかかる数値制御装置１が有するパターン決定部４及び割り当て部５の一部又は全部が処理回路９１によって実現される場合の処理回路９１を示す図である。つまり、パターン決定部４及び割り当て部５の一部又は全部は、処理回路９１によって実現されてもよい。 FIG. 19 is a diagram illustrating the processing circuit 91 when a part or all of the pattern determining unit 4 and the allocating unit 5 included in the numerical control device 1 according to the first embodiment are realized by the processing circuit 91. That is, a part or all of the pattern determination unit 4 and the assignment unit 5 may be realized by the processing circuit 91.
　処理回路９１は、専用のハードウェアである。処理回路９１は、例えば、単一回路、複合回路、プログラム化されたプロセッサ、並列プログラム化されたプロセッサ、ＡＳＩＣ(Application　Specific　Integrated　Circuit)、ＦＰＧＡ（Field-Programmable　Gate　Array）、又はこれらを組み合わせたものである。 The processing circuit 91 is dedicated hardware. The processing circuit 91 is, for example, a single circuit, a composite circuit, a programmed processor, a parallel programmed processor, an ASIC (Application Specific Integrated Circuit), an FPGA (Field-Programmable Gate Array), or a combination thereof. It is.
　パターン決定部４及び割り当て部５の一部は、残部とは別個の専用のハードウェアであってもよい。 Part of the pattern determination unit 4 and the assignment unit 5 may be dedicated hardware separate from the rest.
　パターン決定部４及び割り当て部５の複数の機能について、当該複数の機能の一部がソフトウェア又はファームウェアで実現され、当該複数の機能の残部が専用のハードウェアで実現されてもよい。このように、パターン決定部４及び割り当て部５の複数の機能は、ハードウェア、ソフトウェア、ファームウェア、又はこれらの組み合わせによって実現することができる。 Regarding the plurality of functions of the pattern determining unit 4 and the allocating unit 5, a part of the plurality of functions may be realized by software or firmware, and the rest of the plurality of functions may be realized by dedicated hardware. As described above, the plurality of functions of the pattern determination unit 4 and the assignment unit 5 can be realized by hardware, software, firmware, or a combination thereof.
　実施の形態２にかかる数値制御装置１Ａが有するパターン決定部４及び割り当て部５Ａの一部又は全部の機能は、上記のプロセッサ８１と同等の機能を有するプロセッサによって実現されてもよい。その場合、実施の形態２にかかる数値制御装置１Ａは、当該プロセッサと、パターン決定部４及び割り当て部５Ａの一部又は全部によって実行されるステップが結果的に実行されることになるプログラムを格納するためのメモリとを有する。当該メモリは、上記のメモリ８２と同等の機能を有するメモリである。実施の形態２にかかる数値制御装置１Ａが有するパターン決定部４及び割り当て部５Ａの一部又は全部は、上記の処理回路９１と同等の機能を有する処理回路によって実現されてもよい。 一部 A part or all of the functions of the pattern determining unit 4 and the allocating unit 5A of the numerical control device 1A according to the second embodiment may be realized by a processor having a function equivalent to the processor 81 described above. In that case, the numerical control device 1A according to the second embodiment stores the processor and a program that results in execution of steps executed by some or all of the pattern determination unit 4 and the assignment unit 5A. And a memory for performing The memory is a memory having the same function as the memory 82 described above. A part or all of the pattern determining unit 4 and the allocating unit 5A included in the numerical control device 1A according to the second embodiment may be realized by a processing circuit having a function equivalent to that of the processing circuit 91.
　実施の形態３にかかる数値制御装置５０が有する分割部５１及び割り当て部５２の一部又は全部の機能は、上記のプロセッサ８１と同等の機能を有するプロセッサによって実現されてもよい。その場合、実施の形態３にかかる数値制御装置５０は、当該プロセッサと、分割部５１及び割り当て部５２の一部又は全部によって実行されるステップが結果的に実行されることになるプログラムを格納するためのメモリとを有する。当該メモリは、上記のメモリ８２と同等の機能を有するメモリである。実施の形態３にかかる数値制御装置５０が有する分割部５１及び割り当て部５２の一部又は全部は、上記の処理回路９１と同等の機能を有する処理回路によって実現されてもよい。 一部 A part or all of the functions of the dividing unit 51 and the allocating unit 52 included in the numerical control device 50 according to the third embodiment may be realized by a processor having the same function as the processor 81 described above. In that case, the numerical control device 50 according to the third embodiment stores the processor and a program that results in execution of steps executed by some or all of the dividing unit 51 and the allocating unit 52. And a memory for The memory is a memory having the same function as the memory 82 described above. Part or all of the dividing unit 51 and the allocating unit 52 included in the numerical control device 50 according to the third embodiment may be realized by a processing circuit having a function equivalent to the processing circuit 91 described above.
　以上の実施の形態に示した構成は、本発明の内容の一例を示すものであり、別の公知の技術と組み合わせることも可能であるし、本発明の要旨を逸脱しない範囲で、構成の一部を省略、変更することも可能である。 The configurations described in the above embodiments are merely examples of the contents of the present invention, and can be combined with another known technology, and can be combined with other known technologies without departing from the gist of the present invention. Parts can be omitted or changed.
　１，５０　数値制御装置、２　マルチコアプロセッサ、３，５３　記憶部、４　パターン決定部、５，５２　割り当て部、１１　モータ制御アンプ、１２　モータ、１３　表示器、１４　入出力装置、１５　ネットワーク装置、２１　第１コアプロセッサ、２２　第２コアプロセッサ、２３　第３コアプロセッサ、２４　第４コアプロセッサ、３１　加工プログラム、３２　加工プログラム読込み処理、３３　加工プログラム解析処理、３４　補間処理、３５　加減速処理、３６　軸制御処理、３７　ＨＭＩ処理、３８　Ｉ／Ｏ制御処理、３９　通信処理、４１　処理パターン情報、４２　リソース情報、４３　機械構成情報、４４　ソフトウェア構成情報、５１　分割部、８１　プロセッサ、８２　メモリ、９１　処理回路。 1,50 numerical control unit, 2 multi-core processor, 3,53 storage unit, 4 pattern determination unit, 5,52 allocation unit, 11 motor control amplifier, 12 motor, 13 display, 14 input / output device, 15 network device, 21 First core processor, 22 second core processor, 23 third core processor, 24 fourth core processor, 31 machining program, 32 machining program reading process, 33 machining program analysis process, 34 interpolation process, 35 acceleration / deceleration process, 36 axis Control processing, 37 HMI processing, 38 I / O control processing, 39 communication processing, 41 processing pattern information, 42 resource information, 43 machine configuration information, 44 software configuration information, 51 division unit, 81 processor, 82 memory, 91 processing circuit .

Claims (5)

  1. 　工作機械を制御する数値制御装置であって、
    　複数のコアプロセッサを含むマルチコアプロセッサと、
    　前記マルチコアプロセッサに含まれるコアプロセッサの個数を示す情報を含むリソース情報、前記工作機械を構成するハードウェアに関する機械構成情報、及び、前記マルチコアプロセッサによって実行される処理がソフトウェアが用いられて実行される場合の前記ソフトウェアの構成を示すソフトウェア構成情報をもとに、複数の処理パターンのなかから、前記マルチコアプロセッサが前記処理を実行する際の処理時間が、前記複数のコアプロセッサのうちのひとつのコアプロセッサが前記処理を実行する際の処理時間より短くなる処理パターンを選択し、選択された処理パターンを前記複数のコアプロセッサが前記処理を実行する際の処理パターンと決定するパターン決定部と、
    　前記パターン決定部によって決定された前記処理パターンにしたがって、前記処理を構成する複数のサブ処理を分散させて前記複数のコアプロセッサに割り当てる割り当て部とを備え、
    　前記複数の処理パターンの各々は、前記複数のサブ処理のうちの実行される順序の変更が許可されない複数のサブ処理を実行の順序が変更されることなく実行させる処理パターンである
    　ことを特徴とする数値制御装置。     A numerical controller for controlling a machine tool,
    A multi-core processor including a plurality of core processors;
    Resource information including information indicating the number of core processors included in the multi-core processor, machine configuration information on hardware configuring the machine tool, and processing executed by the multi-core processor are executed using software Based on software configuration information indicating the configuration of the software in the case, from among a plurality of processing patterns, a processing time when the multi-core processor executes the processing is one core of the plurality of core processors. A pattern determination unit that selects a processing pattern that is shorter than a processing time when the processor performs the processing, and determines the selected processing pattern as a processing pattern when the plurality of core processors perform the processing.
    According to the processing pattern determined by the pattern determination unit, an allocation unit that distributes a plurality of sub-processing constituting the processing and allocates the plurality of core processors to the plurality of core processors,
    Each of the plurality of processing patterns is a processing pattern that causes a plurality of sub-processes of the plurality of sub-processes, of which execution order change is not permitted, to be executed without changing the order of execution. Numerical control device.
  2. 　前記パターン決定部は、前記リソース情報、前記機械構成情報及び前記ソフトウェア構成情報をもとに、前記複数の処理パターンのなかから、前記マルチコアプロセッサが前記処理を実行する際の処理時間が最短となる処理パターンを選択し、選択された処理パターンを前記複数のコアプロセッサが前記処理を実行する際の処理パターンと決定する
    　ことを特徴とする請求項１に記載の数値制御装置。     The pattern determination unit is configured to minimize a processing time when the multi-core processor executes the processing from among the plurality of processing patterns based on the resource information, the machine configuration information, and the software configuration information. The numerical control device according to claim 1, wherein a processing pattern is selected, and the selected processing pattern is determined as a processing pattern when the plurality of core processors execute the processing.
  3. 　前記パターン決定部は、前記複数のサブ処理の各々の処理時間を事前に計測し、計測された前記処理時間を利用して、前記複数の処理パターンのなかから、前記マルチコアプロセッサが前記処理を実行する際の処理時間が最短となる処理パターンを選択し、選択された処理パターンを前記複数のコアプロセッサが前記処理を実行する際の処理パターンと決定する
    　ことを特徴とする請求項２に記載の数値制御装置。     The pattern determination unit measures the processing time of each of the plurality of sub-processes in advance, and uses the measured processing time to execute the process from among the plurality of processing patterns. The processing pattern that minimizes the processing time when performing the processing is selected, and the selected processing pattern is determined as the processing pattern when the plurality of core processors execute the processing. The method according to claim 2, wherein Numerical control unit.
  4. 　前記割り当て部は、前記複数のサブ処理の一部を前記数値制御装置に割り当てると共に、前記複数のサブ処理の残部を前記数値制御装置に接続されている他の数値制御装置又は計算装置に割り当て、前記マルチコアプロセッサが前記一部を実行する期間に、前記残部を前記他の数値制御装置又は前記計算装置に実行させる
    　ことを特徴とする請求項１又は２に記載の数値制御装置。     The allocating unit allocates a part of the plurality of sub-processes to the numerical control device, and allocates the rest of the plurality of sub-processes to another numerical control device or a calculation device connected to the numerical control device. The numerical control device according to claim 1, wherein the other numerical control device or the calculation device executes the remaining portion while the multi-core processor executes the part.
  5. 　工作機械を制御する数値制御装置であって、
    　複数のコアプロセッサを含むマルチコアプロセッサと、
    　前記マルチコアプロセッサによって実行される処理を分割し、分割を行うことによって得られた複数の１次サブ処理の個数が前記複数のコアプロセッサの個数より多い場合、前記複数の１次サブ処理の一部を分割して複数の２次サブ処理を得る分割部と、
    　前記分割部によって得られた前記複数の１次サブ処理のうちの前記一部以外である残部の１次サブ処理と、前記複数の２次サブ処理とを、分散させて前記複数のコアプロセッサに割り当てる割り当て部とを備え、
    　前記割り当て部は、
    　　前記複数の２次サブ処理の各々についての実行順を保持させると共に、
    　　前記複数の２次サブ処理のうちの第１の１次サブ処理を分割することによって得られる第１の２次サブ処理と第２の２次サブ処理との間に、前記複数の２次サブ処理のうちの第２の１次サブ処理を分割することによって得られる第３の２次サブ処理を割り込ませ、前記第１の２次サブ処理、前記第３の２次サブ処理及び前記第２の２次サブ処理を、この順に、複数のコアプロセッサのうちのひとつのコアプロセッサに割り当て、
    　　前記複数の２次サブ処理のうちの第３の１次サブ処理を分割することによって得られる第４の２次サブ処理と第５の２次サブ処理との間に、前記複数の２次サブ処理のうちの第２の１次サブ処理を分割することによって得られる第６の２次サブ処理を割り込ませ、前記第４の２次サブ処理、前記第６の２次サブ処理及び前記第５の２次サブ処理を、この順に、複数のコアプロセッサのうちの別のひとつのコアプロセッサに割り当てる
    　ことを特徴とする数値制御装置。     A numerical controller for controlling a machine tool,
    A multi-core processor including a plurality of core processors,
    If the number of the plurality of primary sub-processes obtained by dividing the process executed by the multi-core processor and performing the division is larger than the number of the plurality of core processors, a part of the plurality of the primary sub-processes A dividing unit that divides the sub-process into a plurality of secondary sub-processes,
    Among the plurality of primary sub-processes obtained by the division unit, the remaining primary sub-processes other than the part and the plurality of secondary sub-processes are distributed to the plurality of core processors. And an assignment unit to be assigned.
    The allocating unit includes:
    While maintaining the execution order for each of the plurality of secondary sub-processes,
    Between the first secondary sub-process and the second secondary sub-process obtained by dividing a first primary sub-process of the plurality of secondary sub-processes, A third secondary sub-process obtained by dividing a second primary sub-process of the process is interrupted, and the first secondary sub-process, the third secondary sub-process, and the second Is assigned to one of the plurality of core processors in this order,
    Between the fourth secondary sub-process and the fifth secondary sub-process obtained by dividing a third primary sub-process of the plurality of secondary sub-processes, A sixth secondary sub-process obtained by dividing the second primary sub-process of the process is interrupted, and the fourth secondary sub-process, the sixth secondary sub-process, and the fifth A second sub-process of the numerical controller is assigned to another one of the plurality of core processors in this order.
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