WO2020029377A1

WO2020029377A1 - Liquid crystal display device

Info

Publication number: WO2020029377A1
Application number: PCT/CN2018/106426
Authority: WO
Inventors: 徐向阳
Original assignee: 深圳市华星光电半导体显示技术有限公司
Priority date: 2018-08-06
Filing date: 2018-09-19
Publication date: 2020-02-13
Also published as: CN109003588A

Abstract

Disclosed is a liquid crystal display device, comprising: a plurality of source lines (D1-DM); a plurality of gate lines (G1-GN), the source lines (D1-DM) and the gate lines (G1-GN) defining a plurality of pixels (14); and a GOA driving circuit (12) comprising a plurality of cascaded GOA modules (120), each stage of GOA module (120) being electrically connected to at least two gate lines (G1-GN) of the plurality of gate lines (G1-GN) and supplying scanning signals sequentially to at least two gate lines (G1-GN) of the plurality of gate lines (G1-GN).

Description

Liquid crystal display device

Technical field

The present disclosure relates to a display device, and more particularly to a liquid crystal display device.

Background technique

In a liquid crystal display panel, the scanning line is a gate driving integrated circuit (Integrated) which is external to the liquid crystal display panel. Circuit (IC).

Another technique for driving scan lines is GOA (Gate driver On Array) technology. GOA technology means that the gate driving circuit is directly fabricated on the array substrate of the liquid crystal display panel, so the above-mentioned external gate driving integrated circuit is not needed. Since the gate driving circuit can be directly fabricated on the array substrate by using the existing manufacturing process, the manufacturing cost can be reduced, and the liquid crystal display device can be applied to a narrow bezel and a thin liquid crystal display device.

The existing GOA driving circuit includes a plurality of GOA modules, and each GOA module is used to provide a scanning signal to a scanning line. That is, N GOA modules are required for N scan lines. The number of GOA modules will limit the liquid crystal display device in achieving narrow frames and thinning purposes.

Therefore, solutions to the problems in the prior art are needed.

technical problem

The number of GOA modules will limit the liquid crystal display device in achieving narrow frames and thinning purposes.

Technical solutions

An object of the present disclosure is to provide a liquid crystal display device that can solve the problems in the prior art.

To solve the above problems, a liquid crystal display device provided by the present disclosure includes: a plurality of source lines; a plurality of gate lines, the source lines and the gate lines defining a plurality of pixels; and a GOA driving circuit, Including multiple cascaded GOA modules, each level of GOA module is electrically connected to at least two scan lines of the plurality of scan lines and sequentially provides scanning to at least two scan lines of the plurality of scan lines signal. The GOA driving circuit alternately receives a first clock signal and a second clock signal, the first clock signal and the second clock signal are signals with opposite phases, and the first clock signal is input to a singular stage GOA module, the second clock signal is input to the GOA module of an even-numbered stage.

In one embodiment, each level of the GOA module is electrically connected to three scanning lines of the plurality of scanning lines and sequentially provides a scanning signal to the three scanning lines of the plurality of scanning lines. The three scan lines of the GOA module are controlled by a control signal. When the control signal is turned on and the first clock signal is input to the GOA module in the singular order, the scan line corresponding to the control signal receives the turned-on scan signal. When the control signal is turned on and the second clock signal is input to the GOA module of an even-numbered stage, the scanning line corresponding to the control signal receives the turned-on scanning signal.

In one embodiment, the control signals controlling the three scan lines of the GOA module of each stage are sequentially turned on.

In an embodiment, each level of the GOA module includes: a pull-up control module for generating a scan level signal according to a start signal or a scan signal of a previous level; a pull-up module electrically connected to an office The pull-up control module is used to pull up the scan-level signal according to the scan-level signal and a clock signal of this stage; a pull-down module is electrically connected to the pull-up control module and the pull-up module and used A low-level voltage provided by a low-level constant-voltage source is output to an output terminal of one of the scanning signals of the current stage according to the scanning signal of the next stage or the starting signal; a first pull-down maintaining module, Is electrically connected to the pull-up control module, the pull-up module and the pull-down module and is used to maintain the scanning signal of the current level to a low level; a second pull-down maintenance module is electrically connected to the pull-up control A module, the pull-up module, the pull-down module, and the first pull-down maintaining module and configured to maintain a scanning level signal of the current level to a low level; and a bootstrap capacitor electrically connected to the pull-up Control module Pull module, the pull-down module, the first module and the second pull-down to maintain the pull-down to maintain a high level module and scanning for the signal level of the cost of raw stage.

In an embodiment, the pull-up control module includes: a pull-up control thin film transistor, and a gate and a source of the pull-up control thin film transistor are used to receive the start signal or the scan signal of the previous stage The drain of the pull-up control thin film transistor is used to generate the scanning level signal.

In an embodiment, the pull-up module includes: a pull-up thin film transistor, and a gate of the pull-up thin film transistor is electrically connected to a drain of the pull-up control thin film transistor and configured to receive the scan level. A signal, a source of the pull-up thin film transistor receives the first clock signal or the second clock signal, and a drain of the pull-up thin film transistor is electrically connected to an output terminal of the scan signal.

In an embodiment, the pull-down module includes a first pull-down thin film transistor, and a gate of the first pull-down thin film transistor is electrically connected to a scan signal of the next-level GOA module or is electrically connected to The start signal, the source of the first pull-down thin film transistor is electrically connected to the scan level signal, and the drain of the first pull-down thin film transistor is electrically connected to the low-level constant voltage source. And a second pull-down thin film transistor, the gate of the second pull-down thin film transistor is electrically connected to the scan signal of the next-level GOA module or the start signal, and the second pull-down thin film transistor The source of is electrically connected to the drain of the pull-up thin film transistor, and the drain of the second pull-down thin film transistor is electrically connected to the low-level constant voltage source.

In an embodiment, the first pull-down sustaining module includes a first pull-down sustaining thin film transistor, and a source of the first pull-down sustaining thin film transistor is electrically connected to a drain of the pull-up thin film transistor. A drain of the first pull-down sustaining thin film transistor is electrically connected to the low-level constant voltage source; a second pull-down sustaining thin film transistor, and a gate of the second pull-down maintaining thin film transistor is electrically connected to all The gate of the first pull-down sustaining thin film transistor, the source of the second pull-down sustaining thin film transistor is electrically connected to the scan level signal, and the drain of the second pull-down sustaining thin film transistor is electrically connected to the A low-level constant voltage source; a third pull-down sustaining thin film transistor, the gate and source of the third pull-down sustaining thin film transistor are electrically connected to a first pull-down control signal; a fourth pull-down sustaining thin film transistor, The gate of the fourth pull-down sustaining thin film transistor is electrically connected to the scan level signal, and the source of the fourth pull-down sustaining thin film transistor is electrically connected to the third pull-down sustaining thin film transistor. The fourth pull-down sustaining thin film transistor is electrically connected to the low-level constant voltage source; a fifth pull-down sustaining thin-film transistor, and the fifth pull-down maintaining thin-film transistor is electrically connected to the gate The drain of the third pull-down sustaining thin film transistor is electrically connected to the source of the first pull-down control signal, and the drain of the fifth pull-down sustaining thin film transistor is electrically connected to A gate of the first pull-down sustaining thin film transistor; and a gate of a sixth pull-down sustaining thin film transistor, the gate of the sixth pull-down sustaining thin-film transistor is electrically connected to the scan level signal, and the sixth pull-down sustains The source of the thin film transistor is electrically connected to the gate of the first pull-down sustaining thin film transistor, and the drain of the sixth pull-down sustaining thin film transistor is electrically connected to the low-level constant voltage source.

In an embodiment, the second pull-down sustaining module includes: a seventh pull-down sustaining thin film transistor, a source of the seventh pull-down sustaining thin film transistor is electrically connected to a drain of the pull-up thin film transistor, and The drain of the seventh pull-down sustaining thin film transistor is electrically connected to the low-level constant voltage source; an eighth pull-down sustains the thin film transistor, and the gate of the eighth pull-down sustaining thin film transistor is electrically connected to the seventh pull-down The gate of the thin film transistor is maintained, the source of the eighth pull-down sustaining thin film transistor is electrically connected to the scan level signal, and the drain of the eighth pull-down sustaining thin film transistor is electrically connected to the low-level constant A voltage source; a ninth pull-down sustaining thin film transistor, the gate and source of the ninth pull-down sustaining thin film transistor are electrically connected to a second pull-down control signal; a tenth pull-down sustaining thin film transistor, and the tenth pull-down sustaining The gate of the thin film transistor is electrically connected to the scan level signal, and the source of the tenth pull-down sustaining thin film transistor is electrically connected to the ninth pull-down sustaining thin film transistor. The drain of the tenth pull-down sustaining thin film transistor is electrically connected to the low-level constant voltage source; a eleventh pull-down sustains the thin-film transistor, and the eleventh pull-down sustains the gate of the thin-film transistor. To the drain of the ninth pull-down sustaining thin film transistor, the source of the eleventh pull-down sustaining thin film transistor is electrically connected to the second pull-down control signal, and the eleventh pull-down sustaining thin film transistor A drain electrode is electrically connected to the gate of the seventh pull-down sustaining thin film transistor; and a twelfth pull-down sustaining thin film transistor is electrically connected to the scan level Signal, the source of the twelfth pull-down sustaining thin film transistor is electrically connected to the gate of the seventh pull-down sustaining thin film transistor. The drain of the twelfth pull-down sustaining thin film transistor is electrically connected to the low-level constant voltage source.

To solve the above problems, a liquid crystal display device provided by the present disclosure includes: a plurality of source lines; a plurality of gate lines, the source lines and the gate lines defining a plurality of pixels; and a GOA driving circuit, Including multiple cascaded GOA modules, each level of GOA module is electrically connected to at least two scan lines of the plurality of scan lines and sequentially provides scanning to at least two scan lines of the plurality of scan lines signal.

In one embodiment, the GOA driving circuit alternately receives a first clock signal and a second clock signal.

In an embodiment, the pull-up control module includes: a pull-up control thin film transistor, and a gate and a source of the pull-up control thin film transistor are used to receive the start signal or the scan signal of the previous stage. The drain of the pull-up control thin film transistor is used to generate the scanning level signal.

Beneficial effect

Compared with the prior art, in the liquid crystal display device of the present disclosure, since each stage of the GOA module is electrically connected to at least two scan lines, the number of GOA modules can be saved, thereby achieving a narrower frame and a thinner purpose.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a liquid crystal display device according to an embodiment of the present disclosure.

FIG. 2 shows a GOA module according to an embodiment of the present disclosure.

FIG. 3 is a driving waveform diagram according to an embodiment of the present disclosure.

Embodiments of the invention

The following descriptions of the embodiments are made with reference to the attached drawings to illustrate specific embodiments that the present disclosure can be implemented.

Please refer to FIG. 1, which illustrates a liquid crystal display device according to an embodiment of the present disclosure. The liquid crystal display device includes a plurality of scanning lines G1-GN, a plurality of data lines D1-DM, and a GOA driving circuit 12.

The data lines D1-DM are formed along a first direction. The scan lines G1-GN are formed along a second direction. The first direction is perpendicular to the second direction. The data lines D1-DM and the scanning lines G1-GN define a plurality of pixels 14. Each of the pixels 104 is electrically connected to a thin film transistor 16.

The GOA driving circuit 12 includes a plurality of cascaded GOA modules 120. Each level of GOA module receives the corresponding clock signal.

One feature of the liquid crystal display device of the present disclosure is that each stage of the GOA module 120 is electrically connected to at least two scan lines of the plurality of scan lines G1-GN and sequentially enters the plurality of scan lines G1-GN. The scanning signals are provided by at least two scanning lines. The at least two scan lines are two consecutive scan lines.

In the embodiment of FIG. 1, each stage of the GOA module 120 is electrically connected to three scanning lines in the plurality of scanning lines G1-GN and sequentially toward the three scanning lines in the plurality of scanning lines G1-GN. Provides scanning signals. The three scanning lines are three consecutive scanning lines. For example, the first GOA module 120 is electrically connected to the scan lines G1-G3 and sequentially provides scan signals to the scan lines G1-G3. In other words, the first GOA module 120 does not provide scan signals to the scan lines G1-G3 at the same time. Similarly, the second GOA module 120 is electrically connected to the scanning lines G4-G6 and sequentially provides scanning signals to the scanning lines G4-G6. In other words, the second GOA module 120 does not provide scan signals to the scan lines G4-G6 at the same time.

Please refer to FIG. 1 and FIG. 2. FIG. 2 shows a GOA module 120 according to an embodiment of the present disclosure.

The GOA module 120 includes a pull-up control module 1200, a pull-up module 1202, a pull-down module 1204, a first pull-down maintenance module 1206, a second pull-down maintenance module 1208, and a bootstrap capacitor C.

In the liquid crystal display device of the present disclosure, the GOA driving circuit 12 receives a first clock signal CLK1 and a second clock signal CLK2 alternately. The first clock signal CLK1 and the second clock signal CLK2 are signals with opposite phases and each has a high level and a low level. The first clock CLK1 is input to the GOA module 120 in a single order, that is, the GOA unit module 120 in the first, third, fifth, ... stages. The second clock signal CLK2 is input to the GOA module 120 of an even-numbered stage, that is, the GOA unit module 120 of the second, fourth, sixth, ... stages.

A low-level constant voltage source VSS is electrically connected to the first pull-down sustaining module 1206, the second pull-down sustaining module 1208, and the pull-down module 1204. The low-level constant-voltage source VSS is used for fixedly providing a low-level voltage.

The pull-up control module 1200 is used according to a start signal (STV, when the GOA module 120 is the first stage) or a scan signal G (N-1) of the previous stage (when the GOA module 120 For one of the second to N stages), a scan level signal Q (N) is generated.

The pull-up module 1202 is electrically connected to the pull-up control module 1200 and is configured to pull up the signal according to the scan level signal and a clock signal of the current level (the first clock CLK1 or the second clock signal CLK2). The scan level signal is described.

The pull-down module 1204 is electrically connected to the pull-up control module 1200 and the pull-up module 1202 and is configured to be based on a scanning signal of the next level (when the GOA module 120 is one of the first to N-1 levels) One of them) or according to the start signal (STV, when the GOA module 120 is the Nth stage), output the low-level voltage provided by the low-level constant-voltage source VSS to the scanning signal of the current stage G (N) output.

The first pull-down maintaining module 1206 is electrically connected to the pull-up control module 1200, the pull-up module 1202, and the pull-down module 1204 and is configured to maintain a scanning signal of a current level at a low level.

The second pull-down maintenance module 1208 is electrically connected to the pull-up control module 1200, the pull-up module 1202, the pull-down module 1204, and the first pull-down maintenance module 1206 and is used to maintain the scanning power of the current level. The flat signal is low.

The bootstrap capacitor C is electrically connected to the pull-up control module 1200, the pull-up module 1202, the pull-down module 1204, the first pull-down maintenance module 1206, and the second pull-down maintenance module 1208 in combination. It is used to generate the high level of the scanning level signal of this stage.

The pull-up control module 1200 includes a pull-up control thin film transistor T11.

The gate and source of the pull-up control thin film transistor T11 are used to receive the start signal (when the GOA module 120 is the first stage) or the scan signal G (N-1) of the previous stage ( When the GOA module 120 is one of the second to Nth stages). The drain of the pull-up control thin film transistor T11 is used to generate the scan level signal Q (N).

The pull-up module 1202 includes a pull-up thin film transistor T21.

The gate of the pull-up thin film transistor T21 is electrically connected to the drain of the pull-up control thin film transistor T11 and is used to receive the scan level signal Q (N). The source of the pull-up thin film transistor T21 receives the first clock signal CLK1 (when the GOA module 120 is a singular GOA module 120) or the second clock signal CLK2 (when the GOA module 120 is Even GOA module 120). A drain of the pull-up thin film transistor T21 is electrically connected to an output terminal of the scan signal G (N).

The pull-down module 1204 includes a first pull-down thin film transistor T41 and a second pull-down thin film transistor T31.

The gate of the first pull-down thin film transistor T41 is electrically connected to the scanning signal G (N + 1) of the next-level GOA module 120 (when the GOA module 120 is the first to N-1th stages) One of them) or is electrically connected to the start signal (STV, when the GOA module 120 is the Nth stage). The source of the first pull-down thin film transistor T41 is electrically connected to the scan level signal Q (N). The drain of the first pull-down thin film transistor T41 is electrically connected to the low-level constant voltage source VSS.

The gate of the second pull-down thin film transistor T31 is electrically connected to the scan signal G (N + 1) of the next-level GOA module 120 (when the GOA module 120 is between the first level to the N-1th level) One of them) or is electrically connected to the start signal (STV, when the GOA module 120 is the Nth stage). The source of the second pull-down thin film transistor T31 is electrically connected to the drain of the pull-up thin film transistor T21. The drain of the second pull-down thin film transistor T31 is electrically connected to the low-level constant voltage source VSS.

The first pull-down sustaining module 1206 includes a first pull-down sustaining thin film transistor T32, a second pull-down sustaining thin film transistor T42, a third pull-down sustaining thin film transistor T51, a fourth pull-down sustaining thin film transistor T52, and a fifth The pull-down sustaining thin film transistor T53 and a sixth pull-down sustaining thin film transistor T54.

A source of the first pull-down sustaining thin film transistor T32 is electrically connected to a drain of the pull-up thin film transistor T21. The drain of the first pull-down sustaining thin film transistor T32 is electrically connected to the low-level constant voltage source VSS.

The gate of the second pull-down sustaining thin film transistor T42 is electrically connected to the gate of the first pull-down sustaining thin film transistor T32. The source of the second pull-down sustaining thin film transistor T42 is electrically connected to the scan level signal Q (N). The drain of the second pull-down sustaining thin film transistor T42 is electrically connected to the low-level constant voltage source VSS.

The gate and source of the third pull-down sustaining thin film transistor T51 are electrically connected to a first pull-down control signal LC1.

The gate of the fourth pull-down sustaining thin film transistor T52 is electrically connected to the scan level signal Q (N). The source of the fourth pull-down sustaining thin film transistor T52 is electrically connected to the drain of the third pull-down sustaining thin film transistor T51. The drain of the fourth pull-down sustaining thin film transistor T52 is electrically connected to the low-level constant voltage source VSS.

The gate of the fifth pull-down sustaining thin film transistor T53 is electrically connected to the drain of the third pull-down sustaining thin film transistor T51. The source of the fifth pull-down sustaining thin film transistor T53 is electrically connected to the first pull-down control signal LC1. The drain of the fifth pull-down sustaining thin film transistor T53 is electrically connected to the gate of the first pull-down sustaining thin film transistor T32.

The gate of the sixth pull-down sustaining thin film transistor T54 is electrically connected to the scan level signal Q (N). The source of the sixth pull-down sustaining thin film transistor T54 is electrically connected to the gate of the first pull-down sustaining thin film transistor T32. The drain of the sixth pull-down sustaining thin film transistor T54 is electrically connected to the low-level constant voltage source VSS.

The second pull-down sustaining module 1208 includes a seventh pull-down sustaining thin film transistor T33, an eighth pull-down sustaining thin film transistor T43, a ninth pull-down sustaining thin film transistor T61, a tenth pull-down sustaining thin film transistor T62, and an eleventh The pull-down sustaining thin film transistor T63 and a twelfth pull-down sustaining thin film transistor T64.

The source of the seventh pull-down sustaining thin film transistor T33 is electrically connected to the drain of the pull-up thin film transistor T21. The drain of the seventh pull-down sustaining thin film transistor T33 is electrically connected to the low-level constant voltage source VSS.

The gate of the eighth pull-down sustaining thin film transistor T43 is electrically connected to the gate of the seventh pull-down sustaining thin film transistor T33. The source of the eighth pull-down sustaining thin film transistor T43 is electrically connected to the scan level signal Q (N). The drain of the eighth pull-down sustaining thin film transistor T43 is electrically connected to the low-level constant voltage source VSS.

The gate and source of the ninth pull-down sustaining thin film transistor T61 are electrically connected to a second pull-down control signal LC2.

The gate of the tenth pull-down sustaining thin film transistor T62 is electrically connected to the scan level signal Q (N). The source of the tenth pull-down sustaining thin film transistor T62 is electrically connected to the drain of the ninth pull-down sustaining thin film transistor T61. The drain of the tenth pull-down sustaining thin film transistor T62 is electrically connected to the low-level constant voltage source VSS.

The gate of the eleventh pull-down sustaining thin film transistor T63 is electrically connected to the drain of the ninth pull-down sustaining thin film transistor T61. The source of the eleventh pull-down sustaining thin film transistor T63 is electrically connected to the second pull-down control signal LC2. The drain of the eleventh pull-down sustaining thin film transistor T63 is electrically connected to the gate of the seventh pull-down sustaining thin film transistor T33.

The gate of the twelfth pull-down sustaining thin film transistor T64 is electrically connected to the scan level signal Q (N). A source of the twelfth pull-down sustaining thin film transistor T64 is electrically connected to a gate of the seventh pull-down sustaining thin film transistor T33. The drain of the twelfth pull-down sustaining thin film transistor T64 is electrically connected to the low-level constant voltage source VSS.

Please refer to FIGS. 1 to 3. FIG. 3 shows driving waveforms according to an embodiment of the present disclosure.

As shown in FIG. 3, after the start signal STV is switched from a high level to a low level, the liquid crystal display device starts scanning the scan lines G1-GN.

As described above, in the liquid crystal display device of FIG. 1, each stage of the GOA module 120 is electrically connected to three scanning lines and sequentially provides a scanning signal to the three scanning lines. More specifically, the three scan lines correspond to a control signal, that is, the three scan lines are controlled by a control signal. For example, the scanning line G1 corresponds to the control signal CLT1, the scanning line G2 corresponds to the control signal CLT2, and the scanning line G3 corresponds to the control signal CLT3. The control signals CLT1-CLT3 are sequentially turned on.

When the control signal is turned on and the clock signal (the first clock signal CLK1 or the second clock signal CLK2) is turned on, the corresponding scanning line will receive the turned-on scanning signal.

As shown in FIG. 3, when the control signal CLT1 is turned on (at a high level) and the first clock signal CLK1 is turned on (at a high level), the corresponding scanning line G1 receives the turned on scanning signal. When the control signal CLT2 is turned on (at a high level) and the first clock signal CLK1 is turned on (at a high level), the corresponding scanning line G2 receives the turned on scanning signal. When the control signal CLT3 is turned on (at a high level) and the first clock signal CLK1 is turned on (at a high level), the corresponding scanning line G3 receives the turned on scanning signal.

In the liquid crystal display device of the present disclosure, since each stage of the GOA module is electrically connected to at least two scan lines, the number of GOA modules can be saved, and the purposes of narrower frames and thinner can be achieved.

In summary, although the present disclosure has been disclosed as above with preferred embodiments, the above-mentioned preferred embodiments are not intended to limit the present disclosure. Those skilled in the art can make various modifications without departing from the spirit and scope of the present disclosure. This kind of modification and retouching, therefore, the scope of protection of this disclosure is subject to the scope defined by the claims.

Claims

A liquid crystal display device includes:

Multiple source lines;

A plurality of gate lines, the source lines and the gate lines defining a plurality of pixels; and

The GOA driving circuit includes a plurality of cascaded GOA modules, and each stage of the GOA module is electrically connected to at least two scan lines of the plurality of scan lines and sequentially toward at least two of the plurality of scan lines. The scanning line provides a scanning signal,

The GOA driving circuit alternately receives a first clock signal and a second clock signal. The first clock signal and the second clock signal are signals with opposite phases, and the first clock signal is input to a singular stage. The GOA module, the second clock signal is input to the GOA module of an even-numbered stage.
The liquid crystal display device according to claim 1, wherein each stage of the GOA module is electrically connected to three scanning lines of the plurality of scanning lines and sequentially provides scanning signals to the three scanning lines of the plurality of scanning lines. , The three scanning lines of each level of GOA module are controlled by a control signal,

When the control signal is turned on and the first clock signal is input to a GOA module of a single order, the scanning line corresponding to the control signal receives the turned-on scanning signal,

When the control signal is turned on and the second clock signal is input to the GOA module of an even-numbered stage, the scanning line corresponding to the control signal receives the turned-on scanning signal.
The liquid crystal display device according to claim 3, wherein the control signals controlling the three scan lines of the GOA module of each stage are sequentially turned on.
The liquid crystal display device according to claim 1, wherein each stage of the GOA module comprises:

A pull-up control module for generating a scan level signal according to a start signal or a scan signal of a previous stage;

A pull-up module, which is electrically connected to the pull-up control module and is configured to pull up the scan-level signal according to the scan-level signal and a clock signal of this level;

A pull-down module, which is electrically connected to the pull-up control module and the pull-up module and is configured to convert a low-level voltage provided by a low-level constant-voltage source according to a scanning signal of the next stage or according to the start signal. Output to the output of one of the scanning signals in this stage;

A first pull-down maintaining module, which is electrically connected to the pull-up control module, the pull-up module and the pull-down module and is used to maintain the scanning signal of the current level at a low level;

A second pull-down sustaining module, which is electrically connected to the pull-up control module, the pull-up module, the pull-down module, and the first pull-down sustain module and is used to maintain the scanning level signal of the current stage at a low power. Level; and

A bootstrap capacitor is electrically connected to the pull-up control module, the pull-up module, the pull-down module, the first pull-down sustain module, and the second pull-down sustain module and is used to generate a current-level scan. High level of the level signal.
The liquid crystal display device according to claim 4, wherein the pull-up control module comprises:

A pull-up control thin film transistor. The gate and source of the pull-up control thin film transistor are used to receive the start signal or the scanning signal of the previous stage, and the drain of the pull-up control thin film transistor is used to generate The scanning level signal.
The liquid crystal display device according to claim 5, wherein the pull-up module comprises:

A pull-up thin film transistor, a gate of the pull-up thin film transistor is electrically connected to a drain of the pull-up control thin film transistor and configured to receive the scan level signal, and a source of the pull-up thin film transistor receives The first clock signal or the second clock signal, and a drain of the pull-up thin film transistor is electrically connected to an output terminal of the scan signal.
The liquid crystal display device according to claim 6, wherein the pull-down module comprises:

A first pull-down thin film transistor, a gate of the first pull-down thin film transistor is electrically connected to a scan signal of the next-level GOA module or is electrically connected to the start signal, the first pull-down thin film A source of the transistor is electrically connected to the scan level signal, and a drain of the first pull-down thin film transistor is electrically connected to the low-level constant voltage source; and

A second pull-down thin film transistor, a gate of the second pull-down thin film transistor is electrically connected to a scan signal of the next-level GOA module or is electrically connected to the start signal, a source of the second pull-down thin film transistor The electrode is electrically connected to the drain of the pull-up thin film transistor, and the drain of the second pull-down thin film transistor is electrically connected to the low-level constant voltage source.
The liquid crystal display device according to claim 7, wherein the first pull-down maintaining module comprises:

A first pull-down sustaining thin film transistor, the source of the first pull-down sustaining thin film transistor is electrically connected to the drain of the pull-up thin film transistor, and the first pull-down sustaining thin film transistor is electrically connected To the low-level constant voltage source;

A second pull-down sustaining thin film transistor, a gate of the second pull-down sustaining thin film transistor is electrically connected to the gate of the first pull-down sustaining thin film transistor, and a source of the second pull-down sustaining thin film transistor is electrically connected To the scan level signal, the drain of the second pull-down sustaining thin film transistor is electrically connected to the low-level constant voltage source;

A third pull-down sustaining thin film transistor, the gate and source of the third pull-down sustaining thin film transistor are electrically connected to a first pull-down control signal;

A fourth pull-down sustaining thin film transistor, a gate of the fourth pull-down sustaining thin film transistor is electrically connected to the scan level signal, and a source of the fourth pull-down sustaining thin film transistor is electrically connected to the third pull-down Maintaining the drain of the thin film transistor, and the drain of the fourth pull-down maintaining thin film transistor is electrically connected to the low-level constant voltage source;

A fifth pull-down sustaining thin film transistor, a gate of the fifth pull-down sustaining thin film transistor is electrically connected to a drain of the third pull-down sustaining thin-film transistor, and a source of the fifth pull-down sustaining thin-film transistor is electrically connected to The first pull-down control signal, the drain of the fifth pull-down sustaining thin film transistor is electrically connected to the gate of the first pull-down sustaining thin film transistor; and

A sixth pull-down sustaining thin film transistor, a gate of the sixth pull-down sustaining thin film transistor is electrically connected to the scan level signal, and a source of the sixth pull-down sustaining thin film transistor is electrically connected to the first down The gate of the thin film transistor is pulled and maintained, and the drain of the sixth pull film is electrically connected to the low-level constant voltage source.
The liquid crystal display device according to claim 8, wherein the second pull-down maintaining module comprises:

A seventh pull-down sustaining thin film transistor, a source of the seventh pull-down sustaining thin film transistor is electrically connected to a drain of the pull-up thin film transistor, and a drain of the seventh pull-down sustaining thin film transistor is electrically connected to the drain Low-level constant voltage source;

An eighth pull-down sustaining thin film transistor, a gate of the eighth pull-down sustaining thin film transistor is electrically connected to the gate of the seventh pull-down sustaining thin film transistor, and a source of the eighth pull-down sustaining thin film transistor is electrically connected to The scan level signal, the drain of the eighth pull-down sustaining thin film transistor is electrically connected to the low-level constant voltage source;

A ninth pull-down sustaining thin film transistor, the gate and source of the ninth pull-down sustaining thin film transistor are electrically connected to a second pull-down control signal;

A tenth pull-down sustaining thin film transistor, a gate of the tenth pull-down sustaining thin film transistor is electrically connected to the scan level signal, and a source of the tenth pull-down sustaining thin film transistor is electrically connected to the ninth pull-down Maintaining the drain of the thin film transistor, and the drain of the tenth pull-down maintaining thin film transistor is electrically connected to the low-level constant voltage source;

The eleventh pull-down sustaining thin film transistor is electrically connected to the gate of the eleventh pull-down sustaining thin-film transistor, and the eleventh pull-down sustaining thin-film transistor is electrically connected to the drain of the ninth pull-down sustaining thin-film transistor. A source is electrically connected to the second pull-down control signal, and a drain of the eleventh pull-down sustaining thin film transistor is electrically connected to a gate of the seventh pull-down sustaining thin film transistor; and

A twelfth pull-down sustaining thin film transistor, a gate of the twelfth pull-down sustaining thin film transistor is electrically connected to the scan level signal, and a source of the twelfth pull-down sustaining thin film transistor is electrically connected to the The seventh pull-down sustains the gate of the thin film transistor. The drain of the twelfth pull-down sustaining thin film transistor is electrically connected to the low-level constant voltage source.
A liquid crystal display device includes:

Multiple source lines;

A plurality of gate lines, the source lines and the gate lines defining a plurality of pixels; and

The GOA driving circuit includes a plurality of cascaded GOA modules, and each stage of the GOA module is electrically connected to at least two scan lines of the plurality of scan lines and sequentially toward at least two of the plurality of scan lines. The scan line provides a scan signal.
The liquid crystal display device according to claim 10, wherein the GOA driving circuit alternately receives a first clock signal and a second clock signal.
The liquid crystal display device according to claim 11, wherein each stage of the GOA module is electrically connected to three scanning lines of the plurality of scanning lines and sequentially supplies scanning signals to the three scanning lines of the plurality of scanning lines. , The three scanning lines of each level of GOA module are controlled by a control signal,

When the control signal is turned on and the first clock signal is input to a GOA module of a single order, the scanning line corresponding to the control signal receives the turned-on scanning signal,

When the control signal is turned on and the second clock signal is input to the GOA module of an even-numbered stage, the scanning line corresponding to the control signal receives the turned-on scanning signal.
The liquid crystal display device according to claim 12, wherein the control signals controlling the three scan lines of the GOA module of each stage are sequentially turned on.
The liquid crystal display device according to claim 11, wherein each stage of the GOA module comprises:

A pull-up control module for generating a scan level signal according to a start signal or a scan signal of a previous stage;

A pull-up module, which is electrically connected to the pull-up control module and is configured to pull up the scan-level signal according to the scan-level signal and a clock signal of this level;

A pull-down module, which is electrically connected to the pull-up control module and the pull-up module and is configured to convert a low-level voltage provided by a low-level constant-voltage source according to a scanning signal of the next stage or according to the start signal. Output to the output of one of the scanning signals in this stage;

A first pull-down maintaining module, which is electrically connected to the pull-up control module, the pull-up module and the pull-down module and is used to maintain the scanning signal of the current level at a low level;

A second pull-down sustaining module, which is electrically connected to the pull-up control module, the pull-up module, the pull-down module, and the first pull-down sustain module and is used to maintain the scanning level signal of the current stage at a low power. Level; and

A bootstrap capacitor is electrically connected to the pull-up control module, the pull-up module, the pull-down module, the first pull-down sustain module, and the second pull-down sustain module and is used to generate a current-level scan. High level of the level signal.
The liquid crystal display device according to claim 14, wherein the pull-up control module comprises:

A pull-up control thin film transistor. The gate and source of the pull-up control thin film transistor are used to receive the start signal or the scanning signal of the previous stage, and the drain of the pull-up control thin film transistor is used to generate The scanning level signal.
The liquid crystal display device according to claim 15, wherein the pull-up module comprises:

A pull-up thin film transistor, a gate of the pull-up thin film transistor is electrically connected to a drain of the pull-up control thin film transistor and configured to receive the scan level signal, and a source of the pull-up thin film transistor receives The first clock signal or the second clock signal, and a drain of the pull-up thin film transistor is electrically connected to an output terminal of the scan signal.
The liquid crystal display device according to claim 16, wherein the pull-down module comprises:

A first pull-down thin film transistor, a gate of the first pull-down thin film transistor is electrically connected to a scan signal of the next-level GOA module or is electrically connected to the start signal, the first pull-down thin film A source of the transistor is electrically connected to the scan level signal, and a drain of the first pull-down thin film transistor is electrically connected to the low-level constant voltage source; and

A second pull-down thin film transistor, a gate of the second pull-down thin film transistor is electrically connected to a scan signal of the next-level GOA module or is electrically connected to the start signal, a source of the second pull-down thin film transistor The electrode is electrically connected to the drain of the pull-up thin film transistor, and the drain of the second pull-down thin film transistor is electrically connected to the low-level constant voltage source.
The liquid crystal display device according to claim 17, wherein the first pull-down maintaining module comprises:

A first pull-down sustaining thin film transistor, the source of the first pull-down sustaining thin film transistor is electrically connected to the drain of the pull-up thin film transistor, and the first pull-down sustaining thin film transistor is electrically connected To the low-level constant voltage source;

A second pull-down sustaining thin film transistor, a gate of the second pull-down sustaining thin film transistor is electrically connected to the gate of the first pull-down sustaining thin film transistor, and a source of the second pull-down sustaining thin film transistor is electrically connected To the scan level signal, the drain of the second pull-down sustaining thin film transistor is electrically connected to the low-level constant voltage source;

A third pull-down sustaining thin film transistor, the gate and source of the third pull-down sustaining thin film transistor are electrically connected to a first pull-down control signal;

A fourth pull-down sustaining thin film transistor, a gate of the fourth pull-down sustaining thin film transistor is electrically connected to the scan level signal, and a source of the fourth pull-down sustaining thin film transistor is electrically connected to the third pull-down Maintaining the drain of the thin film transistor, and the drain of the fourth pull-down maintaining thin film transistor is electrically connected to the low-level constant voltage source;

A fifth pull-down sustaining thin film transistor, a gate of the fifth pull-down sustaining thin film transistor is electrically connected to a drain of the third pull-down sustaining thin-film transistor, and a source of the fifth pull-down sustaining thin-film transistor is electrically connected to The first pull-down control signal, the drain of the fifth pull-down sustaining thin film transistor is electrically connected to the gate of the first pull-down sustaining thin film transistor; and

A sixth pull-down sustaining thin film transistor, a gate of the sixth pull-down sustaining thin film transistor is electrically connected to the scan level signal, and a source of the sixth pull-down sustaining thin film transistor is electrically connected to the first down The gate of the thin film transistor is pulled and maintained, and the drain of the sixth pull film is electrically connected to the low-level constant voltage source.
The liquid crystal display device according to claim 18, wherein the second pull-down maintaining module comprises:

A seventh pull-down sustaining thin film transistor, a source of the seventh pull-down sustaining thin film transistor is electrically connected to a drain of the pull-up thin film transistor, and a drain of the seventh pull-down sustaining thin film transistor is electrically connected to the drain Low-level constant voltage source;

An eighth pull-down sustaining thin film transistor, a gate of the eighth pull-down sustaining thin film transistor is electrically connected to the gate of the seventh pull-down sustaining thin film transistor, and a source of the eighth pull-down sustaining thin film transistor is electrically connected to The scan level signal, the drain of the eighth pull-down sustaining thin film transistor is electrically connected to the low-level constant voltage source;

A ninth pull-down sustaining thin film transistor, the gate and source of the ninth pull-down sustaining thin film transistor are electrically connected to a second pull-down control signal;

A tenth pull-down sustaining thin film transistor, a gate of the tenth pull-down sustaining thin film transistor is electrically connected to the scan level signal, and a source of the tenth pull-down sustaining thin film transistor is electrically connected to the ninth pull-down Maintaining the drain of the thin film transistor, and the drain of the tenth pull-down maintaining thin film transistor is electrically connected to the low-level constant voltage source;

The eleventh pull-down sustaining thin film transistor is electrically connected to the gate of the eleventh pull-down sustaining thin-film transistor, and the eleventh pull-down sustaining thin-film transistor is electrically connected to the drain of the ninth pull-down sustaining thin-film transistor. A source is electrically connected to the second pull-down control signal, and a drain of the eleventh pull-down sustaining thin film transistor is electrically connected to a gate of the seventh pull-down sustaining thin film transistor; and

A twelfth pull-down sustaining thin film transistor, a gate of the twelfth pull-down sustaining thin film transistor is electrically connected to the scan level signal, and a source of the twelfth pull-down sustaining thin film transistor is electrically connected to the The seventh pull-down sustains the gate of the thin film transistor. The drain of the twelfth pull-down sustaining thin film transistor is electrically connected to the low-level constant voltage source.