WO2020029037A1

WO2020029037A1 - Igzo thin film transistor, preparation method, and display panel

Info

Publication number: WO2020029037A1
Application number: PCT/CN2018/099046
Authority: WO
Inventors: 晏国文; 蔡武卫; 金敏澈
Original assignee: 深圳市柔宇科技有限公司
Priority date: 2018-08-06
Filing date: 2018-08-06
Publication date: 2020-02-13
Also published as: CN112703608A

Abstract

Disclosed is an IGZO thin film transistor, comprising a first drain/source; a metal layer, comprising an inclined section, the inclined section being connected to the first source/drain; an insulating layer, formed on the metal layer and the first source/drain, an opening being formed in the insulating layer so as to expose at least part of the first source/drain; and an IGZO layer, covering the first source/drain exposed in the opening. Also disclosed are a display panel and a preparation method for the IGZO thin film transistor. In the present application, the transverse length of the IGZO thin film transistor is shorter.

Description

IGZO thin film transistor, preparation method and display panel

Technical field

The present invention relates to the field of display technology, and in particular, to an IGZO thin film transistor, a preparation method and a display panel.

Background technique

The resolution of the display panel can be classified from two directions: display resolution and image resolution. As a new type of semiconductor material, IGZO (indium gallium zinc oxide) is a kind of channel material with higher electron mobility than amorphous silicon. It is commonly used in a new generation of high performance thin film transistors (TFTs). In order to improve the display resolution of the display panel, a large-screen OLED TV becomes possible. However, the smaller the size of the thin film transistor, the more it is conducive to the improvement of the image resolution of the display panel; therefore, how to obtain a smaller IGZO thin film transistor to obtain a higher display resolution and image resolution at the same time has become a manufacturer's first research The problem.

Summary of the invention

The embodiment of the technical solution discloses an IGZO thin film transistor, a preparation method and a display panel. The IGZO thin film transistor proposed by the technical solution has a small size, which is beneficial to the improvement of the display resolution and the image resolution of the display panel.

An IGZO thin film transistor includes a first source and drain; a metal layer includes an inclined section, the inclined section is connected to the first source and drain; an insulating layer is formed on the metal layer and the first On the source and drain, an opening is formed in the insulating layer to expose at least part of the first source and drain; and an IGZO layer covers the insulating layer corresponding to the inclined section and is connected and exposed to the The first source and drain in the opening.

A method for manufacturing an IGZO thin film transistor includes: forming a metal layer and a first source and drain; the metal layer includes an inclined section, and the inclined section is in contact with the first source and drain; An insulating layer is formed on the surface of the layer and the first source and drain, and an opening is formed in the insulating layer to expose at least part of the first source and drain; forming an IGZO layer, and the IGZO layer covers the oblique A segment corresponding to the insulating layer is connected to the first source-drain surface exposed in the opening.

A display panel includes the above-mentioned IGZO thin film transistor.

The display panel, the IGZO thin film transistor, and the preparation method of the technical solution directly connect the metal layer and the source and drain without the need to open a through-hole connection, that is, the space for the through-holes can be saved, which is also beneficial to reducing the size of the thin-film transistor. Size, which is also conducive to the improvement of the resolution of the display panel image; and the inclined layer is provided on the metal layer, so that the lateral length of the IGZO thin film transistor is smaller, which is more conducive to reducing the size of the thin film transistor, and further facilitate the display panel image resolution Increase in rate.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to explain the technical solutions in the embodiments of the present invention more clearly, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are just some embodiments of the technical solutions. For those of ordinary skill in the art, other drawings can be obtained according to these drawings without paying creative labor.

FIG. 1 is a schematic cross-sectional view of an IGZO thin film transistor according to a first embodiment of the present technical solution.

FIG. 2 is a flowchart of a method for manufacturing an IGZO thin film transistor according to a second embodiment of the present technical solution.

FIG. 3 is a schematic cross-sectional view of forming a buffer protection layer according to a second embodiment of the technical solution.

FIG. 4 is a schematic cross-sectional view of forming a metal layer and a first source / drain on a surface of the buffer protection layer according to a second embodiment of the present technical solution.

FIG. 5 is a schematic cross-sectional view of forming an insulating layer on the metal layer and the surface of the first source and drain according to the second embodiment of the present technical solution.

FIG. 6 is a schematic cross-sectional view of forming a second source and drain electrode on a surface of the insulating layer according to a second embodiment of the technical solution.

FIG. 7 is a schematic cross-sectional view of forming an IGZO layer in the second embodiment of the present technical solution.

FIG. 8 is a schematic cross-sectional view of forming a gate insulating layer and a gate on the IGZO layer corresponding to the inclined section according to the second embodiment of the present technical solution.

FIG. 9 is a schematic structural diagram of a display panel according to a third embodiment of the present technical solution.

detailed description

The following will clearly and completely describe the technical solutions in the technical solution embodiments of the present invention with reference to the accompanying drawings in the technical solution embodiments of the present invention. Obviously, the described embodiments are only a part of the technical solutions, but not all of them. The examples. Based on the embodiments in this technical solution, all other embodiments obtained by a person of ordinary skill in the art without making creative work fall into the protection scope of this technical solution.

Please refer to Figure 1. FIG. 1 is a schematic cross-sectional view of an IGZO thin film transistor according to a first embodiment of the present technical solution.

An IGZO thin film transistor 10 includes a metal layer 14 and a first source and drain electrode 15, an insulating layer 16 formed on the metal layer 14 and the first source and drain electrode 15, and an IGZO layer 18. Wherein, the metal layer 14 includes an inclined section 141, and the inclined section 141 is directly connected to the first source and drain electrodes 15. An opening 161 is formed in the insulating layer 16 so as to expose at least part of the first source and drain electrodes 15. The IGZO layer 18 covers the insulating layer 16 corresponding to the inclined section 141 and is connected to and exposed to all The first source and drain electrodes 15 in the opening 161.

A region corresponding to the inclined section 141 forms a channel region 101 of the IGZO thin film transistor 10.

In an alternative embodiment, as shown in FIG. 1, the IGZO thin film transistor 10 further includes a buffer protection layer 11, and the metal layer 14 and the first source and drain electrodes 15 are formed on the buffer protection layer 11. The buffer protection layer 11 includes a first surface 111, a second surface 112, and an inclined surface 113 formed between the first surface 111 and the second surface 112. The metal layer 14 is formed on the first surface 111. On a surface 111 and the inclined surface 113, the first source and drain electrodes 15 are formed on the second surface 112. The inclined section 141 of the metal layer 14 corresponds to and is formed on the inclined surface 113. on.

In an alternative embodiment, as shown in FIG. 1, the buffer protection layer 11 includes a first buffer layer 12 and a second buffer layer 13. The first buffer layer 12 includes the second surface 112, and the second surface 112 is substantially planar. The second buffer layer 13 is formed on the second surface 112 of the first buffer layer 12. The second buffer layer 13 includes a first surface 111 on a side far from the second surface 112 and is formed on the second surface 112. The inclined surface 113 between the first surface 111 and the second surface 112. The first surface 111 is substantially parallel to the second surface 112. Therefore, the cross section of the second buffer layer 13 is substantially trapezoidal, and the longer bottom edge is located on the second surface 112 side.

In other optional embodiments, the buffer protection layer 11 may also be an integrated structure, that is, both the first buffer layer 12 and the second buffer layer 13 are integrated, and the buffer protection layer 11 is not provided in layers. .

Preferably, an included angle between the inclined surface 113 and the second surface 112 is less than or equal to 60 degrees, and more preferably, less than 30 degrees to smoothly connect the first surface 111 and the second surface Surface 112.

In other optional embodiments, the manner of setting the buffer protection layer 11 may also be other manners, which is not limited to this embodiment.

In an alternative embodiment, as shown in FIG. 1, the first source and drain electrodes 15 and the metal layer 14 are metal of the same layer and are seamlessly connected. Further, the first source and drain electrodes 15 and the metal layer 14 may be integrally formed under the same process.

Preferably, the first source and drain electrodes 15 and the metal layer 14 are metal layers with good conductivity, such as molybdenum (Mo), copper (Cu), aluminum (Al), or a composite metal film layer thereof.

In an alternative embodiment, as shown in FIG. 1, the insulating layer 16 covers the first source and drain electrodes 15 and the metal layer 14, and also covers the first source and drain electrodes 15 and the non-formed layers. The first surface 111 and the second surface 112 of the metal layer 14.

In an alternative embodiment, as shown in FIG. 1, the size of the opening 161 on the insulating layer 16 is smaller than the size of the first source and drain electrode 15, so that part of the first source and drain electrode is exposed. 15.

In an alternative embodiment, as shown in FIG. 1, the IGZO thin film transistor 10 further includes a second source and drain electrode 17 formed on the insulating layer 16.

Wherein, the positions of the second source and drain electrodes 17 and the positions of the first source and drain electrodes 15 and the inclined section 141 are staggered from each other, that is, the second source and drain electrodes 17 are in the buffer protection layer 11. The vertical projection and the vertical projection of the first source and drain 15 and the inclined section 141 on the buffer protection layer 11 are staggered from each other and do not coincide.

In an alternative embodiment, as shown in FIG. 1, the second source and drain electrodes 17 are located on the surface of the insulating layer 16 near the inclined surface 113, and the first source and drain electrodes 15 are located on the surface. An edge of the second surface 112 is close to the inclined surface 113.

As shown in FIG. 1, the IGZO layer 18 covers the insulating layer 16 corresponding to the inclined section 141 and covers the first source and drain electrodes 15.

In an alternative embodiment, as shown in FIG. 1, the IGZO layer 18 also covers the second source and drain electrodes 17.

In an alternative embodiment, as shown in FIG. 1, the IGZO layer 18 fills the bottom and sidewalls of the opening 161, so as to directly connect the first source-drain exposed in the opening 161. Electrode 15, because the IGZO layer 18 fills the bottom and side walls of the opening 161, the IGZO layer 18 also forms a recess 182 at a position corresponding to the opening 161; It is shown that, in order to prevent the IGZO layer 18 from being easily peeled from the opening 161, the IGZO layer 18 also covers the peripheral area of the opening 161, that is, an annular ring structure 181 is formed at the opening 161. .

In an optional embodiment, the IGZO layer 18 can also completely fill the openings 161, that is, fill the openings 161 without forming the depressions 182.

In an alternative embodiment, as shown in FIG. 1, the IGZO thin film transistor 10 further includes a gate insulating layer (GI) 19 and a gate 20. The gate insulating layer 19 is formed on the IGZO layer 18, and a position of the gate insulating layer 19 corresponds to a position between the first source and drain electrodes 15 and the second source and drain electrode 17. The gate 20 covers the gate insulating layer 19, so that the position of the gate 20 also corresponds to the position between the first source and drain electrodes 15 and the second source and drain electrode 17. That is, the gate insulating layer 19 and the gate 20 are both formed in the channel region 101 of the IGZO thin film transistor 10.

In an alternative embodiment, as shown in FIG. 1, the IGZO thin film transistor 10 further includes a passivation layer 21. The passivation layer 21 covers the gate 20, the IGZO layer 18 around the gate 20, and the insulating layer 16 around the IGZO layer 18.

In an alternative embodiment, as shown in FIG. 1, the passivation layer 21 includes a third surface 211 away from the buffer protection layer 11, and the third surface 211 is substantially the same as the second surface 112. Phase parallel.

Please refer to Figure 2. FIG. 2 is a manufacturing flowchart of an IGZO thin film transistor according to a second embodiment of the present technical solution.

A method for preparing an IGZO thin film transistor includes the steps:

S201, forming a buffer protection layer;

S202. A metal layer and a first source and drain are formed on the surface of the buffer protection layer, the metal layer includes an inclined section, and the inclined section is connected to the first source and drain;

S203, forming an insulating layer on the metal layer and the surface of the first source and drain, and forming an opening in the insulating layer to expose at least part of the first source and drain;

S204, forming a second source and drain on a surface of the insulating layer;

S205. An IGZO layer is formed, and the IGZO layer covers the insulating layer corresponding to the inclined section, and covers the surface of the first source and drain electrodes exposed in the opening;

S206, forming a gate insulating layer and a gate on the IGZO layer corresponding to the inclined section; and

S207, a passivation layer is formed.

specifically:

In S201, please refer to FIG. 3 together to form a buffer protection layer 11. The buffer protection layer 11 includes a first surface 111, a second surface 112, and the first surface 111 and the first surface 111. The inclined surface 113 between the two surfaces 112.

In an alternative embodiment, the inclined surface 113 may be formed by controlling an exposure amount.

In an alternative embodiment, a first buffer layer 12 may be formed first, and then a second buffer layer 13 may be formed on the first buffer layer 12. The first buffer layer 12 includes the second surface 112, and the second surface 112 is substantially planar. The second buffer layer 13 is formed on the second surface 112 of the first buffer layer 12. The second buffer layer 13 includes a first surface 111 and a side away from the second surface 112. The inclined surface 113 is formed between the first surface 111 and the second surface 112. The first surface 111 is substantially parallel to the second surface 112. Therefore, the cross section of the second buffer layer 13 is substantially trapezoidal, and the longer bottom edge is located on the second surface 112 side. The first buffer layer 12 and the second buffer layer 13 together constitute the buffer protection layer 11. Wherein, a buffer film layer can be formed on the first buffer layer 12, the second buffer layer 13 can be obtained by exposing and developing the buffer film layer, and the second buffer layer 13 can be controlled by controlling the exposure amount. The inclined surface 113 is formed on one side of the layer 13.

In S202, please refer to FIG. 4 together, a metal layer 14 and a first source and drain electrode 15 are formed on the surface of the buffer protection layer 11; wherein the metal layer 14 is formed on the first surface 111 and the first surface 111 On the inclined surface 113, the first source and drain electrodes 15 are formed on the second surface 112 and are directly connected to the metal layer 14. The metal layer 14 includes an inclined section 141 corresponding to the inclined surface 113, and the inclined section 141 is directly connected to the first source and drain electrodes 15.

In an optional embodiment, the metal layer 14 and the first source / drain 15 are formed simultaneously in the same process, so that the first source / drain 15 and the metal layer 14 are the same layer of metal. And seamlessly. For example, the metal layer 14 and the first source and drain electrodes 15 may be simultaneously deposited and formed at predetermined positions by means of chemical deposition or electrodeposition.

In S203, please refer to FIG. 5 together. An insulating layer 16 is formed on the surface of the metal layer 14 and the first source and drain electrodes 15, and an opening 161 is formed in the insulating layer 16 to expose at least part of the surface. First source-drain 15.

In an optional embodiment, the insulating layer 16 may be formed on the surface of the metal layer 14 and the first source and drain electrodes 15, and then the openings may be formed in the insulating layer 16 by laser ablation or the like. 161.

In an alternative embodiment, as shown in FIG. 5, the insulating layer 16 further covers the first surface 111 and the second surface of the first source and drain electrode 15 and the metal layer 14, which are not formed. 112.

In an alternative embodiment, as shown in FIG. 5, the size of the opening 161 in the insulating layer 16 is smaller than the size of the first source and drain electrode 15, thereby exposing a portion of the first source and drain electrode. 15.

In S204, referring to FIG. 6 together, a second source and drain electrode 17 is formed on a surface of the insulating layer 16.

In an alternative embodiment, as shown in FIG. 6, the second source and drain electrodes 17 are located near the inclined surface 113 of the insulating layer 16, and the first source and drain electrodes 15 are located in the second An edge of the surface 112 is close to the inclined surface 113.

S205, please refer to FIG. 7 together to form an IGZO layer 18, which covers the insulating layer 16 corresponding to the inclined section 141 and covers the first source and drain exposed in the opening 161. Pole 15 surface.

In an optional embodiment, as shown in FIG. 7, the IGZO layer 18 also covers the second source and drain electrodes 17.

In an alternative embodiment, as shown in FIG. 7, the IGZO layer 18 is filled in the bottom and sidewalls of the opening 161 to connect the second source and drain exposed in the opening 161. 15. Because the IGZO layer 18 fills the bottom and sidewalls of the opening 161, from which the IGZO layer 18 also forms a recess 182 at a position corresponding to the opening 161; of which, as shown in FIG. In order to prevent the IGZO layer 18 from being easily peeled from the opening 161, the IGZO layer 18 also covers a peripheral area of the opening 161, that is, an annular ring structure 181 is formed at the opening 161.

In S206, referring to FIG. 8 together, a gate insulating layer (GI) 19 and a gate 20 are formed.

Wherein, the gate insulating layer 19 is formed on the IGZO layer 18, and a position of the gate insulating layer 19 corresponds to a position between the first source drain 15 and the second source drain 17 position. The gate 20 covers the gate insulating layer 19, so that the position of the gate 20 also corresponds to the position between the first source and drain electrodes 15 and the second source and drain electrode 17. That is, the gate insulating layer 19 and the gate 20 are both formed in the channel region 101 of the IGZO thin film transistor 10.

In an optional embodiment, after step S206, a step of conducting treatment may be further included. The conductive treatment is mainly performed in a region other than a region corresponding to the channel region 101.

In an optional embodiment, the conductive treatment step includes performing a plasma treatment on the IGZO layer 18 around the gate 20.

In S207, referring to FIG. 1 together, a passivation layer 21 is formed.

The passivation layer 21 covers the gate electrode 20, the IGZO layer 18 around the gate electrode 20, and the insulating layer 16 around the IGZO layer 18.

Please refer to Figure 9. FIG. 9 is a schematic cross-sectional view of a display panel according to a third embodiment of the present technical solution. The display panel 100 includes an IGZO thin film transistor 10.

Among them, preferably, the IGZO thin film transistor 10 may be the IGZO thin film transistor 10 as the first embodiment of the present technical solution, and details are not described herein again.

Compared with the traditional display panel, IGZO thin film transistor, and manufacturing process, the display panel, IGZO thin film transistor, and manufacturing method of the embodiment of the present technical solution have the following advantages:

1. In the embodiment of the technical solution, the channel region of the IGZO thin film transistor is set on an inclined plane, and the same channel region length, the lateral length of the IGZO thin film transistor of this case is smaller, which is more conducive to reducing the size of the thin film transistor, and further Conducive to the improvement of the image resolution of the display panel;

2. The back channel metal layer and source and drain of the traditional IGZO thin film transistor are located on different layers, and a via connection needs to be opened; the back channel metal layer and source and drain of the embodiment of the present technical solution are located on the same layer, and it is not necessary to open a via Hole connection, that is, the space for laying through holes can be saved, which is also conducive to reducing the size of the thin film transistor and further improving the image resolution of the display panel;

3. Further, in the conventional IGZO thin film transistor process, a via connection is established between the back channel metal layer and the source and drain, and the process is difficult; between the back channel metal layer and the source and drain in the embodiment of the technical solution, There is no need to open through-hole connections, which can reduce the process difficulty and improve the manufacturing yield of IGZO thin film transistors.

The above is a preferred embodiment of the technical solution. It should be pointed out that for those of ordinary skill in the art, without departing from the principles of the technical solution, several improvements and retouching can be made. These improvements and retouching It can also be regarded as the protection scope of this technical solution.

Claims

An IGZO thin film transistor including

First source and drain

The metal layer includes an inclined section, and the inclined section is connected to the first source and drain;

An insulating layer is formed on the metal layer and the first source and drain electrodes, and an opening is formed on the insulating layer to expose at least part of the first source and drain electrodes; and

An IGZO layer covers the insulating layer corresponding to the inclined section, and connects the first source and drain electrodes exposed in the opening.
The IGZO thin film transistor according to claim 1, further comprising a buffer protection layer, wherein the metal layer and the first source and drain electrodes are formed on the buffer protection layer; the buffer protection layer includes a first A surface, a second surface, and an inclined surface formed between the first surface and the second surface, the metal layer is formed on the first surface and the inclined surface, and the first source and drain Formed on the second surface; the inclined section of the metal layer corresponds to and is formed on the inclined surface.
The IGZO thin film transistor according to claim 2, wherein the buffer protection layer includes a first buffer layer and a second buffer layer; the first buffer layer includes the second surface; and the second buffer layer Formed on the second surface of the first buffer layer, the second buffer layer includes the first surface away from the second surface, and is formed on the first surface and the second surface Between the inclined surfaces; the first surface is parallel to the second surface.
The IGZO thin film transistor according to claim 3, wherein an included angle between the inclined surface and the second surface is less than or equal to 60 degrees.
The IGZO thin film transistor according to claim 1, wherein the IGZO thin film transistor further comprises a second source and drain formed on the insulating layer; wherein the position of the second source and drain is the same as the position of the second source and drain. The positions of the first source and drain and the inclined section are staggered from each other.
The IGZO thin film transistor according to claim 5, wherein the IGZO layer further covers the second source and drain.
The IGZO thin film transistor according to claim 1, wherein the IGZO thin film transistor further comprises a gate insulating layer and a gate; the gate insulating layer is formed on the IGZO layer and is formed on the slope Within the region corresponding to the segment; the gate covers the gate insulating layer.
The IGZO thin film transistor according to claim 1, wherein the IGZO layer is filled in the bottom and the sidewall of the opening, so as to directly connect the first source and drain exposed in the opening, Therefore, a recess is formed in the IGZO layer at a position corresponding to the opening.
The IGZO thin film transistor according to claim 1, wherein the first source / drain and the metal layer are metal of the same layer and are seamlessly connected.
The IGZO thin film transistor according to claim 1, wherein a size of the opening in the insulating layer is smaller than a size of the first source and drain, so that part of the first source and drain is exposed.
A method for preparing an IGZO thin film transistor includes:

Forming a metal layer and a first source and drain; the metal layer includes an inclined section, and the inclined section is connected to the first source and drain;

Forming an insulating layer on the metal layer and the surface of the first source and drain, and forming an opening in the insulating layer to expose at least part of the first source and drain;

An IGZO layer is formed, and the IGZO layer covers the insulation layer corresponding to the inclined section, and is connected to the surface of the first source and drain exposed in the opening.
The method for manufacturing an IGZO thin film transistor according to claim 11, further comprising steps before forming the metal layer and the first source and drain electrodes:

Forming a buffer protection layer; wherein the buffer protection layer includes a first surface, a second surface, and an inclined surface formed between the first surface and the second surface; Mentioned inclined surface.
The method for manufacturing an IGZO thin film transistor according to claim 12, wherein forming the buffer protection layer comprises the steps of:

Forming a first buffer layer first; the first buffer layer includes the second surface, and the second surface is a flat surface; and

A second buffer layer is formed. The second buffer layer is formed on the second surface of the first buffer layer. The second buffer layer includes the first surface away from the second surface and The inclined surface formed between the first surface and the second surface; the first surface is parallel to the second surface.
The method for manufacturing an IGZO thin film transistor according to claim 11, wherein the metal layer and the first source and drain electrodes are formed simultaneously by chemical deposition or electrodeposition.
The method for manufacturing an IGZO thin film transistor according to claim 11, wherein after forming an opening in the insulating layer to expose at least part of the first source and drain electrodes, and before forming the IGZO layer, Also includes steps:

A second source / drain is formed on the surface of the insulating layer; wherein the position of the second source / drain and the positions of the first source / drain and the inclined section are staggered from each other.
The method of claim 15, wherein the IGZO layer further covers the second source and drain electrodes.
The method for manufacturing an IGZO thin film transistor according to claim 11, further comprising forming a gate insulating layer on the IGZO layer corresponding to the inclined section and forming a gate electrode on the gate insulating layer. step.
The IGZO thin film transistor according to claim 17, further comprising a step of forming a passivation layer after forming the gate insulating layer and the gate.
The IGZO thin film transistor according to claim 11, wherein the IGZO layer is filled in the bottom and the sidewall of the opening, so as to directly connect the first source and drain exposed in the opening, Therefore, a recess is formed in the IGZO layer at a position corresponding to the opening.
A display panel includes the IGZO thin film transistor according to any one of claims 1 to 10.