WO2020026387A1 - Élément d'imagerie et endoscope - Google Patents

Élément d'imagerie et endoscope Download PDF

Info

Publication number
WO2020026387A1
WO2020026387A1 PCT/JP2018/028934 JP2018028934W WO2020026387A1 WO 2020026387 A1 WO2020026387 A1 WO 2020026387A1 JP 2018028934 W JP2018028934 W JP 2018028934W WO 2020026387 A1 WO2020026387 A1 WO 2020026387A1
Authority
WO
WIPO (PCT)
Prior art keywords
chip
layer
semiconductor substrate
imaging
imaging device
Prior art date
Application number
PCT/JP2018/028934
Other languages
English (en)
Japanese (ja)
Inventor
理 足立
Original Assignee
オリンパス株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by オリンパス株式会社 filed Critical オリンパス株式会社
Priority to PCT/JP2018/028934 priority Critical patent/WO2020026387A1/fr
Publication of WO2020026387A1 publication Critical patent/WO2020026387A1/fr

Links

Images

Classifications

    • A—HUMAN NECESSITIES
    • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
    • A61B1/00—Instruments for performing medical examinations of the interior of cavities or tubes of the body by visual or photographical inspection, e.g. endoscopes; Illuminating arrangements therefor
    • A61B1/04—Instruments for performing medical examinations of the interior of cavities or tubes of the body by visual or photographical inspection, e.g. endoscopes; Illuminating arrangements therefor combined with photographic or television appliances
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith

Definitions

  • the present disclosure relates to an imaging device and an endoscope that generate image data by imaging a subject.
  • the image sensor used in the conventional endoscope is required to have a high image quality and a reduced area in order to reduce the load when the image sensor is inserted into a subject. Since the ratio of the peripheral circuit for driving the array and the wiring area of the peripheral circuit is larger than the ratio of the area of the pixel array, this is an obstacle to further reduction in the area. For this reason, even if the area is reduced by stacking the pixel chip and the circuit chip as in the technique of Patent Document 1 described above, the increase in the number of wiring layers only causes an increase in cost. In addition, processing of a TSV (Through Silicon Via) connecting the first semiconductor chip and the second semiconductor chip becomes difficult, and the area required for arranging the TSV increases. It was difficult to reduce the area.
  • TSV Three Silicon Via
  • the present disclosure has been made in view of the above, and has as its object to provide an imaging element and an endoscope that can further reduce the area.
  • an image sensor includes a pixel unit in which a plurality of pixels that generate an image signal according to a received light amount are arranged in a two-dimensional matrix, A first chip having a peripheral circuit that selects any one of the plurality of pixels, reads an image signal from the selected pixel, and outputs the read image signal; an external reference clock and a reset pulse And a second chip including an interface circuit that drives a first chip in response to a power supply voltage and outputs an imaging signal read out from the selected pixel to the outside, wherein the first chip is stacked; Wherein the second chip comprises a first semiconductor substrate, a first multilayer wiring layer which is laminated on a surface side of the first semiconductor substrate, and constitutes the interface circuit, Said laminated on the back surface side of the first semiconductor substrate made corresponding to the region overlapping the light receiving surface of the Motobu, having a first chip and electrically connected to the rewiring layer.
  • connection unit that electrically connects the first chip and the rewiring layer in a region other than the pixel unit along a direction parallel to the light receiving surface. Is further provided.
  • connection portion may be formed in a wall shape around the light receiving surface.
  • the imaging device according to the present disclosure is provided between the first chip and the second chip, is formed using a light blocking member that blocks light, and
  • the semiconductor device further includes an adhesive layer that adheres the chip and the second chip.
  • the rewiring layer includes a first rewiring layer electrically connected to an external ground line.
  • the rewiring layer is electrically connected to a transmission cable that transmits a power supply voltage input from the outside, and transmits the power supply voltage to the first chip. It has a second redistribution layer.
  • an endoscope includes an insertion unit that is inserted into a subject, and an imaging device that is provided at a distal end of the insertion unit and captures an image of the subject.
  • a pixel unit in which a plurality of pixels that generate an imaging signal according to the amount are arranged in a two-dimensional matrix, and any one of the plurality of pixels is selected, and an imaging signal is read from the selected pixel; and
  • a second chip having the first chip stacked thereon, wherein the second chip has a first semiconductor substrate and a first semiconductor substrate.
  • a first multilayer wiring layer that forms the interface On the surface side of A first multilayer wiring layer that forms the interface, and a first chip that is stacked on a back surface side of the first semiconductor substrate corresponding to a region overlapping with a light receiving surface of the pixel portion; And a redistribution layer electrically connected to the wiring.
  • FIG. 1 is a diagram schematically illustrating an entire configuration of the endoscope system according to the first embodiment.
  • FIG. 2 is a front view on the light receiving surface side of the first chip constituting the imaging device according to the first embodiment.
  • FIG. 3 is a front view of the back surface side of the second chip constituting the image sensor according to the first embodiment.
  • FIG. 4 is a sectional view taken along the line IV-IV in FIGS. 2 and 3.
  • FIG. 5 is a sectional view taken along line VV of FIGS. 2 and 3.
  • FIG. 6 is a front view of the light receiving surface side of the first chip constituting the image sensor according to the second embodiment.
  • FIG. 7 is a front view of the back surface side of the second chip included in the imaging device according to the second embodiment.
  • FIG. 8 is a sectional view taken along line VIII-VIII in FIGS. 6 and 7.
  • FIG. 9 is a sectional view taken along line IX-IX of FIGS. 6 and 7.
  • an endoscope system including an endoscope inserted into a subject will be described. Further, the present disclosure is not limited by the embodiments. Further, in the description of the drawings, the same portions will be denoted by the same reference numerals and described. Furthermore, it should be noted that the drawings are schematic, and the relationship between the thickness and the width of each member, the ratio of each member, and the like are different from reality. In addition, the drawings include portions having different dimensions and ratios.
  • FIG. 1 is a diagram schematically illustrating an entire configuration of the endoscope system according to the first embodiment.
  • the endoscope system 1 illustrated in FIG. 1 includes an endoscope 2, a transmission cable 3, a connector unit 5, a processing device 6, a display device 7, and a light source device 8.
  • the endoscope 2 captures an image of the inside of the subject by inserting the insertion section 100 that is a part of the transmission cable 3 into the body cavity of the subject.
  • the endoscope 2 outputs an imaging signal generated by imaging the inside of the subject to the processing device 6.
  • the endoscope 2 is provided with an imaging element 20 (imaging device) for performing imaging on one end side of the transmission cable 3 and on the distal end portion 101 side of the insertion section 100 inserted into the body cavity of the subject. I have.
  • an operation unit 4 that receives various operations on the endoscope 2 is connected to the base end 102 side of the insertion unit 100.
  • An imaging signal generated by imaging by the imaging device 20 is output to the connector unit 5 via the transmission cable 3 having a length of several meters, for example. The detailed configuration of the image sensor 20 will be described later.
  • the connector section 5 is detachably connected to the processing device 6 and the light source device 8.
  • the connector section 5 performs predetermined signal processing on the image pickup signal transmitted from the transmission cable 3 and outputs the signal to the processing device 6.
  • the processing device 6 performs predetermined image processing on the image pickup signal input from the connector unit 5 and outputs the image signal to the display device 7. Further, the processing device 6 totally controls the entire endoscope system 1.
  • the display device 7 displays an image corresponding to the image signal on which the processing device 6 has performed the image processing. In addition, the display device 7 displays various information related to the endoscope system 1.
  • the light source device 8 irradiates the subject with illumination light from the distal end portion 101 of the insertion section 100 of the endoscope 2 via the connector section 5 and the transmission cable 3 under the control of the processing apparatus 6.
  • the light source device 8 is configured using, for example, a xenon lamp or a white LED (Light Emitting Diode).
  • a xenon lamp or a white LED (Light Emitting Diode).
  • a white LED Light Emitting Diode
  • FIG. 2 is a front view of the first chip included in the image sensor 20 on the light receiving surface side.
  • FIG. 3 is a front view of the back surface side of the second chip constituting the image sensor 20.
  • FIG. 4 is a sectional view taken along the line IV-IV in FIGS. 2 and 3.
  • FIG. 5 is a sectional view taken along line VV of FIGS. 2 and 3.
  • the imaging device 20 shown in FIGS. 2 to 5 is configured by using a BSI (Back Side Illumination) type CMOS (Complementary Metal Oxide Semiconductor).
  • the imaging element 20 includes a first chip 21 and a second chip 22.
  • the imaging element 20 is formed by laminating an adhesive layer 23 formed using a transparent adhesive such as a resin on the back side of the second chip 22 and then laminating the first chip 21.
  • the first chip 21 and the second chip 22 are electrically connected using the first connection part 24.
  • the first chip 21 is arranged in a two-dimensional matrix and has a pixel portion 201 having a plurality of pixels that output an imaging signal according to the amount of received light, a driving signal, a control signal, and a driving signal input from the second chip 22.
  • the pixel unit is driven based on the driving voltage, a predetermined pixel is selected from the pixel unit, an image signal is read from the selected pixel, and the read image signal is output to the second chip 22 that outputs the image signal.
  • a peripheral circuit 202 is configured using, for example, a photodiode, a color filter, a microlens, a plurality of transistors, and the like.
  • the peripheral circuit 202 is configured using a horizontal scanning circuit, a vertical scanning circuit, a timing generator, and the like. The detailed configuration of the first chip 21 will be described later.
  • the second chip 22 generates a drive signal, a control signal, and a drive voltage based on the reference clock, the reset pulse, and the power supply voltage input from the processing device 6, and converts the drive signal, the control signal, and the drive voltage into the first signal. Is output to the chip 21. In addition, the second chip 22 outputs the imaging signal input from the first chip 21 to the processing device 6 via the transmission cable 3. The detailed configuration of the second chip 22 will be described later.
  • the second chip 22 has a first semiconductor substrate 221 made of, for example, silicon (Si). Above the first semiconductor substrate 221 (on the first chip side), the rewiring layer 222 and the second One passivation layer 223 is formed in this order.
  • the second chip 22 is formed by laminating a first multilayer wiring layer 224 and a second passivation layer 225 in this order under the first semiconductor substrate 221.
  • an interface circuit for outputting an image signal to the transmission cable 3 is formed by the first multilayer wiring layer 224.
  • the rewiring layer 222 is electrically connected to the transmission cable 3, and includes a first rewiring layer 222 a serving as a VDD wiring for transmitting the power supply voltage transmitted from the transmission cable 3 to the first chip 21, and an external wiring. Is electrically connected to the ground terminal to which the ground line is connected, and the second rewiring layer 222b, which is a VSS wiring, is formed on the same surface (see FIG. 3). Specifically, each of the first redistribution layer 222a and the second redistribution layer 222b is formed on the same surface on the back side (the upper side in FIGS. 4 and 5) of the first semiconductor substrate 221. .
  • Each of the first redistribution layer 222a and the second redistribution layer 222b is configured using, for example, copper (Cu), aluminum (Al), tungsten (W), or the like.
  • the rewiring layer 222 is laminated on the back surface of the first semiconductor substrate 221 corresponding to the region overlapping the light receiving surface of the pixel portion 201 of the first chip 21, and is electrically connected to the first chip 21. You. Note that the shape and the area ratio of each of the first redistribution layer 222a and the second redistribution layer 222b can be changed as appropriate. it can.
  • a plurality of openings 223a are provided in the first passivation layer 223, and a part of the rewiring layer 222 is exposed.
  • the first passivation layer 223 is configured using, for example, silicon nitride (SiN) and polyimide (PI).
  • the first connection portion 24 is provided in each opening 223a.
  • the first connection portion 24 electrically connects the first chip 21 and the rewiring layer 222 in a region other than the pixel portion 201 along a direction parallel to the light receiving surface of the pixel portion 201 in the first chip 21. I do. Specifically, the first connection portion 24 is formed in a wall shape around the light receiving surface of the pixel portion 201 of the first chip 21, and is connected to a second connection PAD 215 c of the first chip 21 described later. The redistribution layer 222 of the second chip 22 is electrically connected.
  • the first connection unit 24 is configured using, for example, gold (Au) or the like.
  • the first multilayer wiring layer 224 has a wiring layer 2241 on which an interface circuit for outputting an image signal to the transmission cable 3 is formed, and an interlayer insulating layer 2242 for insulating between the wiring layers 2241.
  • the interface circuit formed in the first multilayer wiring layer 224 generates a drive signal, a control signal, and a drive voltage based on the reference clock, the reset pulse, and the power supply voltage input from the processing device 6, and generates the drive signal.
  • a signal, a control signal, and a drive voltage are output to the first chip 21.
  • the wiring layer 2241 includes an uppermost wiring layer 224a closest to the first semiconductor substrate 221, an intermediate wiring layer 224b, and a lowermost first connection PAD 224c.
  • Each of the wiring layer 224a, the wiring layer 224b, and the first connection PAD 224c is configured using, for example, copper (Cu), aluminum (Al), tungsten (W), or the like.
  • the interlayer insulating layer 2242 is formed between the wiring layers 2241.
  • the interlayer insulating layer 2242 is formed using, for example, silicon dioxide (SiO 2) and silicon nitride (SiN). Note that each of the plurality of wiring layers 2241 and the interlayer insulating layer 2242 may be formed using the same material in all layers, or may be formed using two or more materials depending on the layer.
  • the first multilayer wiring layer 224 has a first scribe seal 226 provided so as to surround a range corresponding to a light receiving surface of the pixel portion 201 of the first chip 21 described later.
  • the first scribe seal 226 has an upper side electrically connected to the wiring layer 224a or the first semiconductor substrate 221 and a lower side partially electrically connected to the first connection PAD 224c.
  • the first scribe seal 226 is a region overlapping the light receiving surface of the first chip 21 in a region other than the light receiving surface of the pixel portion 201 along a direction orthogonal to the light receiving surface of the pixel portion 201 of the first chip 21 described later.
  • the first scribe seal 226 is configured using, for example, copper (Cu), aluminum (Al), and tungsten (W). That is, the first scribe seal 226 prevents the liquid such as moisture from invading the inside of the second chip 22. Further, since the second chip 22 is shielded from light by the first scribe seal 226 and the rewiring layer 222 so as to surround the first multilayer wiring layer 224, hot carriers generated in the first multilayer wiring layer 224 are generated. Leakage of light to the first chip 21 can be prevented.
  • a penetration electrode 227 (TSV: Through Silicon Silicon Via) penetrating the first semiconductor substrate 221 and electrically connecting the rewiring layer 222 and the wiring layer 2241. Is provided.
  • a plurality of openings 225a are provided in the second passivation layer 225, and the first connection PAD224c is exposed.
  • the second connection portion 25 is provided in each opening 225a.
  • the second connection unit 25 is electrically connected to, for example, a silicon interposer or a third chip (capacitance chip) not shown.
  • the first chip 21 has a second semiconductor substrate 211 made of, for example, silicon (Si). On the upper side (surface on the light receiving surface side) of the second semiconductor substrate 211, an inspection PAD 212, a color filter layer 213 and the microlens layer 214 in this order.
  • the second semiconductor substrate 211 is formed by laminating the second multilayer wiring layer 215 and the third passivation layer 216 in this order on the lower side (the rear surface on the second chip 22 side).
  • the second semiconductor substrate 211 is provided with a plurality of photodiodes 211a, a plurality of transistors 211b for driving the photodiodes 211a, and a peripheral circuit 202 for controlling the plurality of transistors 211b. Further, the second semiconductor substrate 211 has a second through electrode 217 (TSV) that penetrates the second semiconductor substrate 211 at a predetermined position and electrically connects the inspection PAD 212 and the second multilayer wiring layer 215. ) Is provided.
  • TSV second through electrode 217
  • any one of an R filter, a G filter, and a B filter is disposed for each light receiving surface of the photodiode 211a.
  • An opening 213a is provided at a predetermined position in the color filter layer 213, and the inspection PAD 212 is exposed.
  • the microlens layer 214 is provided with a microlens 214a for each photodiode 211a.
  • the micro lens 214a focuses light on the photodiode 211a.
  • the plurality of photodiodes 211a, the plurality of transistors 211b, the color filter layer 213, and the microlens layer 214 function as a plurality of pixels that generate an imaging signal.
  • the second multilayer wiring layer 215 has a wiring layer 2151 and an interlayer insulating layer 2152 for insulating between the wiring layers 2151.
  • the wiring layer 2151 includes an uppermost wiring layer 2151a closest to the second semiconductor substrate 211, an intermediate wiring layer 2151b, and a lowermost second connection PAD 2151c.
  • the wiring layer 2151a, the wiring layer 2151b, and the second connection PAD 2151c are configured using, for example, copper (Cu), aluminum (Al), tungsten (W), or the like.
  • the interlayer insulating layer 2152 is formed using, for example, silicon dioxide (Si02) and silicon nitride (SiN). Note that each of the plurality of wiring layers 2151 and the interlayer insulating layer 2152 may be formed using the same material in all layers, or may be formed using two or more materials depending on the layer.
  • the second multilayer wiring layer 215 has a second scribe seal 218.
  • the second scribe seal 218 surrounds a region other than the light receiving surface of the pixel portion 201 and overlapping with the light receiving surface of the first chip 21 in a direction other than the light receiving surface of the pixel portion 201 along the direction orthogonal to the light receiving surface of the pixel portion 201 of the first chip 21. And formed in a wall shape.
  • the upper side of the second scribe seal 218 is electrically connected to the wiring layer 215a or the second semiconductor substrate 211, and the lower side is electrically connected to the second connection PAD 2151c. That is, the second scribe seal 218 prevents the liquid such as moisture from invading the inside of the first chip 21.
  • the third passivation layer 216 is provided with a plurality of openings 216a, the second connection PAD2151c is exposed, and the first connection 24 is provided.
  • the imaging element 20 configured as described above performs the VSS wiring and the VDD wiring of the first chip 21 by using the rewiring layer 222 of the second chip 22, and thereby the VSS wiring and the VDD of the first chip 21. By reducing the area required for the wiring, the size of the imaging device 20 can be reduced.
  • the rewiring layer 222 is laminated on the back surface side of the first semiconductor substrate 221 corresponding to the region overlapping with the light receiving surface of the pixel portion 201 of the first chip 21, Since it is electrically connected to the chip 21, the area can be further reduced.
  • the first redistribution layer 222a serving as the VDD wiring and the second redistribution layer 222b serving as the VSS wiring are arranged below the pixel portion 201 of the first chip 21. Accordingly, the TSV processing area can be reduced while the number of wiring layers of the VSS wiring and the VDD wiring of the first chip 21 is reduced, so that further downsizing can be achieved and manufacturing can be performed at low cost. it can.
  • the first scribe seal 226 and the rewiring layer 222 shield the light so as to surround the first multilayer wiring layer 224, hot light generated in the first multilayer wiring layer 224 is generated. It is possible to prevent light emitted by the carrier from leaking to the first chip 21.
  • the first connecting portion 24, the first scribe seal 226, and the second scribe seal 218 are formed along the direction orthogonal to the light receiving surface of the pixel portion 201 of the first chip 21. Since a region other than the light receiving surface of the pixel portion 201 is formed in a wall shape surrounding the region overlapping with the light receiving surface of the first chip 21, light entering from the outside can be prevented, and light entering from the outside can be prevented. Invasion of liquid or moisture can be prevented.
  • the adhesive layer 23 is formed using a transparent adhesive.
  • a light-blocking member that blocks light such as a black adhesive or aluminum, may be used.
  • the first chip 21 and the second chip 22 may be bonded together. Accordingly, it is possible to reliably prevent light emission due to hot carriers generated in the second chip 22 from leaking to the first chip 21, thereby suppressing reflection from the rewiring layer 222 and deteriorating image quality due to ghosts and the like. Can be prevented.
  • the image sensor 20 is a BSI CMOS, but in the second embodiment, the imaging device 20 is configured using a Front Side Illumination (FSI) CMOS.
  • FSI Front Side Illumination
  • the configuration of the imaging device according to the second embodiment will be described. Note that the same components as those of the image sensor 20 according to Embodiment 1 described above are denoted by the same reference numerals, and detailed description is omitted.
  • FIG. 6 is a front view of the light receiving surface side of the first chip constituting the image sensor according to the second embodiment.
  • FIG. 7 is a front view of the back surface side of the second chip constituting the image sensor according to the second embodiment.
  • FIG. 8 is a sectional view taken along line VIII-VIII in FIGS. 6 and 7.
  • FIG. 9 is a sectional view taken along line IX-IX of FIGS. 6 and 7.
  • the imaging device 20A shown in FIGS. 6 to 9 includes a first chip 21A instead of the first chip 21 of the imaging device 20 according to Embodiment 1 described above. Hereinafter, a detailed configuration of the first chip 21A will be described.
  • the first chip 21A has a second semiconductor substrate 211A made of, for example, silicon (Si). On the second semiconductor substrate 211A (on the light receiving surface side), a multilayer wiring layer, an interlayer insulating film and It is formed by laminating a planarization layer 215A including a color filter and a microlens layer 214 in this order. The second semiconductor substrate 211A is formed by laminating a third passivation layer 216A on the lower side (on the side of the second chip 22).
  • the second semiconductor substrate 211A is provided with a plurality of photodiodes, a plurality of transistors 211b for driving the photodiodes, and a peripheral circuit 202 for controlling the plurality of transistors 211b.
  • the second semiconductor substrate 211A penetrates the second semiconductor substrate 211A at a predetermined position, and is electrically connected to the first connection portion 24, a connection PAD 2161 described later, and a second multilayer wiring layer 2151A.
  • a second through electrode 217A (TSV) is provided.
  • a plurality of openings 2162 are provided in the third passivation layer 216A, and the first connection portion 24 and the second connection PAD 2161 are provided in each opening 2162 in a stacked manner.
  • the planarization layer 215A has a second multilayer wiring layer 2151A and an interlayer insulating layer 2152 insulating between the layers of the second multilayer wiring layer 2151A.
  • the second multilayer wiring layer 2151A has a test PAD 212, an intermediate wiring layer 2152bb, and a wiring layer 2152cc.
  • Each of the inspection PAD 212, the wiring layer 2152bb, and the wiring layer 2152cc is configured using, for example, copper (Cu), aluminum (Al), tungsten (W), or the like.
  • the interlayer insulating layer 2152A is formed using, for example, silicon dioxide (Si02), silicon nitride (SiN), or the like. Note that each of the second multilayer wiring layer 2151A and the interlayer insulating layer 2152A may be formed using the same material in all layers, or may be formed using two or more materials depending on the layer.
  • the planarization layer 215A has a second scribe seal 218A formed in a wall shape surrounding the pixel region of the pixel portion 201.
  • the second scribe seal 218A has an upper side connected to the inspection PAD 212 and a lower side electrically connected to the second semiconductor substrate 211A.
  • the rewiring layer 222 is stacked on the back surface side of the first semiconductor substrate 221A corresponding to the region overlapping with the light receiving surface of the pixel portion 201 of the first chip 21A, Since it is electrically connected to the chip 21, the area can be further reduced.
  • the first redistribution layer 222a serving as the VDD wiring and the second redistribution layer 222b serving as the VSS wiring are disposed below the pixel unit 201 of the first chip 21A.
  • the TSV processing area can be reduced while reducing the number of wiring layers of the VSS wiring and the VDD wiring of the first chip 21A, so that further downsizing can be achieved and manufacturing can be performed at low cost. it can.
  • the first scribe seal 226 and the rewiring layer 222 shield the light so as to surround the first multilayer wiring layer 224, the hot light generated in the first multilayer wiring layer 224 is generated. It is possible to prevent light emitted by the carrier from leaking to the first chip 21A.
  • Various inventions can be formed by appropriately combining a plurality of components disclosed in the first and second embodiments of the present disclosure described above. For example, some components may be deleted from all the components described in the first and second embodiments of the present disclosure. Furthermore, the components described in the first and second embodiments of the present disclosure described above may be appropriately combined.
  • control device and the light source device are separate bodies, but may be formed integrally.
  • Embodiments 1 and 2 of the present disclosure the endoscope system has been described. However, for example, a video microscope for imaging a subject, a mobile phone having an imaging function, and a tablet terminal having an imaging function may be used. Can be applied.
  • the endoscope system includes a flexible endoscope.
  • an endoscope system including a hard endoscope and an industrial endoscope may be used.
  • the present invention can be applied to an endoscope system provided.
  • the endoscope system including the endoscope to be inserted into the subject is described.
  • the endoscope system including the rigid endoscope, the sinus The present invention can also be applied to endoscopes and endoscope systems such as electric scalpels and inspection probes.
  • the “unit” described above can be read as “means” or “circuit”.
  • the control unit can be read as a control unit or a control circuit.

Landscapes

  • Health & Medical Sciences (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Surgery (AREA)
  • Physics & Mathematics (AREA)
  • Animal Behavior & Ethology (AREA)
  • Public Health (AREA)
  • Radiology & Medical Imaging (AREA)
  • Optics & Photonics (AREA)
  • Nuclear Medicine, Radiotherapy & Molecular Imaging (AREA)
  • Biomedical Technology (AREA)
  • Heart & Thoracic Surgery (AREA)
  • Medical Informatics (AREA)
  • Molecular Biology (AREA)
  • Biophysics (AREA)
  • General Health & Medical Sciences (AREA)
  • Pathology (AREA)
  • Veterinary Medicine (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Endoscopes (AREA)

Abstract

La présente invention concerne un élément d'imagerie et un endoscope pour lesquels la zone peut être encore réduite. L'élément d'imagerie comprend une première puce et une seconde puce. La seconde puce comprend : un premier substrat semi-conducteur ; une première couche de câblage multicouche qui est stratifiée sur le côté de surface avant du premier substrat semi-conducteur, et qui configure un circuit d'interface pour délivrer en sortie des signaux d'imagerie vers l'extérieur ; et une couche de recâblage qui est stratifiée sur le côté de surface arrière du premier substrat semi-conducteur correspondant à une région chevauchant une surface de réception de lumière d'une partie de pixel de la première puce, et qui est électriquement connectée à la première puce.
PCT/JP2018/028934 2018-08-01 2018-08-01 Élément d'imagerie et endoscope WO2020026387A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/JP2018/028934 WO2020026387A1 (fr) 2018-08-01 2018-08-01 Élément d'imagerie et endoscope

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2018/028934 WO2020026387A1 (fr) 2018-08-01 2018-08-01 Élément d'imagerie et endoscope

Publications (1)

Publication Number Publication Date
WO2020026387A1 true WO2020026387A1 (fr) 2020-02-06

Family

ID=69231484

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2018/028934 WO2020026387A1 (fr) 2018-08-01 2018-08-01 Élément d'imagerie et endoscope

Country Status (1)

Country Link
WO (1) WO2020026387A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20220328400A1 (en) * 2021-04-12 2022-10-13 Nanya Technology Corporation Semiconductor device with test pad and method for fabricating the same

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6900429B1 (en) * 2004-03-23 2005-05-31 Stack Devices Corp. Image capture device
JP2011082215A (ja) * 2009-10-02 2011-04-21 Olympus Corp 撮像素子、撮像ユニット
JP2015135938A (ja) * 2013-12-19 2015-07-27 ソニー株式会社 半導体装置、半導体装置の製造方法、及び電子機器
WO2016185901A1 (fr) * 2015-05-15 2016-11-24 ソニー株式会社 Dispositif d'imagerie à semi-conducteurs, son procédé de fabrication, et instrument électronique
WO2017057291A1 (fr) * 2015-10-01 2017-04-06 オリンパス株式会社 Élément d'imagerie, endoscope et système d'endoscope

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6900429B1 (en) * 2004-03-23 2005-05-31 Stack Devices Corp. Image capture device
JP2011082215A (ja) * 2009-10-02 2011-04-21 Olympus Corp 撮像素子、撮像ユニット
JP2015135938A (ja) * 2013-12-19 2015-07-27 ソニー株式会社 半導体装置、半導体装置の製造方法、及び電子機器
WO2016185901A1 (fr) * 2015-05-15 2016-11-24 ソニー株式会社 Dispositif d'imagerie à semi-conducteurs, son procédé de fabrication, et instrument électronique
WO2017057291A1 (fr) * 2015-10-01 2017-04-06 オリンパス株式会社 Élément d'imagerie, endoscope et système d'endoscope

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20220328400A1 (en) * 2021-04-12 2022-10-13 Nanya Technology Corporation Semiconductor device with test pad and method for fabricating the same
US20220328401A1 (en) * 2021-04-12 2022-10-13 Nanya Technology Corporation Method for fabricating semiconductor device with test pad
US11495534B2 (en) * 2021-04-12 2022-11-08 Nanya Technology Corporation Semiconductor device with test pad and method for fabricating the same
US11749598B2 (en) * 2021-04-12 2023-09-05 Nanya Technology Corporation Method for fabricating semiconductor device with test pad

Similar Documents

Publication Publication Date Title
US11991468B2 (en) Solid-state imaging apparatus, manufacturing method of the same, and electronic device
US11532651B2 (en) Image pickup device and electronic apparatus
JP5820979B2 (ja) 固体撮像デバイス
WO2017169755A1 (fr) Dispositif d'imagerie à semi-conducteurs
US11923395B2 (en) Semiconductor device, solid-state image pickup element, image pickup device, and electronic apparatus
US10542226B2 (en) Imaging element, endoscope, and endoscope system
JP6266185B2 (ja) 撮像素子、内視鏡、及び内視鏡システム
WO2020026387A1 (fr) Élément d'imagerie et endoscope
US10299664B2 (en) Solid-state imaging device and endoscope system

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18928220

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 18928220

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: JP