WO2020024207A1

WO2020024207A1 - Service request processing method, device and storage system

Info

Publication number: WO2020024207A1
Application number: PCT/CN2018/098277
Authority: WO
Inventors: 卢玥; 余思; 龚骏辉; 毛依平; 陈贞
Original assignee: 华为技术有限公司
Priority date: 2018-08-02
Filing date: 2018-08-02
Publication date: 2020-02-06
Also published as: CN110178119A; CN110178119B

Abstract

The present application provides a method for processing a service request in a storage system, wherein the storage system contains a plurality of processor cores, and is characterized by comprising: Receiving a request of the current stage of a service request, wherein the request of the current stage is a request of one stage of a plurality of stages of the service request; Determining a first processor core set for performing the request of the current stage, wherein the first processor core set is a processor core subset of a plurality of processor cores; Sending the request of the current stage to the processor core with least load in the first processor core set. The method can ensure load balance between the processor cores and reduce the time delay of processing the service request.

Description

Method, device and storage system for processing service request

Technical field

The present application relates to the field of information technology, and more particularly, to a method, an apparatus, and a processor for processing a service request.

Background technique

In storage systems, the central processing unit (CPU) of the array controller is a key factor affecting system performance. Generally, the more processor cores a CPU includes, the higher the performance of the storage system.

However, in a storage system where the array controller includes multiple processor cores, as the number of processor cores increases, the problem of load imbalance among processor cores occurs when scheduling processor cores to process business requests.

Current technology estimates the load of the processor core based on the number of pending service requests on the processor core, and finally sends the service request to the processor core with the smallest load. Although this method can improve the load imbalance between processor cores, the time complexity of processing business requests will linearly expand as the number of processor cores increases, resulting in uncontrollable delays in processing business requests.

Summary of the invention

In a first aspect, a method for processing a service request in a storage system is provided. The storage system includes multiple processor cores, including: receiving a request for a current stage of a service request, where the current stage request is the service request A request of one of the multiple stages of the request; determining a first set of processor cores to execute the request of the current stage, the first set of processor cores being one processor core of the plurality of processor cores Send the request of the current stage to the first processor core set with the lightest load processor core.

By dividing the pending business request into multiple stages of requests for execution, allocating a certain number of processor cores (for example, a set of processor cores) to each stage of the request, and sending each stage of the request to The lightest-loaded processor core in the set of processor cores requested for allocation at this stage, compared to sending the business request to the lightest-loaded processor core among multiple processor cores in the storage system, this application processes business requests. The method can ensure load balancing between processor cores, determine the set of processor cores for each stage of business request, and schedule the current stage of requests within the scope of the processor set. Compared to directly selecting the lightest load in the storage system, The processor core considers the correlation between the request of each stage and the delay that affects the processing of the request by the processor core, and reduces the delay of processing service requests.

Optionally, the determining a first set of processor cores to execute the request of the current phase includes: querying a core binding relationship, determining the first set of processor cores to execute the request of the current phase, and The core binding relationship is used to indicate an association relationship between the request in the current stage and the first processor core set.

With reference to the first aspect, in some implementations of the first aspect, the method further includes: re-determining the number of processor cores that executes the request of the current stage according to the first set of processor cores; Re-determining the number of processor cores that execute the request of the current phase, and allocating, in the plurality of processor cores, the request of the current phase to a second set of processor cores that meets the number; according to the The second processor core set generates a new core binding relationship, where the new core binding relationship is used to indicate an association relationship between the request at the current stage and the second processor core set.

Optionally, re-determining the number of processor cores that executes the request in the current phase according to the first set of processor cores includes: determining a utilization of the processor cores in the first set of processor cores And the average utilization rate of the plurality of processor cores; and re-determining the execution location according to the total utilization rate of the processor cores in the first processor core set and the average utilization rate of the plurality of processor cores. Describes the number of processor cores requested in the current phase.

By periodically monitoring the utilization of processor cores in the storage system, and according to changes in the utilization of processor cores allocated for requests at any stage, reallocating processor cores for requests at the corresponding stage can be based on The change of the utilization rate of the processor cores is periodically adjusted to the processor cores allocated to the requests in the corresponding phases, thereby improving the load imbalance between the processor cores.

Optionally, the re-determining the processor core executing the request of the current stage according to the sum of the utilization ratio of the processor cores in the first processor core set and the average utilization ratio of the plurality of processor cores. The number includes: re-determining the execution of the request of the current stage based on the following relationship according to the sum of the utilization of the processor cores in the first processor core set and the average utilization of the plurality of processor cores. Number of processor cores:

N = U _P / U _ave

Wherein N is the number of re-determined processor cores executing the current stage request, U _P is the total utilization of the processor cores in the first set of processor cores, and U _ave is the multiple processes. Processor core average utilization.

With reference to the first aspect, in some implementation manners of the first aspect, the allocating, in the plurality of processor cores, the request of the current stage for the current stage request to a second set of processor cores including: generating Multiple sets of allocation results. Each set of allocation results includes a set of processor cores that satisfy the corresponding number of requests for reassignment for each stage of the request. Multiple path lengths are determined for the multiple sets of allocation results, and each set of allocation results corresponds to a path Length, the path length L satisfies:

Among them, c _{i, i + 1} represents the communication volume generated by the interaction between the processor cores executing the requests in adjacent stages, and d _{i, i + 1} represents the average topological distance between the processor cores executing the requests in the adjacent stages. M is the number of requests in multiple stages of the service request; according to a set of allocation results corresponding to the shortest path length among the plurality of path lengths, the request in the current stage is allocated a second that satisfies the number Processor core collection.

According to the determined number of processor cores allocated for the requests of each stage, generate multiple sets of processor core allocation results, determine multiple path lengths for the multiple sets of allocation results, and consider the allocation of processor cores for the requests of each stage The topological distance between processor cores determines the allocation result corresponding to the shortest path length among multiple path lengths as the final processor core allocation result, thereby ensuring load balancing between processor cores and reducing the delay in processing business requests .

With reference to the first aspect, in some implementations of the first aspect, the first set of processor cores includes K processor cores, where K is an integer greater than or equal to 3, and the first processor core The processor with the lightest load in the core set sending the request of the current stage includes: determining a scheduler for the request of the current stage among the K processor cores according to the sliding window length w and the sliding step d. Region, the scheduling sub-region includes w processor cores, w is an integer greater than or equal to 2 and less than K, and d is an integer greater than or equal to 1 and less than K; the load is the largest among the w processor cores The light processor core sends the request at the current stage.

When determining the processor core that executes a request at any stage, by introducing a sliding window mechanism, the search range of the processor core with the lightest search load is narrowed, so that the processor core with the lightest load in the scheduling subregion executes the request of the corresponding stage To ensure load balancing between processor cores and further reduce the delay in processing business requests.

With reference to the first aspect, in some implementation manners of the first aspect, the d and the K are prime numbers each other.

After the sliding window mechanism is introduced, when there is a binding relationship between a request in multiple stages and the same processor core set, and when the load of each processor core in the processor core set is the same, at this time, in In order to process the requests in multiple stages in order, in order to ensure load balancing among processor cores, it is necessary to ensure that processor cores with the same load (that is, the same number of pending request queues) are selected for the same probability of request execution That is, it is necessary to ensure that each processor core has the same probability as the search starting point in the sliding window. When the number of processor cores K in the processor core set and the sliding step size d are prime numbers, it can be guaranteed that The probabilities of the processor cores as search starting points in the sliding window are the same.

In a second aspect, a configuration method for processing a service request is provided, including: configuring a first set of processor cores for a request in a first stage of a service request, the first set of processor cores being used to execute the first stage Request; configure a first rule, the first rule instructing to send the request of the first stage to the lightest-loaded processor core in the first processor core set.

By allocating a certain number of processor cores (for example, a set of processor cores) for each stage of a business request, and sending requests for each stage to a load in the set of processor cores allocated for the request for that stage The lightest processor core, as opposed to sending the business request to the lightest-loaded processor core among the multiple processor cores in the storage system, the configuration method for processing a business request of the present application enables the processor to be guaranteed when processing a business request. Load balancing between cores takes into account the correlation between the requests in each phase and the delay that affects the processor core's processing of requests in each phase, reducing the delay in processing business requests.

With reference to the second aspect, in some implementations of the second aspect, the method further includes: configuring a second set of processor cores for a request in a second phase of a service request, the second set of processor cores being used for execution The request of the second phase; configuring a second rule, the second rule instructing to send the request of the second phase to the lightest-loaded processor core in the second set of processor cores.

According to a third aspect, an apparatus for processing a service request is provided. The apparatus is configured in a storage system, and the apparatus is configured to execute the method in any one of the possible implementation manners of the first aspect or the second aspect. Specifically, the apparatus may include a module for executing a method in any possible implementation manner of the first aspect or the second aspect.

According to a fourth aspect, a storage system is provided. The storage system includes a plurality of processor cores and a memory; the memory is configured to store computer instructions; and one or more of the plurality of processor cores are configured to execute Computer instructions stored in the memory, when the computer instructions in the memory are executed, the one or more processor cores are configured to execute any one of the possible implementations of the first aspect or the second aspect above method.

According to a fifth aspect, a computer-readable storage medium is provided, where the computer-readable storage medium stores computer instructions, and when the computer instructions are run on a computer, the computer is caused to execute any one of the first aspect or the second aspect Methods in possible implementations.

According to a sixth aspect, a computer program product including computer instructions is provided, and when the computer instructions are run on a computer, the computer is caused to execute the method in any possible implementation manner of the first aspect or the second aspect.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of a storage array architecture according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of a controller of a storage array according to an embodiment of the present invention.

FIG. 3 is a schematic diagram of a distributed block storage system according to an embodiment of the present invention.

FIG. 4 is a schematic structural block diagram of a server of a distributed block storage system.

FIG. 5 is a schematic block diagram of a processor according to an embodiment of the present invention.

FIG. 6 is a schematic flowchart of a method for processing a service request in a storage system according to an embodiment of the present invention.

FIG. 7 is a schematic diagram of scheduling a processor core based on a sliding window mechanism according to an embodiment of the present invention.

FIG. 8 is a schematic diagram of a topology distance between logical cores sharing different levels of memory or cache under a NUMA architecture according to an embodiment of the present invention.

FIG. 9 is a schematic flowchart of a configuration method for processing a service request according to an embodiment of the present invention.

FIG. 10 is a schematic block diagram of an apparatus for processing a service request according to an embodiment of the present invention.

FIG. 11 is a schematic block diagram of a storage system according to an embodiment of the present invention.

detailed description

The technical solutions in the embodiments of the present invention will be described below with reference to the drawings.

First, a storage system applicable to the embodiment of the present invention is described.

As shown in FIG. 1, the storage system in the embodiment of the present invention may be a storage array (such as Huawei

Oceanstor

18000 series,

V3 series). The storage array includes a storage controller 101 and a plurality of hard disks. The hard disks include a solid state disk (SSD), a mechanical hard disk, or a hybrid hard disk. Mechanical hard disks such as HDD (hard disk drive). As shown in FIG. 2, the controller 101 includes a central processing unit (CPU) 201, a memory 202, and an interface 203. The memory 202 stores computer instructions, and the CPU 201 includes multiple processor cores (not shown in FIG. 2). The CPU 201 executes computer instructions in the memory 202 to perform management and data access operations on the storage system. In addition, in order to save the computing resources of the CPU 201, a field programmable gate array (FPGA) or other hardware can also be used to perform all operations of the CPU 201 in the embodiment of the present invention, or the FPGA or other hardware and the CPU 201 are respectively used for The operations of the CPU 201 according to the embodiment of the present invention are performed. For convenience of description, in the embodiment of the present invention, the CPU 201 and the memory 202 are referred to as a processor, or the FPGA and other hardware replacing the CPU 201 are referred to as a processor, or the combination of the FPGA and other hardware replacing the CPU 201 and the CPU 201 are collectively referred to as a processor. The processor is in communication with the interface 203. The interface 203 may be a network interface card (NIC), a host bus adaptor (HBA), or the like.

As shown in FIG. 1 and FIG. 2, the CPU 201 is configured to process a service request, such as receiving a service request sent by a host or a client, and use the method for processing a service request provided by an embodiment of the present invention to process the service request.

Further, the storage system in the embodiment of the present invention may also be a distributed file storage system (such as Huawei

of

9000 series), distributed block storage systems (such as Huawei

of

Series) and so on. Huawei

of

Series as an example. As shown in FIG. 3 by way of example, a distributed block storage system includes multiple servers, such as server 1, server 2, server 3, server 4, server 5, and server 6, and infiniband technology or Ethernet is used between the servers Waiting to communicate with each other. In practical applications, the number of servers in the distributed block storage system can be increased according to actual needs, which is not limited in the embodiment of the present invention.

The server of the distributed block storage system includes a structure as shown in FIG. 4. As shown in FIG. 4, each server in the distributed block storage system includes a central processing unit (CPU) 401, a memory 402, an interface 403, a hard disk 1, a hard disk 2, and a hard disk 3. The memory 402 stores computer instructions The CPU 401 includes multiple processor cores (not shown in FIG. 4), and the CPU 401 executes computer instructions in the memory 402 to perform corresponding operations. The interface 403 may be a hardware interface, such as a network interface card (NIC) or a host bus adapter (HBA), or a program interface module. The hard disk includes a solid state disk (SSD), a mechanical hard disk, or a hybrid hard disk. Mechanical hard disks such as HDD (hard disk drive). In addition, in order to save the computing resources of the CPU401, a field programmable gate array (FPGA) or other hardware can also perform the corresponding operations in place of the CPU401, or FPGA or other hardware can perform the corresponding operations in conjunction with the CPU401. . For convenience of description, in the embodiment of the present invention, the CPU 401 and the memory 402 are referred to as a processor, or the FPGA and other hardware replacing the CPU 401 are referred to as a processor, or the combination of the FPGA and other hardware replacing the CPU 401 and the CPU 401 are collectively referred to as a processor. The interface 403 may be a network interface card (NIC), a host bus adapter (HBA), or the like.

As shown in the distributed block storage system shown in FIG. 3 and FIG. 4, the CPU 401 is configured to process a service request, such as receiving a service request sent by a host or a client, and use the method for processing a service request provided by an embodiment of the present invention to process the service request.

The general method of processing business requests is briefly introduced below:

When processing a business request, the load of the processor core is estimated based on the number of business requests to be processed on each processor core in a storage system containing multiple processor cores, and the business request is finally sent to the load in the storage system The lightest (for example, the least number of pending business requests) processor core.

Although this method can improve the load imbalance between processor cores, the time complexity of processing business requests will linearly expand as the number of processor cores increases, resulting in uncontrollable delays in processing business requests. .

In view of the above problems, an embodiment of the present invention proposes a method for processing a service request. The pending service request can be divided into multiple stages of request execution, and a certain number of processor cores (for example, processors) are allocated for each stage of the request. Core set), and send each stage request to the lightest-loaded processor core in the set of processor cores allocated for the request in this stage, as opposed to sending business requests to all processor cores in the storage system Lightest processor core. In the embodiment of the present invention, factors that affect the delay, such as the access delay, access distance, connection relationship between processors, or bus type, for each level of memory or cache accessed by the CPU (such as a processor core) are for each stage. Request to allocate a collection of processor cores. The method for processing service requests in the embodiments of the present invention can ensure load balancing among processor cores, and schedule requests at the current stage within the scope of the processor core set. Compared with directly selecting the lightest load processor core in the storage system, consider The correlation between the request of each stage and the delay of the processor core processing the request of each stage is reduced, and the delay of processing the service request is reduced. Exemplarily, the access request can be divided into two phases: a resource waiting phase and a resource using phase. Among them, requests in the resource waiting phase generally require special resources, such as disks, memory, and files. When resources are occupied by the previous request and not released, requests in the resource waiting phase are blocked until the resource can be used; A request using the resource phase is a request that actually performs a data access phase. For another example, taking a small computer system interface (SCSI) subsystem as an example, the SCSI subsystem is a layered architecture, which is divided into three layers. The top layer, which is called the upper layer, represents the highest interface of the operating system kernel to access the SCSI protocol device and the driver of the main device type. Next is the middle layer, also known as the common layer or unified layer, in this layer contains some of the higher and lower layers of the SCSI stack public services. Finally, the lower layer represents the actual driver for the physical interface of the device that is suitable for the SCSI protocol. SCSI-based access requests are also divided into three stages of requests.

Before introducing the method for processing a service request in the storage system provided by the embodiment of the present invention, the processor (for example, the CPU 201 in FIG. 2 and the CPU 401 in FIG. 4) provided by the embodiment of the present invention is first introduced.

As shown in FIG. 5, the processor in the embodiment of the present invention includes multiple processor cores (for example, processor core 0 to processor core S, S ≧ 2), and one of the multiple processor cores The load balancing module 501 and the binding core calculation module 502 are included. The other processor cores include a scheduling module 503. Among them, the load balancing module 501 is used to calculate the number of processor cores to be bound for each stage of a service request; the core binding relationship calculation module 502 is used to allocate a request that satisfies a corresponding number of requests for each stage of a service request. A processor core, which in turn generates a binding relationship, which indicates a correspondence between a request for a phase of a service request and a set of processor cores that process the request for the phase; a scheduling module 503 is configured to save the binding relationship and receive When a business request is made in a certain stage, query the binding core relationship, determine the set of processing cores used to execute the request in this stage, and send the request in this stage to the lightest-loaded processor core in the set of processor cores. The request of this stage is executed by the processor core.

In addition, among the processor cores on which the scheduling module 503 is deployed, at least one processor core is provided with a listening module 504. The listening module 504 is configured to monitor a service request from a host or a client. When a service request is sent, the service request is sent to the scheduling module 503 in the processor core.

It should be noted that, the processor in the embodiment of the present invention is described above only by taking the load balancing module 501 and the core relationship calculation module 502 as an example to deploy in the processor core S, but the embodiment of the present invention is not limited to this. The load balancing module 501 and the binding relationship calculation module 502 may be deployed in any one of the processor cores 0 to S, and the load balancing module 501 and the binding relationship calculation module 502 may be deployed in the same process. Processor cores can also be deployed in different processor cores.

The method 600 for processing a service request in a storage system according to an embodiment of the present invention is described in detail below. FIG. 6 shows a schematic flowchart of a method for processing a service request in a storage system, including steps 601 to 603.

601. Receive a request of a current stage of a service request, where the current stage request is one of a plurality of stages of the service request. It should be noted that, in the embodiment of the present invention, the processing of the service request is divided into multiple stages, and a set of processor cores is allocated for each stage, and the lightest-loaded processor core in the corresponding set of processor cores is allocated. Processes requests for the appropriate stages of a business request. A request in the current pending stage of a business request is called a request in the current stage.

Specifically, for example, when the listening module 504 in the processor core (for example, the listening module 504 in processor core 1) listens to the service request from the host or the client, the service request in the current stage is a multiple of the service request. The request of the first stage among the requests of the stage.

The monitoring module 504 in the processor core 1 sends the request of the current stage to the scheduling module 503 in the processor core 1.

602. Determine a first set of processor cores to execute the request in the current phase, where the first set of processor cores is a subset of the plurality of processor cores.

Specifically, the scheduling module 503 in the processor core 1 determines a set of processor cores (for example, a first set of processor cores) that executes the request of the current phase for the received request of the current phase.

For example, the scheduling module 503 may determine a first set of processor cores that executes the request of the current phase according to the specific type of the request of the current phase, and the first set of processor cores is a processor core of multiple processor cores in the storage system. set.

For another example, determining the first set of processor cores that executes the request of the current phase includes: querying the core binding relationship, determining the first set of processor cores used to execute the request of the current phase, and the binding core relationship is used to indicate An association relationship between the request in the current stage and the first processor core set.

Specifically, the scheduling module 503 in the processor core 1 may query a binding core relationship, where the binding core relationship indicates a set of processor cores allocated for each stage of the service request request, and each processor core set includes A plurality of processor cores, and the scheduling module 503 in the processor core 1 determines a first set of processor cores that executes the request in the current stage according to the core-binding relationship.

For example, the scheduling module 503 in the processor core 1 queries the binding core relationship to determine the processor core set including the processor core 1, the processor core 2, the processor core 4, the processor core 7 and the processor core 9 and the current core. There is an association relationship between the requests of the phases, and then the processor core set is determined as the first processor core set that executes the request of the current phase.

603. Send the request of the current stage to the processor core with the lightest load in the first processor core set.

Specifically, after determining the first set of processor cores for executing the request of the current stage, the scheduling module 503 in processor core 1 sends the service request to the lightest-loaded processing in the first set of processor cores Processor core, which executes the request at the current stage.

For example, the scheduling module 503 in processor core 1 determines the lightest-loaded processing among processor core 1, processor core 2, processor core 4, processor core 7, and processor core 9 in the first set of processor cores. The processor core is the processor core 7, and the scheduling module 503 in the processor core 1 sends a service request to the processor core 7, and the processor core 7 executes the request at the current stage.

After the processor core 7 finishes executing the request of the current phase, the service request enters the next execution phase. The scheduling module 503 in the processor core 7 determines the The processor core set for the next stage request is sent to the processor core with the lightest load in the processor core set, and the processor core executes the request for the next stage.

Repeat the above operations in turn until the processing of the service request is finally completed.

By dividing the pending business request into multiple phases for execution, a certain number of processor cores (for example, a set of processor cores) are allocated to the requests for each phase, and the requests for each phase are sent to the The lightest-loaded processor core in the set of processor cores requesting allocation, compared to sending a service request to the lightest-loaded processor core among multiple processor cores in a storage system, the embodiment of the present invention The method can ensure load balancing among processor cores, determine the set of processor cores for each stage of business request, and schedule the current stage of requests within the scope of the processor set. Compared to directly selecting the lightest load processing in the storage system, The processor core considers the correlation between the requests in each phase and the delay that affects the processing of the requests by the processor core, reducing the delay in processing business requests.

Optionally, the first processor core set includes K processor cores, where K is an integer greater than or equal to 3, and the lightest-loaded processor core in the first processor core set is sent the current stage The request includes: according to the sliding window length w and the sliding step d, determining a scheduling sub-region for the current stage request in the K processor cores, the scheduling sub-region includes w processor cores, and w is greater than or An integer equal to 2 and less than K, and d is an integer greater than or equal to 1 and less than K; sending the request of the current stage to the lightest-loaded processor core among the w processor cores.

Specifically, after the scheduling module 503 determines the first set of processor cores for executing the request of the current phase, it may send the request of the current phase to the lightest-loaded processor core in the first set of processor cores, The processor core executes the request of the current stage; or, the processor core executing the request of the current stage may also be determined based on the sliding window mechanism.

After determining the first set of processor cores used to execute the request of the current phase, the scheduling module 503 may use the sliding window length w and the sliding step d to determine the The phase request determines a scheduling sub-area, determines the lightest-loading processor core from the processor cores included in the scheduling sub-area, and sends the service request to the lightest-loading processor core in the scheduling sub-area.

For example, the processor core in the first set of processor cores determined by the scheduling module 503 to execute the request of the current phase according to the binding core relationship is processor core 1, processor core 3, processor core 4, processor core 5 , Processor core 8, processor core 9, and processor core 10 (i.e., K = 7). For example, w = 3, d = 2, the scheduling sub-region determined by the scheduling module 503 for the request of the current stage is shown in FIG. 7. It can be seen from FIG. 7 that the processor core included in the scheduling sub-region is the processor. Core 1, processor core 3, and processor core 4, the scheduling module 503 sends the request of the current stage to the processor core 1, processor core 3, and processor core 4 with the lightest load processor core, and the load The lightest processor core executes the request at this stage.

When the processor set including processor core 1, processor core 3, processor core 4, processor core 5, processor core 8, processor core 9, and processor core 10 is also used to process the request at the current stage When a request for a certain stage of other business requests follows, the scheduling sub-area of the request for a certain stage of the other service request is to slide the sliding window backwards by two processor cores. The processor core 4 and the processor core 5. In the sub-area formed by the processor core 8, the scheduling module 503 sends a request for a certain stage of the other service request to the processor core 4, the processor core 5, and the processor core 8 with the lightest load processor core. The processor core executes a request of a certain stage of the other service request.

When determining the processor core that executes a request at any stage, by introducing a sliding window mechanism, the search range of the processor core with the lightest search load is narrowed, so that the processor core with the lightest load in the scheduling subregion executes the request of the corresponding stage The method for processing service requests in the embodiments of the present invention can ensure load balancing among processor cores, determine a set of processor cores for each stage of service request requests, and schedule requests in the current stage within the scope of the processor set. The processor core with the lightest load in the storage system is directly selected, and the correlation between the request of each stage and the delay that affects the processing of the request by the processor core is considered, which further reduces the delay of processing business requests.

It should be noted that when the storage system starts to run, the binding relationship may be pre-configured, and then the binding relationship calculation module 502 in the processor core updates the binding relationship, that is, generates a new Nuclear ties.

The method for generating a new core binding relationship provided in the embodiment of the present invention is described in detail below.

By way of example and not limitation, the method further includes: re-determining the number of processor cores that execute the request of the current stage according to the first set of processor cores; and according to the re-determined processor core that executes the request of the current stage The number of second processor core sets that satisfy the number of requests for the current stage among the multiple processor cores; according to the second processor core set, a new core binding relationship is generated, and the new core binding The relationship is used to indicate an association relationship between the request in the current stage and the second processor core set.

Specifically, with the running of the storage system, the load balancing module 501 in the processor core S periodically determines the processing in the set of processor cores used to execute the requests of each phase for the requests of multiple phases of the service request. The number of processor cores, and the determined number of processor cores in the set of processor cores used to execute the request of each phase is provided to the binding core relationship calculation module 502 according to the load balancing module 501 Re-determine the number of processor cores in the set of processor cores used to execute the request for each phase, reallocate the request for each phase to meet the corresponding number of processor cores, and reallocate according to the request for each phase Satisfy the corresponding number of processor cores and periodically generate new core binding relationships.

The following uses the load balancing module 501 to re-determine the number of processor cores used to execute the request of the current stage as an example, and describes a method to re-determine the number of processor cores used to execute the request of each stage.

By way of example and not limitation, re-determining the number of processor cores executing the request of the current stage according to the first set of processor cores includes: determining a total utilization rate of the processor cores in the first set of processor cores With the average utilization of the plurality of processor cores; and re-determining the execution of the request at the current stage according to the sum of the utilization of the processor cores in the first processor core set and the average utilization of the plurality of processor cores The number of processor cores.

Specifically, the load balancing module 501 monitors the utilization rate of each processor core in the storage system in real time, wherein the utilization rate of the processor core is a ratio of the running time of the processor core to the sum of the running time and the idle time, and according to the processing, Changes in the utilization of processor cores, and re-determine the number of processor cores in the set of processor cores used to execute the request in the current phase.

For example, in the current monitoring cycle, the first set of processor cores bound to the request at the current stage is represented as P, and the utilization rate of the first processor core set is represented by U _P , then the utilization rate of the first processor core set is U _P is equal to the total utilization of the processor cores in the first processor core set in the current cycle, which is expressed as:

U _P = ΣU _j , j∈P (1)

Among them, U _j represents the utilization rate of any processor core in the first processor core set in the current cycle.

A plurality of processor cores in a storage system in the current cycle average utilization is expressed as U _ave, the scheduling module 503 in accordance with the U _P U _ave execution request for re-determining the current phase of the processing core of the set of processors The number of processor cores.

By way of example and not limitation, the number of processor cores executing the request of the current stage is re-determined according to the sum of the utilization ratios of the processor cores in the first processor core set and the average utilization ratio of the plurality of processor cores. Including: re-determining the number of processor cores executing the request of the current phase based on the following relationship according to the sum of the utilization ratio of the processor cores in the first processor core set and the average utilization ratio of the plurality of processor cores :

N = U _P / U _ave (2)

Among them, N is the number of processor cores that are re-determined to execute the request at the current stage, U _{P is} the total utilization of the processor cores in the first set of processor cores, and U _{ave is} the Average utilization.

After the load balancing module 501 re-determines the number N of processor cores used to execute the request of the current stage in the current cycle, it will determine the processor cores in the set of processor cores used to execute the request of the current stage. The number is provided to the core relationship calculation module 502, and the core relationship calculation module 502 reallocates a set of processor cores (for example, a second processor core set) that meets the foregoing number N at the beginning of the next cycle for the request of the current stage. ).

For example, the number of processor cores used to execute the request of the current phase in the current cycle is 8, and after the load balancing module 501 re-determines the number of processor cores used to execute the request of the current phase in the current cycle, for example, The number of processor cores re-determined by the load balancing module 501 in the current cycle to execute the request of the current phase is 6, and the load balancing module 501 provides the number of processor cores 6 re-determined for the request of the current phase to the core binding relationship. Calculation module 502, the binding core calculation module 502 may delete two processor cores from the eight processor cores stored in the binding relationship to execute the request of the current phase at the beginning of the next cycle, that is, generate a new processor core Nuclear ties.

As another example, the load balancing module 501 provides the number of processor cores 6 that is re-determined for the current request to the binding core calculation module 502. At this time, the binding core calculation module 502 does not use the Two processor cores are deleted from the eight processor cores executing the current phase of the request, but six processor cores are reassigned in the storage system for the current phase of the request, and the core relationship will be tied at the beginning of the next cycle The 8 processor cores that were originally allocated for the current stage request are replaced with the 6 processor cores that were reassigned to generate a new core-binding relationship.

In the following, a method for assigning the core relationship calculation module 502 to the current stage request in the storage system to satisfy the number of processor cores is taken as an example. For the core relationship calculation module 502 in the storage system, the request for each phase is provided. The method of allocating the corresponding number of processor cores will be described in detail.

In a storage system, multiple processor cores usually share different levels of memory or cache. The different levels of memory or cache can include L ₁ cache, L ₂ cache, L ₃ cache, and local memory. When the processor core When sharing different levels of memory or cache, the topological distance between processor cores is also different.

In a non-uniform memory access architecture (NUMA), each processor core can access local memory in a remote node (hereinafter referred to as "remote memory"). When using hyper-threaded communication, each Each processor core can be abstracted into multiple logical cores. For example, each processor core is abstracted into two logical cores, which are respectively logical core 0 and logical core 1, as shown in FIG. 8.

Figure 8 shows a schematic diagram of the topology distance between logical cores sharing different levels of memory or cache under the NUMA architecture. It can be seen that under the NUMA architecture, there are nodes 0 and 1, and the logical cores in node 0 can be connected to nodes. The logical core in 1 shares the local memory in node 1. The local memory in node 1 is the remote memory for node 0.

As can be seen from FIG. 8, the topological distance between two logical cores sharing L ₁ cache in node 0 is D ₁ , the topological distance between two logical cores sharing L ₂ cache is D ₂ , and L _{3 is} shared The topological distance between the two logical cores of the cache is D ₃ , and the topological distance between the two logical cores sharing local memory is D _4. The logical core in node 0 and the logical core in node 1 share the In local memory, the topological distance between the two logical cores is D ₅ .

According to the CPU manuals of each version released by Intel, you can obtain the access latency data of the CPU access to the memory or cache of various levels. Taking the Xeon E5-2658v2 CPU as an example, the access delay is shown in Table 1.

Table 1

共享的内存或缓存Shared memory or cache	访问时延Access delay
L ₁ cache L ₁ cache	1.3ns1.3ns
L ₂ cache L ₂ cache	3.7ns3.7ns
L ₃ cache L ₃ cache	12.8ns12.8ns
本地内存Local memory	56.5ns56.5ns

By referring to the proportional relationship between the latency of the CPU accessing different levels of memory or cache, the topological distance between two logical cores sharing different levels of memory or cache can be quantified. Assuming the topological distance D ₁ = 1 between the two logical cores sharing the L ₁ cache, one of the two logical cores sharing different levels of memory or cache can be obtained according to the access delay of the CPU accessing the memory of each level or the cache. The topological distance between them is shown in Table 2.

In the NUMA architecture, the access latency ratio of accessing local memory and remote memory is approximately 8:12, so the topological distance between logical cores that share remote memory between nodes can be calculated as 64.

Table 2

共享的内存或缓存Shared memory or cache	两个逻辑核之间的拓扑距离Topological distance between two logical cores
L ₁ cache L ₁ cache	11
L ₂ cache L ₂ cache	33
L ₃ cache L ₃ cache	1010
本地内存Local memory	4343
远端内存Remote memory	6464

The following assumes that the CPU in the storage system satisfies the topology shown in FIG. 8, and takes the allocation of the corresponding number of logical cores for the request of the current stage as an example. The binding core calculation module 502 of the embodiment of the present invention is in each stage of the storage system A method for requesting allocation of a processor core satisfying a corresponding number will be described in detail. Among them, node 0 and node 1 in FIG. 8 are in a NUMA architecture and communicate with each other through hyper-threading.

By way of example and not limitation, allocating a second processor core set that meets the number of requests for the current stage in multiple processors includes generating multiple sets of allocation results, and each set of allocation results includes requests for each stage The allocated set of processor cores meets the corresponding number; multiple path lengths are determined for the multiple sets of allocation results, and each set of allocation results corresponds to a path length, and the path length L satisfies:

Among them, c _{i, i + 1} represents the communication volume generated by the interaction between the processor cores executing requests in adjacent phases, and d _{i, i + 1} represents the average topological distance between the processor cores executing requests in the adjacent phases, M is the number of requests in multiple stages of the service request; where the communication volume can represent the number of interactions between processor cores.

According to a set of allocation results corresponding to the shortest path length among the multiple path lengths, the request of the current stage is allocated to satisfy the number of processor cores.

Specifically, in the CPU topology shown in FIG. 8, when using hyper-threaded communication, each processor core is abstracted into logical core 0 and logical core 1, and 16 processor cores are abstracted into 32 logical cores.

Assume that the business request needs to be processed in three phases. The three phase requests are denoted as M ₀ , M _1, and M _{2 respectively} . For example, the processor core used to execute the request of the current phase is determined by the foregoing. The method of determining the number of logic cores used to execute M ₀ , M ₁ and M ₂ in the current cycle. Among them, it is determined that the number of logic cores used to execute M ₀ is 8, the number of logic cores used to execute M ₁ is determined, and the number of logic cores used to execute M ₂ is 16.

The binding relationship calculation module 502 generates multiple sets of allocation results according to the number of logical cores determined for M ₀ , M _1, and M _2. Each group of allocation results includes logical cores that satisfy a corresponding number of allocations for each stage of the request.

For example, the allocation result 1 is: logical cores 0 to 7 in node 0 are assigned to M ₀ , logical cores 8 to 15 of node 0 are assigned to M ₁ , and logical cores 0 to 15 of node 1 are assigned to M ₂ ;

The allocation result 2 is: logic cores 0 to 3 in node 0 and logic cores 0 to 3 in node 1 are allocated to M ₀ , and logic cores 4 to 7 in node 0 and logic cores 4 to 7 in node 1 It is assigned to M ₁ , and logical cores 8 to 15 in node 0 and logical cores 8 to 15 in node 1 are assigned to M ₂ .

For the allocation result 1, use Equation (3) to calculate the path length, where the average topological distance between the logical cores that execute M ₀ and M ₁ is recorded as d _0,1 , and the logical cores when M ₁ and M ₂ are executed The average topological distance between them is recorded as d _1,2 , then d _0,1 = D ₄ , d _1,2 = D ₅ , and the communication volume generated by the interaction between the logical cores when performing M ₀ and M ₁ is recorded as c _{0 , 1} , Let C _1,2 be the communication volume generated by the interaction between the logical cores when M ₁ and M ₂ are executed, then the path length L ₁ corresponding to the allocation result ₁ satisfies:

L ₁ = c _0,1 × D ₄ + c _1,2 × D ₅ (4)

It is known from Table 2 that if D ₃ = 10, D ₄ = 43, and D ₅ = 64, then L ₁ = c _0,1 × 43 + c _1,2 × 64.

For the distribution result 2, use Equation (3) to calculate the path length, where the average topological distance between the logical cores when M ₀ and M ₁ are executed is denoted as d _0,1 , and the logical cores when M ₁ and M ₂ are executed The average topological distance between them is recorded as d _1,2 , then d _0,1 = D ₃ × 0.5 + D ₅ × 0.5, d _1,2 = D ₄ × 0.5 + D ₅ × 0.5, M ₀ and M ₁ will be executed The communication volume generated by the interaction between the logical cores at time is recorded as c _0,1 , and the communication volume generated by the interaction between the logical cores at the time of executing M ₁ and M ₂ is recorded as c _1,2 , then the path length L corresponding to the allocation result 2 ₂ meets:

L ₂ = c _0,1 × (D ₃ × 0.5 + D ₅ × 0.5) + c _0,2 × (D ₄ × 0.5 + D ₅ × 0.5) (5)

It is known from Table 2 that if D ₃ = 10, D ₄ = 43, and D ₅ = 64, then L ₂ = c _0,1 × 37 + c _1,2 × 53.5.

It can be seen that the path length corresponding to allocation result 2 is shorter than allocation result 1, so the binding core calculation module 502 will allocate logical cores 0 to 3 in node 0 and logical cores 0 to 3 in node 1. To M ₀ , assign logical cores 4 to 7 in node 0 and logical cores 4 to 7 in node 1 to M ₁ , and assign logical cores 8 to 15 in node 0 and logical cores 8 to 15 in node 1. Give M ₂ and replace the processor core originally allocated for the request of each stage of the business request in the binding relationship with the reallocated processor core at the beginning of the next cycle.

According to the allocation results of multiple sets of processor cores generated in the above embodiment, multiple path lengths are determined for the multiple sets of allocation results. By assigning processor cores to business modules, the topological distance between processor cores is considered, and multiple paths are The allocation result corresponding to the shortest path length in the length is determined as the final processor core allocation result, thereby ensuring load balancing among the processor cores, determining the processor core set for each stage of the business request request, and within the scope of the processor set. Compared with the direct selection of the lightest load processor core in the storage system, the scheduling of requests in the current phase takes into account the correlation between the requests in each phase and the delay that affects the processing of requests by the processor core in each phase, reducing the processing of business requests. Delay.

It should be noted that the above-mentioned enumeration results of only two types of logical cores are merely exemplary explanations for explaining the problem, and do not constitute any limitation on the embodiments of the present invention. In actual applications, multiple allocation results may be randomly generated and The allocation result corresponding to the shortest path length among the multiple sets of allocation results allocates logical cores to the requests of each stage. Exemplarily, in the embodiments of the present invention, a processor core set may be allocated for each stage of the request based on factors such as the connection relationship between processors or the type of bus that affects the delay. The embodiment of the present invention does not limit this.

The following describes in detail a configuration method 700 for processing a service request according to an embodiment of the present invention. FIG. 9 shows a schematic flowchart of a configuration method for processing a service request.

701. Configure a first set of processor cores for a request in a first phase of a service request, where the first set of processor cores is used to execute the first phase of the request.

Specifically, the processing of the service request is divided into multiple stages, and the multiple stages correspond to the multiple stage requests. For example, the multiple stage requests include the first stage requests, and a processor is configured for the first stage requests. A set of cores (eg, a first set of processor cores) through which the first stage of requests are processed.

702. Configure a first rule, where the first rule instructs to send the request of the first stage to the lightest-loaded processor core in the first processor core set.

Specifically, a first rule may be configured, and the first rule may indicate that the lightest-loaded processor core in the first set of processor cores configured for the request of the first stage executes the request of the first stage.

Optionally, the method further includes:

703. Configure a second set of processor cores for the requests in the second phase of the service request, where the second set of processor cores is used to execute the requests in the second phase.

Specifically, for example, the service request also includes a request in a second phase, and the request in the second phase may be a request in a phase subsequent to the request in the first phase, and a processor core set is configured for the request in the second phase. (For example, a second set of processor cores), through which the requests in the second stage are processed.

704. Configure a second rule, where the second rule instructs to send the request of the second stage to the lightest-loaded processor core in the second processor core set.

Specifically, a second rule may be configured, and the second rule may indicate that the lightest-loaded processor core in the second set of processor cores configured for the request of the second stage executes the request of the second stage.

Regarding how to configure the corresponding set of processor cores for the request in the first phase and the request in the second phase, please refer to the related description in the method 600. For the sake of brevity, it will not be repeated here.

By allocating a certain number of processor cores (for example, a set of processor cores) for each stage of a business request, and sending requests for each stage to a load in the set of processor cores allocated for the request for that stage The lightest processor core, compared to the lightest load processor core among multiple processor cores in the storage system, sends the service request to the service request configuration method according to the embodiment of the present invention, which can ensure that when processing a service request, Load balancing among processor cores, determining the set of processor cores for each stage of a business request, and scheduling the current stage of requests within the scope of the processor set. Compared to directly selecting the lightest-loading processor core in the storage system, The correlation between the request of each stage and the delay that affects the processing of the request by the processor core is considered to reduce the delay of processing business requests.

It should be noted that the above description is only based on the example that the service request includes the request of the first stage and the request of the second stage, and does not specifically limit the embodiment of the present invention. For example, the service request may also include requests of other stages.

Further, for the method for determining the processor core set in the foregoing configuration method embodiment, reference may be made to the description of the relevant part of the foregoing embodiment of the present invention, and details are not described herein again.

The method for processing service requests and the method for processing service requests in the storage system according to the embodiments of the present invention are described above with reference to FIGS. 6 to 9. The following describes service processing requests provided by the embodiments of the present invention with reference to FIGS. 10 to 11. Device and storage system.

FIG. 10 is a schematic block diagram of an apparatus 800 for processing a service request according to an embodiment of the present invention. The apparatus 800 is configured in a storage system and includes a transceiver module 801 and a processing module 802.

The transceiver module 801 is configured to receive a request in a current stage of a service request, where the request in the current stage is a request in one of a plurality of stages in the service request.

The processing module 802 is configured to determine a first set of processor cores that executes the request at the current stage, where the first set of processor cores is a subset of the plurality of processor cores.

The transceiver module 801 is further configured to send the request of the current stage to the processor core with the lightest load in the first processor core set.

Optionally, the processing module 802 is further configured to query a core binding relationship and determine the first processor core set used to execute the request of the current phase, and the core binding relationship is used to indicate that the request of the current phase and the first phase Association between processor core sets.

Optionally, the processing module 802 is further configured to re-determine the number of processor cores that execute the request of the current stage according to the first set of processor cores; and according to the re-determined processor that executes the request of the current stage The number of cores, among the plurality of processor cores, for the current stage request, a second set of processor cores satisfying the number is allocated; according to the second set of processor cores, a new binding core relationship is generated, and the new binding The core relationship is used to indicate an association relationship between the request in the current stage and the second processor core set.

Optionally, the processing module 802 is further configured to determine a total utilization rate of the processor cores in the first processor core set and an average utilization rate of the plurality of processor cores; according to the first processor core set, The sum of the utilization of the processor cores and the average utilization of the plurality of processor cores re-determines the number of processor cores executing the request in the current stage.

Optionally, the processing module 802 is further configured to re-determine the execution of the current based on the following relationship based on the sum of the utilization rates of the processor cores in the first processor core set and the average utilization rate of the plurality of processor cores. Number of requested processor cores for the phase:

N = U _P / U _ave

Optionally, the processing module 802 is further configured to generate multiple sets of allocation results, and each set of allocation results includes a set of processor cores that meets a corresponding number of requests for reallocation for each stage of the request; Path length, each group of allocation results corresponds to a path length, the path length L satisfies:

Among them, c _{i, i + 1} represents the communication volume generated by the interaction between the processor cores executing requests in adjacent phases, and d _{i, i + 1} represents the average topological distance between the processor cores executing requests in the adjacent phases, M is the number of requests in multiple stages of the service request; according to a set of allocation results corresponding to the shortest path length among the multiple path lengths, the request for the current stage is allocated a second set of processor cores that meets the number.

Optionally, the first processor core set includes K processor cores, where K is an integer greater than or equal to 3, and the processing module 802 is further configured to, according to the sliding window length w and the sliding step size d, in the K Among the processor cores, a scheduling sub-region is determined for the request of the current stage. The scheduling sub-region includes w processor cores, where w is an integer greater than or equal to 2 and less than K, and d is an integer greater than or equal to 1 and less than K. Integer

The transceiver module 801 is further configured to send the request of the current stage to the lightest-loaded processor core among the w processor cores.

Optionally, d and K are prime numbers each other.

The apparatus 800 for processing a service request according to the embodiment of the present invention may correspond to executing the method 600 or the method 700 described in the embodiment of the present invention, and the above and other operations and / or functions of each module in the apparatus 800 are respectively implemented in order to implement FIG. 6. Corresponding processes of the method 600 in FIG. 9 or the method 700 in FIG. 9, correspondingly, each module shown in FIG. 5 may correspond to one or more modules shown in FIG. 8. For brevity, I will not repeat them here.

Further, the specific implementation of the apparatus 800 for processing a service request in the embodiment of the present invention may be a processor, or a software module, or a combination of a processor and a software module, which is not limited in the embodiment of the present invention.

11 is a schematic block diagram of a storage system 900 according to an embodiment of the present invention. The storage system includes a processor 901 and a memory 902, and the processor 901 includes multiple processor cores.

A memory 902, configured to store computer instructions;

One or more processor cores in the plurality of processor cores are used to execute computer instructions stored in the memory 902. When the computer instructions in the memory 902 are executed, the one or more processor cores are used to execute The following operations: receiving a request of a current stage of a service request, the current stage request being one of a plurality of stage requests of the service request; determining a first set of storage system cores to execute the current stage request, the The first storage system core set is a subset of the storage system cores of the plurality of storage system cores; and the request of the current stage is sent to the storage system core with the lightest load in the first storage system core set.

Optionally, the one or more processor cores are further configured to query a core binding relationship, determine the first storage system core set used to execute the request of the current phase, and the core binding relationship is used to indicate the current phase. An association relationship between the request and the first storage system core set.

Optionally, the one or more processor cores are further configured to re-determine the number of storage system cores that execute the request of the current phase according to the first set of storage system cores; The number of requested storage system cores, and among the multiple storage system cores, a second storage system core set that satisfies the number is allocated to the current stage of the request; and a new binding core relationship is generated according to the second storage system core set, The new core binding relationship is used to indicate an association relationship between the request in the current stage and the second storage system core set.

Optionally, the one or more processor cores are further configured to determine a sum of utilization rates of the storage system cores in the first storage system core set and an average utilization rate of the plurality of storage system cores; according to the first processing The sum of the utilization rates of the processor cores in the processor core set and the average utilization rate of the plurality of processor cores re-determines the number of processor cores executing the request in the current stage.

Optionally, the one or more processor cores are further configured to re-based on the sum of the utilization rates of the processor cores in the first processor core set and the average utilization rate of the plurality of processor cores based on the following relationship: Determine the number of processor cores executing requests for this current phase:

N = U _P / U _ave

Optionally, the one or more processor cores are further configured to generate multiple groups of allocation results, and each group of allocation results includes a set of processor cores that meets a corresponding number of requests reallocated for each stage of the request; The allocation result determines multiple path lengths. Each group of allocation results corresponds to a path length. The path length L satisfies:

Optionally, the first set of processor cores includes K processor cores, where K is an integer greater than or equal to 3, and the one or more processor cores are further used according to the sliding window length w and the sliding step size d. , In the K processor cores, determine a scheduling sub-region for the request of the current stage, the scheduling sub-region includes w processor cores, w is an integer greater than or equal to 2 and less than K, and d is greater than or equal to 1 And an integer smaller than K; sending the request of the current stage to the lightest-loaded processor core among the w processor cores.

Optionally, the d and the K are prime numbers each other.

Each module shown in FIG. 5 in the embodiment of the present invention may be hardware logic in the processor core, or may be computer instructions executed by the processor core, or a combination of hardware logic and computer instructions, which is not limited in the embodiment of the present invention. .

Each module of the apparatus 800 for processing a service request according to an embodiment of the present invention may be implemented by a processor, may be implemented by a processor and a memory together, or may be implemented by a software module. Accordingly, each module shown in FIG. 5 may correspond to one or more modules shown in FIG. 8, and the module shown in FIG. 8 includes corresponding functions of the module shown in FIG. 5.

An embodiment of the present invention provides a computer-readable storage medium. The computer-readable storage medium stores computer instructions. When the computer instructions are run on a computer, the computer executes a method for processing a service request in an embodiment of the present invention. Or configuration methods for processing business requests.

Embodiments of the present invention provide a computer program product containing computer instructions, and when the computer instructions are run on a computer, the computer is caused to execute the method for processing a service request or the method for configuring a service request in an embodiment of the present invention.

It should be understood that the processor mentioned in the embodiments of the present invention may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), and application-specific integrated circuits (DSPs). application specific integrated circuit (ASIC), ready-made programmable gate array (field programmable gate array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or the processor may be any conventional processor or the like.

It should also be understood that the memory mentioned in the embodiments of the present invention may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memory. Among them, the non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (erasable PROM, EPROM), electrical memory Erase programmable read-only memory (EPROM, EEPROM) or flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (synchronous DRAM, SDRAM), double data rate synchronous dynamic random access memory (double SDRAM, DDR SDRAM), enhanced synchronous dynamic random access memory (enhanced SDRAM, ESDRAM), synchronous connection dynamic random access memory (synchlink DRAM, SLDRAM ) And direct memory bus random access memory (direct RAMbus RAM, DR RAM).

It should be noted that when the processor is a general-purpose processor, a DSP, an ASIC, an FPGA, or other programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component, the memory (memory module) is integrated in the processor.

It should be noted that the memory described herein is intended to include, but is not limited to, these and any other suitable types of memory.

Those of ordinary skill in the art may realize that the units and algorithm steps of each example described in connection with the embodiments disclosed herein can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed by hardware or software depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the embodiments of the present invention.

Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices, and units described above can refer to the corresponding processes in the foregoing method embodiments, and are not repeated here.

In the several embodiments provided by the embodiments of the present invention, it should be understood that the disclosed systems, devices, and methods may be implemented in other manners. For example, the device embodiments described above are only schematic. For example, the division of the unit is only a logical function division. In actual implementation, there may be another division manner. For example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored or not implemented. In addition, the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, which may be electrical, mechanical or other forms.

The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, may be located in one place, or may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the objective of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist separately physically, or two or more units may be integrated into one unit.

If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiment of the present invention is essentially a part that contributes to the existing technology or a part of the technical solution may be embodied in the form of a software product, which is stored in a storage medium. Including a plurality of computer instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The foregoing storage media include: U disks, mobile hard disks, read-only memories (ROM), random access memories (RAM), magnetic disks or compact discs, and other media that can store computer instructions .

The above are only specific implementations of the embodiments of the present invention, but the scope of protection of the embodiments of the present invention is not limited to this. Any person familiar with the technical field can easily implement the technical scope disclosed by the embodiments of the present invention. Any change or replacement is considered to be covered by the protection scope of the embodiments of the present invention. Therefore, the protection scope of the embodiments of the present invention shall be subject to the protection scope of the claims.

Claims

A method for processing a service request in a storage system. The storage system includes multiple processor cores, and is characterized in that it includes:

Receiving a request of a current stage of a service request, where the current stage request is one of a plurality of stages of the service request;

Determining a first set of processor cores that executes the request in the current phase, the first set of processor cores being a subset of the plurality of processor cores;

And sending the request of the current stage to the processor core with the lightest load on the first processor core set.
The method according to claim 1, wherein the determining a first set of processor cores to execute the request of the current phase comprises:

Query a core binding relationship to determine the first processor core set used to execute the request of the current phase, and the core binding relationship is used to indicate a relationship between the request of the current phase and the first processor core set Relationship.
The method according to claim 2, further comprising:

Re-determine the number of processor cores that execute the request in the current phase according to the first set of processor cores;

Allocating a second set of processor cores that meets the number of requests in the current stage among the plurality of processor cores according to the newly determined number of processor cores that executes the requests in the current stage;

Generating a new core binding relationship according to the second processor core set, where the new core binding relationship is used to indicate an association relationship between the request at the current stage and the second processor core set.
The method according to claim 3, wherein the re-determining the number of processor cores executing the request of the current phase according to the first set of processor cores comprises:

Determining a total utilization rate of processor cores in the first processor core set and an average utilization rate of the plurality of processor cores;

And re-determining the number of processor cores executing the request in the current stage according to the sum of the utilization ratios of the processor cores in the first processor core set and the average utilization ratio of the plurality of processor cores.
The method according to claim 4, wherein the re-determining the execution unit is based on a sum of utilization rates of processor cores in the first set of processor cores and an average utilization rate of the plurality of processor cores. Describes the number of processor cores requested at the current stage, including:

Re-determining the number of processor cores executing the request in the current stage based on the sum of the utilization ratio of the processor cores in the first processor core set and the average utilization ratio of the plurality of processor cores based on the following relationship :

N = U P / U ave

Wherein N is the number of re-determined processor cores executing the current stage request, U P is the total utilization of the processor cores in the first set of processor cores, and U ave is the multiple processes. Processor core average utilization.
The method according to any one of claims 3 to 5, characterized in that, in the plurality of processor cores, the request of the current stage is allocated a second set of processor cores that satisfies the number, include:

Generate multiple sets of allocation results, each set of allocation results including a set of processor cores that are re-allocated for each stage of the request;

Multiple path lengths are determined for the multiple sets of allocation results, each set of allocation results corresponds to a path length, and the path length L satisfies:

Among them, c i, i + 1 represents the communication volume generated by the interaction between the processor cores executing the requests in adjacent stages, and d i, i + 1 represents the average topological distance between the processor cores executing the requests in the adjacent stages. M is the number of requests in multiple stages of the service request;

According to a set of allocation results corresponding to the shortest path length among the plurality of path lengths, the request of the current stage is allocated a second set of processor cores that satisfies the number.
The method according to any one of claims 1 to 6, wherein the first set of processor cores includes K processor cores, K is an integer greater than or equal to 3, and the The lightest-loaded processor core in a processor core set sending the request in the current stage includes:

According to the sliding window length w and sliding step d, a scheduling sub-region is determined for the current stage request in the K processor cores, the scheduling sub-region includes w processor cores, and w is greater than or equal to An integer of 2 and less than K, and d is an integer of 1 or more and less than K;

Sending the request of the current stage to the lightest-loaded processor core among the w processor cores.
The method according to claim 7, wherein the d and the K are prime numbers each other.
An apparatus for processing a service request, wherein the apparatus is configured in a storage system and includes:

A transceiver module, configured to receive a request of a current stage of a service request, where the request of the current stage is a request of one of the multiple stages of the service request;

A processing module, configured to determine a first set of processor cores that executes the request at the current stage, where the first set of processor cores is a subset of the plurality of processor cores;

The transceiver module is further configured to send the request of the current stage to the processor core with the lightest load in the first processor core set.
The apparatus according to claim 9, wherein the processing module is further configured to query a core binding relationship, and determine the first set of processor cores used to execute the request of the current phase, the core binding The relationship is used to indicate an association relationship between the request in the current stage and the first processor core set.
The apparatus according to claim 10, wherein the processing module is further configured to re-determine the number of processor cores that execute the request of the current stage according to the first set of processor cores; Re-determining the number of processor cores executing the request in the current phase, and allocating, in the plurality of processor cores, the request in the current phase to a second set of processor cores satisfying the number; The two processor core sets generate a new core binding relationship, where the new core binding relationship is used to indicate an association relationship between the request at the current stage and the second processor core set.
The apparatus according to claim 11, wherein the processing module is further configured to determine a sum of utilization rates of processor cores in the first set of processor cores and an average utilization of the plurality of processor cores Rate; and re-determining the number of processor cores executing the request in the current stage according to the sum of the utilization rates of the processor cores in the first set of processor cores and the average utilization rate of the plurality of processor cores.
The apparatus according to claim 12, wherein the processing module is further configured to: according to a sum of utilization rates of processor cores in the first set of processor cores and an average utilization of the plurality of processor cores Rate, based on the following relationship to re-determine the number of processor cores executing the request in the current stage:

N = U P / U ave

Wherein N is the number of re-determined processor cores executing the current stage request, U P is the total utilization of the processor cores in the first set of processor cores, and U ave is the multiple processes. Processor core average utilization.
The device according to any one of claims 11 to 13, wherein the processing module is further configured to:

Generate multiple sets of allocation results. Each set of allocation results includes a set of processor cores that satisfy the corresponding number of requests for reallocation of each stage of the request; determine multiple path lengths for the multiple set of allocation results, and each set of allocation results corresponds to one Path length, where the path length L satisfies:

Among them, c i, i + 1 represents the communication volume generated by the interaction between the processor cores executing the requests in adjacent stages, and d i, i + 1 represents the average topological distance between the processor cores executing the requests in the adjacent stages. M is the number of requests in multiple stages of the service request; according to a set of allocation results corresponding to the shortest path length among the plurality of path lengths, the request in the current stage is allocated a second that satisfies the number Processor core collection.
The device according to any one of claims 9 to 14, wherein the first set of processor cores includes K processor cores, where K is an integer greater than or equal to 3, and the processing module further comprises: It is used to determine a scheduling sub-region for the current stage request in the K processor cores according to the sliding window length w and the sliding step d. The scheduling sub-region includes w processor cores, where w is greater than Or an integer of 2 and less than K, and d is an integer of 1 and less than K;

The transceiver module is further configured to send the request of the current stage to the processor core with the lightest load among the w processor cores.
The device according to claim 15, wherein the d and the K are prime numbers to each other.
A storage system, characterized in that the storage system includes multiple processor cores and memories;

Memory for storing computer instructions;

One or more processor cores in the plurality of processor cores are used to execute computer instructions stored in the memory, and when the computer instructions in the memory are executed, the one or more processor cores are used in to:

Receiving a request of a current stage of a service request, where the current stage request is one of a plurality of stage requests of the service request; determining a first set of storage system cores to execute the current stage request, so The first storage system core set is a subset of the storage system cores of the plurality of storage system cores; and sending the request of the current stage to the storage system core with the lightest load in the first storage system core set.
The storage system according to claim 17, wherein the one or more processor cores are further configured to:

Query a core binding relationship to determine the first storage system core set used to execute the request of the current phase, and the core binding relationship is used to indicate a relationship between the current phase request and the first storage system core set Relationship.
The storage system according to claim 18, wherein the one or more processor cores are further configured to:

Re-determining the number of storage system cores executing the request of the current phase according to the first set of storage system cores; Among the storage system cores, a second storage system core set that satisfies the number of requests for the current stage is allocated; and a new binding core relationship is generated according to the second storage system core set, and the new binding core relationship is used for And indicating an association relationship between the request in the current stage and the second storage system core set.
The storage system according to claim 19, wherein the one or more processor cores are further configured to:

Determining a total utilization rate of the storage system cores in the first storage system core set and an average utilization rate of the plurality of storage system cores; and The average utilization of the plurality of processor cores re-determines the number of processor cores that executes the request in the current stage.
The storage system according to claim 20, wherein the one or more processor cores are further configured to:

Re-determining the number of processor cores executing the request in the current stage based on the sum of the utilization ratio of the processor cores in the first processor core set and the average utilization ratio of the plurality of processor cores :

N = U P / U ave

Wherein N is the number of re-determined processor cores executing the current stage request, U P is the total utilization of the processor cores in the first set of processor cores, and U ave is the multiple processes. Processor core average utilization.
The storage system according to any one of claims 19 to 21, wherein the one or more processor cores are further configured to:

Generate multiple sets of allocation results. Each set of allocation results includes a set of processor cores that meets the corresponding number for each stage of the request for reassignment; determine multiple path lengths for the multiple set of allocation results, one for each set of allocation results Path length, where the path length L satisfies:

Among them, c i, i + 1 represents the communication volume generated by the interaction between the processor cores executing the requests in adjacent stages, and d i, i + 1 represents the average topological distance between the processor cores executing the requests in the adjacent stages. M is the number of requests in multiple stages of the service request; according to a set of allocation results corresponding to the shortest path length among the plurality of path lengths, the request in the current stage is allocated a second that satisfies the number Processor core collection.
The storage system according to any one of claims 17 to 22, wherein the first processor core set includes K processor cores, K is an integer greater than or equal to 3, and the one or more Processor cores, also used for:

According to the sliding window length w and sliding step d, a scheduling sub-region is determined for the current stage request in the K processor cores, the scheduling sub-region includes w processor cores, and w is greater than or equal to An integer of 2 and less than K, and d is an integer of 1 or more and less than K; sending the request of the current stage to the lightest-loaded processor core among the w processor cores.
The storage system according to claim 23, wherein the d and the K are prime numbers to each other.