WO2020024115A1

WO2020024115A1 - Chip assembly and terminal device

Info

Publication number: WO2020024115A1
Application number: PCT/CN2018/097814
Authority: WO
Inventors: 常明; 葉冠宏
Original assignee: 华为技术有限公司
Priority date: 2018-07-31
Filing date: 2018-07-31
Publication date: 2020-02-06
Also published as: CN111886691B; CN111886691A

Abstract

A chip assembly and a terminal device, which are used to achieve the bonding of an upper substrate to a lower substrate, so that the relative position of the upper substrate and the lower substrate is stabilized, thereby improving the performance of the chip assembly. The chip assembly comprises: a first substrate and a second substrate arranged opposite to each other, the second substrate being provided with a feeding path; a first radiation patch disposed on a surface of the first substrate facing toward or away from the second substrate; a second radiation patch disposed on a surface of the second substrate facing toward the first substrate, the first radiation patch being coupled to the second radiation patch; a radio frequency processing chip disposed on a surface of the second substrate facing away from the first substrate and electrically connected to the second substrate for use in feeding the second radiation patch by means of the feeding path; one or more solder balls, each solder ball being placed between the first substrate and the second substrate for use in achieving the connection of the first substrate and the second substrate; and one or more pieces of first adhesive, wherein the first substrate is provided with one or more via holes, one end of each piece of first adhesive is disposed in one via hole, and the other end is connected to the surface of the second substrate facing toward the first substrate for use in fixing the relative position of the first substrate and the second substrate.

Description

Chip assembly and terminal equipment

Technical field

The present application relates to the field of electronic and communication technologies, and in particular, to a chip assembly and a terminal device.

Background technique

With the advent of the high-speed communication era, communication systems have increasingly higher requirements for bandwidth, delay, and transmission path loss. In order to comply with this development trend, an antenna (package) (AIP) application was born. Among them, the packaged antenna has the following characteristics: 1. In the packaged antenna, the feeding path is extremely short, which can maximize the equivalent isotropic radiated power (EIRP) of the antenna, which is conducive to achieving high bandwidth; 2. Compared with the traditional printed circuit board (PCB) processing technology, packaged antennas have a high degree of integration and high processing accuracy, so it is not easy for the electrical performance to deteriorate due to low processing accuracy. Good electrical performance.

A schematic structural diagram of a package antenna using a double-layer patch can be shown in FIG. 1. In Figure 1, the upper substrate is used to carry the auxiliary radiator of the antenna, and the lower substrate is connected to a radio frequency (RF) chip and carries the main radiator of the antenna. The RF chip is fed to the main radiator by a feeder circuit in the lower substrate. Electricity (for simplicity, only three feed paths are shown in Figure 1). The packaged antenna may further include a ball grid array (BGA) connected to the lower substrate, and the packaged antenna may be connected to the motherboard (ie, a PCB board) through the BGA. In addition, the upper substrate and the lower substrate are connected by a solder ball.

In the packaged antenna shown in FIG. 1, the distance and alignment between the upper and lower substrates determine the relative positions of the primary and secondary radiators. Since the primary and secondary radiators in this packaged antenna are coupled to feed the secondary radiators, Therefore, the relative position has a greater impact on the frequency band and performance covered by the antenna. Therefore, how to achieve accurate and stable adhesion between the upper substrate and the lower substrate is one of the key points for preparing the antenna shown in FIG. 1.

In the prior art, the solder balls in FIG. 1 are usually used to achieve the bonding between the upper substrate and the lower substrate. Because the solder ball has thermal instability, the manufacturing process of the package antenna and subsequent testing and application processes include multiple high-temperature reflow soldering operations (the temperature is raised and then lowered to achieve soldering). Therefore, the solder ball is used to realize the upper substrate. The adhesion to the lower substrate may cause the relative position of the upper substrate and the lower substrate to be unstable, thereby affecting the performance of the antenna.

In summary, there is an urgent need for a package antenna solution to achieve the bonding of the upper substrate and the lower substrate, so that the relative position of the upper substrate and the lower substrate is stable, and the performance of the package antenna is improved.

Summary of the invention

The embodiments of the present application provide a chip assembly and a terminal device, which are used to achieve the adhesion between the upper substrate and the lower substrate, so that the relative position of the upper substrate and the lower substrate is stable, thereby improving the performance of the chip assembly.

In a first aspect, an embodiment of the present application provides a chip assembly. The chip assembly includes: a first substrate and a second substrate opposite to each other, wherein the second substrate is provided with a feeding path; and a first radiation patch is provided. On the surface of the first substrate facing or facing away from the second substrate; the second radiation patch is disposed on the surface of the second substrate facing the first substrate; the first radiation patch is coupled to the second radiation patch; the radio frequency processing chip is provided The surface of the second substrate facing away from the first substrate is electrically connected to the second substrate and is used to feed the second radiation patch radially through the feeding circuit; one or more solder balls, each solder ball is placed on the first substrate And the second substrate for connecting the first substrate to the second substrate; one or more first adhesives, wherein the first substrate is provided with one or more vias, one end of each first adhesive It is arranged in one via hole, and the other end is connected with the surface of the second substrate facing the first substrate, and is used for fixing the relative position of the first substrate and the second substrate.

It should be noted that, in the embodiments of the present application, a plurality refers to two or more than two, for example, two, three, and four.

The solder ball includes one or more of tin core solder balls, copper core solder balls, and plastic core solder balls.

In addition, the chip assembly can be connected to a motherboard (ie, a PCB board) through a BGA. From the stacking order of two substrates (the first substrate and the second substrate) and two radiation patches (the first radiation patch and the second radiation patch) in practical applications, the first substrate can be regarded as an upper substrate The second substrate can be regarded as the lower substrate (that is, for the mother board, the first substrate, and the second substrate, the stacking order is the mother board, the second substrate, and the first substrate from bottom to top, that is, It is said that the first substrate is stacked on the second substrate), the first radiation patch can be regarded as the upper radiation patch, and the second radiation patch can be regarded as the lower radiation patch (that is, for the mother board, the first radiation patch For the third and second radiation patches, the stacking order from the bottom to the top is the mother board, the second radiation patch, and the first radiation patch, that is, the first radiation patch is stacked on the second Radiation patch).

The chip assembly provided in the first aspect is used to realize the connection between the first substrate and the second substrate through one or more solder balls, and the relative positions of the first substrate and the second substrate are fixed by the first adhesive. Since the first substrate and the second substrate are connected by solder balls in the chip assembly, the relative positions of the first radiation patch and the second radiation patch are also aligned when the two are connected. , There will be no performance defects such as reduced gain, poor return loss, deteriorated pattern, and large frequency deviation, and the frequency band covered by the chip assembly can meet the needs of users, and the performance of the chip assembly is improved.

Further, the first adhesive in the chip assembly can fix the relative positions of the first substrate and the second substrate. When the solder ball collapses or deforms due to thermal instability during multiple high-temperature reflow soldering processes, The first adhesive can still maintain the relative position of the first substrate and the second substrate in an aligned state, and the problem of the unstable relative position of the first substrate and the second substrate will not occur, so that the chip assembly can be improved. performance.

The RF processing chip may be flip-chip mounted on a surface of the second substrate that does not face the first substrate. Specifically, the RF processing chip may be connected to the second substrate through a solder bump or solder paste, or may be directly connected to the first substrate. The two substrates are physically connected.

In order to improve the performance of the chip assembly, both the upper radiation patch and the second radiation patch may be in the form of an antenna array. That is, the first radiation patch contains M first array elements, the second radiation patch contains M second array elements, and the M second array elements are respectively coupled with the M first array elements. The M electron feeding paths included in the path feed M second array elements, respectively, where M> 1. When both the first radiation patch and the second radiation patch are in the form of an antenna array, the chip assembly can cover a wide frequency range and obtain better antenna gain.

In a possible design, each second element and the first element coupled to it have the same shape and size, and are centered.

In a possible design, the chip assembly further includes one or more second adhesives, each of which is used to connect the edge of the first substrate and the edge of the second substrate, that is, the second adhesive It is distributed between the first substrate and the second substrate, and is disposed near the edge of the first substrate (or the second substrate). When the second adhesive is distributed near the edge of the first substrate (or the second substrate), the stress between the first substrate and the second substrate can be more effectively dispersed, and the first substrate and the second substrate can be more firmly fixed. The relative position of the substrate.

In a possible design, the chip assembly provided by the first aspect may further include one or more first green oil-resistance rubber dams, and each first green oil-resistance rubber dam includes a plurality of first green oil resistance dams. A first fixing block, a part of the plurality of first fixing blocks, the first fixing block being disposed on a surface of the first substrate facing the second substrate, and another part of the plurality of first fixing blocks being disposed on the second substrate facing The surface of the first substrate. That is, a first green oil-resistance rubber dam can be used to fix the position of a solder ball. The first green oil-resistance rubber dam is used to fix the solder ball, so that the position of the solder ball can be more stable, and the connection between the first substrate and the second substrate can be more stably achieved. In addition, the first green oil-resistance rubber dam can prevent the material in the solder ball (such as tin, copper, plastic, etc.) from overflowing and contaminating the radiation patch when the solder ball collapses and deforms, and avoid the spilled material from affecting the performance of the chip assembly. influences.

In a possible design, the chip assembly provided by the first aspect may further include one or more second green oil-resistance rubber dams, each of which includes a plurality of second green oil-resistance rubber dams. Second fixing blocks, a part of the plurality of second fixing blocks is disposed on a surface of the first substrate facing the second substrate, and another part of the plurality of second fixing blocks is disposed on the second substrate Towards the surface of the first substrate. That is, a second green oil-resistance rubber dam can be used to fix the position of a first adhesive. The use of the second green oil-resistance rubber dam to fix the first adhesive can make the first adhesive more stable, thereby making the relative positions of the first substrate and the second substrate more stable. In addition, the second green oil barrier dam can also prevent the adhesive in the first adhesive from overflowing from contaminating the radiation patches in the chip assembly, so as to avoid the spilled material from affecting the performance of the chip assembly.

In addition, in order to prevent the first adhesive from collapsing and deforming during the high temperature reflow soldering (raising the temperature and then dropping it down to achieve soldering) during the chip assembly preparation process and subsequent testing and application processes, the first Adhesives can use low-flow adhesives, and are glued on the chip assembly to form one or more first adhesives and then baked and cured, so that the first adhesive is more stable, and the first adhesive is more firmly fixed. The relative position of a substrate and a second substrate.

Similarly, in order to prevent the second adhesive from collapsing and deforming during the high temperature reflow soldering (raising the temperature and then dropping it down to achieve soldering) during the preparation of the chip assembly and subsequent testing and application, the first The material of the two-viscous adhesive can also be a low-fluidity glue, and the second adhesive can also be baked and cured, which will not be repeated here.

In a possible design, one or more solder balls can also be used to achieve alignment of the relative positions of the first substrate and the second substrate.

In a possible design, the second substrate in the chip assembly provided by the first aspect may be a multilayer circuit board. When the second substrate uses a multilayer circuit board, the internal structure of the multilayer circuit board can be used to connect the second radiation patch and the RF processing chip, so that the wiring is three-dimensional, and the wiring area on the second substrate is reduced, thereby reducing the The complexity of the wiring of the two substrates.

In a second aspect, an embodiment of the present application further provides a method for preparing a chip assembly, which includes the following steps: using a ball-planting process to grow one or more solder balls on the surface of a first substrate to obtain a first sample, wherein The first radiation patch is disposed on the surface of the first substrate; the first sample is aligned and placed on the second substrate using a film loading device to obtain a second sample, and the surface of the first substrate grows one or more solder balls. The second substrate is quasi-secondary, and the second radiation patch is disposed on the surface of the second substrate facing the first substrate; the second sample is soldered using a high temperature reflow process to obtain a third sample; one or more are drilled on the first substrate A fourth sample is obtained through the vias; a dispensing process is performed in the one or more vias to form a fifth sample containing one or more first adhesives, one end of each first adhesive It is arranged in a via hole and the other end is connected to the surface of the second substrate facing the first substrate; the surface of the second substrate on which the second radiation patch is not placed is flip-chip RF processing chip to obtain a chip assembly.

In a possible design, before flipping the RF processing chip, it is also possible to perform dispensing between the first substrate and the second substrate, and near the edge of the first substrate and the edge of the second substrate to form one or Multiple second viscose.

In a possible design, the material of the first adhesive and the second adhesive is a low-flow adhesive.

In a possible design, after the dispensing process is performed in the one or more via holes to form a fifth sample, the method further includes: baking and curing the fifth sample.

In a third aspect, the terminal device includes a chip assembly and a printed circuit board PCB provided in the first aspect or any one of its possible designs, and the chip assembly is disposed on a surface of the PCB.

Specifically, the terminal device includes, but is not limited to, a smart phone, a smart watch, a tablet computer, a virtual reality (VR) device, an augmented reality (AR) device, a personal computer, a handheld computer, and a personal digital assistant.

In addition, for the technical effects brought by any one of the possible design methods in the second aspect to the third aspect, refer to the technical effects brought by the different design methods in the first aspect, which will not be repeated here.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic structural diagram of a packaged antenna provided in the prior art; FIG.

2 is a schematic structural diagram of a first chip assembly according to an embodiment of the present application;

3 is a schematic structural diagram of a second chip assembly according to an embodiment of the present application;

4 is a schematic structural diagram of a third chip assembly according to an embodiment of the present application;

5 is a schematic structural diagram of a fourth chip assembly according to an embodiment of the present application;

6 is a schematic structural diagram of a fifth chip assembly according to an embodiment of the present application;

7 is a schematic structural diagram of a sixth chip assembly according to an embodiment of the present application;

8 is a schematic structural diagram of a seventh chip assembly according to an embodiment of the present application;

9 is a schematic structural diagram of an eighth chip assembly according to an embodiment of the present application;

10 is a schematic structural diagram of a ninth chip assembly according to an embodiment of the present application;

11 is a schematic structural diagram of a tenth chip assembly according to an embodiment of the present application;

12 is a schematic structural diagram of an eleventh chip assembly according to an embodiment of the present application;

13 is a schematic structural diagram of a twelfth chip assembly according to an embodiment of the present application;

14 is a schematic flowchart of a method for preparing a chip assembly according to an embodiment of the present application;

FIG. 15 is a schematic flowchart of another method for manufacturing a chip assembly according to an embodiment of the present application.

detailed description

As described in the background art, in a package antenna using a double-layered patch, is the distance and alignment between the upper substrate carrying the upper-layer patch and the lower substrate carrying the lower-layer patch accurate? Greater impact.

In the packaged antenna shown in FIG. 1, the upper substrate is used to carry the auxiliary radiator of the antenna, the lower substrate is connected to the RF chip and carries the main radiator of the antenna, and the main radiator passes through the feed circuit in the lower substrate to the main radiator. Feed. The main radiator is an antenna array and includes multiple array elements (hereinafter referred to as lower-level array elements); the sub-radiator is also an antenna array and includes multiple array elements (hereinafter referred to as upper-level array elements). Each upper element is coupled to a lower element, and each lower element and the upper element coupled to it have the same shape and size, and are centered. The radio frequency processing chip feeds the main radiator through a feeder circuit in the lower substrate. Each lower element in the main radiator supplies power to the corresponding upper element through a coupling feed, thereby increasing the bandwidth of the packaged antenna. .

In the packaged antenna shown in FIG. 1, if the center of the lower layer element is not aligned with the center of the upper layer element, or the shape and size of the lower layer element and the upper layer element are different, the gain of the packaged antenna will be reduced and the return loss Will worsen and the pattern will worsen. In addition, the distance between the upper array element and the lower array element will also affect the frequency offset of the packaged antenna. Therefore, for a package antenna using a double-layer patch, how to achieve accurate and stable adhesion between the upper substrate and the lower substrate is one of the key technologies.

In the packaged antenna shown in FIG. 1, the upper substrate and the lower substrate are bonded by a solder ball. Because the solder ball has thermal instability, the manufacturing process of the packaged antenna and subsequent testing and application processes include multiple high-temperature reflow soldering operations (the temperature is increased and then lowered to achieve soldering). Due to the solder ball's thermal instability In the high temperature reflow process, the solder ball easily collapses and deforms, resulting in changes in the pitch and misalignment between the upper and lower substrates, affecting the alignment between the upper and lower substrates and the performance of the package antenna. Make an impact.

Therefore, the use of solder balls to achieve the bonding between the upper substrate and the lower substrate may cause the relative position of the upper substrate and the lower substrate to be unstable, thereby affecting the performance of the packaged antenna.

Based on the above problems, the embodiments of the present application provide a chip assembly, a method for preparing the chip assembly, and a terminal device, so as to realize the adhesion between the upper substrate and the lower substrate, so that the relative position of the upper substrate and the lower substrate is stable, thereby improving Chip assembly performance.

The embodiments of the present application will be further described in detail below with reference to the accompanying drawings.

It should be noted that, in the embodiments of the present application, multiple means two or more. In addition, it should be understood that in the description of this application, the words "first" and "second" are used only for the purpose of distinguishing descriptions, and cannot be understood as indicating or implying relative importance, nor as indicating Or imply order.

Referring to FIG. 2, a chip assembly 200 according to an embodiment of the present application is provided. The chip assembly 200 includes a first substrate 202 and a second substrate 204 opposite to each other; and a first radiation patch 201 provided on the first substrate 202. Facing or facing away from the surface of the second substrate 204; the second radiation patch 203 is disposed on the surface of the second substrate 204 facing the first substrate 202, and the first radiation patch 201 and the second radiation patch 203 are coupled; The chip assembly 200 further includes a radio frequency processing chip 205, one or more solder balls 206, and one or more first adhesives 207.

The second substrate 204 is provided with a feeding path; the first radiation patch 201 is coupled to the second radiation patch 203; the radio frequency processing chip 205 is disposed on a surface of the second substrate 204 facing away from the first substrate 202, and is connected to the second substrate 204. The substrate 204 is electrically connected to feed the second radiation patch 203 radially through a feeder circuit; each solder ball 206 is placed between the first substrate 202 and the second substrate 204 to implement the first substrate 202 and the second substrate 202. Connection of substrate 204; one or more vias are provided on the first substrate 202, one end of each first adhesive 207 is disposed in one via, and the other end is connected to the surface of the second substrate 204 facing the first substrate 202 For fixing the relative positions of the first substrate 202 and the second substrate 204.

It should also be noted that the chip assembly 200 shown in FIG. 2 can be regarded as the aforementioned packaged antenna. The chip assembly 200 shown in FIG. 2 may be connected to a motherboard (ie, a PCB board) through a BGA. From the stacking order of two substrates (first substrate 202 and second substrate 204) and two radiation patches (first radiation patch 201 and second radiation patch 203) in practical applications, the first substrate 202 Can be regarded as the upper substrate, the second substrate 204 can be regarded as the lower substrate (that is, for the three motherboards, the first substrate 202 and the second substrate 204, the stacking order from the bottom to the top is the motherboard, the second Substrate 204, first substrate 202, that is, the first substrate 202 is stacked on the second substrate 204); the first radiation patch 201 can be regarded as an upper radiation patch, and the second radiation patch 203 can be regarded as a lower layer Radiation patch (that is, for the mother board, the first radiation patch 201 and the second radiation patch 203, the stacking order is from the bottom to the top, the mother board, the second radiation patch 203, and the first radiation The patch 201, that is, the first radiation patch 201 is stacked on the second radiation patch 203).

In order to make the description in the embodiments of the present application more concise and express the above-mentioned superposition relationship, in the description of the following embodiments, the first radiation patch 201 is replaced with the upper radiation patch 201, and the second radiation patch 203 is replaced with the lower layer. The radiation patch 203 is replaced, the first substrate 202 is replaced with an upper substrate 202, and the second substrate 204 is replaced with a lower substrate 204.

In the embodiment of the present application, the one or more solder balls 206 may also be used to achieve alignment of the relative positions of the upper substrate 202 and the lower substrate 204. That is, while the upper substrate 202 and the lower substrate 204 are connected through one or more solder balls 206, the one or more solder balls 206 can also align the relative positions of the upper substrate 202 and the lower substrate 204 so that two The relative position after the connection is a position that can satisfy the performance of the chip assembly 200.

Among them, the radio frequency processing chip 205 may also be called radio frequency integrated circuits (radio frequency integrated circuits, RFIC). The RF processing chip 205 may be flip-chip mounted on a surface of the lower substrate 204 that does not face the upper substrate 202. Specifically, the radio frequency processing chip 205 may be connected to the lower substrate 204 through a solder bump, a solder paste, or the like. The radio frequency processing chip 205 may also be physically connected to the lower substrate 204 directly. In the embodiment of the present application, the connection manner of the radio frequency processing chip 205 and the lower substrate 204 is not specifically limited. For the sake of simplicity, the drawings in the embodiments of the present application all take the RF processing chip 205 connected to the lower substrate 204 through a solder bump as an example for illustration.

In addition, in the embodiment of the present application, the upper radiation patch 201 may be disposed on a surface of the upper substrate 202 facing the lower substrate 204, or may be disposed on a surface of the upper substrate 202 facing away from the lower substrate 204, which is not done in the embodiment of the present application Specific limitations. The manner in which the upper-layer radiation patch 201 shown in FIG. 2 is disposed on the surface of the upper substrate 202 facing away from the lower substrate 204 is merely an example. In the subsequent drawings, the embodiments of the present application all illustrate a scheme in which the upper radiation patch 201 is disposed on the surface of the upper substrate 202 facing away from the lower substrate 204, but in actual implementation, the position of the upper radiation patch 201 is not limited This is the way illustrated in the drawings.

Further, in the embodiment of the present application, both the upper radiation patch 201 and the lower radiation patch 203 may be in the form of an antenna array, that is, the upper radiation patch 201 includes M upper array elements, and the lower radiation patch 203 includes M lower layers. Array elements, M lower-level array elements are respectively coupled with M upper-level array elements. At this time, the radio frequency processing chip 205 feeds M lower-layer array elements through M feeding paths included in the feeding path, respectively, and M> 1.

When both the upper radiation patch 201 and the lower radiation patch 203 are in the form of an antenna array, a schematic structural diagram of the chip assembly 200 can be shown in FIG. 3. A top view of the chip assembly shown in FIG. 3 may be shown in FIG. 4. In the chip assembly 200 shown in FIG. 3 and FIG. 4, the upper radiation patch 201 includes eight upper array elements and the lower radiation patch 203 includes eight lower array elements as an example. In actual implementation, the number of array elements included in the upper radiation patch 201 and the lower radiation patch 203 is not specifically limited in the implementation of the present application.

When both the upper radiation patch 201 and the lower radiation patch 203 are in the form of an antenna array, the chip assembly 200 can cover a wide frequency range and obtain better antenna gain.

In addition, in one possible example, each lower element and the upper element coupled to it have the same shape and size, and are centered. In this way, the chip assembly 200 can obtain better electrical performance.

In the embodiment of the present application, the feeding manner of the chip assembly 200 shown in FIG. 2 can be understood as follows: the RF processing chip 205 feeds the radial radiation patch 203 to the lower layer through the feeding circuit in the lower substrate 204; the lower radiation patch The sheet 203 is not directly connected to the upper radiation patch 201, but feeds power to the upper radiation patch 201 by means of coupling feeding.

Specifically, when feeding the radio frequency processing chip 205 to the lower-level radiation patch 203, a direct feeding method or a coupling feeding method may be adopted. The solution using the direct power feeding method can be shown in FIG. 2, that is, the power feeding path in the lower substrate 204 is directly connected to the lower radiation patch 203. When the coupled feeding method is adopted, the chip assembly 200 shown in FIG. 2 may be shown in FIG. 5.

In the chip assembly 200 shown in FIG. 5, a platform extending from an end of the feeding path in the lower substrate 204 away from the radio frequency processing chip 205 forms a resonance with the lower radiation patch 203 to implement the radio frequency processing chip. 205 is coupled to feed power through a feeding circuit in the lower substrate 204 to the radial lower radiation patch 203.

It should be noted that, in the chip assembly 200 shown in FIG. 2, the relative positions of the upper substrate 202 and the lower substrate 204 are aligned by one or more solder balls 206 and one or more first adhesives are used. 207 fixes the relative positions of the upper substrate 202 and the lower substrate 204.

That is, in the manufacturing process of the chip assembly 200, the connection between the upper substrate 202 and the lower substrate 204 is first realized by using one or more solder balls 206. In the case that the two are connected and the alignment is accurate when the connection is made, when the lower radiation patch 203 is coupled to the upper radiation patch 201 and fed, the aforementioned gain reduction, return loss deterioration, pattern deterioration, and frequency deviation will not occur. A larger problem, and the coverage band of the chip assembly 200 can meet the user's needs, so that the performance of the chip assembly 200 can be improved. Then, in order to avoid the problem that the solder ball 206 collapses and deforms due to thermal instability during multiple high-temperature reflow processes, which affects the alignment of the upper substrate 202 and the lower substrate 204, one or Glue is injected into each of the plurality of vias to form one or more first adhesives 207, so as to fix the relative positions of the upper substrate 202 and the lower substrate 204.

Among them, before the first adhesive 207 is provided, in order to enable the solder balls 206 to align the relative positions of the upper substrate 202 and the lower substrate 204 and maintain the relative positions of the two, the solder balls 206 may be stable and have no fluidity. Materials such as tin, copper, plastic, etc.

In one possible example, the solder ball 206 includes, but is not limited to, a tin core solder ball, a copper core solder ball, or a plastic core solder ball. That is, the material of the outer surface of the solder ball 206 is tin, and the material of the inner core of the solder ball 206 includes, but is not limited to, tin, copper, and plastic.

In addition, in the embodiment of the present application, the solder ball 206 may also be replaced by a structure with other shapes, as long as the structure can be used to achieve the connection between the upper substrate 202 and the lower substrate 204. For example, the solder ball 206 may be replaced by a cube-shaped or cuboid-shaped tin block.

In order to prevent the first adhesive 207 from collapsing and deforming during the high temperature reflow soldering (raising the temperature and then falling down to achieve soldering) during the preparation process of the chip assembly 200 and subsequent testing and application, the first The adhesive 207 can be a low-flow adhesive and baked and cured after the dispensing operation on the chip assembly 200, so that the first adhesive 207 is more stable, and the relative position of the upper substrate 202 and the lower substrate 204 is fixed. .

In addition, the shape of the first adhesive 207 is not specifically limited in the embodiment of the present application. For example, the first adhesive 207 may be spherical, cubic, rectangular or any irregular shape, as long as the first adhesive 207 can be used to fix the upper substrate. The relative positions of 202 and the lower substrate 204 may be sufficient.

It should be noted that, in the embodiment of the present application, the number of the solder balls 206 and the first adhesive 207 are not specifically limited. The number of the solder balls 206 may be one or plural. Similarly, the number of the first adhesive 207 may be one or plural.

Generally, in order to make the relative positions of the upper substrate 202 and the lower substrate 204 more stable, a plurality of solder balls 206 may be disposed symmetrically between the upper substrate 202 and the lower substrate 204. In FIG. 2, the chip assembly 200 is illustrated only by using two solder balls 206 and one first adhesive 207 as an example. In actual implementation, the number of the solder balls 206 and the first adhesive 207 is not limited to the number shown in FIG. 2.

In addition, it should also be noted that the positions of the solder balls 206 and the positions of the adhesive 207 are not specifically limited in the embodiment of the present application. The position distribution of the solder balls 206 in the chip assembly 200 and the position distribution of the first adhesive 207 in the chip assembly 200 are introduced below.

First, the position distribution of the solder ball 206 in the chip assembly 200

The solder balls 206 may be placed between the upper substrate 202 and the lower substrate 204 and located near the edge of the upper substrate 202 (or the lower substrate 204); the solder balls 206 may also be symmetrically distributed around the vertical line of the lower substrate 204 The solder balls 206 may be scattered randomly at any position between the upper substrate 202 and the lower substrate 204.

Exemplarily, when the number of the solder balls 206 is plural, the plurality of solder balls 206 may be symmetrically distributed around the vertical line of the lower substrate 204. At this time, the cross-sectional view of the chip assembly 200 may be as shown in FIG. 6. In FIG. 6, eight solder balls 206 are used for illustration. In actual implementation, the number of solder balls 206 is not limited to eight. In addition, in actual implementation, the top view of the chip assembly 200 can only see the upper substrate 202 and the upper radiation patch 201 (in the case where the upper radiation patch 201 is disposed on the surface of the upper substrate 202 facing away from the lower substrate 204) or only The upper substrate 202 can be seen (in the case where the upper radiation patch 201 is disposed on the surface of the upper substrate 202 facing the lower substrate 204). In order to illustrate the position distribution of the plurality of solder balls 206 in FIG. 6, eight solder balls 206 are seen through. The form of the figure is shown (the lines are indicated by dotted lines).

When the plurality of solder balls 206 are symmetrically distributed around the vertical line of the lower substrate 204, the structure of the plurality of solder balls 206 is more stable, so that the plurality of solder balls 206 can more reliably realize the upper substrate 202 and the lower substrate 204. connection.

It should be noted that the solder balls 206 can be used to achieve alignment of the relative positions of the upper substrate 202 and the lower substrate 204. That is, before the upper substrate 202 and the lower substrate 204 are assembled together, the solder balls 206 have been soldered on the upper substrate 202 (or the lower substrate 204) by a process such as ball implantation. Then, the solder balls 206 can be scattered randomly at any position between the upper and lower substrates, as long as the positions of the solder balls 206 do not interfere with the normal operation of the radiation patch. When the plurality of solder balls 206 are symmetrically distributed, the connection between the upper substrate 202 and the lower substrate 204 can be more stably achieved.

It should be noted that in order to avoid the material (such as tin, copper, plastic, etc.) of the solder ball 206 from overflowing and contaminating the radiation patch (including the upper radiation patch 201 and the lower radiation patch 203), the solder ball 206 can be selected as far away as possible. Areas of the upper radiation patch 201 and the lower radiation patch 203.

Second, the position distribution of the first adhesive 207 in the chip assembly 200

As described above, one end of each first adhesive 207 is disposed in a via hole on the upper substrate 202, and the other end is connected to the surface of the lower substrate 204 facing the upper substrate 202. That is, the position of the first adhesive 207 is determined by the position of the via hole provided on the upper substrate 202. In the embodiment of the present application, the positions and numbers of vias on the upper substrate 202 are not specifically limited.

The via hole may be a mechanical circular hole, a semi-circular hole, or a slot hole. The shape and size of the via hole are not specifically limited in the embodiment of the present application. In the embodiments of the present application, a circular via is used as an example for illustration. In actual implementation, the shape of the via is not limited to a circular shape. In particular, in one possible example, the via hole may be a semi-circular hole provided at an edge of the upper substrate 202. In addition, since the via hole is provided for the subsequent dispensing operation to form the first adhesive 207, the size of the via hole can be set according to the size of the needle of the dispensing equipment during specific implementation.

Exemplarily, when the number of vias on the upper substrate 202 is two and the centers of the substrates 202 above the two vias are symmetrically distributed, the structural schematic diagram of the chip assembly 200 may be shown in FIG. 7. In FIG. 7, the two first adhesives 207 are symmetrically distributed around a vertical line of the upper substrate 202.

Exemplarily, when the number of via holes on the upper substrate 202 is one and the via holes are disposed at the center of the upper substrate 202, a schematic structural diagram of the chip assembly 200 can be shown in FIG. 8. In FIG. 8, the first adhesive 207 is formed by injecting glue at the center of the upper substrate 202.

In addition, in the embodiment of the present application, the chip assembly 200 may further include one or more second adhesives, each of which is used to connect the edge of the upper substrate 202 and the edge of the lower substrate 204. When the chip assembly 200 includes two second adhesives, a schematic structural diagram of the chip assembly 200 shown in FIG. 8 may be shown in FIG. 9.

As can be seen from FIG. 9, when the two second adhesives are symmetrically disposed near the edge of the upper substrate 202 (or the lower substrate 204), the second adhesive can more effectively disperse between the upper substrate 202 and the lower substrate 204. The relative position of the upper substrate 202 and the lower substrate 204 is more firmly fixed.

It should be noted that the number of the second adhesives is not specifically limited in the embodiment of the present application, and only two second adhesives are used as an example for illustration in FIG. 9. In actual implementation, the number of second adhesives is not limited to two as shown in FIG. 9. In addition, the material of the second viscose may also be a low fluidity glue, which is not repeated here.

It should be noted that, because the material of the first adhesive 207 (such as low fluidity glue) may contaminate the radiation patches (including the upper radiation patch 201 and the lower radiation patch 203) in the chip assembly 200, the first The adhesive 207 can be selected as far as possible from a region away from the upper radiation patch 201 and the lower radiation patch 203.

In other words, when opening the upper substrate 201 to set the first adhesive 207, it is possible to select a position far away from the upper radiation patch 201 and the lower radiation patch 203 for opening, so that the first adhesive 207 will It is distributed away from the radiation patch to prevent the first adhesive 207 from contaminating the radiation patch.

For example, for the chip assembly 200 shown in FIG. 7, the first adhesive 207 placed in the two vias on the upper substrate 201 is located far from the upper radiation patch 201 and the lower radiation patch 203; For example, for the chip assembly 200 shown in FIG. 8, both the upper radiation patch 201 and the lower radiation patch 203 are in the form of an antenna array. At this time, when opening the upper substrate 201 to set the first adhesive 207, The position between the two upper array elements can be selected as much as possible for opening, so that the first adhesive 207 can be disposed between the two upper array elements, and the first adhesive 207 can be prevented from contaminating the upper and lower array elements.

In addition, in the embodiment of the present application, if the chip assembly 200 includes a plurality of first adhesives 207, a plurality of vias for setting the plurality of first adhesives 207 may also be distributed and distributed at any position on the upper substrate 202. . As long as these positions do not interfere with the normal operation of the radiation patch, and the first adhesive 207 provided at one end in the via hole can play a role of fixing the relative positions of the upper substrate 202 and the lower substrate 204.

It should be noted that the first adhesive 207 can be used to fix the relative positions of the upper substrate 202 and the lower substrate 204. That is, the first adhesive 207 is formed by a process such as dispensing after the upper substrate 202 and the lower substrate 204 are assembled together. Therefore, in order to facilitate subsequent dispensing operations, it is necessary to drill holes in the upper substrate 202 in advance, and then perform dispensing through the via holes drilled in the upper substrate 202 to form the first adhesive 207. For the second adhesive, since the second adhesive is distributed near the edge sides of the upper substrate 202 and the lower substrate 204, the second adhesive can be directly formed by a dispensing process, and it is not necessary to punch holes in the upper substrate 202. operating.

In the chip assembly 200 provided in the embodiment of the present application, it may further include one or more first green oil resist dams (the green oil resist dams may also be referred to as green oil DAM), and each of the first green oil resist dams The dam includes a plurality of first fixing blocks disposed around a solder ball 206, a part of the plurality of first fixing blocks is disposed on a surface of the upper substrate 202 facing the lower substrate 204, and another one of the plurality of first fixing blocks is provided. A part of the first fixing block is disposed on a surface of the lower substrate 204 facing the upper substrate 202. That is, a first green oil-resistance rubber dam can be used to fix the position of a solder ball 206.

Among them, the first green oil resist dam can adopt non-solder mask (defined) design (also known as green oil large window design), solder mask definition (SMD) design (Also known as green oil small window design) or copper-free pad design. The specific design scheme is the prior art, which will not be described in detail in the embodiments of the present application.

The first green oil-resistance rubber dam is used to fix the solder ball 206, so that the position of the solder ball 206 can be more stable, thereby achieving a more stable connection between the upper substrate 202 and the lower substrate 204, and the relative position of the upper substrate 202 and the lower substrate 204. Of alignment. In addition, the first green oil-resistance rubber dam can prevent the material (such as tin, copper, plastic, etc.) in the solder ball 206 from overflowing and contaminating the radiation patch when the solder ball 206 collapses and deforms, thereby preventing the spilled material from affecting the chip assembly. The performance of 200 has an impact.

Exemplarily, when two first green oil-resistance rubber dams are provided in the chip assembly 200 shown in FIG. 9, the structure of the chip assembly 200 may be as shown in FIG. 10.

In the chip assembly 200 provided in the embodiment of the present application, it may further include one or more second green oil-resistance rubber dams, and each second green oil-resistance rubber dam includes a plurality of first green oil dams disposed around a first adhesive 207. Two fixing blocks, a part of the plurality of second fixing blocks is disposed on the surface of the upper substrate 202 facing the lower substrate 204, and another part of the plurality of second fixing blocks is disposed on the lower substrate 204 facing upward The surface of the substrate 202. That is, a second green oil-resistance rubber dam can be used to fix the position of a first adhesive 207.

Among them, the second green oil-resistance rubber dam can adopt any of NSMD design, SMD design, or copper-free pad design. The specific design scheme is the prior art, which will not be described in detail in the embodiments of the present application.

Using the second green oil-resistance rubber dam to fix the first adhesive 207 can make the first adhesive 207 more stable, thereby making the relative positions of the upper substrate 202 and the lower substrate 204 more stable. In addition, the second green oil barrier dam can also prevent the adhesive in the first adhesive 207 from overflowing from contaminating the radiation patches in the chip assembly 200, and avoid the spilled material from affecting the performance of the chip assembly 200.

For example, when a second green oil-resistance rubber dam is provided in the chip assembly 200 shown in FIG. 9, the structure of the chip assembly 200 may be shown in FIG. 11.

It should be noted that if the chip assembly 200 includes a plurality of first adhesives 207, the chip assembly 200 may also be provided with a plurality of second green oil-resistance rubber dams, each of the second green oil-resistance rubber dams. For fixing a first adhesive 207.

In addition, if the chip assembly 200 further includes a second adhesive, then the chip assembly 200 may further include one or more green oil resist dams for the second adhesive, each green oil resist dam includes a plurality of Fixing block for fixing the second adhesive. For the specific setting method, refer to the related descriptions in the setting methods of the first green oil resistance rubber dam and the second green oil resistance rubber dam, and details are not described herein again.

In combination with the above description, when the first green oil resist dam, the second green oil resist dam, and the green oil resist dam for fixing the second viscose are simultaneously provided in the chip assembly 200 shown in FIG. 9, the The structure of the chip assembly 200 may be as shown in FIG. 12.

In addition, in the embodiment of the present application, according to different wiring and performance requirements for the chip assembly 200, the lower substrate 204 may be a multilayer circuit board. For example, in the chip assembly 200 shown in FIG. 2, the lower substrate 204 may adopt a two-layer circuit board.

When the lower substrate 204 is a multilayer circuit board, the internal structure of the multilayer circuit board can be used to connect the lower radiation patch 203 and the RF processing chip 205 to make the wiring three-dimensional and reduce the wiring area on the lower substrate 204, thereby reducing The wiring complexity of the lower substrate 204.

It should be understood that when the multilayer substrate is used for the lower substrate 204, the number of layers of the multilayer substrate is not limited. For example, it can be two layers, three layers, six layers, eight layers, and the like.

With the chip assembly 200 provided in the embodiment of the present application, the upper substrate 202 and the lower substrate 204 are connected through one or more solder balls 206, and the upper substrate 202 and the lower substrate 204 are fixed by one or more first adhesives 207. Relative position. In the chip assembly 200, the upper substrate 202 and the lower substrate 204 are first connected through one or more solder balls 206. Therefore, when the two are connected, the upper radiation patch 201 and the lower radiation patch 203 are opposite to each other. Positions can also be aligned without the aforementioned problems of lowered gains, worse return loss, worsened pattern, and larger frequency deviations, and the coverage of the chip assembly 200 can meet the needs of users. The chip assembly The performance of 200 is improved.

Further, the relative positions of the upper substrate 202 and the lower substrate 204 can be fixed by one or more first adhesives 207 in the chip assembly 200. When the solder ball 206 collapses or deforms due to thermal instability during multiple high-temperature reflow processes, the one or more first adhesives 207 can still maintain the relative positions of the upper substrate 201 and the lower substrate 203 in an aligned manner. In this state, the problem that the relative position of the upper substrate 201 and the lower substrate 203 is unstable will not occur, so that the performance of the chip assembly 200 can be improved.

For example, it can be known from the prior art that the distance (that is, the height difference) between the upper radiation patch 201 and the lower radiation patch 203 will affect the frequency offset of the chip assembly 200, and for working in a specific frequency band For the chip assembly, when the distance between the upper radiation patch 201 and the lower radiation patch 203 is a certain value, the frequency deviation of the signal generated by the chip assembly 200 for data transmission and reception is the smallest. For simplicity, we This value is called "specified height". The package antenna provided by the prior art is used, and the upper substrate and the lower substrate are connected by solder balls, that is, the two are adhered through the solder balls. The distance between the upper substrate and the lower substrate after the adhesion is "specified height". During the manufacturing process and subsequent testing and application of the packaged antenna, multiple high-temperature reflow soldering operations are required. The solder balls will collapse and deform due to high temperatures. Therefore, it is difficult to maintain the distance between the upper substrate and the lower substrate at the "specified height." . Therefore, when transmitting and receiving data through the packaged antenna, the signal will generate a large frequency offset, which affects the performance of the packaged antenna. By using the chip assembly 200 provided in the embodiment of the present application, the upper substrate 202 and the lower substrate 204 are bonded by solder balls, and the distance between the upper substrate 202 and the lower substrate 204 after the bonding is "specified height". In addition, because the first adhesive 207 uses low-flow adhesive, the first adhesive 207 can fix the relative position of the upper substrate 202 and the lower substrate 204 during the high-temperature reflow process. Therefore, the upper substrate 202 and the lower substrate 204 The spacing can be kept at "specified height". Therefore, when data is transmitted and received through the chip assembly 200, the frequency offset generated by the signal is small. Compared with the packaged antenna provided by the prior art, the chip assembly 200 can improve performance.

Based on the same inventive concept, an embodiment of the present application further provides a chip assembly. The chip assembly can be regarded as a specific example of the chip assembly shown in FIG. 2. Referring to FIG. 13, the chip assembly includes:

Opposing upper and lower substrates;

An upper radiation patch composed of a plurality of upper array elements, the upper radiation patch being disposed on a surface of the upper substrate facing away from the lower substrate;

A lower radiation patch composed of a plurality of lower array elements, the lower radiation patch being disposed on a surface of the lower substrate facing the upper substrate;

RF processing chip connected to the lower substrate through solder bumps;

Two solder balls placed between the upper substrate and the lower substrate, and two green oil DAMs for fixing the two solder balls;

Three adhesives placed between the upper and lower substrates, and three green oil DAMs for fixing the three adhesives.

In addition, the chip assembly may also include a BGA, which may be used to connect the chip assembly to a PCB.

Among them, the lower substrate is a six-layer circuit board, so that the wiring is three-dimensional, and the wiring area is reduced; a feeding path is provided in the lower substrate, and the radio frequency processing chip feeds the radial radiation patch through the feeder circuit, and the lower radiation patch Coupling feed to the upper radiation patch. In addition, in this chip assembly, two solder balls are used to connect the upper substrate to the lower substrate, and three adhesives are used to fix the relative positions of the upper substrate and the lower substrate.

In the chip assembly shown in FIG. 13, the solder ball can be regarded as a specific example of the foregoing solder ball 206; the green oil DAM used for fixing the solder ball can be regarded as a specific example of the aforementioned first green oil resistance rubber dam; The green oil DAM for fixing viscose can be regarded as a specific example of the aforementioned second green oil resisting dam. The chip assembly shown in FIG. 13 can be regarded as a specific example of the chip assembly 200 shown in FIG. 2. For implementation methods and technical effects not described in detail in the chip assembly shown in FIG. 13, refer to FIG. 2. Related description in the chip assembly 200.

Based on the above embodiments, the embodiment of the present application further provides a method for preparing a chip assembly, which can be used to prepare the aforementioned chip assembly 200. Referring to FIG. 14, the method includes the following steps:

S1401: Grow one or more solder balls on the surface of the upper substrate by using a ball-planting process to obtain a first sample.

The upper radiation patch is disposed on the surface of the upper substrate.

S1402: Align and place the first sample on the lower substrate by using a loading device to obtain a second sample.

The surface on which the one or more solder balls are grown on the upper substrate is aligned with the lower substrate, and the lower radiation patch is disposed on the surface of the lower substrate facing the upper substrate.

S1403: The second sample is soldered by using a high-temperature reflow soldering process to obtain a third sample.

The high-temperature reflow process can be performed in a reflow furnace.

S1404: Drill one or more via holes on the upper substrate to obtain a fourth sample.

It should be noted that the execution order of the operation of drilling through holes in the upper substrate in S1404 is not strictly limited, and this operation may be performed before the completion of the dispensing operation in S1405. For example, this operation may be performed before the ball planting operation is performed in S1401.

S1405: Dispensing is respectively performed in the one or more via holes by a dispensing process to form a fifth sample including one or more first adhesives.

One end of each first adhesive is disposed in a via hole, and the other end is connected to a surface of the second substrate facing the first substrate.

Specifically, the operation flow of the dispensing process may refer to the operation flow of the underfill process.

S1406: flip the RF processing chip on the surface of the lower substrate without the lower radiation patch to obtain a chip assembly.

Specifically, when the chip assembly is prepared by using the manufacturing method shown in FIG. 14, a schematic diagram of a sample or a finished product prepared through each step may be shown in FIG. 15.

Optionally, before the flip-chip RF processing chip, the method further includes: performing dispensing between the upper substrate and the lower substrate, and near the edge of the upper substrate and the edge of the lower substrate to form one or more second adhesives.

Each of the second adhesives formed through the above scheme can be used to connect the edge of the upper substrate and the edge of the lower substrate. It should be noted that the chip assembly prepared by the method shown in FIG. 14 may include multiple adhesives. In specific implementation, the above-mentioned dispensing solution and the solution described in S1405 may be used to form multiple adhesives (for example, the first Viscose and second viscose).

Optionally, the material of the first adhesive and the second adhesive may be a low-flow adhesive.

Optionally, after a dispensing process is performed in the one or more via holes to form a fifth sample, the fifth sample may be baked and cured.

By adopting the above solution, the fifth sample is baked and cured after the dispensing operation, which can make the first adhesive more stable, and then fix the relative positions of the upper substrate and the lower substrate.

In addition, during the above preparation process, one or more first green oil-resistance rubber dams may be provided on the upper substrate and the lower substrate. Each first green oil-resistance rubber dam is used for fixing a solder ball, and each first The green oil resistance rubber dam includes a plurality of first fixing blocks, a part of the plurality of first fixing blocks is disposed on a surface of the upper substrate facing the lower substrate, and another part of the plurality of first fixing blocks is the first fixing block. It is disposed on the surface of the lower substrate facing the upper substrate.

Setting one or more first green oil-resistance rubber dams in the chip assembly can make the positions of one or more solder balls more stable, so as to achieve a more stable connection between the upper substrate and the lower substrate. In addition, the first green oil-resistance rubber dam can prevent the material in the solder ball (such as tin, copper, plastic, etc.) from overflowing and contaminating the radiation patch when the solder ball collapses and deforms, and avoid the spilled material from affecting the performance of the chip assembly. influences.

Similarly, during the above preparation process, one or more second green oil-resistance rubber dams may be provided on the upper substrate and the lower substrate. Each second green oil-resistance rubber dam is used to fix a first adhesive. Each second green oil-resistance rubber dam includes a plurality of second fixing blocks, a part of the plurality of second fixing blocks is disposed on a surface of the upper substrate facing the lower substrate, and another part of the plurality of second fixing blocks is The two fixing blocks are disposed on a surface of the lower substrate facing the upper substrate.

Setting a second green oil-resistance rubber dam in the chip assembly can make the first adhesive more stable, thereby making the relative positions of the upper substrate and the lower substrate more stable. In addition, the second green oil barrier dam can also prevent the adhesive in the first adhesive from overflowing from contaminating the radiation patches in the chip assembly, so as to avoid the spilled material from affecting the performance of the chip assembly.

It should be noted that the method for preparing the chip assembly shown in FIG. 14 can be used to prepare the aforementioned chip assembly 200. For implementation methods and technical effects not described in detail in the preparation method shown in FIG. 14, refer to the chip assembly 200. Related description.

Based on the above embodiments, an embodiment of the present application further provides a terminal device. The terminal device includes the chip assembly 200 and a PCB, and the chip assembly 200 is disposed on a surface of the PCB. Specifically, the PCB may be connected to the lower substrate 204 in the chip assembly 200 through the BGA.

Exemplarily, the terminal device includes, but is not limited to, a smart phone, a smart watch, a tablet computer, a VR device, an AR device, a personal computer, a handheld computer, and a personal digital assistant.

Among them, the communication system adopted by the terminal device includes, but is not limited to, code division multiple access (CDMA), wide-band code division multiple access (WCDMA), time division synchronization Code division multiple access (time division-synchronous code division multiple access (TD-SCDMA), long term evolution (LTE), and 5th generation (5G) standards.

In particular, by using the terminal device provided in the embodiment of the present application, the chip assembly 200 in the terminal device can realize high-gain and large-bandwidth communication requirements in a frequency band of 10 GHz to 40 GHz.

Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. In this way, if these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application also intends to include these changes and variations.

Claims

A chip assembly, comprising:

A first substrate and a second substrate opposite to each other, wherein a feeding path is provided in the second substrate;

A first radiation patch, disposed on a surface of the first substrate facing or facing away from the second substrate;

A second radiation patch is disposed on a surface of the second substrate facing the first substrate, and the first radiation patch is coupled to the second radiation patch;

A radio frequency processing chip, disposed on a surface of the second substrate facing away from the first substrate, and electrically connected to the second substrate, and configured to feed the second radiation patch radially through the feeding circuit;

One or more solder balls, each of which is placed between the first substrate and the second substrate, and is used to achieve the connection between the first substrate and the second substrate;

One or more first adhesives, wherein the first substrate is provided with one or more vias, one end of each of the first adhesives is disposed in the vias, and the other end is connected to the second substrate The surface facing the first substrate is connected to fix a relative position between the first substrate and the second substrate.
The chip assembly according to claim 1, further comprising:

One or more second adhesives, each of which is used to connect an edge of the first substrate and an edge of the second substrate.
The chip assembly according to claim 1 or 2, further comprising:

One or more first green oil-resistance rubber dams, each of the first green oil-resistance rubber dams includes a plurality of first fixing blocks disposed around one of the solder balls, and a part of the plurality of first fixing blocks A first fixing block is disposed on a surface of the first substrate facing the second substrate, and another portion of the plurality of first fixing blocks is disposed on a surface of the second substrate facing the first substrate. surface.
The chip assembly according to any one of claims 1 to 3, further comprising:

One or more second green oil-resistance rubber dams, each of said second green oil-resistance rubber dams includes a plurality of second fixing blocks disposed around one of said first adhesives, A portion of the second fixing block is disposed on a surface of the first substrate facing the second substrate, and another portion of the plurality of second fixing blocks is disposed on the second substrate facing the first substrate. The surface of the substrate.
The chip assembly according to any one of claims 1 to 4, wherein a material of the first adhesive and the second adhesive is a low-flow adhesive.
A terminal device, comprising the chip assembly according to any one of claims 1 to 5 and a printed circuit board PCB, wherein the chip assembly is disposed on a surface of the PCB.