WO2020020038A1

WO2020020038A1 - Data format conversion method

Info

Publication number: WO2020020038A1
Application number: PCT/CN2019/096467
Authority: WO
Inventors: 冯万健; 林宗严; 廖嘉祥
Original assignee: 厦门亿联网络技术股份有限公司
Priority date: 2018-07-27
Filing date: 2019-07-18
Publication date: 2020-01-30
Also published as: CN109189703A

Abstract

Disclosed is a data format conversion method, comprising: connecting N latches; successively outputting m-bit data to the N latches, and then controlling the latches to latch the data; the N latches completing the latching of the data and outputting (N*m)-bit data in parallel in cooperation with a data enable signal; and then, driving a horizontal synchronization signal clock transition edge to transition to complete reading of the (N*m)-bit data. The problem of an interface conflict caused by a difference in the number of bits of data can be effectively solved, and the material cost is greatly reduced.

Description

Data format conversion method

Cross-quote

This disclosure is based on a Chinese patent application with an application number of 201810851326.3 and an application date of 2018-27-07 and claims the priority of the Chinese patent application. The entire contents of this Chinese patent application are incorporated herein by reference.

Technical field

The present disclosure relates to the technical field of multiple data conversion, and in particular, to a method for converting data format using a latch.

Background technique

At present, the GPIO of the control chip often has a function multiplexing phenomenon. When there are many system function applications, there is a problem of interface conflicts. Currently, PLD is usually used for software programming to solve the problem of interface conflicts caused by different data bits. But PLD is more expensive and more reproducible.

Summary of the Invention

The present disclosure provides a data format conversion method, which can greatly reduce the cost of materials while solving the interface conflicts caused by different data bits.

An embodiment of the present disclosure provides a data format conversion method, including: sequentially outputting m-bit data to N latches, so that each of the latches sequentially latches the m-bit data; m ≥1;

The N latches are sequentially connected in parallel; N≥2;

When the N latches have completed latching the m-bit data, the N latches are configured to output N * m-bit data to the receiver in parallel by using a data enable signal;

Driving the clock synchronization edge of the line synchronization signal to perform a transition so that the receiver completes reading the N * m-bit data.

Further, the m-bit data is sequentially output to the N latches, so that each of the latches sequentially latches the m-bit data, specifically:

Each latch is provided with multiple data bit interfaces;

Output the m-bit data to the i-th latch through the data bit interface of the i-th latch, and complete the locking of the m-bit data in the i-th latch After saving, output the m-bit data to the i + 1th latch through the data bit interface of the i + 1th latch latch, so that the i + 1th latch The memory outputs the m-bit data; N-1≥i≥1.

Further, the N latches are sequentially connected in parallel, specifically:

Between the N latches, the data bit interfaces with the same number are connected in parallel with each other.

Further, outputting the m-bit data to the i-th latch is specifically:

The LE pin of the i-th latch is controlled to be at a high level, and the m-bit data is input to the i-th latch through the data bit.

Further, each of the latches sequentially latches the m-bit data, specifically:

When the data is input to the latch, the LE pin of the latch is controlled to be at a low level to latch the m-bit data.

Further, when the N latches have completed latching the m-bit data, the N latches are configured to output N * m-bit data to the receiver in parallel by using a data enable signal. Specifically, for:

When the N latches have completed latching the m-bit data, the data enable pin sends a data enable signal to control the output pins of the N latches to output the N to the receiver in parallel. * m-bit data.

Further, driving the clock synchronization edge of the line synchronization signal to perform a transition so that the receiver completes reading the N * m-bit data is specifically:

After sending the N * m as data to the receiver, driving the transition edge of the line synchronization signal clock to align with the m-bit data, so that the receiver completes reading the N * m-bit data .

A simple and effective data format conversion method provided by the embodiment of the present disclosure, by using a plurality of latches to sequentially latch a plurality of data, and after completing the latching of a plurality of data, multi-bit data is output in parallel to realize the data format conversion. At the same time, material costs are greatly reduced.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic flowchart of an embodiment of a data format conversion method provided by the present disclosure.

FIG. 2 is a schematic diagram of a connection structure of a latch according to an embodiment of the present disclosure.

detailed description

The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, but not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by a person having ordinary skill in the art without making creative efforts fall within the protection scope of the present disclosure.

FIG. 1 is a schematic flowchart of an embodiment of a data format conversion method provided by the present disclosure. include:

S11. Output m-bit data to N latches in sequence, so that each latch sequentially latches m-bit data, m≥1. m is a positive integer.

Specifically, the m-bit data is sequentially output to the i-th latch, and after the m-bit data is latched by the i-th latch, the m-bit data is output to the i + 1th latch. Data, so that the i + 1th latch outputs m-bit data. Where N-1≥i≥1, i is a positive integer. By controlling the sequence of latches, the latches that have received data are not affected by the new input data.

Further, N latches are sequentially connected in parallel. N≥2, the specific connection method is: the latch has multiple data bits. Data bits are numbered from 1 to a, and data bits of the same number are connected in parallel. a≥2 and a is a positive integer.

Further, by controlling the LE pin of the i-th latch to be at a high level, the m-bit data is input to the i-th latch through a data bit.

Further, when data is input to the latch, the LE pin of the latch is controlled to be at a low level, so that the latch latches m-bit data.

S12. When the N latches have completed latching the m-bit data, the N latches are configured to output N * m-bit data to the receiver in parallel by using a data enable signal.

Specifically, when the N latches have completed latching the m-bit data, the data enable pin sends a data enable signal to control the output pins of the latches to output N * m-bit data in parallel. Because the time for sending data is determined, the timing control of data sending and data enabling can be made without deviation.

S13. Drive a clock synchronization edge of the line synchronization signal to perform a transition so that the receiver completes reading the N * m-bit data.

Specifically, because the data reception is only related to the clock transition edge, after the data output of all the latches is completed, the clock transition edge is aligned with all the data to enable the receiver to complete the N * m-bit data. Read.

It should be noted that, before all the latched data is completely latched, the clock triggering edge will not jump to avoid receiving data reading errors. The receiver can be a device such as liquid crystal that can be used for data display.

Further, referring to FIG. 2, it is a schematic diagram of a connection structure of an embodiment of a latch provided by the present disclosure. Including a plurality of latches 101.

The latch 101 has a plurality of data bits, and the data bits are numbered from 1 to N. The N latches 101 have the same number of data bits connected in parallel and are used to receive m-bit data. The LE pins between the N latches 101 are individually connected, so that the LE pin level of only one latch 101 can be changed at a time, so that multiple m-bit data can be stored in different latches 101. After latching all the m-bit data, the output pins On of the N latches 101 send out the m-bit data latched by each latch 101 in parallel, thereby outputting N * m-bit data.

It should be noted that the latch may be, but is not limited to, a D-type latch.

An embodiment of the present disclosure provides a data format conversion method. By connecting a plurality of latches and sequentially latching the data, finally outputting N * m-bit data at the same time, and driving the clock synchronization edge and Data alignment to complete the reading of N * m-bit data. By adopting the present disclosure, the problem of interface conflicts caused by different data bits can be effectively solved, and the material cost can be greatly reduced.

The above is the preferred embodiment of the present disclosure. It should be noted that for those of ordinary skill in the art, without departing from the principles of the present disclosure, several improvements and retouches can be made. The scope of protection of the present disclosure.

Claims

A data format conversion method includes:

Output m-bit data to N latches in sequence, so that each of the latches sequentially latches the m-bit data, wherein the N latches are connected in parallel in order; m≥1; N≥2;

After the N latches have completed latching the m-bit data, the N latches are configured to output N * m-bit data to the receiver in parallel by using a data enable signal;

Driving the clock synchronization edge of the line synchronization signal to perform a transition so that the receiver completes reading the N * m-bit data.
The data format conversion method according to claim 1, wherein the m-bit data is sequentially output to the N latches, so that each of the latches sequentially processes the m-bit data. Perform latching as follows:

Each latch is provided with multiple data bit interfaces;

Output the m-bit data to the i-th latch through the data bit interface of the i-th latch, and complete the locking of the m-bit data in the i-th latch After saving, output the m-bit data to the i + 1th latch through the data bit interface of the i + 1th latch, so that the i + 1th latch outputs The m-bit data; N-1≥i≥1.
The data format conversion method according to claim 2, wherein the N latches are sequentially connected in parallel, specifically:

Between the N latches, the data bit interfaces with the same number are connected in parallel with each other.
The data format conversion method according to claim 2, wherein the outputting the m-bit data to the i-th latch is specifically:

The LE pin of the i-th latch is controlled to be at a high level, and the m-bit data is input to the i-th latch through the data bit interface.
The data format conversion method according to claim 2, wherein each of the latches sequentially latches the m-bit data, specifically:

When the m-bit data is input to the latch, the LE pin of the latch is controlled to be at a low level to latch the m-bit data.
The data format conversion method according to claim 1, wherein, when the N latches have completed latching the m-bit data, the N latches are enabled by a data enable signal. The latch outputs N * m bits of data to the receiver in parallel, specifically:

When the N latches have completed latching the m-bit data, the control data enable pin sends a data enable signal, so that the output pins of the N latches are controlled in parallel to the receiver. The N * m-bit data is output.
The data format conversion method according to claim 6, wherein the driving of the clock synchronization edge of the driving line synchronization signal to make the receiving side complete the reading of the N * m-bit data comprises:

After sending the N * m-bit data to the receiver, driving the transition edge of the line synchronization signal clock to align with the m-bit data, so that the receiver completes reading the N * m-bit data .
The data format conversion method according to any one of claims 1 to 7, wherein the latch is a D-type latch.