WO2020000989A1 - 可抵御边信道攻击的缓存加固方法及装置 - Google Patents

可抵御边信道攻击的缓存加固方法及装置 Download PDF

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Publication number
WO2020000989A1
WO2020000989A1 PCT/CN2018/125953 CN2018125953W WO2020000989A1 WO 2020000989 A1 WO2020000989 A1 WO 2020000989A1 CN 2018125953 W CN2018125953 W CN 2018125953W WO 2020000989 A1 WO2020000989 A1 WO 2020000989A1
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Prior art keywords
cache
entry
allocator
identifier
operation request
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PCT/CN2018/125953
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English (en)
French (fr)
Inventor
窦强
赵天磊
张承义
高军
薛洪波
刘晓燕
李文哲
王玉姣
苑佳红
孙龙鹏
李水晶涛
丁哲
王晓凤
王小岛
曹文辉
郑帅克
游柏青
袁媛
邹小立
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天津飞腾信息技术有限公司
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Priority to US16/627,369 priority Critical patent/US11334668B2/en
Publication of WO2020000989A1 publication Critical patent/WO2020000989A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
    • G06F21/55—Detecting local intrusion or implementing counter-measures
    • G06F21/556—Detecting local intrusion or implementing counter-measures involving covert channels, i.e. data leakage between processes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2221/00—Indexing scheme relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F2221/03—Indexing scheme relating to G06F21/50, monitoring users, programs or devices to maintain the integrity of platforms
    • G06F2221/034—Test or assess a computer or a system

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  • the present invention relates to a cache management technology in a microprocessor, and in particular, to a cache hardening method and device capable of resisting side channel attacks.
  • Cache is a device that is used extensively in microprocessors. Its main function is to save some common information during program execution, such as instruction codes, data, virtual-real address mapping, branch direction bias history, branch target address history, and so on. By storing this information in the cache on the microprocessor chip, you can reduce the delay in accessing them, avoid the energy consumption caused by obtaining this information off-chip, or reduce the processor pipeline pause time, so as to improve performance or reduce power. Consumption purpose.
  • Figure 1 shows the general structure of the cache in the processor. Each cache item includes tags, attributes, and data.
  • the cache involved in the present invention includes instruction cache (Instruction cache, ICache), data cache (Data cache, DCache), unified cache (Unified cache), page table cache (Translation Look-asideBuffer (TLB), branch direction history table (Branch (History Buffer (BHB)), Branch target history table (BranchTarget buffer, BTB), Indirect branch target history buffer (Indirect), Target buffer (IBTB), Write buffer (Store buffer, SB), Line fill buffer (Line, Fill buffer, FB ), Loop Buffer (LB), and other caches with similar functions.
  • instruction cache Instruction cache
  • ICache Instruction cache
  • Data cache Data cache
  • DCache Data cache
  • unified cache Unified cache
  • page table cache Translation Look-asideBuffer (TLB)
  • branch direction history table Branch (History Buffer (BHB)
  • Branch target history table BTB
  • Indirect branch target history buffer Indirect
  • Target buffer IBTB
  • Write buffer Store buffer, SB
  • Line fill buffer Line, Fill buffer, FB
  • Processor hardware usually sets several privilege levels, user programs usually run at the lowest privilege level, and the operating system, virtual machine manager, and security manager software run at higher privilege levels.
  • the processor provides a hardware protection mechanism for system registers and storage areas. Low-privileged software cannot access protected system registers or storage areas. Among them, the access right of the system register is generally fixed, and the access right of the storage area is usually configurable.
  • low-privileged software Under these hardware privilege protection mechanisms, low-privileged software usually cannot access system registers or memory of highly-privileged software. However, if the state of the processor cache is changed during the running of high-privileged software, and there is a correlation between the change in cache state and the data accessed by the highly-privileged software, then by detecting the change in cache state, low-privileged software can obtain To data accessed by highly privileged software. Because highly privileged software can access a lot of sensitive information, including data of all user programs, a malicious user program can steal sensitive information that it does not have access to through side-channel attacks against the cache.
  • Flush + Reload One form of side-channel attacks against caches is Flush + Reload.
  • the attack software runs at a low-privileged level, which flushes out all or part of its cache entries, and then calls certain services of the high-privileged software.
  • some sensitive data was contacted, some other new data was allocated into the cache, and there was a correlation between the newly allocated cached data and sensitive data.
  • the state of the cache will affect the execution speed of the instruction. For example, when the cache hits, the program execution speed is usually faster. By measuring the execution speed of the instruction, you can detect which data is allocated into the cache. The correlation between the values extracts sensitive data.
  • Prime + Probe Another form of side-channel attack against the cache is Prime + Probe.
  • the attack software runs at a low privilege level, which first fills all or part of the cache entry with its own data, and then calls certain services of the high privilege level software.
  • some sensitive data was contacted, and some other new data was allocated into the cache.
  • the attacker's cache entry was replaced, and between the replaced cache entry and the sensitive data Relevant.
  • the state of the cache will affect the execution speed of the instruction. For example, when the cache hits, the program execution speed is usually faster. By measuring the execution speed of the instruction, you can detect which cache items have been replaced. The correlation between the values extracts sensitive data.
  • the technical problem to be solved by the present invention is to provide a cache hardening method and device capable of resisting side channel attacks in response to the above-mentioned problems of the prior art.
  • the present invention can implement the hardening of the cache in the processor with less hardware so as to resist Side-channel attacks, which improve the security of the processor, have the advantages of simple implementation, wide application range, and low performance cost.
  • the technical solution adopted by the present invention is:
  • a buffer hardening method capable of resisting side channel attacks the implementation steps include:
  • the cache entry can only be hit if the identifier of the currently running software domain of the processor and the ALLOCATOR field in the cache entry are the same; if the processor is currently running The identifier of the software domain is different from the ALLOCATOR field in the cache entry, you cannot hit the cache entry; end and exit;
  • the identification of the software domain in step 2) specifically refers to one or a combination of a current privilege level, a virtual machine ID, a process ID, and a software domain partition ID within the process.
  • the method further includes waiting for a specified number of T clock cycles, and then using the data stored in the cache entry to change the ALLOCATOR field of the entry to the identifier of the software domain that the processor is currently running. .
  • the detailed steps of emptying the entire cache in step 4) include: if the cache adopts a fully associative organization method, directly replace the selected cache entry to be replaced; if the cache adopts a group associative organization method, it is invalidated and replaced The whole road where the line is.
  • the present invention also provides a cache hardening method capable of resisting side channel attacks.
  • the implementation steps include:
  • the access cache hardening strategy is executed: the cache entry can only be hit if the identifier of the currently running software domain of the processor and the ALLOCATOR field in the cache entry are the same; if If the identifier of the currently running software domain of the processor is different from the ALLOCATOR field in the cache entry, the cache entry cannot be hit; end and exit;
  • the replacement cache hardening strategy is performed: if the cache entry to be replaced is invalid, or its ALLOCATOR field is the same as the identifier of the software domain currently running on the processor, it can be replaced directly Go out; if the cache entry to be replaced is valid, and its ALLOCATOR field is different from the identifier of the software domain currently running on the processor, clear the entire cache; end and exit.
  • the present invention also provides a cache hardening method capable of resisting side channel attacks.
  • the implementation steps include:
  • the access cache hardening strategy is executed: the cache entry can only be hit if the identifier of the currently running software domain of the processor and the ALLOCATOR field in the cache entry are the same; if If the identifier of the currently running software domain of the processor is different from the ALLOCATOR field in the cache entry, the cache entry cannot be hit; end and exit;
  • the replacement cache hardening strategy is performed: if the cache entry to be replaced is invalid, or its ALLOCATOR field is the same as the identifier of the software domain currently running on the processor, it can be directly replaced Go out; if the cache entry to be replaced is valid, and its ALLOCATOR field is different from the identifier of the software domain currently running on the processor, clear the entire cache; end and exit.
  • the present invention also provides a cache hardening method capable of resisting side channel attacks.
  • the implementation steps include:
  • the access cache hardening strategy is performed: only when the identifier of the currently running software domain of the processor and the ALLOCATOR field in the cache entry are the same Hit the cache entry; if the identifier of the currently running software domain of the processor and the ALLOCATOR field in the cache entry are different, the cache entry cannot be hit; end and exit;
  • the replacement cache hardening strategy is executed: if the cache entry to be replaced is invalid, or its ALLOCATOR field and the identifier of the software domain currently running on the processor If they are the same, they can be replaced directly; if the cache entry to be replaced is valid and its ALLOCATOR field is different from the identifier of the software domain currently running on the processor, the entire cache is cleared; end and exit.
  • the present invention also provides a cache hardening method capable of resisting side channel attacks.
  • the implementation steps include:
  • the access cache hardening strategy is executed: only when the identifier of the currently running software domain of the processor and the ALLOCATOR field in the cache entry are the same Hit the cache entry; if the identifier of the currently running software domain of the processor and the ALLOCATOR field in the cache entry are different, the cache entry cannot be hit; end and exit;
  • the replacement cache hardening strategy is executed: if the cache entry to be replaced is invalid, or its ALLOCATOR field and the identifier of the software domain currently running on the processor If they are the same, they can be replaced directly; if the cache entry to be replaced is valid and its ALLOCATOR field is different from the identifier of the software domain currently running on the processor, the entire cache is cleared; end and exit.
  • the invention also provides a cache hardening device capable of resisting side channel attacks, which includes a microprocessor with a cache management module, and the cache management module is programmed to perform the steps of the cache hardening method of the invention which can resist side channel attacks.
  • the present invention has the following beneficial effects:
  • the present invention can prevent low-privileged software from detecting changes in the cache state of highly-privileged software, and prevent low-privileged software from changing the cache content.
  • the specific settings of IE affect the behavior of highly-privileged software, thereby preventing low-privileged software from stealing sensitive data contacted by highly-privileged software through cache side-channel attack technology.
  • the present invention only needs to add an ALLOCATOR field and related hit judgment and replacement logic in each cache entry.
  • the ALLOCATOR field usually only takes 2 to 3 bits of storage space (depending on the number of privilege levels of the instruction system), the ALLOCATOR judgment logic is only a 2 to 3 bits of equality judgment logic, and the replacement processing logic is not complicated, so the hardware implementation overhead Very small.
  • the cache hardening method proposed by the present invention can be completely implemented by hardware, and the software basically does not need any modification, and can be completely compatible with existing software.
  • the cache hardening method proposed by the present invention is applicable to various cache structures in a processor, including, but not limited to, an instruction cache, a data cache, a unified cache, a page table cache, a branch direction history table, a branch target history table, and an indirect branch target history table. , Write cache, line fill cache, circular cache, etc.
  • FIG. 1 is a schematic diagram of a prior art cache structure.
  • FIG. 2 is a schematic flowchart of a method according to a first embodiment of the present invention.
  • FIG. 3 is a schematic diagram of a reinforced cache structure according to the first embodiment of the present invention.
  • FIG. 4 is a strengthened TLB cache structure according to the first embodiment of the present invention.
  • FIG. 5 is a TLB access process after hardening according to the first embodiment of the present invention.
  • the implementation steps of the cache hardening method capable of resisting side channel attacks in this embodiment include:
  • the cache entry can only be hit if the identifier of the currently running software domain of the processor and the ALLOCATOR field in the cache entry are the same; if the processor is currently running The identifier of the software domain is different from the ALLOCATOR field in the cache entry. You cannot hit the cache entry; end and exit; as shown in Figure 5, when accessing the cache, first generate an index, access the entry corresponding to the index, and then determine whether Hit. If it hits, it is judged whether the identifier of the currently running software domain of the processor and the ALLOCATOR field in the cache entry are the same.
  • the data is returned only when they are the same and the permission check is passed, otherwise it returns a trigger exception; if the cache or processor is not hit If the identifier of the currently running software domain is different from the ALLOCATOR field in the cache entry, the cache is returned as invalid;
  • the identification of the software domain in step 2) specifically refers to one or a combination of the current privilege level, virtual machine ID, process ID, and in-process software domain partition ID.
  • the cache entry when the cache entry cannot be hit in step 3), it also includes waiting for a specified number of T clock cycles, and then using the data stored in the cache entry, changing the ALLOCATOR field of the entry to the software domain currently running by the processor.
  • T can generally take a value approximately equal to the delay of cache invalidation.
  • the detailed steps of emptying the entire cache in step 4) include: if the cache adopts a fully associative organization method, directly replace the selected cache entry to be replaced; if the cache adopts a group associative organization method, it is invalidated The entire road where the line to be replaced is located.
  • the invention can realize the reinforcement of the cache in the processor with less hardware to resist side channel attacks, improve the security of the processor, and has the advantages of simple implementation, wide application range and low performance cost.
  • this embodiment also provides a cache hardening device capable of resisting side channel attacks, which includes a microprocessor with a cache management module, and the cache management module is programmed to execute a cache hardening method capable of resisting side channel attacks in this embodiment. step.
  • This embodiment is basically the same as the first embodiment.
  • the main difference is that a unified hardware control bit SC_HARDEN_EN_G is added to control whether to execute a corresponding hardening strategy.
  • the access cache hardening strategy is executed: the cache entry can only be hit if the identifier of the currently running software domain of the processor and the ALLOCATOR field in the cache entry are the same; if If the identifier of the currently running software domain of the processor is different from the ALLOCATOR field in the cache entry, the cache entry cannot be hit; end and exit;
  • the replacement cache hardening strategy is performed: if the cache entry to be replaced is invalid, or its ALLOCATOR field is the same as the identifier of the software domain currently running on the processor, it can be replaced directly Go out; if the cache entry to be replaced is valid, and its ALLOCATOR field is different from the identifier of the software domain currently running on the processor, clear the entire cache; end and exit.
  • This embodiment is basically the same as the first embodiment.
  • the main difference is that the hardware control bit SC_HARDEN_EN_TLB corresponding to the cache is added to control whether the cache or the reclassified cache executes the corresponding hardening strategy.
  • the access cache hardening strategy is executed: the cache entry can only be hit if the identifier of the currently running software domain of the processor and the ALLOCATOR field in the cache entry are the same; if If the identifier of the currently running software domain of the processor is different from the ALLOCATOR field in the cache entry, the cache entry cannot be hit; end and exit;
  • the replacement cache hardening strategy is performed: if the cache entry to be replaced is invalid, or its ALLOCATOR field is the same as the identifier of the software domain currently running on the processor, it can be directly replaced Go out; if the cache entry to be replaced is valid, and its ALLOCATOR field is different from the identifier of the software domain currently running on the processor, clear the entire cache; end and exit.
  • Embodiment 4 is a diagrammatic representation of Embodiment 4:
  • This embodiment is basically the same as the first embodiment. The main difference is that a unified hardware control bit SC_HARDEN_EN_G and a hardware control bit SC_HARDEN_EN_TLB corresponding to the cache are added.
  • the hardware control bit SC_HARDEN_EN_TLB corresponding to the unified hardware control bit cache is used to control Whether the cache or reclassified cache implements the corresponding hardening strategy.
  • the access cache hardening strategy is performed: only when the identifier of the currently running software domain of the processor and the ALLOCATOR field in the cache entry are the same Hit the cache entry; if the identifier of the currently running software domain of the processor and the ALLOCATOR field in the cache entry are different, the cache entry cannot be hit; end and exit;
  • the replacement cache hardening strategy is executed: if the cache entry to be replaced is invalid, or its ALLOCATOR field and the identifier of the software domain currently running on the processor If they are the same, they can be replaced directly; if the cache entry to be replaced is valid and its ALLOCATOR field is different from the identifier of the software domain currently running on the processor, the entire cache is cleared; end and exit.
  • a unified control bit SC_HARDEN_EN_G and a separate control bit SC_HARDEN_EN_TLB are set at the same time, and all the caches in the entire processor are controlled by the unified control bit SC_HARDEN_EN_G.
  • the above-mentioned hardening mechanism is turned on. When the control bit is turned on, the hardening mechanism of a certain type or type of TLB in the processor is individually enabled.
  • Embodiment 5 is a diagrammatic representation of Embodiment 5:
  • This embodiment is basically the same as the fourth embodiment.
  • the main difference is that the hardware control bit SC_HARDEN_EN_TLB corresponding to the target cache in this embodiment is not controlled by the unified hardware control bit SC_HARDEN_EN_G, and the entire processor is controlled by the unified control bit SC_HARDEN_EN_G. All of the caches of the above-mentioned strengthening mechanism are enabled, and the separate control bit SC_HARDEN_EN_TLB is used to enable the strengthening mechanism of a certain TLB or a certain type of processor separately when the unified control bit is not enabled (closed).
  • the access cache hardening strategy is executed: only when the identifier of the currently running software domain of the processor and the ALLOCATOR field in the cache entry are the same Hit the cache entry; if the identifier of the currently running software domain of the processor and the ALLOCATOR field in the cache entry are different, the cache entry cannot be hit; end and exit;
  • the replacement cache hardening strategy is executed: if the cache entry to be replaced is invalid, or its ALLOCATOR field and the identifier of the software domain currently running on the processor If they are the same, they can be replaced directly; if the cache entry to be replaced is valid and its ALLOCATOR field is different from the identifier of the software domain currently running on the processor, the entire cache is cleared; end and exit.

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Abstract

本发明公开了一种可抵御边信道攻击的缓存加固方法及装置，本发明每个缓存表项中增加一个分配者标识ALLOCATOR字段；每当在缓存中分配一个表项时，将处理器的当前运行的软件域的标识填入到所分配表项的ALLOCATOR字段中；访问缓存时，只有处理器的当前运行的软件域的标识和缓存表项中的ALLOCATOR字段相同时才能命中该缓存项；替换缓存中的已有表项时，若待替换的缓存表项无效或者其ALLOCATOR字段和处理器当前运行的软件域的标识相同，则可以直接替换出去；否则将整个缓存清空。本发明能够以较少的硬件实现对处理器中缓存的加固，抵御针对缓存的边信道攻击，提高处理器的安全性。

Description

可抵御边信道攻击的缓存加固方法及装置 技术领域
本发明涉及微处理器中的缓存管理技术，具体涉及一种可抵御边信道攻击的缓存加固方法及装置。
背景技术
缓存是微处理器中大量使用的一种装置，其主要作用是保存程序执行过程中的一些常用信息，比如指令码、数据、虚实地址映射、分支方向偏向历史、分支目标地址历史等。通过将这些信息保存在微处理器芯片上的缓存中，可以降低访问它们的延迟、避免从片外获取这些信息带来的能量消耗、或者降低处理器流水线暂停时间，从而达到提高性能或降低功耗的目的。图1所示为处理器中缓存的一般结构，每一个缓存项目包括Tag、属性和数据。
本发明中涉及的缓存包括指令缓存(Instruction Cache,ICache)、数据缓存(Data Cache,DCache)、统一缓存(Unified Cache)、页表缓存(Translation Look-asideBuffer,TLB)、分支方向历史表(Branch History Buffer,BHB)、分支目标历史表(BranchTarget Buffer,BTB)、间接分支目标历史缓存(Indirect Branch Target Buffer,IBTB)、写数缓存(Store Buffer,SB)、行填充缓存(Line Fill Buffer,FB)、循环缓存(Loop Buffer,LB)、以及具有类似功能的其它缓存。
处理器中的各种缓存虽然具有提高性能、降低功耗等优点，但是存在易于受到边信道攻击的缺点。针对缓存的边信道攻击的原理是，特权软件在处理敏感信息时，处理器的缓存状态会发生改变，而这种改变和敏感信息之间通常具有很强的相关性。通过探测缓存状态的改变，即可提取出攻击者本无权访问的敏感信息。具体如下。
处理器硬件通常会设置若干特权级，用户程序通常在最低特权级下运行，操作系统、虚拟机管理器、安全管理器软件分别在更高的几个特权级下运行。处理器提供了对系统寄存器和存储区域的硬件保护机制，低特权软件无法访问受保护的系统寄存器或存储区域。其中，系统寄存器的访问权限一般是固定的，存储区域的访问权限通常是可配置的。
在这些硬件特权保护机制下，低特权软件通常无法访问高特权软件的系统寄存器或内存。然而，如果高特权软件运行过程中改变了处理器缓存的状态，并且缓存状态的改变和高特权软件所访问的数据之间存在相关性，则通过探测缓存状态的改变，低特权软件就能获取到高特权软件所访问的数据。由于高特权软件可以接触很多敏感信 息，包括所有用户程序的数据，所以通过针对缓存的边信道攻击，恶意用户程序就可以窃取其本无权访问的敏感信息。
针对缓存的边信道攻击的其中一种形式是Flush+Reload。在该攻击形式中，攻击软件运行于低特权级，其先刷空全部或部分缓存项，然后调用高特权级软件的某些服务。高特权级软件工作过程中，接触了某些敏感数据，将另外一些新数据分配进了缓存，并且新分配进缓存的数据和敏感数据之间有相关性。因为缓存的状态会影响指令的执行速度，比如缓存命中时，程序的执行速度通常会快一些，通过测量指令执行速度，即可探测哪些数据被分配进了缓存，并可根据缓存状态和敏感数据之间的相关性提取出敏感数据的值。
针对缓存的边信道攻击的另外一种形式是Prime+Probe。在该攻击形式中，攻击软件运行于低特权级，其先用自己的数据填充全部或部分缓存项，然后调用高特权级软件的某些服务。高特权级软件工作过程中，接触了某些敏感数据，将另外一些新数据分配进了缓存，分配的时候将攻击者的缓存项替换了出去，并且被替换出去的缓存项和敏感数据之间有相关性。因为缓存的状态会影响指令的执行速度，比如缓存命中时，程序的执行速度通常会快一些，通过测量指令执行速度，即可探测哪些缓存项被替换了出去，并可根据缓存状态和敏感数据之间的相关性提取出敏感数据的值。
因此，如何抵御边信道攻击的缓存加固，以有效提升微处理器及整个信息系统的安全性，已经成为一项亟待解决的关键技术问题。
发明内容
本发明要解决的技术问题：针对现有技术的上述问题，提供一种可抵御边信道攻击的缓存加固方法及装置，本发明能够以较少的硬件实现对处理器中缓存的加固以可抵御边信道攻击，提高处理器的安全性，具有实现简单、适用范围广、性能代价低的优点。
为了解决上述技术问题，本发明采用的技术方案为：
一种可抵御边信道攻击的缓存加固方法，实施步骤包括：
1)获取针对缓存的操作请求，所述缓存的表项中包含分配者标识ALLOCATOR字段；当操作请求为分配表项时，跳转执行步骤2)；当操作请求为访问表项时，跳转执行步骤3)；当操作请求为替换表项时，跳转执行步骤4)；
2)针对操作请求分配表项，且执行分配缓存加固策略：将处理器的当前运行的软件域的标识填入到所分配表项的ALLOCATOR字段中；结束并退出；
3)针对操作请求访问缓存，且执行访问缓存加固策略：只有处理器的当前运行的软件域的标识和缓存表项中的ALLOCATOR字段相同时，才能命中该缓存项；若处理器 的当前运行的软件域的标识和缓存表项中的ALLOCATOR字段不同，则不能命中该缓存表项；结束并退出；
4)针对操作请求替换缓存，且执行替换缓存加固策略：若待替换的缓存表项无效，或者其ALLOCATOR字段和处理器当前运行的软件域的标识相同，则可以直接替换出去；若待替换缓存表项有效，且其ALLOCATOR字段和处理器当前运行的软件域的标识不同，则将整个缓存清空；结束并退出。
优选地，步骤2)中的软件域的标识具体是指当前特权级、虚拟机ID、进程ID、进程内软件域分区ID中的一个或某几个的组合。
优选地，步骤3)中不能命中该缓存表项时还包括等待指定数量T个时钟周期，然后使用缓存表项中保存的数据，更改表项的ALLOCATOR字段为处理器当前运行的软件域的标识。
优选地，步骤4)中将整个缓存清空的详细步骤包括：若缓存采用全相联组织方式，则直接替换所选中的待替换缓存表项；若缓存采用组相联组织方式，则作废待替换行所在的整个路。
本发明还提供一种可抵御边信道攻击的缓存加固方法，实施步骤包括：
1)读取统一的硬件控制位SC_HARDEN_EN_G；获取针对缓存的操作请求，所述缓存的表项中包含分配者标识ALLOCATOR字段；当操作请求为分配表项时，跳转执行步骤2)；当操作请求为访问表项时，跳转执行步骤3)；当操作请求为替换表项时，跳转执行步骤4)；
2)针对操作请求分配表项，如果硬件控制位SC_HARDEN_EN_G开启则执行分配缓存加固策略：将处理器的当前运行的软件域的标识填入到所分配表项的ALLOCATOR字段中；结束并退出；
3)针对操作请求访问缓存，如果硬件控制位SC_HARDEN_EN_G开启则执行访问缓存加固策略：只有处理器的当前运行的软件域的标识和缓存表项中的ALLOCATOR字段相同时，才能命中该缓存项；若处理器的当前运行的软件域的标识和缓存表项中的ALLOCATOR字段不同，则不能命中该缓存表项；结束并退出；
4)针对操作请求替换缓存，如果硬件控制位SC_HARDEN_EN_G开启则执行替换缓存加固策略：若待替换的缓存表项无效，或者其ALLOCATOR字段和处理器当前运行的软件域的标识相同，则可以直接替换出去；若待替换缓存表项有效，且其ALLOCATOR字段和处理器当前运行的软件域的标识不同，则将整个缓存清空；结束并退出。
本发明还提供一种可抵御边信道攻击的缓存加固方法，实施步骤包括：
1)获取针对缓存的操作请求，读取当前操作请求的目标缓存所对应的硬件控制位SC_HARDEN_EN_TLB，所述缓存的表项中包含分配者标识ALLOCATOR字段；当操作请求为分配表项时，跳转执行步骤2)；当操作请求为访问表项时，跳转执行步骤3)；当操作请求为替换表项时，跳转执行步骤4)；
2)针对操作请求分配表项，如果硬件控制位SC_HARDEN_EN_TLB开启则执行分配缓存加固策略：将处理器的当前运行的软件域的标识填入到所分配表项的ALLOCATOR字段中；结束并退出；
3)针对操作请求访问缓存，如果硬件控制位SC_HARDEN_EN_TLB开启则执行访问缓存加固策略：只有处理器的当前运行的软件域的标识和缓存表项中的ALLOCATOR字段相同时，才能命中该缓存项；若处理器的当前运行的软件域的标识和缓存表项中的ALLOCATOR字段不同，则不能命中该缓存表项；结束并退出；
4)针对操作请求替换缓存，如果硬件控制位SC_HARDEN_EN_TLB开启则执行替换缓存加固策略：若待替换的缓存表项无效，或者其ALLOCATOR字段和处理器当前运行的软件域的标识相同，则可以直接替换出去；若待替换缓存表项有效，且其ALLOCATOR字段和处理器当前运行的软件域的标识不同，则将整个缓存清空；结束并退出。
本发明还提供一种可抵御边信道攻击的缓存加固方法，实施步骤包括：
1)读取统一的硬件控制位SC_HARDEN_EN_G；获取针对缓存的操作请求，读取当前操作请求的目标缓存所对应的硬件控制位SC_HARDEN_EN_TLB，所述缓存的表项中包含分配者标识ALLOCATOR字段；当操作请求为分配表项时，跳转执行步骤2)；当操作请求为访问表项时，跳转执行步骤3)；当操作请求为替换表项时，跳转执行步骤4)；
2)针对操作请求分配表项，如果硬件控制位SC_HARDEN_EN_G开启且硬件控制位SC_HARDEN_EN_TLB开启则执行分配缓存加固策略：将处理器的当前运行的软件域的标识填入到所分配表项的ALLOCATOR字段中；结束并退出；
3)针对操作请求访问缓存，如果硬件控制位SC_HARDEN_EN_G开启且硬件控制位SC_HARDEN_EN_TLB开启则执行访问缓存加固策略：只有处理器的当前运行的软件域的标识和缓存表项中的ALLOCATOR字段相同时，才能命中该缓存项；若处理器的当前运行的软件域的标识和缓存表项中的ALLOCATOR字段不同，则不能命中该缓存表项；结束并退出；
4)针对操作请求替换缓存，如果硬件控制位SC_HARDEN_EN_G开启且硬件控制位SC_HARDEN_EN_TLB开启则执行替换缓存加固策略：若待替换的缓存表项无效，或者其ALLOCATOR字段和处理器当前运行的软件域的标识相同，则可以直接替换出去；若待替 换缓存表项有效，且其ALLOCATOR字段和处理器当前运行的软件域的标识不同，则将整个缓存清空；结束并退出。
本发明还提供一种可抵御边信道攻击的缓存加固方法，实施步骤包括：
1)读取统一的硬件控制位SC_HARDEN_EN_G；获取针对缓存的操作请求，读取当前操作请求的目标缓存所对应的硬件控制位SC_HARDEN_EN_TLB，所述缓存的表项中包含分配者标识ALLOCATOR字段；当操作请求为分配表项时，跳转执行步骤2)；当操作请求为访问表项时，跳转执行步骤3)；当操作请求为替换表项时，跳转执行步骤4)；
2)针对操作请求分配表项，如果硬件控制位SC_HARDEN_EN_G关闭且硬件控制位SC_HARDEN_EN_TLB开启则执行分配缓存加固策略：将处理器的当前运行的软件域的标识填入到所分配表项的ALLOCATOR字段中；结束并退出；
3)针对操作请求访问缓存，如果硬件控制位SC_HARDEN_EN_G关闭且硬件控制位SC_HARDEN_EN_TLB开启则执行访问缓存加固策略：只有处理器的当前运行的软件域的标识和缓存表项中的ALLOCATOR字段相同时，才能命中该缓存项；若处理器的当前运行的软件域的标识和缓存表项中的ALLOCATOR字段不同，则不能命中该缓存表项；结束并退出；
4)针对操作请求替换缓存，如果硬件控制位SC_HARDEN_EN_G关闭且硬件控制位SC_HARDEN_EN_TLB开启则执行替换缓存加固策略：若待替换的缓存表项无效，或者其ALLOCATOR字段和处理器当前运行的软件域的标识相同，则可以直接替换出去；若待替换缓存表项有效，且其ALLOCATOR字段和处理器当前运行的软件域的标识不同，则将整个缓存清空；结束并退出。
本发明还提供一种可抵御边信道攻击的缓存加固装置，包括带有缓存管理模块的微处理器，缓存管理模块被编程以执行本发明可抵御边信道攻击的缓存加固方法的步骤。
和现有技术相比，本发明具有下述有益效果：
1.通过在缓存表项中增加ALLOCATOR字段，标识分配该表项时处理器的特权级，本发明可以避免低特权软件探测高特权软件对缓存状态的改变，并避免低特权软件通过对缓存内容的特定设置影响高特权软件的行为，从而避免低特权软件通过缓存边信道攻击技术窃取高特权软件所接触的敏感数据。
2.硬件开销小。本发明仅需要在每个缓存表项中增加一个ALLOCATOR字段及相关的命中判断和替换逻辑。ALLOCATOR字段通常仅占用2～3位存储空间(取决于指令系统的特权级数量)，ALLOCATOR判断逻辑也仅仅是一个2～3位的相等判断逻辑，替换处理逻辑也并不复杂，因此硬件实现开销很小。
3.性能代价低。本发明提出的方法仅仅在查找缓存时增加一个2～3位数的比较，替换逻辑不在关键路径上，因此对时序的影响非常小。此外，由于不需要在切换特权级时清空缓存，仅仅避免在不同特权级之间共享缓存表项，因此性能代价相比软件方法而言很低。
4.兼容性好。本发明提出的缓存加固方法可完全由硬件实现，软件基本无需任何改动，可以完整兼容现有软件。
5.适用范围广。本发明提出的缓存加固方法适用于处理器中的多种缓存结构，包括但不限于指令缓存、数据缓存、统一缓存、页表缓存、分支方向历史表、分支目标历史表、间接分支目标历史表、写数缓存、行填充缓存、循环缓存等。
附图说明
图1为现有技术的缓存结构示意。
图2为本发明实施例一方法的基本流程示意图。
图3为本发明实施例一加固后的缓存结构示意。
图4为本发明实施例一加固后的TLB缓存结构。
图5为本发明实施例一加固后的TLB的访问流程。
具体实施方式
如图2所示，本实施例可抵御边信道攻击的缓存加固方法的实施步骤包括：
1)获取针对缓存的操作请求，所述缓存的表项中包含分配者标识ALLOCATOR字段，如图3和图4所示；当操作请求为分配表项时，跳转执行步骤2)；当操作请求为访问表项时，跳转执行步骤3)；当操作请求为替换表项时，跳转执行步骤4)；
2)针对操作请求分配表项，且执行分配缓存加固策略：将处理器的当前运行的软件域的标识填入到所分配表项的ALLOCATOR字段中；结束并退出；
3)针对操作请求访问缓存，且执行访问缓存加固策略：只有处理器的当前运行的软件域的标识和缓存表项中的ALLOCATOR字段相同时，才能命中该缓存项；若处理器的当前运行的软件域的标识和缓存表项中的ALLOCATOR字段不同，则不能命中该缓存表项；结束并退出；如图5所示，访问缓存时，首先生成索引、访问索引对应的表项，然后判断是否命中，如果命中则判断处理器的当前运行的软件域的标识和缓存表项中的ALLOCATOR字段是否相同，仅仅在相同且权限检查通过才返回数据，否则返回触发异常；如果未命中缓存或者处理器的当前运行的软件域的标识和缓存表项中的ALLOCATOR字段不同，则返回缓存失效；
4)针对操作请求替换缓存，且执行替换缓存加固策略：若待替换的缓存表项无效，或者其ALLOCATOR字段和处理器当前运行的软件域的标识相同，则可以直接替换出去； 若待替换缓存表项有效，且其ALLOCATOR字段和处理器当前运行的软件域的标识不同，则将整个缓存清空；结束并退出。
本实施例中，步骤2)中的软件域的标识具体是指当前特权级、虚拟机ID、进程ID、进程内软件域分区ID中的一个或某几个的组合。
本实施例中，步骤3)中不能命中该缓存表项时还包括等待指定数量T个时钟周期，然后使用缓存表项中保存的数据，更改表项的ALLOCATOR字段为处理器当前运行的软件域的标识，其中T一般可取值为约等于缓存失效的延迟。
本实施例中，步骤4)中将整个缓存清空的详细步骤包括：若缓存采用全相联组织方式，则直接替换所选中的待替换缓存表项；若缓存采用组相联组织方式，则作废待替换行所在的整个路。
本发明能够以较少的硬件实现对处理器中缓存的加固以可抵御边信道攻击，提高处理器的安全性，具有实现简单、适用范围广、性能代价低的优点。此外，本实施例还提供一种可抵御边信道攻击的缓存加固装置，包括带有缓存管理模块的微处理器，缓存管理模块被编程以执行本实施例可抵御边信道攻击的缓存加固方法的步骤。
实施例二：
本实施例与实施例一基本相同，其主要不同点为增加了统一的硬件控制位SC_HARDEN_EN_G，用于控制是否执行相应的加固策略。
本实施例可抵御边信道攻击的缓存加固方法的实施步骤包括：
1)读取统一的硬件控制位SC_HARDEN_EN_G；获取针对缓存的操作请求，所述缓存的表项中包含分配者标识ALLOCATOR字段；当操作请求为分配表项时，跳转执行步骤2)；当操作请求为访问表项时，跳转执行步骤3)；当操作请求为替换表项时，跳转执行步骤4)；
2)针对操作请求分配表项，如果硬件控制位SC_HARDEN_EN_G开启则执行分配缓存加固策略：将处理器的当前运行的软件域的标识填入到所分配表项的ALLOCATOR字段中；结束并退出；
3)针对操作请求访问缓存，如果硬件控制位SC_HARDEN_EN_G开启则执行访问缓存加固策略：只有处理器的当前运行的软件域的标识和缓存表项中的ALLOCATOR字段相同时，才能命中该缓存项；若处理器的当前运行的软件域的标识和缓存表项中的ALLOCATOR字段不同，则不能命中该缓存表项；结束并退出；
4)针对操作请求替换缓存，如果硬件控制位SC_HARDEN_EN_G开启则执行替换缓存加固策略：若待替换的缓存表项无效，或者其ALLOCATOR字段和处理器当前运行的 软件域的标识相同，则可以直接替换出去；若待替换缓存表项有效，且其ALLOCATOR字段和处理器当前运行的软件域的标识不同，则将整个缓存清空；结束并退出。
实施例三：
本实施例与实施例一基本相同，其主要不同点为增加了缓存所对应的硬件控制位SC_HARDEN_EN_TLB，用于控制该缓存或者改类缓存是否执行相应的加固策略。
本实施例可抵御边信道攻击的缓存加固方法的实施步骤包括：
1)获取针对缓存的操作请求，读取当前操作请求的目标缓存所对应的硬件控制位SC_HARDEN_EN_TLB，所述缓存的表项中包含分配者标识ALLOCATOR字段；当操作请求为分配表项时，跳转执行步骤2)；当操作请求为访问表项时，跳转执行步骤3)；当操作请求为替换表项时，跳转执行步骤4)；
2)针对操作请求分配表项，如果硬件控制位SC_HARDEN_EN_TLB开启则执行分配缓存加固策略：将处理器的当前运行的软件域的标识填入到所分配表项的ALLOCATOR字段中；结束并退出；
3)针对操作请求访问缓存，如果硬件控制位SC_HARDEN_EN_TLB开启则执行访问缓存加固策略：只有处理器的当前运行的软件域的标识和缓存表项中的ALLOCATOR字段相同时，才能命中该缓存项；若处理器的当前运行的软件域的标识和缓存表项中的ALLOCATOR字段不同，则不能命中该缓存表项；结束并退出；
4)针对操作请求替换缓存，如果硬件控制位SC_HARDEN_EN_TLB开启则执行替换缓存加固策略：若待替换的缓存表项无效，或者其ALLOCATOR字段和处理器当前运行的软件域的标识相同，则可以直接替换出去；若待替换缓存表项有效，且其ALLOCATOR字段和处理器当前运行的软件域的标识不同，则将整个缓存清空；结束并退出。
实施例四：
本实施例与实施例一基本相同，其主要不同点为增加了统一的硬件控制位SC_HARDEN_EN_G和缓存所对应的硬件控制位SC_HARDEN_EN_TLB，统一的硬件控制位缓存所对应的硬件控制位SC_HARDEN_EN_TLB用于控制该缓存或者改类缓存是否执行相应的加固策略。
本实施例可抵御边信道攻击的缓存加固方法的实施步骤包括：
1)读取统一的硬件控制位SC_HARDEN_EN_G；获取针对缓存的操作请求，读取当前操作请求的目标缓存所对应的硬件控制位SC_HARDEN_EN_TLB，所述缓存的表项中包含分配者标识ALLOCATOR字段；当操作请求为分配表项时，跳转执行步骤2)；当操作请求为访问表项时，跳转执行步骤3)；当操作请求为替换表项时，跳转执行步骤4)；
2)针对操作请求分配表项，如果硬件控制位SC_HARDEN_EN_G开启且硬件控制位SC_HARDEN_EN_TLB开启则执行分配缓存加固策略：将处理器的当前运行的软件域的标识填入到所分配表项的ALLOCATOR字段中；结束并退出；
3)针对操作请求访问缓存，如果硬件控制位SC_HARDEN_EN_G开启且硬件控制位SC_HARDEN_EN_TLB开启则执行访问缓存加固策略：只有处理器的当前运行的软件域的标识和缓存表项中的ALLOCATOR字段相同时，才能命中该缓存项；若处理器的当前运行的软件域的标识和缓存表项中的ALLOCATOR字段不同，则不能命中该缓存表项；结束并退出；
4)针对操作请求替换缓存，如果硬件控制位SC_HARDEN_EN_G开启且硬件控制位SC_HARDEN_EN_TLB开启则执行替换缓存加固策略：若待替换的缓存表项无效，或者其ALLOCATOR字段和处理器当前运行的软件域的标识相同，则可以直接替换出去；若待替换缓存表项有效，且其ALLOCATOR字段和处理器当前运行的软件域的标识不同，则将整个缓存清空；结束并退出。
本实施例中同时设置一个统一的控制位SC_HARDEN_EN_G和一个单独的控制位SC_HARDEN_EN_TLB，通过统一的控制位SC_HARDEN_EN_G控制整个处理器中的所有缓存全部开启上述加固机制，通过单独的控制位SC_HARDEN_EN_TLB用于在统一控制位开启时，单独的开启处理器中的某个或某类TLB的加固机制。
实施例五：
本实施例与实施例四基本相同，其主要区别点为本实施例中目标缓存所对应的硬件控制位SC_HARDEN_EN_TLB不受统一的硬件控制位SC_HARDEN_EN_G的控制，通过统一的控制位SC_HARDEN_EN_G控制整个处理器中的所有缓存全部开启上述加固机制，通过单独的控制位SC_HARDEN_EN_TLB用于在统一控制位未开启(关闭)时，单独的开启处理器中的某个或某类TLB的加固机制。
本实施例可抵御边信道攻击的缓存加固方法的实施步骤包括：
1)读取统一的硬件控制位SC_HARDEN_EN_G；获取针对缓存的操作请求，读取当前操作请求的目标缓存所对应的硬件控制位SC_HARDEN_EN_TLB，所述缓存的表项中包含分配者标识ALLOCATOR字段；当操作请求为分配表项时，跳转执行步骤2)；当操作请求为访问表项时，跳转执行步骤3)；当操作请求为替换表项时，跳转执行步骤4)；
2)针对操作请求分配表项，如果硬件控制位SC_HARDEN_EN_G关闭且硬件控制位SC_HARDEN_EN_TLB开启则执行分配缓存加固策略：将处理器的当前运行的软件域的标识填入到所分配表项的ALLOCATOR字段中；结束并退出；
3)针对操作请求访问缓存，如果硬件控制位SC_HARDEN_EN_G关闭且硬件控制位SC_HARDEN_EN_TLB开启则执行访问缓存加固策略：只有处理器的当前运行的软件域的标识和缓存表项中的ALLOCATOR字段相同时，才能命中该缓存项；若处理器的当前运行的软件域的标识和缓存表项中的ALLOCATOR字段不同，则不能命中该缓存表项；结束并退出；
4)针对操作请求替换缓存，如果硬件控制位SC_HARDEN_EN_G关闭且硬件控制位SC_HARDEN_EN_TLB开启则执行替换缓存加固策略：若待替换的缓存表项无效，或者其ALLOCATOR字段和处理器当前运行的软件域的标识相同，则可以直接替换出去；若待替换缓存表项有效，且其ALLOCATOR字段和处理器当前运行的软件域的标识不同，则将整个缓存清空；结束并退出。
以上所述仅是本发明的优选实施方式，本发明的保护范围并不仅局限于上述实施例，凡属于本发明思路下的技术方案均属于本发明的保护范围。应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明原理前提下的若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (9)

  1. 一种可抵御边信道攻击的缓存加固方法，其特征在于实施步骤包括：
    1)获取针对缓存的操作请求，所述缓存的表项中包含分配者标识ALLOCATOR字段；当操作请求为分配表项时，跳转执行步骤2)；当操作请求为访问表项时，跳转执行步骤3)；当操作请求为替换表项时，跳转执行步骤4)；
    2)针对操作请求分配表项，且执行分配缓存加固策略：将处理器的当前运行的软件域的标识填入到所分配表项的ALLOCATOR字段中；结束并退出；
    3)针对操作请求访问缓存，且执行访问缓存加固策略：只有处理器的当前运行的软件域的标识和缓存表项中的ALLOCATOR字段相同时，才能命中该缓存项；若处理器的当前运行的软件域的标识和缓存表项中的ALLOCATOR字段不同，则不能命中该缓存表项；结束并退出；
    4)针对操作请求替换缓存，且执行替换缓存加固策略：若待替换的缓存表项无效，或者其ALLOCATOR字段和处理器当前运行的软件域的标识相同，则可以直接替换出去；若待替换缓存表项有效，且其ALLOCATOR字段和处理器当前运行的软件域的标识不同，则将整个缓存清空；结束并退出。
  2. 根据权利要求1所述的可抵御边信道攻击的缓存加固方法，其特征在于：步骤2)中的软件域的标识具体是指当前特权级、虚拟机ID、进程ID、进程内软件域分区ID中的一个或某几个的组合。
  3. 根据权利要求1所述的可抵御边信道攻击的缓存加固方法，其特征在于：步骤3)中不能命中该缓存表项时还包括等待指定数量T个时钟周期，然后使用缓存表项中保存的数据，更改表项的ALLOCATOR字段为处理器当前运行的软件域的标识。
  4. 根据权利要求1所述的可抵御边信道攻击的缓存加固方法，其特征在于：步骤4)中将整个缓存清空的详细步骤包括：若缓存采用全相联组织方式，则直接替换所选中的待替换缓存表项；若缓存采用组相联组织方式，则作废待替换行所在的整个路。
  5. 一种可抵御边信道攻击的缓存加固方法，其特征在于实施步骤包括：
    1)读取统一的硬件控制位SC_HARDEN_EN_G；获取针对缓存的操作请求，所述缓存的表项中包含分配者标识ALLOCATOR字段；当操作请求为分配表项时，跳转执行步2)；当操作请求为访问表项时，跳转执行步骤3)；当操作请求为替换表项时，跳转执行步骤4)；
    2)针对操作请求分配表项，如果硬件控制位SC_HARDEN_EN_G开启则执行分配缓存加固策略：将处理器的当前运行的软件域的标识填入到所分配表项的ALLOCATOR字段中；结束并退出；
    3)针对操作请求访问缓存，如果硬件控制位SC_HARDEN_EN_G开启则执行访问缓存加固策略：只有处理器的当前运行的软件域的标识和缓存表项中的ALLOCATOR字段相同时，才能命中该缓存项；若处理器的当前运行的软件域的标识和缓存表项中的ALLOCATOR字段不同，则不能命中该缓存表项；结束并退出；
    4)针对操作请求替换缓存，如果硬件控制位SC_HARDEN_EN_G开启则执行替换缓存加固策略：若待替换的缓存表项无效，或者其ALLOCATOR字段和处理器当前运行的软件域的标识相同，则可以直接替换出去；若待替换缓存表项有效，且其ALLOCATOR字段和处理器当前运行的软件域的标识不同，则将整个缓存清空；结束并退出。
  6. 一种可抵御边信道攻击的缓存加固方法，其特征在于实施步骤包括：
    1)获取针对缓存的操作请求，读取当前操作请求的目标缓存所对应的硬件控制位SC_HARDEN_EN_TLB，所述缓存的表项中包含分配者标识ALLOCATOR字段；当操作请求为分配表项时，跳转执行步骤2)；当操作请求为访问表项时，跳转执行步骤3)；当操作请求为替换表项时，跳转执行步骤4)；
    2)针对操作请求分配表项，如果硬件控制位SC_HARDEN_EN_TLB开启则执行分配缓存加固策略：将处理器的当前运行的软件域的标识填入到所分配表项的ALLOCATOR字段中；结束并退出；
    3)针对操作请求访问缓存，如果硬件控制位SC_HARDEN_EN_TLB开启则执行访问缓存加固策略：只有处理器的当前运行的软件域的标识和缓存表项中的ALLOCATOR字段相同时，才能命中该缓存项；若处理器的当前运行的软件域的标识和缓存表项中的ALLOCATOR字段不同，则不能命中该缓存表项；结束并退出；
    4)针对操作请求替换缓存，如果硬件控制位SC_HARDEN_EN_TLB开启则执行替换缓存加固策略：若待替换的缓存表项无效，或者其ALLOCATOR字段和处理器当前运行的软件域的标识相同，则可以直接替换出去；若待替换缓存表项有效，且其ALLOCATOR字段和处理器当前运行的软件域的标识不同，则将整个缓存清空；结束并退出。
  7. 一种可抵御边信道攻击的缓存加固方法，其特征在于实施步骤包括：
    1)读取统一的硬件控制位SC_HARDEN_EN_G；获取针对缓存的操作请求，读取当前操作请求的目标缓存所对应的硬件控制位SC_HARDEN_EN_TLB，所述缓存的表项中包含分配者标识ALLOCATOR字段；当操作请求为分配表项时，跳转执行步骤2)；当操作请求为访问表项时，跳转执行步骤3)；当操作请求为替换表项时，跳转执行步骤4)；
    2)针对操作请求分配表项，如果硬件控制位SC_HARDEN_EN_G开启且硬件控制位SC_HARDEN_EN_TLB开启则执行分配缓存加固策略：将处理器的当前运行的软件域的标识填入到所分配表项的ALLOCATOR字段中；结束并退出；
    3)针对操作请求访问缓存，如果硬件控制位SC_HARDEN_EN_G开启且硬件控制位SC_HARDEN_EN_TLB开启则执行访问缓存加固策略：只有处理器的当前运行的软件域的标识和缓存表项中的ALLOCATOR字段相同时，才能命中该缓存项；若处理器的当前运行的软件域的标识和缓存表项中的ALLOCATOR字段不同，则不能命中该缓存表项；结束并退出；
    4)针对操作请求替换缓存，如果硬件控制位SC_HARDEN_EN_G开启且硬件控制位SC_HARDEN_EN_TLB开启则执行替换缓存加固策略：若待替换的缓存表项无效，或者其ALLOCATOR字段和处理器当前运行的软件域的标识相同，则可以直接替换出去；若待替换缓存表项有效，且其ALLOCATOR字段和处理器当前运行的软件域的标识不同，则将整个缓存清空；结束并退出。
  8. 一种可抵御边信道攻击的缓存加固方法，其特征在于实施步骤包括：
    1)读取统一的硬件控制位SC_HARDEN_EN_G；获取针对缓存的操作请求，读取当前操作请求的目标缓存所对应的硬件控制位SC_HARDEN_EN_TLB，所述缓存的表项中包含分配者标识ALLOCATOR字段；当操作请求为分配表项时，跳转执行步骤2)；当操作请求为访问表项时，跳转执行步骤3)；当操作请求为替换表项时，跳转执行步骤4)；
    2)针对操作请求分配表项，如果硬件控制位SC_HARDEN_EN_G关闭且硬件控制位SC_HARDEN_EN_TLB开启则执行分配缓存加固策略：将处理器的当前运行的软件域的标识填入到所分配表项的ALLOCATOR字段中；结束并退出；
    3)针对操作请求访问缓存，如果硬件控制位SC_HARDEN_EN_G关闭且硬件控制位SC_HARDEN_EN_TLB开启则执行访问缓存加固策略：只有处理器的当前运行的软件域的标识和缓存表项中的ALLOCATOR字段相同时，才能命中该缓存项；若处理器的当前运行的软件域的标识和缓存表项中的ALLOCATOR字段不同，则不能命中该缓存表项；结束并退出；
    4)针对操作请求替换缓存，如果硬件控制位SC_HARDEN_EN_G关闭且硬件控制位SC_HARDEN_EN_TLB开启则执行替换缓存加固策略：若待替换的缓存表项无效，或者其ALLOCATOR字段和处理器当前运行的软件域的标识相同，则可以直接替换出去；若待替换缓存表项有效，且其ALLOCATOR字段和处理器当前运行的软件域的标识不同，则将整个缓存清空；结束并退出。
  9. 一种可抵御边信道攻击的缓存加固装置，包括带有缓存管理模块的微处理器，其特征在于，所述缓存管理模块被编程以执行权利要求1～8中任意一项所述可抵御边信道攻击的缓存加固方法的步骤。
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Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109033826B (zh) 2018-06-26 2019-06-28 天津飞腾信息技术有限公司 可抵御边信道攻击的缓存加固方法及装置
CN110059482A (zh) * 2019-04-26 2019-07-26 海光信息技术有限公司 独占缓存空间单元的独占更新方法及相关装置
CN110889147B (zh) * 2019-11-14 2022-02-08 中国人民解放军国防科技大学 一种利用填充缓存抵御Cache边信道攻击的方法
CN111289890A (zh) * 2020-02-27 2020-06-16 致能装备科技(集团)有限公司 一种基于边信道的dtu安全监测方法
CN113449344B (zh) * 2020-03-27 2023-03-17 支付宝(杭州)信息技术有限公司 一种安全计算方法、装置、设备及介质
US11630771B2 (en) 2021-07-13 2023-04-18 Apple Inc. Poison mechanisms for deferred invalidates

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1870627A (zh) * 2005-08-09 2006-11-29 华为技术有限公司 Arp缓存表防攻击方法
US20150373036A1 (en) * 2014-06-24 2015-12-24 Qualcomm Incorporated Methods and Systems for Side Channel Analysis Detection and Protection
CN105550574A (zh) * 2015-12-11 2016-05-04 南京大学 基于内存活动的边信道攻击取证系统及方法
CN106878247A (zh) * 2016-08-11 2017-06-20 阿里巴巴集团控股有限公司 一种攻击识别方法和装置
CN109033826A (zh) * 2018-06-26 2018-12-18 天津飞腾信息技术有限公司 可抵御边信道攻击的缓存加固方法及装置

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6715036B1 (en) * 2000-08-01 2004-03-30 International Business Machines Corporation Method, system, and data structures for transferring blocks of data from a storage device to a requesting application
US7958320B2 (en) * 2006-12-05 2011-06-07 Intel Corporation Protected cache architecture and secure programming paradigm to protect applications
US9448942B2 (en) * 2012-08-20 2016-09-20 Freescale Semiconductor, Inc. Random access of a cache portion using an access module
US9311251B2 (en) * 2012-08-27 2016-04-12 Apple Inc. System cache with sticky allocation
CN103118148B (zh) * 2013-01-31 2016-06-08 杭州华三通信技术有限公司 一种arp缓存更新方法和设备
KR101807441B1 (ko) * 2013-12-04 2017-12-08 엠파이어 테크놀로지 디벨롭먼트 엘엘씨 가상 머신들 간의 사이드 채널 공격들의 검출
US9703951B2 (en) * 2014-09-30 2017-07-11 Amazon Technologies, Inc. Allocation of shared system resources
US9961104B2 (en) * 2014-12-02 2018-05-01 Empire Technology Development Llc Side channel attack deterrence in networks
KR102028096B1 (ko) * 2017-04-18 2019-10-02 한국전자통신연구원 하이퍼바이저 기반의 가상 머신 격리 장치 및 방법

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1870627A (zh) * 2005-08-09 2006-11-29 华为技术有限公司 Arp缓存表防攻击方法
US20150373036A1 (en) * 2014-06-24 2015-12-24 Qualcomm Incorporated Methods and Systems for Side Channel Analysis Detection and Protection
CN105550574A (zh) * 2015-12-11 2016-05-04 南京大学 基于内存活动的边信道攻击取证系统及方法
CN106878247A (zh) * 2016-08-11 2017-06-20 阿里巴巴集团控股有限公司 一种攻击识别方法和装置
CN109033826A (zh) * 2018-06-26 2018-12-18 天津飞腾信息技术有限公司 可抵御边信道攻击的缓存加固方法及装置

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