WO2019244350A1 - Display device and method for manufacturing same - Google Patents
Display device and method for manufacturing same Download PDFInfo
- Publication number
- WO2019244350A1 WO2019244350A1 PCT/JP2018/023848 JP2018023848W WO2019244350A1 WO 2019244350 A1 WO2019244350 A1 WO 2019244350A1 JP 2018023848 W JP2018023848 W JP 2018023848W WO 2019244350 A1 WO2019244350 A1 WO 2019244350A1
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- WO
- WIPO (PCT)
- Prior art keywords
- display device
- electrode
- openings
- layer
- organic
- Prior art date
Links
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Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/80—Constructional details
- H10K59/87—Passivation; Containers; Encapsulations
- H10K59/871—Self-supporting sealing arrangements
- H10K59/8723—Vertical spacers, e.g. arranged between the sealing arrangement and the OLED
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
- H05B33/00—Electroluminescent light sources
- H05B33/02—Details
- H05B33/06—Electrode terminals
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
- H05B33/00—Electroluminescent light sources
- H05B33/12—Light sources with substantially two-dimensional radiating surfaces
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
- H05B33/00—Electroluminescent light sources
- H05B33/12—Light sources with substantially two-dimensional radiating surfaces
- H05B33/22—Light sources with substantially two-dimensional radiating surfaces characterised by the chemical or physical composition or the arrangement of auxiliary dielectric or reflective layers
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
- H05B33/00—Electroluminescent light sources
- H05B33/12—Light sources with substantially two-dimensional radiating surfaces
- H05B33/26—Light sources with substantially two-dimensional radiating surfaces characterised by the composition or arrangement of the conductive material used as an electrode
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/80—Constructional details
- H10K59/805—Electrodes
- H10K59/8051—Anodes
Definitions
- the present invention relates to a display device and a method for manufacturing the same.
- the organic EL element includes, for example, a plurality of first electrodes provided in a matrix in a display area, an edge cover provided in a grid shape so as to cover a peripheral end of each first electrode, and an edge cover.
- An organic EL layer provided on each of the first electrodes exposed from above, and a second electrode provided to cover each of the organic EL layers.
- the organic EL layer includes, for example, a hole injecting layer, a hole transporting layer, a light emitting layer, an electron transporting layer, and an electron injecting layer.
- Patent Literature 1 discloses a display device and a manufacturing method thereof, in which an installation area of a deposition mask support at a central portion of a display area is larger than an installation area of an evaporation mask support at an edge of the display area. Have been.
- a display area is required. May be lower than the columnar spacers formed in the display area. In this case, particles are likely to be generated from the columnar spacers formed in the display area due to contact with the deposition mask to be placed, and there is room for improvement.
- the present invention has been made in view of such a point, and an object of the present invention is to make the contact between a deposition mask and a columnar spacer uniform to suppress generation of particles.
- a display device includes a base substrate, a TFT layer provided on the base substrate, a light emitting element provided on the TFT layer and forming a display region, A frame region provided around a display region, wherein the light-emitting element includes a plurality of first electrodes provided on the TFT layer and a plurality of first electrodes covering a peripheral end of each of the first electrodes.
- An edge cover provided in a lattice shape having one opening, a plurality of light emitting element layers provided on each of the first electrodes exposed from each of the first openings of the edge cover, and each of the light emitting elements
- a second electrode provided so as to cover a layer, wherein the edge cover is provided so as to protrude from the plurality of first openings to a surface opposite to the base substrate in the display area.
- a plurality of first columnar spacers In the display device, in the frame region, peripheral electrodes are provided on the TFT layer in the same layer as the first electrodes using the same material, and the edge cover is provided in the frame region in the frame region.
- a plurality of second openings formed in the same shape and at the same pitch as the one opening, and a plurality of second openings provided between the plurality of second openings so as to protrude to a surface opposite to the base substrate; And a two-column spacer.
- the edge cover includes a plurality of first openings exposing each of the first electrodes in the display area, and a plurality of first columnar spacers protruding from a surface opposite to the base substrate.
- the region includes a plurality of second openings having the same shape and the same pitch as the plurality of first openings, and a plurality of second columnar spacers protruding from the surface on the side opposite to the base substrate. The contact with the columnar spacers can be made uniform and the generation of particles can be suppressed.
- FIG. 1 is a plan view showing a schematic configuration of the organic EL display device according to the first embodiment of the present invention.
- FIG. 2 is a plan view of a display area of the organic EL display device according to the first embodiment of the present invention.
- FIG. 3 is a cross-sectional view of the display area of the organic EL display device along the line III-III in FIG.
- FIG. 4 is an equivalent circuit diagram of a TFT layer included in the organic EL display device according to the first embodiment of the present invention.
- FIG. 5 is a sectional view of an organic EL layer included in the organic EL display device according to the first embodiment of the present invention.
- FIG. 6 is a cross-sectional view of the frame region of the organic EL display device along the line VI-VI in FIG. FIG.
- FIG. 7 is a cross-sectional view of the frame region of the organic EL display device along the line VII-VII in FIG.
- FIG. 8 is a plan view of an edge cover included in the organic EL display device according to the first embodiment of the present invention.
- FIG. 9 is a plan view of a modification of the edge cover and the peripheral electrodes constituting the organic EL display device according to the first embodiment of the present invention.
- FIG. 10 is a cross-sectional view illustrating a first electrode forming step of a light emitting element forming step in the method for manufacturing an organic EL display device according to the first embodiment of the present invention.
- FIG. 11 is a cross-sectional view illustrating an edge cover forming step of the light emitting element forming step in the method for manufacturing the organic EL display device according to the first embodiment of the present invention.
- FIG. 12 is a cross-sectional view showing a light emitting element layer forming step of the light emitting element forming step in the method for manufacturing the organic EL display device according to the first embodiment of the present invention.
- FIG. 1 is a plan view showing a schematic configuration of the organic EL display device 50 of the present embodiment.
- FIG. 2 is a plan view of a display area D of the organic EL display device 50.
- FIG. 3 is a cross-sectional view of the display area D of the organic EL display device 50 along the line III-III in FIG.
- FIG. 4 is an equivalent circuit diagram of the TFT layer 20 included in the organic EL display device 50.
- FIG. 5 is a sectional view of the organic EL layer 23 constituting the organic EL display device 50.
- 6 and 7 are cross-sectional views of the frame region F of the organic EL display device 50 taken along lines VI-VI and VII-VII in FIG.
- FIG. 8 is a plan view of an edge cover 22a included in the organic EL display device 50.
- the organic EL display device 50 includes, for example, a rectangular display area D for displaying an image, and a frame area F provided around the display area D.
- a plurality of sub-pixels P are arranged in a matrix as shown in FIG.
- a sub-pixel P having a red light-emitting area Lr for performing red display a sub-pixel P having a green light-emitting area Lg for performing green display
- a sub-pixel P having a blue light-emitting region Lb for performing blue display is provided adjacent to each other.
- one pixel is configured by three adjacent sub-pixels P having a red light emitting area Lr, a green light emitting area Lg, and a blue light emitting area Lb.
- a terminal portion T is provided at the lower end of the frame region F in FIG. 1 so as to extend in one direction (horizontal direction in FIG. 1). Further, in the frame region F, a slit S penetrating the flattening film 19 is provided in a frame shape so as to surround the display region D, as shown in FIG. In the frame region F, the first flattening film 19 between the slit S and the display region D has a trench G penetrating the first flattening film 19 and an edge cover 22a described later, as shown in FIG. Are provided in a substantially C-shape.
- the trench G is formed in a substantially C-shape in plan view so that the terminal portion T side is opened in plan view, and the trench Ga penetrates the first planarization film 19 (FIG. 6). And a trench Gb (see FIG. 6) penetrating the edge cover 22a.
- the organic EL display device 50 includes, in the display region D, a resin substrate layer 10 provided as a base substrate, a TFT layer 20 provided on the resin substrate layer 10, and
- the organic EL device includes an organic EL element 25 provided as a light emitting element constituting the display region D, and a sealing film 30 provided so as to cover the organic EL element 25.
- the resin substrate layer 10 is made of, for example, a polyimide resin.
- the TFT layer 20 includes a base coat film 11 provided on the resin substrate layer 10, a plurality of first TFTs 9a, a plurality of second TFTs 9b, and a plurality of capacitors 9c provided on the base coat film 11. It has a flattening film 19 provided on each first TFT 9a, each second TFT 9b, and each capacitor 9c.
- a plurality of gate lines 14 are provided so as to extend in parallel in the horizontal direction in the drawing.
- a plurality of source lines 18f are provided so as to extend in parallel with each other in the vertical direction in the figure.
- a plurality of power lines 18g are provided so as to extend parallel to each other in the vertical direction in the figure.
- Each power line 18g is provided adjacent to each source line 18f, as shown in FIG.
- a first TFT 9a, a second TFT 9b, and a capacitor 9c are provided in each sub-pixel P.
- the pixel circuit in which the first TFT 9a, the second TFT 9b, and the capacitor 9c are provided in each sub-pixel P is illustrated.
- the present invention is a pixel circuit having a compensation circuit such as an internal compensation and an external compensation. There may be.
- the base coat film 11 is composed of, for example, a single-layer film or a laminated film of an inorganic insulating film such as silicon nitride, silicon oxide, or silicon oxynitride.
- the first TFT 9a is electrically connected to the corresponding gate line 14 and source line 18f in each sub-pixel P, as shown in FIG.
- the first TFT 9a includes a semiconductor layer 12a, a gate insulating film 13, a gate electrode 14a, a first interlayer insulating film 15, a second interlayer insulating film 17, and a semiconductor layer 12a sequentially provided on the base coat film 11. It has a source electrode 18a and a drain electrode 18b.
- the semiconductor layer 12a is provided in an island shape on the base coat film 11, as shown in FIG. 3, and has a channel region, a source region, and a drain region, as described later. Further, as shown in FIG.
- the gate insulating film 13 is provided so as to cover the semiconductor layer 12a. Further, as shown in FIG. 3, the gate electrode 14a is provided on the gate insulating film 13 so as to overlap the channel region of the semiconductor layer 12a. Further, as shown in FIG. 3, the first interlayer insulating film 15 and the second interlayer insulating film 17 are sequentially provided so as to cover the gate electrode 14a. The source electrode 18a and the drain electrode 18b are provided on the second interlayer insulating film 17 so as to be separated from each other, as shown in FIG. Further, as shown in FIG.
- the source electrode 18a and the drain electrode 18b are connected via respective contact holes formed in a laminated film of the gate insulating film 13, the first interlayer insulating film 15 and the second interlayer insulating film 17, It is electrically connected to the source region and the drain region of the semiconductor layer 12a, respectively.
- the gate insulating film 13, the first interlayer insulating film 15, and the second interlayer insulating film 17 are each formed of a single-layer film or a laminated film of an inorganic insulating film such as silicon nitride, silicon oxide, or silicon oxynitride. .
- the second TFT 9b is electrically connected to the corresponding first TFT 9a and the power supply line 18g in each sub-pixel P.
- the first TFT 9b includes a semiconductor layer 12b, a gate insulating film 13, a gate electrode 14b, a first interlayer insulating film 15, a second interlayer insulating film 17, and a semiconductor layer 12b sequentially provided on the base coat film 11. It has a source electrode 18c and a drain electrode 18d.
- the semiconductor layer 12b is provided in an island shape on the base coat film 11, and has a channel region, a source region, and a drain region, like the semiconductor layer 12a. Further, as shown in FIG.
- the gate insulating film 13 is provided so as to cover the semiconductor layer 12b. Further, as shown in FIG. 3, the gate electrode 14b is provided on the gate insulating film 13 so as to overlap the channel region of the semiconductor layer 12b. Further, as shown in FIG. 3, the first interlayer insulating film 15 and the second interlayer insulating film 17 are sequentially provided so as to cover the gate electrode 14b. The source electrode 18c and the drain electrode 18d are provided on the second interlayer insulating film 17 so as to be separated from each other, as shown in FIG. In addition, as shown in FIG.
- the source electrode 18c and the drain electrode 18d are connected via respective contact holes formed in a stacked film of the gate insulating film 13, the first interlayer insulating film 15 and the second interlayer insulating film 17, It is electrically connected to the source region and the drain region of the semiconductor layer 12b, respectively.
- first TFT 9a and the second TFT 9b of the top gate type are illustrated, but the first TFT 9a and the second TFT 9b may be of the bottom gate type.
- the capacitor 9c is electrically connected to the corresponding first TFT 9a and the power supply line 18g in each sub-pixel P.
- the capacitor 9c includes a lower conductive layer 14c formed of the same material on the same layer as the gate line 14 and the like, and a first interlayer insulating film provided to cover the lower conductive layer 14c. 15 and an upper conductive layer 16 provided on the first interlayer insulating film 15 so as to overlap the lower conductive layer 14c.
- the upper conductive layer 16 is electrically connected to a power supply line 18g via a contact hole formed in the second interlayer insulating film 17.
- the flattening film 19 has a flat surface in the display region D, and is made of, for example, an organic resin material such as a polyimide resin.
- an organic resin material such as a polyimide resin.
- the flattening film 19 made of a polyimide resin is exemplified, but the flattening film 19 may be made of an organic resin material such as an acrylic resin or a polysiloxane resin.
- the organic EL element 25 includes a plurality of first electrodes 21a, an edge cover 22a, a plurality of organic EL layers 23, and a second electrode 24 which are sequentially provided on the TFT layer 20.
- the plurality of first electrodes 21a are provided as anodes in a matrix on the planarization film 19 so as to correspond to the plurality of sub-pixels P.
- the first electrode 21a is electrically connected to the drain electrode 18d of each second TFT 9b via a contact hole formed in the flattening film 19.
- the first electrode 21a has a function of injecting holes (holes) into the organic EL layer 23.
- the first electrode 21a is more preferably formed of a material having a large work function in order to improve the efficiency of hole injection into the organic EL layer 23.
- the first electrode 21a for example, silver (Ag), aluminum (Al), vanadium (V), cobalt (Co), nickel (Ni), tungsten (W), gold (Au) , Titanium (Ti), ruthenium (Ru), manganese (Mn), indium (In), ytterbium (Yb), lithium fluoride (LiF), platinum (Pt), palladium (Pd), molybdenum (Mo), iridium ( Metal materials such as Ir) and tin (Sn). Further, the material forming the first electrode 21a may be an alloy such as astatine (At) / astatin oxide (AtO 2 ).
- the material forming the first electrode 21a is, for example, a conductive oxide such as tin oxide (SnO), zinc oxide (ZnO), indium tin oxide (ITO), and indium zinc oxide (IZO). There may be. Further, the first electrode 21a may be formed by stacking a plurality of layers made of the above materials. Note that examples of the compound material having a large work function include indium tin oxide (ITO) and indium zinc oxide (IZO).
- the edge cover 22a is provided in a lattice shape so as to cover the peripheral end of each first electrode 21a in the display area D, as shown in FIGS. Further, as shown in FIGS. 3 and 8, the edge cover 22a includes a plurality of first openings Ha provided in a matrix so as to expose each first electrode 21a in the display area D. Further, as shown in FIGS. 3 and 8, the edge cover 22 a includes a plurality of first covers provided in the display area D so as to protrude to the surface on the sealing film 30 side between the plurality of first openings Ha.
- One spacer Ca is provided.
- examples of a material forming the edge cover 22a include an organic film such as a polyimide resin, an acrylic resin, and a polysiloxane resin.
- each of the organic EL layers 23 is arranged on each first electrode 21a exposed from each first opening Ha of the edge cover 22a, and are arranged in a matrix so as to correspond to the plurality of sub-pixels P. It is provided as a light emitting element layer.
- each of the organic EL layers 23 includes a hole injection layer 1, a hole transport layer 2, a light emitting layer 3, an electron transport layer 4, and an electron injection layer provided in this order on the first electrode 21a. It has a layer 5.
- the hole injection layer 1 is also called an anode buffer layer, and has a function of making the energy levels of the first electrode 21a and the organic EL layer 23 close to each other and improving the efficiency of hole injection from the first electrode 21a to the organic EL layer 23.
- a material constituting the hole injection layer for example, a triazole derivative, an oxadiazole derivative, an imidazole derivative, a polyarylalkane derivative, a pyrazoline derivative, a phenylenediamine derivative, an oxazole derivative, a styrylanthracene derivative, a fluorenone derivative, Hydrazone derivatives, stilbene derivatives and the like can be mentioned.
- the hole transport layer 2 has a function of improving the efficiency of transporting holes from the first electrode 21a to the organic EL layer 23.
- examples of the material constituting the hole transport layer 2 include a porphyrin derivative, an aromatic tertiary amine compound, a styrylamine derivative, polyvinyl carbazole, poly-p-phenylene vinylene, polysilane, a triazole derivative, and oxadiazole.
- Derivatives imidazole derivatives, polyarylalkane derivatives, pyrazoline derivatives, pyrazolone derivatives, phenylenediamine derivatives, arylamine derivatives, amine-substituted chalcone derivatives, oxazole derivatives, styrylanthracene derivatives, fluorenone derivatives, hydrazone derivatives, stilbene derivatives, hydrogenated amorphous silicon, Examples include hydrogenated amorphous silicon carbide, zinc sulfide, and zinc selenide.
- the light emitting layer 3 when a voltage is applied by the first electrode 21a and the second electrode 24, holes and electrons are injected from the first electrode 21a and the second electrode 24, respectively, and the holes and electrons recombine. Area.
- the light emitting layer 3 is formed of a material having high luminous efficiency. Examples of the material constituting the light emitting layer 3 include a metal oxinoid compound [8-hydroxyquinoline metal complex], a naphthalene derivative, an anthracene derivative, a diphenylethylene derivative, a vinylacetone derivative, a triphenylamine derivative, a butadiene derivative, and a coumarin derivative.
- the electron transport layer 4 has a function of efficiently moving electrons to the light emitting layer 3.
- a material constituting the electron transport layer 4 for example, as an organic compound, an oxadiazole derivative, a triazole derivative, a benzoquinone derivative, a naphthoquinone derivative, an anthraquinone derivative, a tetracyanoanthraquinodimethane derivative, a diphenoquinone derivative, a fluorenone derivative , Silole derivatives, metal oxinoid compounds and the like.
- the electron injection layer 5 has a function of making the energy levels of the second electrode 24 and the organic EL layer 23 close to each other and improving the efficiency of injecting electrons from the second electrode 24 into the organic EL layer 23.
- the drive voltage of the organic EL element 25 can be reduced.
- the electron injection layer 5 is also called a cathode buffer layer.
- a material constituting the electron injection layer 5 for example, lithium fluoride (LiF), magnesium fluoride (MgF 2 ), calcium fluoride (CaF 2 ), strontium fluoride (SrF 2 ), barium fluoride Examples thereof include an inorganic alkali compound such as (BaF 2 ), aluminum oxide (Al 2 O 3 ), and strontium oxide (SrO).
- the second electrode 24 is provided as a cathode so as to cover each organic EL layer 23 and the edge cover 22a.
- the second electrode 24 has a function of injecting electrons into the organic EL layer 23. It is more preferable that the second electrode 24 be made of a material having a small work function in order to improve the efficiency of injecting electrons into the organic EL layer 23.
- the second electrode 24 for example, silver (Ag), aluminum (Al), vanadium (V), calcium (Ca), titanium (Ti), yttrium (Y), sodium (Na) , Manganese (Mn), indium (In), magnesium (Mg), lithium (Li), ytterbium (Yb), lithium fluoride (LiF) and the like.
- the second electrode 24 is made of, for example, magnesium (Mg) / copper (Cu), magnesium (Mg) / silver (Ag), sodium (Na) / potassium (K), astatine (At) / astatin oxide (AtO 2).
- the second electrode 24 may be formed of a conductive oxide such as tin oxide (SnO), zinc oxide (ZnO), indium tin oxide (ITO), and indium zinc oxide (IZO), for example. . Further, the second electrode 24 may be formed by stacking a plurality of layers made of the above materials.
- Examples of the material having a small work function include magnesium (Mg), lithium (Li), lithium fluoride (LiF), magnesium (Mg) / copper (Cu), magnesium (Mg) / silver (Ag), and sodium.
- (Na) / potassium (K) lithium (Li) / aluminum (Al), lithium (Li) / calcium (Ca) / aluminum (Al), lithium fluoride (LiF) / calcium (Ca) / aluminum (Al) And the like.
- the sealing film 30 is provided so as to cover the second electrode 24, and the first inorganic film 26, the organic film 27, and the second inorganic film 28 which are sequentially stacked on the second electrode 24 are formed. And has a function of protecting the organic EL layer 23 of the organic EL element 25 from moisture and oxygen.
- the first inorganic film 26 and the second inorganic film 28 are made of, for example, an inorganic insulating film such as a silicon nitride film, a silicon oxide film, and a silicon oxynitride film.
- the organic film 27 is made of, for example, an organic resin material such as an acrylic resin, an epoxy resin, a silicone resin, a polyurea resin, a parylene resin, a polyimide resin, and a polyamide resin.
- an organic resin material such as an acrylic resin, an epoxy resin, a silicone resin, a polyurea resin, a parylene resin, a polyimide resin, and a polyamide resin.
- the organic EL display device 50 includes the resin substrate layer 10, the TFT layer 20 provided on the resin substrate layer 10, and the TFT layer 20 sequentially.
- the TFT layer 20 includes a driving circuit TFT 9d provided on the display region D side of the trench Ga and a driving circuit TFT 9d provided on the slit S side of the trench Ga. And a TFT 9e.
- the drive circuit TFTs 9d and 9e are electrically connected to each other via the gate conductive layer 14d as shown in FIGS. 6 and 7 illustrate the circuit configuration in which the driving circuit TFTs 9d and 9e are electrically connected to each other, but the driving circuit TFTs 9d and 9e may not be electrically connected to each other.
- the drive circuit TFT 9d constitutes, for example, a gate driver circuit and the like
- the drive circuit TFT 9e constitutes, for example, a light emission control circuit and the like.
- the peripheral electrode 21b is substantially C-shaped so as to cover the trench Ga and the slit S (the first slit Sa and the second slit Sb) on the TFT layer 20 in the frame region F. It is provided in a character shape.
- the slit S is provided in a frame shape on the display area D side and penetrates the flattening film 19, and is provided in a frame shape so as to surround the first slit Sa.
- a second slit Sb penetrating the flattening film 19. As shown in FIG.
- the peripheral electrode 21b contacts the second electrode 24 via a second opening Hb or the like of the edge cover 22a as described later, and a low power supply voltage is applied to the second electrode 24. It is configured to be input.
- the peripheral electrode 21b is formed of the same material in the same layer as the first electrode 21a. As shown in FIG. 7, the peripheral electrode 21b is electrically connected to the source conductive layer 18h formed of the same material as the source line 18f and the like through the first slit Sa and the second slit Sb. Have been.
- the source conductive layer 18h is provided, for example, in a frame shape, a part of a side along the terminal portion T is extended to the terminal portion T, and a low power supply voltage is input to the terminal portion T. I have.
- the edge cover 22a is provided on the peripheral electrode 21b in the frame region F, and has a plurality of second openings formed in the same shape and at the same pitch as the plurality of first openings Ha.
- a portion Hb and a plurality of second columnar spacers Cb are provided between the plurality of second openings Hb so as to protrude from the surface on the sealing film 30 side.
- the distances Xb and Yb between the second opening Hb and the second columnar spacer Cb in the frame region F are, as shown in FIG. 8, the distance between the first opening Ha and the first columnar spacer Ca in the display region D. They are equal to the distances Xa and Ya, respectively.
- the intervals Xd and Yd between the adjacent second openings Hb in the frame area F are equal to the intervals Xc and Yc between the first openings Ha in the display area D, respectively, as shown in FIG. I have. That is, the positional relationship between the second opening Hb and the second columnar spacer Cb in the frame region F is set to be equal to the positional relationship between the first opening Ha and the first columnar spacer Ca in the display region D. I have. Further, as shown in FIG. 8, the pitch of the plurality of second columnar spacers Cb is larger than the pitch of the plurality of second openings Hb.
- the plurality of second openings Hb and the plurality of second columnar spacers Cb are provided between the display region D and the trench Gb, as shown in FIGS. And Sa.
- the arrangement density of the second openings Hb arranged between the display area D and the trench Gb is equal to the arrangement density of the second openings Hb arranged between the trench Gb and the first slit Sa.
- the same shape and the same pitch means that the first opening Ha and the second opening Hb are patterned using the same mask pattern, and the variation in the exposure and development of the photosensitive resin. This includes that the shapes and pitches do not exactly match but substantially match due to heat dripping or the like when baking the photosensitive resin.
- FIG. 9 is a plan view of a peripheral electrode 21c which is a modified example of the edge cover 22a and the peripheral electrode 21b constituting the organic EL display device 50.
- the peripheral electrode 21c has an opening Hc whose peripheral end is disposed outside the peripheral end of each second opening Hb, and is not exposed from the edge cover 22a. As a result, the influence of reflection by external light can be suppressed.
- the second electrode 24 extends to the inside of the outermost second columnar spacer Cb, and includes a plurality of second openings Hb and trenches Gb formed in the edge cover 22a, and It is electrically connected to the peripheral electrode 21b via the trench Ga formed in the planarization film 19.
- the same layer as the source line 18f and the like is used on the bottom of the trench Ga.
- a source conductive layer 18e formed of the same material is provided on the bottom of the trench Ga.
- the first dam wall Wa is provided in a frame shape so as to surround the display area D, as shown in FIG. 7, and is configured to suppress the spread of the organic film 27 of the sealing film 30.
- the first dam wall Wa is formed on a part of the flattening film 19 disposed between the first slit Sa and the second slit Sb, and on a part of the flattening film 19.
- a resin layer 22b formed of the same material on the same layer as the edge cover 22a.
- the second dam wall Wb is provided in a frame shape so as to surround the first dam wall Wa, as shown in FIG.
- the second dam wall Wb includes a part of the flattening film 19 disposed outside the second slit Sb and a peripheral electrode 21 b on a part of the flattening film 19. And a resin layer 22c formed of the same material on the same layer as the edge cover 22a.
- the organic film 27 constituting the sealing film 30 is provided in the frame region F through the first inorganic film 26 to the first dam wall Wa, as shown in FIG.
- the configuration in which the organic film 27 is blocked on the side surface of the first blocking wall Wa on the display region D side is exemplified.
- the organic film 27 is, for example, an upper surface of the second blocking wall Wb. May have been reached.
- the stacked film of the first inorganic film 27 and the second inorganic film 28 stacked in the frame region F as a part of the sealing film 30 is formed outside the second dam wall Wb. It is in contact with the second interlayer insulating film 17 and is in contact with at least one of the inorganic insulating films constituting the TFT layer 20.
- a first TFT 9a is turned on by inputting a gate signal to the first TFT 9a via the gate line 14, and the gate electrode of the second TFT 9b is connected via the source line 18f.
- a predetermined voltage corresponding to the source signal is written to the capacitor 14b and the capacitor 9c, and a current is supplied from the power supply line 18g having a size defined based on the gate voltage of the second TFT 9b to the organic EL layer 23, thereby the organic EL layer 23 is turned off.
- the light-emitting layer 3 of the layer 23 emits light to display an image.
- the organic EL display device 50 in each sub-pixel P, even if the first TFT 9a is turned off, the gate voltage of the second TFT 9b is held by the capacitor 9c, so that the gate signal of the next frame is input. Light emission by the light emitting layer 3 is maintained.
- the method for manufacturing the organic EL display device 50 according to the present embodiment includes a TFT layer forming step, an organic EL element forming step including a first electrode forming step, an edge cover forming step, an organic EL layer forming step, and a second electrode forming step. And a sealing film forming step.
- FIGS. 10, 11 and 12 are cross-sectional views showing a first electrode forming step, an edge cover forming step, and an organic EL layer forming step of the organic EL element forming step in the method of manufacturing the organic EL display device 50. .
- ⁇ TFT layer forming step> For example, a base coat film 11, a first TFT 9a, a second TFT 9b, a capacitor 9c, and a planarizing film 19 are formed on a surface of a resin substrate layer 10 formed on a glass substrate by a known method, and a TFT layer 20 is formed. I do.
- the driver circuit TFTs 9d and 9e are simultaneously formed in the frame region F.
- ⁇ Organic EL element forming step> The first electrode 21a, the edge cover 22a, the organic EL layer 23 (the hole injection layer 1, the hole transport layer) are formed on the flattening film 19 of the TFT layer 20 formed in the above-described TFT layer forming step by using a known method.
- the layer 2, the light emitting layer 3, the electron transport layer 4, and the electron injection layer 5) and the second electrode 24 are formed to form the organic EL element 25.
- the edge cover 22a, the organic EL layer 23, and the second electrode 24 first, an ITO film / silver alloy film ( After forming a conductive film 21 such as a (MgAg film) / ITO film, a photolithography process, an etching process, and a resist removal are performed, and the conductive film 21 is patterned, so that the display region D is formed as shown in FIG. A plurality of first electrodes 21a are formed, and a peripheral electrode 21b is formed in the frame region F (first electrode forming step).
- a conductive film 21 such as a (MgAg film) / ITO film
- a photolithography process, an etching process, and a resist removal are performed, and the conductive film 21 is patterned, so that the display region D is formed as shown in FIG.
- a plurality of first electrodes 21a are formed, and a peripheral electrode 21b is formed in the frame region F (first electrode forming step).
- a photosensitive resin 22 made of a polyimide resin is formed by, for example, an inkjet method so as to cover the first electrodes 21a and the peripheral electrodes 21b, exposure, development, and baking using a halftone mask Mh are performed.
- the display region D has a plurality of first openings Ha and a plurality of first columnar spacers Ca
- the frame region F has a plurality of second openings Hb and a plurality of first columnar spacers Ca.
- the edge cover 22a having the two columnar spacers Cb is formed (edge cover forming step).
- the halftone mask Mh includes a shielding portion Ra through which light does not transmit, a half exposure portion Rb in which the amount of transmitted light is controlled, and a full exposure portion opened so as to transmit light.
- This is a multi-tone mask provided with Rc.
- the shielding portion Ra of the halftone mask Mh is arranged in a region of the edge cover 22a where the first columnar spacer Ca and the second columnar spacer Cb are formed, as shown in FIG.
- the full exposure portion Rc of the halftone mask Mh is disposed in a region where the first opening Ha and the second opening Hb of the edge cover 22a are formed.
- the halftone mask Mh is exemplified as the multi-tone mask, but the multi-tone mask may be a gray-tone mask.
- the hole injection layer 1 is formed via the deposition mask Md by, for example, a vacuum deposition method.
- the hole transport layer 2, the light emitting layer 3, the electron transport layer 4, and the electron injection layer 5 are sequentially formed, and the organic EL layer 23 is formed in each sub-pixel P (organic EL layer forming step).
- a silver alloy film (MgAg film) is formed on the substrate on which the organic EL layer 23 is formed by using another evaporation mask, for example, by a vacuum evaporation method so as to cover each organic EL layer 23.
- the second electrode 24 is formed (second electrode forming step).
- ⁇ Sealing film forming step> First, an inorganic insulating film such as a silicon nitride film, a silicon oxide film, or a silicon oxynitride film is formed on the surface of the substrate on which the organic EL element 25 is formed in the organic EL element forming step by a plasma CVD method using a mask.
- the first inorganic film 26 is formed to a thickness of about 1000 nm.
- an organic resin material such as an acrylic resin is formed to a thickness of about 10 ⁇ m on the surface of the substrate on which the first inorganic film 26 is formed, for example, by an inkjet method, thereby forming an organic film 27.
- an inorganic insulating film such as a silicon nitride film, a silicon oxide film, or a silicon oxynitride film is formed to a thickness of about 500 nm by a plasma CVD method on the substrate on which the organic film 27 is formed, using a mask. Then, the sealing film 30 is formed by forming the second inorganic film 28.
- a laser beam is irradiated from the glass substrate side of the resin substrate layer 10 so that the lower surface of the resin substrate layer 10
- the substrate is peeled off, and a protective sheet (not shown) is attached to the lower surface of the resin substrate layer 10 from which the glass substrate has been peeled off.
- the organic EL display device 50 of the present embodiment can be manufactured.
- the edge cover 22a includes the plurality of first openings Ha that expose the first electrodes 21a in the display region D; A plurality of first columnar spacers Ca protruding from the surface on the side of the sealing film 30; a plurality of first columnar spacers Ca provided on the peripheral electrode 21b in the frame region F; A second opening Hb and a plurality of second columnar spacers Cb protruding from the surface on the side of the sealing film 30 are provided.
- a plurality of first electrodes 21a and a plurality of peripheral electrodes 21b simultaneously formed in the first electrode forming step are provided in the display region D and the frame region F, respectively.
- the edge cover forming step the first opening Ha around each first columnar spacer Ca arranged in the display area D is formed on the peripheral end of each first electrode 21a and the edge cover 22a formed on the peripheral electrode 21b.
- the shape and pitch of the second openings Hb around the second columnar spacers Cb arranged in the frame region F are the same.
- the heat drooping occurs in the display region D and the display region D. Since it is uniformly generated in the frame region F, the height of each first columnar spacer Ca and the height of each second columnar spacer Cb can be made equal. As a result, the deposition mask Md can be placed on each of the first columnar spacers Ca and each of the second columnar spacers Cb formed on the substrate to be deposited without tilting. In addition, the contact with each of the second columnar spacers Cb can be made uniform to suppress generation of particles.
- the organic EL layer having a five-layer structure of the hole injection layer, the hole transport layer, the light emitting layer, the electron transport layer, and the electron injection layer is exemplified. It may have a three-layer structure of a hole-transport layer, a light-emitting layer, and an electron-transport layer and an electron-injection layer.
- the organic EL display device in which the first electrode is used as an anode and the second electrode is used as a cathode is exemplified.
- the present invention inverts the stacked structure of the organic EL layer and uses the first electrode as a cathode. Also, the present invention can be applied to an organic EL display device using the second electrode as an anode.
- the organic EL display device in which the electrode of the TFT connected to the first electrode is used as the drain electrode is exemplified.
- the present invention calls the electrode of the TFT connected to the first electrode a source electrode.
- the present invention can be applied to an organic EL display device.
- the organic EL display device is described as an example of the display device.
- the present invention can be applied to a display device including a plurality of light emitting elements driven by current.
- the present invention can be applied to a display device provided with a QLED (Quantum-dot-light-emitting-diode) that is a light-emitting element using a quantum dot-containing layer.
- QLED Quantum-dot-light-emitting-diode
- the present invention is useful for a flexible display device.
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Abstract
An edge cover (22a) of the present invention comprises, in a display region (D), a plurality of first openings (Ha) that are provided so as to expose each first electrode (21a) and a plurality of first columnar spacers (Ca) that are provided between the plurality of first openings (Ha), and comprises, in a frame region (F), a plurality of second openings (Hb) that are formed in the same shape and at the same pitch as the plurality of first openings (Ha) and a plurality of second columnar spacers (Cb) that are provided between the plurality of second openings (Hb).
Description
本発明は、表示装置及びその製造方法に関するものである。
The present invention relates to a display device and a method for manufacturing the same.
近年、液晶表示装置に代わる表示装置として、有機ＥＬ（electroluminescence）素子を用いた自発光型の有機ＥＬ表示装置が注目されている。ここで、有機ＥＬ素子は、例えば、表示領域にマトリクス状に設けられた複数の第１電極と、各第１電極の周端部を覆うように格子状に設けられたエッジカバーと、エッジカバーから露出する各第１電極上に設けられた有機ＥＬ層と、各有機ＥＬ層を覆うように設けられた第２電極とを備えている。そして、上記有機ＥＬ層は、例えば、正孔注入層、正孔輸送層、発光層、電子輸送層及び電子注入層を含み、それらの各層を形成する方法としては、被蒸着基板上に載置した蒸着マスクを介して蒸着を行う方法がよく知られている。
In recent years, a self-luminous organic EL display device using an organic EL (electroluminescence) element has attracted attention as a display device replacing the liquid crystal display device. Here, the organic EL element includes, for example, a plurality of first electrodes provided in a matrix in a display area, an edge cover provided in a grid shape so as to cover a peripheral end of each first electrode, and an edge cover. An organic EL layer provided on each of the first electrodes exposed from above, and a second electrode provided to cover each of the organic EL layers. The organic EL layer includes, for example, a hole injecting layer, a hole transporting layer, a light emitting layer, an electron transporting layer, and an electron injecting layer. A method of performing vapor deposition through a vapor deposition mask is well known.
例えば、特許文献１には、表示領域の中央部における蒸着用マスク支持体の設置面積が、表示領域の縁部における蒸着用マスク支持体の設置面積よりも大きい、表示装置及びその製造方法が開示されている。
For example, Patent Literature 1 discloses a display device and a manufacturing method thereof, in which an installation area of a deposition mask support at a central portion of a display area is larger than an installation area of an evaporation mask support at an edge of the display area. Have been.
ところで、有機ＥＬ表示装置の製造において、エッジカバーと、エッジカバー上に配置して蒸着マスクを支持する柱状スペーサとを同一の感光性樹脂によりハーフ露光を利用して形成する場合には、表示領域の周囲の額縁領域に形成された柱状スペーサが表示領域に形成された柱状スペーサよりも低くなるおそれがある。そうなると、載置される蒸着マスクとの接触により、表示領域に形成された柱状スペーサからパーティクルが発生し易くなるので、改善の余地がある。
In the manufacture of an organic EL display device, when the edge cover and the columnar spacers disposed on the edge cover and supporting the deposition mask are formed using the same photosensitive resin by using half-exposure, a display area is required. May be lower than the columnar spacers formed in the display area. In this case, particles are likely to be generated from the columnar spacers formed in the display area due to contact with the deposition mask to be placed, and there is room for improvement.
本発明は、かかる点に鑑みてなされたものであり、その目的とするところは、蒸着マスクと柱状スペーサとの接触を均一にして、パーティクルの発生を抑制することにある。
The present invention has been made in view of such a point, and an object of the present invention is to make the contact between a deposition mask and a columnar spacer uniform to suppress generation of particles.
上記目的を達成するために、本発明に係る表示装置は、ベース基板と、上記ベース基板上に設けられたＴＦＴ層と、上記ＴＦＴ層上に設けられ、表示領域を構成する発光素子と、上記表示領域の周囲に設けられた額縁領域とを備え、上記発光素子が、上記ＴＦＴ層上に設けられた複数の第１電極と、該各第１電極の周端部を覆うように複数の第１開口部を有する格子状に設けられたエッジカバーと、該エッジカバーの上記各第１開口部から露出する上記各第１電極上にそれぞれ設けられた複数の発光素子層と、該各発光素子層を覆うように設けられた第２電極とを備え、上記エッジカバーが、上記表示領域において、上記複数の第１開口部の間で上記ベース基板と反対側の表面に突出するように設けられた複数の第１柱状スペーサとを備えた表示装置であって、上記額縁領域において、上記ＴＦＴ層上には、上記各第１電極と同一層に同一材料により周辺電極が設けられ、上記エッジカバーは、上記額縁領域において、上記複数の第１開口部と同一形状で同一ピッチに形成された複数の第２開口部と、該複数の第２開口部の間で上記ベース基板と反対側の表面に突出するように設けられた複数の第２柱状スペーサとを備えていることを特徴とする。
In order to achieve the above object, a display device according to the present invention includes a base substrate, a TFT layer provided on the base substrate, a light emitting element provided on the TFT layer and forming a display region, A frame region provided around a display region, wherein the light-emitting element includes a plurality of first electrodes provided on the TFT layer and a plurality of first electrodes covering a peripheral end of each of the first electrodes. An edge cover provided in a lattice shape having one opening, a plurality of light emitting element layers provided on each of the first electrodes exposed from each of the first openings of the edge cover, and each of the light emitting elements A second electrode provided so as to cover a layer, wherein the edge cover is provided so as to protrude from the plurality of first openings to a surface opposite to the base substrate in the display area. And a plurality of first columnar spacers In the display device, in the frame region, peripheral electrodes are provided on the TFT layer in the same layer as the first electrodes using the same material, and the edge cover is provided in the frame region in the frame region. A plurality of second openings formed in the same shape and at the same pitch as the one opening, and a plurality of second openings provided between the plurality of second openings so as to protrude to a surface opposite to the base substrate; And a two-column spacer.
本発明によれば、エッジカバーが、表示領域において、各第１電極を露出させる複数の第１開口部と、ベース基板と反対側の表面に突出する複数の第１柱状スペーサとを備え、額縁領域において、複数の第１開口部と同一形状で同一ピッチの複数の第２開口部と、ベース基板と反対側の表面に突出する複数の第２柱状スペーサとを備えているので、蒸着マスクと柱状スペーサとの接触を均一にして、パーティクルの発生を抑制することができる。
According to the present invention, the edge cover includes a plurality of first openings exposing each of the first electrodes in the display area, and a plurality of first columnar spacers protruding from a surface opposite to the base substrate. The region includes a plurality of second openings having the same shape and the same pitch as the plurality of first openings, and a plurality of second columnar spacers protruding from the surface on the side opposite to the base substrate. The contact with the columnar spacers can be made uniform and the generation of particles can be suppressed.
以下、本発明の実施形態を図面に基づいて詳細に説明する。なお、本発明は、以下の各実施形態に限定されるものではない。
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that the present invention is not limited to the following embodiments.
《第１の実施形態》
図１～図１２は、本発明に係る表示装置及びその製造方法の第１の実施形態を示している。なお、以下の各実施形態では、発光素子を備えた表示装置として、有機ＥＬ素子を備えた有機ＥＬ表示装置を例示する。ここで、図１は、本実施形態の有機ＥＬ表示装置５０の概略構成を示す平面図である。また、図２は、有機ＥＬ表示装置５０の表示領域Ｄの平面図である。また、図３は、図１中のIII－III線に沿った有機ＥＬ表示装置５０の表示領域Ｄの断面図である。また、図４は、有機ＥＬ表示装置５０を構成するＴＦＴ層２０の等価回路図である。また、図５は、有機ＥＬ表示装置５０を構成する有機ＥＬ層２３の断面図である。また、図６及び図７は、図１中のVI－VI線及びVII－VII線に沿った有機ＥＬ表示装置５０の額縁領域Ｆの断面図である。また、図８は、有機ＥＬ表示装置５０を構成するエッジカバー２２ａの平面図である。 << 1st Embodiment >>
1 to 12 show a first embodiment of a display device and a method of manufacturing the same according to the present invention. In the following embodiments, an organic EL display device having an organic EL element will be exemplified as a display device having a light emitting element. Here, FIG. 1 is a plan view showing a schematic configuration of the organicEL display device 50 of the present embodiment. FIG. 2 is a plan view of a display area D of the organic EL display device 50. FIG. 3 is a cross-sectional view of the display area D of the organic EL display device 50 along the line III-III in FIG. FIG. 4 is an equivalent circuit diagram of the TFT layer 20 included in the organic EL display device 50. FIG. 5 is a sectional view of the organic EL layer 23 constituting the organic EL display device 50. 6 and 7 are cross-sectional views of the frame region F of the organic EL display device 50 taken along lines VI-VI and VII-VII in FIG. FIG. 8 is a plan view of an edge cover 22a included in the organic EL display device 50.
図１～図１２は、本発明に係る表示装置及びその製造方法の第１の実施形態を示している。なお、以下の各実施形態では、発光素子を備えた表示装置として、有機ＥＬ素子を備えた有機ＥＬ表示装置を例示する。ここで、図１は、本実施形態の有機ＥＬ表示装置５０の概略構成を示す平面図である。また、図２は、有機ＥＬ表示装置５０の表示領域Ｄの平面図である。また、図３は、図１中のIII－III線に沿った有機ＥＬ表示装置５０の表示領域Ｄの断面図である。また、図４は、有機ＥＬ表示装置５０を構成するＴＦＴ層２０の等価回路図である。また、図５は、有機ＥＬ表示装置５０を構成する有機ＥＬ層２３の断面図である。また、図６及び図７は、図１中のVI－VI線及びVII－VII線に沿った有機ＥＬ表示装置５０の額縁領域Ｆの断面図である。また、図８は、有機ＥＬ表示装置５０を構成するエッジカバー２２ａの平面図である。 << 1st Embodiment >>
1 to 12 show a first embodiment of a display device and a method of manufacturing the same according to the present invention. In the following embodiments, an organic EL display device having an organic EL element will be exemplified as a display device having a light emitting element. Here, FIG. 1 is a plan view showing a schematic configuration of the organic
有機ＥＬ表示装置５０は、図１に示すように、例えば、矩形状に設けられた画像表示を行う表示領域Ｄと、表示領域Ｄの周囲に設けられた額縁領域Ｆとを備えている。
As shown in FIG. 1, the organic EL display device 50 includes, for example, a rectangular display area D for displaying an image, and a frame area F provided around the display area D.
表示領域Ｄには、図２に示すように、複数のサブ画素Ｐがマトリクス状に配列されている。また、表示領域Ｄでは、図２に示すように、例えば、赤色の表示を行うための赤色発光領域Ｌｒを有するサブ画素Ｐ、緑色の表示を行うための緑色発光領域Ｌｇを有するサブ画素Ｐ、及び青色の表示を行うための青色発光領域Ｌｂを有するサブ画素Ｐが互いに隣り合うように設けられている。なお、表示領域Ｄでは、例えば、赤色発光領域Ｌｒ、緑色発光領域Ｌｇ及び青色発光領域Ｌｂを有する隣り合う３つのサブ画素Ｐにより、１つの画素が構成されている。
(2) In the display area D, a plurality of sub-pixels P are arranged in a matrix as shown in FIG. In the display area D, as shown in FIG. 2, for example, a sub-pixel P having a red light-emitting area Lr for performing red display, a sub-pixel P having a green light-emitting area Lg for performing green display, And a sub-pixel P having a blue light-emitting region Lb for performing blue display is provided adjacent to each other. In the display area D, for example, one pixel is configured by three adjacent sub-pixels P having a red light emitting area Lr, a green light emitting area Lg, and a blue light emitting area Lb.
額縁領域Ｆの図１中下端部には、端子部Ｔが一方向（図１中横方向）に延びるように設けられている。また、額縁領域Ｆにおいて、後述する平坦化膜１９には、図１に示すように、表示領域Ｄを囲むように平坦化膜１９を貫通するスリットＳが枠状に設けられている。また、額縁領域Ｆにおいて、スリットＳと表示領域Ｄとの間の第１平坦化膜１９には、図１に示すように、第１平坦化膜１９及び後述するエッジカバー２２ａを貫通するトレンチＧが略Ｃ字状に設けられている。ここで、トレンチＧは、図１に示すように、平面視で端子部Ｔ側が開口するように平面視で略Ｃ字状に形成され、第１平坦化膜１９を貫通するトレンチＧａ（図６参照）と、エッジカバー２２ａを貫通するトレンチＧｂ（図６参照）とを有している。
(1) A terminal portion T is provided at the lower end of the frame region F in FIG. 1 so as to extend in one direction (horizontal direction in FIG. 1). Further, in the frame region F, a slit S penetrating the flattening film 19 is provided in a frame shape so as to surround the display region D, as shown in FIG. In the frame region F, the first flattening film 19 between the slit S and the display region D has a trench G penetrating the first flattening film 19 and an edge cover 22a described later, as shown in FIG. Are provided in a substantially C-shape. Here, as shown in FIG. 1, the trench G is formed in a substantially C-shape in plan view so that the terminal portion T side is opened in plan view, and the trench Ga penetrates the first planarization film 19 (FIG. 6). And a trench Gb (see FIG. 6) penetrating the edge cover 22a.
有機ＥＬ表示装置５０は、図３に示すように、表示領域Ｄにおいて、ベース基板として設けられた樹脂基板層１０と、樹脂基板層１０上に設けられたＴＦＴ層２０と、ＴＦＴ層２０上に表示領域Ｄを構成する発光素子として設けられた有機ＥＬ素子２５と、有機ＥＬ素子２５を覆うように設けられた封止膜３０と備えている。
As shown in FIG. 3, the organic EL display device 50 includes, in the display region D, a resin substrate layer 10 provided as a base substrate, a TFT layer 20 provided on the resin substrate layer 10, and The organic EL device includes an organic EL element 25 provided as a light emitting element constituting the display region D, and a sealing film 30 provided so as to cover the organic EL element 25.
樹脂基板層１０は、例えば、ポリイミド樹脂等により構成されている。
The resin substrate layer 10 is made of, for example, a polyimide resin.
ＴＦＴ層２０は、図３に示すように、樹脂基板層１０上に設けられたベースコート膜１１と、ベースコート膜１１上に設けられた複数の第１ＴＦＴ９ａ、複数の第２ＴＦＴ９ｂ及び複数のキャパシタ９ｃと、各第１ＴＦＴ９ａ、各第２ＴＦＴ９ｂ及び各キャパシタ９ｃ上に設けられた平坦化膜１９とを備えている。ここで、ＴＦＴ層２０では、図２及び図４に示すように、図中横方向に互いに平行に延びるように複数のゲート線１４が設けられている。また、ＴＦＴ層２０では、図２及び図４に示すように、図中縦方向に互いに平行に延びるように複数のソース線１８ｆが設けられている。また、ＴＦＴ層２０では、図２及び図４に示すように、図中縦方向に互いに平行に延びるように複数の電源線１８ｇが設けられている。なお、各電源線１８ｇは、図２に示すように、各ソース線１８ｆと隣り合うように設けられている。また、ＴＦＴ層２０では、図４に示すように、各サブ画素Ｐにおいて、第１ＴＦＴ９ａ、第２ＴＦＴ９ｂ及びキャパシタ９ｃがそれぞれ設けられている。なお、本実施形態では、各サブ画素Ｐに第１ＴＦＴ９ａ、第２ＴＦＴ９ｂ及びキャパシタ９ｃが設けられた画素回路を例示したが、本発明は、内部補償や外部補償等の補償回路を備えた画素回路であってもよい。
As shown in FIG. 3, the TFT layer 20 includes a base coat film 11 provided on the resin substrate layer 10, a plurality of first TFTs 9a, a plurality of second TFTs 9b, and a plurality of capacitors 9c provided on the base coat film 11. It has a flattening film 19 provided on each first TFT 9a, each second TFT 9b, and each capacitor 9c. Here, in the TFT layer 20, as shown in FIG. 2 and FIG. 4, a plurality of gate lines 14 are provided so as to extend in parallel in the horizontal direction in the drawing. Further, in the TFT layer 20, as shown in FIGS. 2 and 4, a plurality of source lines 18f are provided so as to extend in parallel with each other in the vertical direction in the figure. Further, in the TFT layer 20, as shown in FIGS. 2 and 4, a plurality of power lines 18g are provided so as to extend parallel to each other in the vertical direction in the figure. Each power line 18g is provided adjacent to each source line 18f, as shown in FIG. In the TFT layer 20, as shown in FIG. 4, a first TFT 9a, a second TFT 9b, and a capacitor 9c are provided in each sub-pixel P. In the present embodiment, the pixel circuit in which the first TFT 9a, the second TFT 9b, and the capacitor 9c are provided in each sub-pixel P is illustrated. However, the present invention is a pixel circuit having a compensation circuit such as an internal compensation and an external compensation. There may be.
ベースコート膜１１は、例えば、窒化シリコン、酸化シリコン、酸窒化シリコン等の無機絶縁膜の単層膜又は積層膜により構成されている。
The base coat film 11 is composed of, for example, a single-layer film or a laminated film of an inorganic insulating film such as silicon nitride, silicon oxide, or silicon oxynitride.
第１ＴＦＴ９ａは、図４に示すように、各サブ画素Ｐにおいて、対応するゲート線１４及びソース線１８ｆに電気的に接続されている。また、第１ＴＦＴ９ａは、図３に示すように、ベースコート膜１１上に順に設けられた半導体層１２ａ、ゲート絶縁膜１３、ゲート電極１４ａ、第１層間絶縁膜１５、第２層間絶縁膜１７、並びにソース電極１８ａ及びドレイン電極１８ｂを備えている。ここで、半導体層１２ａは、図３に示すように、ベースコート膜１１上に島状に設けられ、後述するように、チャネル領域、ソース領域及びドレイン領域を有している。また、ゲート絶縁膜１３は、図３に示すように、半導体層１２ａを覆うように設けられている。また、ゲート電極１４ａは、図３に示すように、ゲート絶縁膜１３上に半導体層１２ａのチャネル領域と重なるように設けられている。また、第１層間絶縁膜１５及び第２層間絶縁膜１７は、図３に示すように、ゲート電極１４ａを覆うように順に設けられている。また、ソース電極１８ａ及びドレイン電極１８ｂは、図３に示すように、第２層間絶縁膜１７上に互いに離間するように設けられている。また、ソース電極１８ａ及びドレイン電極１８ｂは、図３に示すように、ゲート絶縁膜１３、第１層間絶縁膜１５及び第２層間絶縁膜１７の積層膜に形成された各コンタクトホールを介して、半導体層１２ａのソース領域及びドレイン領域にそれぞれ電気的に接続されている。なお、ゲート絶縁膜１３、第１層間絶縁膜１５及び第２層間絶縁膜１７は、例えば、窒化シリコン、酸化シリコン、酸窒化シリコン等の無機絶縁膜の単層膜又は積層膜により構成されている。
(4) The first TFT 9a is electrically connected to the corresponding gate line 14 and source line 18f in each sub-pixel P, as shown in FIG. As shown in FIG. 3, the first TFT 9a includes a semiconductor layer 12a, a gate insulating film 13, a gate electrode 14a, a first interlayer insulating film 15, a second interlayer insulating film 17, and a semiconductor layer 12a sequentially provided on the base coat film 11. It has a source electrode 18a and a drain electrode 18b. Here, the semiconductor layer 12a is provided in an island shape on the base coat film 11, as shown in FIG. 3, and has a channel region, a source region, and a drain region, as described later. Further, as shown in FIG. 3, the gate insulating film 13 is provided so as to cover the semiconductor layer 12a. Further, as shown in FIG. 3, the gate electrode 14a is provided on the gate insulating film 13 so as to overlap the channel region of the semiconductor layer 12a. Further, as shown in FIG. 3, the first interlayer insulating film 15 and the second interlayer insulating film 17 are sequentially provided so as to cover the gate electrode 14a. The source electrode 18a and the drain electrode 18b are provided on the second interlayer insulating film 17 so as to be separated from each other, as shown in FIG. Further, as shown in FIG. 3, the source electrode 18a and the drain electrode 18b are connected via respective contact holes formed in a laminated film of the gate insulating film 13, the first interlayer insulating film 15 and the second interlayer insulating film 17, It is electrically connected to the source region and the drain region of the semiconductor layer 12a, respectively. Note that the gate insulating film 13, the first interlayer insulating film 15, and the second interlayer insulating film 17 are each formed of a single-layer film or a laminated film of an inorganic insulating film such as silicon nitride, silicon oxide, or silicon oxynitride. .
第２ＴＦＴ９ｂは、図４に示すように、各サブ画素Ｐにおいて、対応する第１ＴＦＴ９ａ及び電源線１８ｇに電気的に接続されている。また、第１ＴＦＴ９ｂは、図３に示すように、ベースコート膜１１上に順に設けられた半導体層１２ｂ、ゲート絶縁膜１３、ゲート電極１４ｂ、第１層間絶縁膜１５、第２層間絶縁膜１７、並びにソース電極１８ｃ及びドレイン電極１８ｄを備えている。ここで、半導体層１２ｂは、図３に示すように、ベースコート膜１１上に島状に設けられ、半導体層１２ａと同様に、チャネル領域、ソース領域及びドレイン領域を有している。また、ゲート絶縁膜１３は、図３に示すように、半導体層１２ｂを覆うように設けられている。また、ゲート電極１４ｂは、図３に示すように、ゲート絶縁膜１３上に半導体層１２ｂのチャネル領域と重なるように設けられている。また、第１層間絶縁膜１５及び第２層間絶縁膜１７は、図３に示すように、ゲート電極１４ｂを覆うように順に設けられている。また、ソース電極１８ｃ及びドレイン電極１８ｄは、図３に示すように、第２層間絶縁膜１７上に互いに離間するように設けられている。また、ソース電極１８ｃ及びドレイン電極１８ｄは、図３に示すように、ゲート絶縁膜１３、第１層間絶縁膜１５及び第２層間絶縁膜１７の積層膜に形成された各コンタクトホールを介して、半導体層１２ｂのソース領域及びドレイン領域にそれぞれ電気的に接続されている。
(4) As shown in FIG. 4, the second TFT 9b is electrically connected to the corresponding first TFT 9a and the power supply line 18g in each sub-pixel P. As shown in FIG. 3, the first TFT 9b includes a semiconductor layer 12b, a gate insulating film 13, a gate electrode 14b, a first interlayer insulating film 15, a second interlayer insulating film 17, and a semiconductor layer 12b sequentially provided on the base coat film 11. It has a source electrode 18c and a drain electrode 18d. Here, as shown in FIG. 3, the semiconductor layer 12b is provided in an island shape on the base coat film 11, and has a channel region, a source region, and a drain region, like the semiconductor layer 12a. Further, as shown in FIG. 3, the gate insulating film 13 is provided so as to cover the semiconductor layer 12b. Further, as shown in FIG. 3, the gate electrode 14b is provided on the gate insulating film 13 so as to overlap the channel region of the semiconductor layer 12b. Further, as shown in FIG. 3, the first interlayer insulating film 15 and the second interlayer insulating film 17 are sequentially provided so as to cover the gate electrode 14b. The source electrode 18c and the drain electrode 18d are provided on the second interlayer insulating film 17 so as to be separated from each other, as shown in FIG. In addition, as shown in FIG. 3, the source electrode 18c and the drain electrode 18d are connected via respective contact holes formed in a stacked film of the gate insulating film 13, the first interlayer insulating film 15 and the second interlayer insulating film 17, It is electrically connected to the source region and the drain region of the semiconductor layer 12b, respectively.
なお、本実施形態では、トップゲート型の第１ＴＦＴ９ａ及び第２ＴＦＴ９ｂを例示したが、第１ＴＦＴ９ａ及び第２ＴＦＴ９ｂは、ボトムゲート型であってもよい。
In the present embodiment, the first TFT 9a and the second TFT 9b of the top gate type are illustrated, but the first TFT 9a and the second TFT 9b may be of the bottom gate type.
キャパシタ９ｃは、図４に示すように、各サブ画素Ｐにおいて、対応する第１ＴＦＴ９ａ及び電源線１８ｇに電気的に接続されている。ここで、キャパシタ９ｃは、図３に示すように、ゲート線１４等と同一層に同一材料により形成された下部導電層１４ｃと、下部導電層１４ｃを覆うように設けられた第１層間絶縁膜１５と、第１層間絶縁膜１５上に下部導電層１４ｃと重なるように設けられた上部導電層１６とを備えている。なお、上部導電層１６は、図３に示すように、第２層間絶縁膜１７に形成されたコンタクトホールを介して電源線１８ｇに電気的に接続されている。
As shown in FIG. 4, the capacitor 9c is electrically connected to the corresponding first TFT 9a and the power supply line 18g in each sub-pixel P. Here, as shown in FIG. 3, the capacitor 9c includes a lower conductive layer 14c formed of the same material on the same layer as the gate line 14 and the like, and a first interlayer insulating film provided to cover the lower conductive layer 14c. 15 and an upper conductive layer 16 provided on the first interlayer insulating film 15 so as to overlap the lower conductive layer 14c. Note that, as shown in FIG. 3, the upper conductive layer 16 is electrically connected to a power supply line 18g via a contact hole formed in the second interlayer insulating film 17.
平坦化膜１９は、表示領域Ｄにおいて平坦な表面を有し、例えば、ポリイミド樹脂等の有機樹脂材料により構成されている。なお、本実施形態では、ポリイミド樹脂製の平坦化膜１９を例示したが、平坦化膜１９は、アクリル樹脂やポリシロキサン樹脂等の有機樹脂材料により構成されていてもよい。
The flattening film 19 has a flat surface in the display region D, and is made of, for example, an organic resin material such as a polyimide resin. In the present embodiment, the flattening film 19 made of a polyimide resin is exemplified, but the flattening film 19 may be made of an organic resin material such as an acrylic resin or a polysiloxane resin.
有機ＥＬ素子２５は、図３に示すように、ＴＦＴ層２０上に順に設けられた複数の第１電極２１ａ、エッジカバー２２ａ、複数の有機ＥＬ層２３及び第２電極２４を備えている。
(3) As shown in FIG. 3, the organic EL element 25 includes a plurality of first electrodes 21a, an edge cover 22a, a plurality of organic EL layers 23, and a second electrode 24 which are sequentially provided on the TFT layer 20.
複数の第１電極２１ａは、図３に示すように、複数のサブ画素Ｐに対応するように、平坦化膜１９上にマトリクス状に陽極として設けられている。ここで、第１電極２１ａは、図３に示すように、平坦化膜１９に形成されたコンタクトホールを介して、各第２ＴＦＴ９ｂのドレイン電極１８ｄに電気的に接続されている。また、第１電極２１ａは、有機ＥＬ層２３にホール（正孔）を注入する機能を有している。また、第１電極２１ａは、有機ＥＬ層２３への正孔注入効率を向上させるために、仕事関数の大きな材料で形成するのがより好ましい。ここで、第１電極２１ａを構成する材料としては、例えば、銀（Ａｇ）、アルミニウム（Ａｌ）、バナジウム（Ｖ）、コバルト（Ｃｏ）、ニッケル（Ｎｉ）、タングステン（Ｗ）、金（Ａｕ）、チタン（Ｔｉ）、ルテニウム（Ｒｕ）、マンガン（Ｍｎ）、インジウム（Ｉｎ）、イッテルビウム（Ｙｂ）、フッ化リチウム（ＬｉＦ）、白金（Ｐｔ）、パラジウム（Ｐｄ）、モリブデン（Ｍｏ）、イリジウム（Ｉｒ）、スズ（Ｓｎ）等の金属材料が挙げられる。また、第１電極２１ａを構成する材料は、例えば、アスタチン（Ａｔ）／酸化アスタチン（ＡｔＯ２）等の合金であっても構わない。さらに、第１電極２１ａを構成する材料は、例えば、酸化スズ（ＳｎＯ）、酸化亜鉛（ＺｎＯ）、インジウムスズ酸化物（ＩＴＯ）、インジウム亜鉛酸化物（ＩＺＯ）のような導電性酸化物等であってもよい。また、第１電極２１ａは、上記材料からなる層を複数積層して形成されていてもよい。なお、仕事関数の大きな化合物材料としては、例えば、インジウムスズ酸化物（ＩＴＯ）やインジウム亜鉛酸化物（ＩＺＯ）等が挙げられる。
As shown in FIG. 3, the plurality of first electrodes 21a are provided as anodes in a matrix on the planarization film 19 so as to correspond to the plurality of sub-pixels P. Here, as shown in FIG. 3, the first electrode 21a is electrically connected to the drain electrode 18d of each second TFT 9b via a contact hole formed in the flattening film 19. Further, the first electrode 21a has a function of injecting holes (holes) into the organic EL layer 23. Further, the first electrode 21a is more preferably formed of a material having a large work function in order to improve the efficiency of hole injection into the organic EL layer 23. Here, as a material forming the first electrode 21a, for example, silver (Ag), aluminum (Al), vanadium (V), cobalt (Co), nickel (Ni), tungsten (W), gold (Au) , Titanium (Ti), ruthenium (Ru), manganese (Mn), indium (In), ytterbium (Yb), lithium fluoride (LiF), platinum (Pt), palladium (Pd), molybdenum (Mo), iridium ( Metal materials such as Ir) and tin (Sn). Further, the material forming the first electrode 21a may be an alloy such as astatine (At) / astatin oxide (AtO 2 ). Further, the material forming the first electrode 21a is, for example, a conductive oxide such as tin oxide (SnO), zinc oxide (ZnO), indium tin oxide (ITO), and indium zinc oxide (IZO). There may be. Further, the first electrode 21a may be formed by stacking a plurality of layers made of the above materials. Note that examples of the compound material having a large work function include indium tin oxide (ITO) and indium zinc oxide (IZO).
エッジカバー２２ａは、図３及び図８に示すように、表示領域Ｄにおいて、各第１電極２１ａの周端部を覆うように格子状に設けられている。また、エッジカバー２２ａは、図３及び図８に示すように、表示領域Ｄにおいて、各第１電極２１ａを露出させるようにマトリクス状に設けられた複数の第１開口部Ｈａを備えている。また、エッジカバー２２ａは、図３及び図８に示すように、表示領域Ｄにおいて、複数の第１開口部Ｈａの間で封止膜３０側の表面に突出するように設けられた複数の第１スペーサＣａを備えている。ここで、エッジカバー２２ａを構成する材料としては、例えば、ポリイミド樹脂、アクリル樹脂、ポリシロキサン樹脂等の有機膜が挙げられる。
(3) The edge cover 22a is provided in a lattice shape so as to cover the peripheral end of each first electrode 21a in the display area D, as shown in FIGS. Further, as shown in FIGS. 3 and 8, the edge cover 22a includes a plurality of first openings Ha provided in a matrix so as to expose each first electrode 21a in the display area D. Further, as shown in FIGS. 3 and 8, the edge cover 22 a includes a plurality of first covers provided in the display area D so as to protrude to the surface on the sealing film 30 side between the plurality of first openings Ha. One spacer Ca is provided. Here, examples of a material forming the edge cover 22a include an organic film such as a polyimide resin, an acrylic resin, and a polysiloxane resin.
複数の有機ＥＬ層２３は、図３に示すように、エッジカバー２２ａの各第１開口部Ｈａから露出する各第１電極２１ａ上に配置され、複数のサブ画素Ｐに対応するように、マトリクス状に発光素子層として設けられている。ここで、各有機ＥＬ層２３は、図５に示すように、第１電極２１ａ上に順に設けられた正孔注入層１、正孔輸送層２、発光層３、電子輸送層４及び電子注入層５を備えている。
As shown in FIG. 3, the plurality of organic EL layers 23 are arranged on each first electrode 21a exposed from each first opening Ha of the edge cover 22a, and are arranged in a matrix so as to correspond to the plurality of sub-pixels P. It is provided as a light emitting element layer. Here, as shown in FIG. 5, each of the organic EL layers 23 includes a hole injection layer 1, a hole transport layer 2, a light emitting layer 3, an electron transport layer 4, and an electron injection layer provided in this order on the first electrode 21a. It has a layer 5.
正孔注入層１は、陽極バッファ層とも呼ばれ、第１電極２１ａと有機ＥＬ層２３とのエネルギーレベルを近づけ、第１電極２１ａから有機ＥＬ層２３への正孔注入効率を改善する機能を有している。ここで、正孔注入層１を構成する材料としては、例えば、トリアゾール誘導体、オキサジアゾール誘導体、イミダゾール誘導体、ポリアリールアルカン誘導体、ピラゾリン誘導体、フェニレンジアミン誘導体、オキサゾール誘導体、スチリルアントラセン誘導体、フルオレノン誘導体、ヒドラゾン誘導体、スチルベン誘導体等が挙げられる。
The hole injection layer 1 is also called an anode buffer layer, and has a function of making the energy levels of the first electrode 21a and the organic EL layer 23 close to each other and improving the efficiency of hole injection from the first electrode 21a to the organic EL layer 23. Have. Here, as a material constituting the hole injection layer 1, for example, a triazole derivative, an oxadiazole derivative, an imidazole derivative, a polyarylalkane derivative, a pyrazoline derivative, a phenylenediamine derivative, an oxazole derivative, a styrylanthracene derivative, a fluorenone derivative, Hydrazone derivatives, stilbene derivatives and the like can be mentioned.
正孔輸送層２は、第１電極２１ａから有機ＥＬ層２３への正孔の輸送効率を向上させる機能を有している。ここで、正孔輸送層２を構成する材料としては、例えば、ポルフィリン誘導体、芳香族第三級アミン化合物、スチリルアミン誘導体、ポリビニルカルバゾール、ポリ－ｐ－フェニレンビニレン、ポリシラン、トリアゾール誘導体、オキサジアゾール誘導体、イミダゾール誘導体、ポリアリールアルカン誘導体、ピラゾリン誘導体、ピラゾロン誘導体、フェニレンジアミン誘導体、アリールアミン誘導体、アミン置換カルコン誘導体、オキサゾール誘導体、スチリルアントラセン誘導体、フルオレノン誘導体、ヒドラゾン誘導体、スチルベン誘導体、水素化アモルファスシリコン、水素化アモルファス炭化シリコン、硫化亜鉛、セレン化亜鉛等が挙げられる。
The hole transport layer 2 has a function of improving the efficiency of transporting holes from the first electrode 21a to the organic EL layer 23. Here, examples of the material constituting the hole transport layer 2 include a porphyrin derivative, an aromatic tertiary amine compound, a styrylamine derivative, polyvinyl carbazole, poly-p-phenylene vinylene, polysilane, a triazole derivative, and oxadiazole. Derivatives, imidazole derivatives, polyarylalkane derivatives, pyrazoline derivatives, pyrazolone derivatives, phenylenediamine derivatives, arylamine derivatives, amine-substituted chalcone derivatives, oxazole derivatives, styrylanthracene derivatives, fluorenone derivatives, hydrazone derivatives, stilbene derivatives, hydrogenated amorphous silicon, Examples include hydrogenated amorphous silicon carbide, zinc sulfide, and zinc selenide.
発光層３は、第１電極２１ａ及び第２電極２４による電圧印加の際に、第１電極２１ａ及び第２電極２４から正孔及び電子がそれぞれ注入されると共に、正孔及び電子が再結合する領域である。ここで、発光層３は、発光効率が高い材料により形成されている。そして、発光層３を構成する材料としては、例えば、金属オキシノイド化合物［８－ヒドロキシキノリン金属錯体］、ナフタレン誘導体、アントラセン誘導体、ジフェニルエチレン誘導体、ビニルアセトン誘導体、トリフェニルアミン誘導体、ブタジエン誘導体、クマリン誘導体、ベンズオキサゾール誘導体、オキサジアゾール誘導体、オキサゾール誘導体、ベンズイミダゾール誘導体、チアジアゾール誘導体、ベンズチアゾール誘導体、スチリル誘導体、スチリルアミン誘導体、ビススチリルベンゼン誘導体、トリススチリルベンゼン誘導体、ペリレン誘導体、ペリノン誘導体、アミノピレン誘導体、ピリジン誘導体、ローダミン誘導体、アクイジン誘導体、フェノキサゾン、キナクリドン誘導体、ルブレン、ポリ－ｐ－フェニレンビニレン、ポリシラン等が挙げられる。
In the light emitting layer 3, when a voltage is applied by the first electrode 21a and the second electrode 24, holes and electrons are injected from the first electrode 21a and the second electrode 24, respectively, and the holes and electrons recombine. Area. Here, the light emitting layer 3 is formed of a material having high luminous efficiency. Examples of the material constituting the light emitting layer 3 include a metal oxinoid compound [8-hydroxyquinoline metal complex], a naphthalene derivative, an anthracene derivative, a diphenylethylene derivative, a vinylacetone derivative, a triphenylamine derivative, a butadiene derivative, and a coumarin derivative. , Benzoxazole derivative, oxadiazole derivative, oxazole derivative, benzimidazole derivative, thiadiazole derivative, benzothiazole derivative, styryl derivative, styrylamine derivative, bisstyrylbenzene derivative, tristyrylbenzene derivative, perylene derivative, perinone derivative, aminopyrene derivative, Pyridine derivative, rhodamine derivative, aquidin derivative, phenoxazone, quinacridone derivative, rubrene, poly-p-phenylene vinylene , Polysilane, and the like.
電子輸送層４は、電子を発光層３まで効率良く移動させる機能を有している。ここで、電子輸送層４を構成する材料としては、例えば、有機化合物として、オキサジアゾール誘導体、トリアゾール誘導体、ベンゾキノン誘導体、ナフトキノン誘導体、アントラキノン誘導体、テトラシアノアントラキノジメタン誘導体、ジフェノキノン誘導体、フルオレノン誘導体、シロール誘導体、金属オキシノイド化合物等が挙げられる。
(4) The electron transport layer 4 has a function of efficiently moving electrons to the light emitting layer 3. Here, as a material constituting the electron transport layer 4, for example, as an organic compound, an oxadiazole derivative, a triazole derivative, a benzoquinone derivative, a naphthoquinone derivative, an anthraquinone derivative, a tetracyanoanthraquinodimethane derivative, a diphenoquinone derivative, a fluorenone derivative , Silole derivatives, metal oxinoid compounds and the like.
電子注入層５は、第２電極２４と有機ＥＬ層２３とのエネルギーレベルを近づけ、第２電極２４から有機ＥＬ層２３へ電子が注入される効率を向上させる機能を有し、この機能により、有機ＥＬ素子２５の駆動電圧を下げることができる。なお、電子注入層５は、陰極バッファ層とも呼ばれる。ここで、電子注入層５を構成する材料としては、例えば、フッ化リチウム（ＬｉＦ）、フッ化マグネシウム（ＭｇＦ２）、フッ化カルシウム（ＣａＦ２）、フッ化ストロンチウム（ＳｒＦ２）、フッ化バリウム（ＢａＦ２）のような無機アルカリ化合物、酸化アルミニウム（Ａｌ２Ｏ３）、酸化ストロンチウム（ＳｒＯ）等が挙げられる。
The electron injection layer 5 has a function of making the energy levels of the second electrode 24 and the organic EL layer 23 close to each other and improving the efficiency of injecting electrons from the second electrode 24 into the organic EL layer 23. The drive voltage of the organic EL element 25 can be reduced. Note that the electron injection layer 5 is also called a cathode buffer layer. Here, as a material constituting the electron injection layer 5, for example, lithium fluoride (LiF), magnesium fluoride (MgF 2 ), calcium fluoride (CaF 2 ), strontium fluoride (SrF 2 ), barium fluoride Examples thereof include an inorganic alkali compound such as (BaF 2 ), aluminum oxide (Al 2 O 3 ), and strontium oxide (SrO).
第２電極２４は、図３に示すように、各有機ＥＬ層２３及びエッジカバー２２ａを覆うように陰極として設けられている。また、第２電極２４は、有機ＥＬ層２３に電子を注入する機能を有している。また、第２電極２４は、有機ＥＬ層２３への電子注入効率を向上させるために、仕事関数の小さな材料で構成するのがより好ましい。ここで、第２電極２４を構成する材料としては、例えば、銀（Ａｇ）、アルミニウム（Ａｌ）、バナジウム（Ｖ）、カルシウム（Ｃａ）、チタン（Ｔｉ）、イットリウム（Ｙ）、ナトリウム（Ｎａ）、マンガン（Ｍｎ）、インジウム（Ｉｎ）、マグネシウム（Ｍｇ）、リチウム（Ｌｉ）、イッテルビウム（Ｙｂ）、フッ化リチウム（ＬｉＦ）等が挙げられる。また、第２電極２４は、例えば、マグネシウム（Ｍｇ）／銅（Ｃｕ）、マグネシウム（Ｍｇ）／銀（Ａｇ）、ナトリウム（Ｎａ）／カリウム（Ｋ）、アスタチン（Ａｔ）／酸化アスタチン（ＡｔＯ２）、リチウム（Ｌｉ）／アルミニウム（Ａｌ）、リチウム（Ｌｉ）／カルシウム（Ｃａ）／アルミニウム（Ａｌ）、フッ化リチウム（ＬｉＦ）／カルシウム（Ｃａ）／アルミニウム（Ａｌ）等の合金により形成されていてもよい。また、第２電極２４は、例えば、酸化スズ（ＳｎＯ）、酸化亜鉛（ＺｎＯ）、インジウムスズ酸化物（ＩＴＯ）、インジウム亜鉛酸化物（ＩＺＯ）等の導電性酸化物により形成されていてもよい。また、第２電極２４は、上記材料からなる層を複数積層して形成されていてもよい。なお、仕事関数が小さい材料としては、例えば、マグネシウム（Ｍｇ）、リチウム（Ｌｉ）、フッ化リチウム（ＬｉＦ）、マグネシウム（Ｍｇ）／銅（Ｃｕ）、マグネシウム（Ｍｇ）／銀（Ａｇ）、ナトリウム（Ｎａ）／カリウム（Ｋ）、リチウム（Ｌｉ）／アルミニウム（Ａｌ）、リチウム（Ｌｉ）／カルシウム（Ｃａ）／アルミニウム（Ａｌ）、フッ化リチウム（ＬｉＦ）／カルシウム（Ｃａ）／アルミニウム（Ａｌ）等が挙げられる。
As shown in FIG. 3, the second electrode 24 is provided as a cathode so as to cover each organic EL layer 23 and the edge cover 22a. The second electrode 24 has a function of injecting electrons into the organic EL layer 23. It is more preferable that the second electrode 24 be made of a material having a small work function in order to improve the efficiency of injecting electrons into the organic EL layer 23. Here, as a material constituting the second electrode 24, for example, silver (Ag), aluminum (Al), vanadium (V), calcium (Ca), titanium (Ti), yttrium (Y), sodium (Na) , Manganese (Mn), indium (In), magnesium (Mg), lithium (Li), ytterbium (Yb), lithium fluoride (LiF) and the like. The second electrode 24 is made of, for example, magnesium (Mg) / copper (Cu), magnesium (Mg) / silver (Ag), sodium (Na) / potassium (K), astatine (At) / astatin oxide (AtO 2). ), Lithium (Li) / aluminum (Al), lithium (Li) / calcium (Ca) / aluminum (Al), and lithium fluoride (LiF) / calcium (Ca) / aluminum (Al). You may. The second electrode 24 may be formed of a conductive oxide such as tin oxide (SnO), zinc oxide (ZnO), indium tin oxide (ITO), and indium zinc oxide (IZO), for example. . Further, the second electrode 24 may be formed by stacking a plurality of layers made of the above materials. Examples of the material having a small work function include magnesium (Mg), lithium (Li), lithium fluoride (LiF), magnesium (Mg) / copper (Cu), magnesium (Mg) / silver (Ag), and sodium. (Na) / potassium (K), lithium (Li) / aluminum (Al), lithium (Li) / calcium (Ca) / aluminum (Al), lithium fluoride (LiF) / calcium (Ca) / aluminum (Al) And the like.
封止膜３０は、図３に示すように、第２電極２４を覆うように設けられ、第２電極２４上に順に積層された第１無機膜２６、有機膜２７及び第２無機膜２８を備え、有機ＥＬ素子２５の有機ＥＬ層２３を水分や酸素から保護する機能を有している。
As shown in FIG. 3, the sealing film 30 is provided so as to cover the second electrode 24, and the first inorganic film 26, the organic film 27, and the second inorganic film 28 which are sequentially stacked on the second electrode 24 are formed. And has a function of protecting the organic EL layer 23 of the organic EL element 25 from moisture and oxygen.
第１無機膜２６及び第２無機膜２８は、例えば、窒化シリコン膜、酸化シリコン膜、酸窒化シリコン膜等の無機絶縁膜により構成されている。
The first inorganic film 26 and the second inorganic film 28 are made of, for example, an inorganic insulating film such as a silicon nitride film, a silicon oxide film, and a silicon oxynitride film.
有機膜２７は、例えば、アクリル樹脂、エポキシ樹脂、シリコーン樹脂、ポリ尿素樹脂、パリレン樹脂、ポリイミド樹脂、ポリアミド樹脂等の有機樹脂材料により構成されている。
The organic film 27 is made of, for example, an organic resin material such as an acrylic resin, an epoxy resin, a silicone resin, a polyurea resin, a parylene resin, a polyimide resin, and a polyamide resin.
また、有機ＥＬ表示装置５０は、図６及び図７に示すように、額縁領域Ｆにおいて、樹脂基板層１０と、樹脂基板層１０上に設けられたＴＦＴ層２０と、ＴＦＴ層２０上に順に設けられた周辺電極２１ｂ、エッジカバー２２ａ及び第２電極２４と、ＴＦＴ層２０の周端部に設けられた第１堰き止め壁Ｗａ及び第２堰き止め壁Ｗｂと、第２電極２４、第１堰き止め壁Ｗａ及び第２堰き止め壁Ｗｂを覆うように設けられた封止膜３０とを備えている。
6 and 7, in the frame region F, the organic EL display device 50 includes the resin substrate layer 10, the TFT layer 20 provided on the resin substrate layer 10, and the TFT layer 20 sequentially. The provided peripheral electrode 21b, the edge cover 22a and the second electrode 24, the first and second blocking walls Wa and Wb provided on the peripheral end of the TFT layer 20, the second electrode 24, the first A sealing film 30 provided so as to cover the blocking wall Wa and the second blocking wall Wb.
ＴＦＴ層２０は、図６及び図７に示すように、額縁領域Ｆにおいて、トレンチＧａの表示領域Ｄ側に設けられた駆動回路用ＴＦＴ９ｄと、トレンチＧａのスリットＳ側に設けられた駆動回路用ＴＦＴ９ｅとを備えている。ここで、駆動回路用ＴＦＴ９ｄ及び９ｅは、図６及び図７に示すように、ゲート導電層１４ｄを介して互いに電気的に接続されている。なお、図６及び図７では、駆動回路用ＴＦＴ９ｄ及び９ｅが互いに電気的に接続された回路構成を例示したが、駆動回路用ＴＦＴ９ｄ及び９ｅは、互いに電気的に接続されていなくてもよい。また、駆動回路用ＴＦＴ９ｄは、例えば、ゲートドライバ回路等を構成し、駆動回路用ＴＦＴ９ｅは、例えば、発光制御回路等を構成している。
As shown in FIGS. 6 and 7, in the frame region F, the TFT layer 20 includes a driving circuit TFT 9d provided on the display region D side of the trench Ga and a driving circuit TFT 9d provided on the slit S side of the trench Ga. And a TFT 9e. Here, the drive circuit TFTs 9d and 9e are electrically connected to each other via the gate conductive layer 14d as shown in FIGS. 6 and 7 illustrate the circuit configuration in which the driving circuit TFTs 9d and 9e are electrically connected to each other, but the driving circuit TFTs 9d and 9e may not be electrically connected to each other. The drive circuit TFT 9d constitutes, for example, a gate driver circuit and the like, and the drive circuit TFT 9e constitutes, for example, a light emission control circuit and the like.
周辺電極２１ｂは、図１、図６及び図７に示すように、額縁領域Ｆにおいて、ＴＦＴ層２０上にトレンチＧａ及びスリットＳ（第１スリットＳａ、第２スリットＳｂ）を覆うように略Ｃ字状に設けられている。ここで、スリットＳは、図７に示すように、表示領域Ｄ側に枠状に設けられて平坦化膜１９を貫通する第１スリットＳａと、第１スリットＳａを囲むように枠状に設けられて平坦化膜１９を貫通する第２スリットＳｂとを備えている。また、周辺電極２１ｂは、図６に示すように、後述するように、エッジカバー２２ａの第２開口部Ｈｂ等を介して第２電極２４に接触して、第２電極２４に低電源電圧が入力されるように構成されている。また、周辺電極２１ｂは、第１電極２１ａと同一層に同一材料により形成されている。また、周辺電極２１ｂは、図７に示すように、第１スリットＳａ及び第２スリットＳｂを介して、ソース線１８ｆ等と同一層に同一材料により形成されたソース導電層１８ｈに電気的に接続されている。なお、ソース導電層１８ｈは、例えば、枠状に設けられ、端子部Ｔに沿った辺の一部が端子部Ｔに延伸され、端子部Ｔで低電源電圧が入力されるように構成されている。
As shown in FIGS. 1, 6, and 7, the peripheral electrode 21b is substantially C-shaped so as to cover the trench Ga and the slit S (the first slit Sa and the second slit Sb) on the TFT layer 20 in the frame region F. It is provided in a character shape. Here, as shown in FIG. 7, the slit S is provided in a frame shape on the display area D side and penetrates the flattening film 19, and is provided in a frame shape so as to surround the first slit Sa. And a second slit Sb penetrating the flattening film 19. As shown in FIG. 6, the peripheral electrode 21b contacts the second electrode 24 via a second opening Hb or the like of the edge cover 22a as described later, and a low power supply voltage is applied to the second electrode 24. It is configured to be input. The peripheral electrode 21b is formed of the same material in the same layer as the first electrode 21a. As shown in FIG. 7, the peripheral electrode 21b is electrically connected to the source conductive layer 18h formed of the same material as the source line 18f and the like through the first slit Sa and the second slit Sb. Have been. Note that the source conductive layer 18h is provided, for example, in a frame shape, a part of a side along the terminal portion T is extended to the terminal portion T, and a low power supply voltage is input to the terminal portion T. I have.
エッジカバー２２ａは、図６～図８に示すように、額縁領域Ｆにおいて、周辺電極２１ｂ上に設けられ、複数の第１開口部Ｈａと同一形状で同一ピッチに形成された複数の第２開口部Ｈｂと、複数の第２開口部Ｈｂの間で封止膜３０側の表面に突出するように設けられた複数の第２柱状スペーサＣｂとを備えている。ここで、額縁領域Ｆにおける第２開口部Ｈｂと第２柱状スペーサＣｂとの距離Ｘｂ及びＹｂは、図８に示すように、表示領域Ｄにおける第１開口部Ｈａと第１柱状スペーサＣａとの距離Ｘａ及びＹａとそれぞれ等しくなっている。また、額縁領域Ｆにおける隣り合う第２開口部Ｈｂ同士間の間隔Ｘｄ及びＹｄは、図８に示すように、表示領域Ｄにおける第１開口部Ｈａ同士間の間隔Ｘｃ及びＹｃとそれぞれ等しくなっている。すなわち、額縁領域Ｆにおける第２開口部Ｈｂと第２柱状スペーサＣｂとの位置関係は、表示領域Ｄにおける第１開口部Ｈａと第１柱状スペーサＣａとの位置関係と等しくなるように設定されている。また、複数の第２柱状スペーサＣｂのピッチは、図８に示すように、複数の第２開口部Ｈｂのピッチよりも大きくなっている。また、複数の第２開口部Ｈｂ及び複数の第２柱状スペーサＣｂは、図６～図８に示すように、表示領域ＤとトレンチＧｂの間に設けられていると共に、トレンチＧｂと第１スリットＳａとの間に設けられている。なお、表示領域ＤとトレンチＧｂの間に配置された第２開口部Ｈｂの配置密度は、トレンチＧｂと第１スリットＳａとの間に配置された第２開口部Ｈｂの配置密度と等しくなっていてもよい。また、上記「同一形状で同一ピッチ」とは、第１開口部Ｈａ及び第２開口部Ｈｂが同じマスクパターンを用いてパターニングされることを意味し、感光性樹脂を露光及び現像する際のばらつき、感光性樹脂を焼成する際の熱だれ等によって形状やピッチが厳密に一致せず実質的に一致することを含んでいる。
As shown in FIGS. 6 to 8, the edge cover 22a is provided on the peripheral electrode 21b in the frame region F, and has a plurality of second openings formed in the same shape and at the same pitch as the plurality of first openings Ha. A portion Hb and a plurality of second columnar spacers Cb are provided between the plurality of second openings Hb so as to protrude from the surface on the sealing film 30 side. Here, the distances Xb and Yb between the second opening Hb and the second columnar spacer Cb in the frame region F are, as shown in FIG. 8, the distance between the first opening Ha and the first columnar spacer Ca in the display region D. They are equal to the distances Xa and Ya, respectively. 8, the intervals Xd and Yd between the adjacent second openings Hb in the frame area F are equal to the intervals Xc and Yc between the first openings Ha in the display area D, respectively, as shown in FIG. I have. That is, the positional relationship between the second opening Hb and the second columnar spacer Cb in the frame region F is set to be equal to the positional relationship between the first opening Ha and the first columnar spacer Ca in the display region D. I have. Further, as shown in FIG. 8, the pitch of the plurality of second columnar spacers Cb is larger than the pitch of the plurality of second openings Hb. Further, the plurality of second openings Hb and the plurality of second columnar spacers Cb are provided between the display region D and the trench Gb, as shown in FIGS. And Sa. The arrangement density of the second openings Hb arranged between the display area D and the trench Gb is equal to the arrangement density of the second openings Hb arranged between the trench Gb and the first slit Sa. You may. Further, “the same shape and the same pitch” means that the first opening Ha and the second opening Hb are patterned using the same mask pattern, and the variation in the exposure and development of the photosensitive resin. This includes that the shapes and pitches do not exactly match but substantially match due to heat dripping or the like when baking the photosensitive resin.
なお、本実施形態では、エッジカバー２２ａの各第２開口部Ｈｂから周辺電極２１ｂが露出する構成を例示したが、図９に示すように、エッジカバー２２ａの各第２開口部Ｈｂから周辺電極２１ｃが露出しない構成であってもよい。ここで、図９は、有機ＥＬ表示装置５０を構成するエッジカバー２２ａ及び周辺電極２１ｂの変形例である周辺電極２１ｃの平面図である。この変形例において、周辺電極２１ｃは、図９に示すように、各第２開口部Ｈｂの周端よりも外側に周端が配置する開口部Ｈｃを有しており、エッジカバー２２ａから露出しないように設けられているので、外光による反射の影響を抑制することができる。
In the present embodiment, the configuration in which the peripheral electrode 21b is exposed from each of the second openings Hb of the edge cover 22a is illustrated. However, as shown in FIG. 9, the peripheral electrode 21b is formed from each of the second openings Hb of the edge cover 22a. The configuration may be such that 21c is not exposed. Here, FIG. 9 is a plan view of a peripheral electrode 21c which is a modified example of the edge cover 22a and the peripheral electrode 21b constituting the organic EL display device 50. In this modification, as shown in FIG. 9, the peripheral electrode 21c has an opening Hc whose peripheral end is disposed outside the peripheral end of each second opening Hb, and is not exposed from the edge cover 22a. As a result, the influence of reflection by external light can be suppressed.
第２電極２４は、図６及び図７に示すように、最外周の第２柱状スペーサＣｂの内側まで延設され、エッジカバー２２ａに形成された複数の第２開口部Ｈｂ及びトレンチＧｂ、並びに平坦化膜１９に形成されたトレンチＧａを介して、周辺電極２１ｂに電気的に接続されている。ここで、トレンチＧａの底部には、図６及び図７に示すように、第２電極２４と周辺電極２１ｂとの電気的な接続をより確実にするために、ソース線１８ｆ等と同一層に同一材料により形成されたソース導電層１８ｅが設けられている。
As shown in FIGS. 6 and 7, the second electrode 24 extends to the inside of the outermost second columnar spacer Cb, and includes a plurality of second openings Hb and trenches Gb formed in the edge cover 22a, and It is electrically connected to the peripheral electrode 21b via the trench Ga formed in the planarization film 19. Here, on the bottom of the trench Ga, as shown in FIGS. 6 and 7, in order to further secure the electrical connection between the second electrode 24 and the peripheral electrode 21b, the same layer as the source line 18f and the like is used. A source conductive layer 18e formed of the same material is provided.
第１堰き止め壁Ｗａは、図７に示すように、表示領域Ｄを囲むように枠状に設けられ、封止膜３０の有機膜２７の拡がりを抑制するように構成されている。ここで、第１堰き止め壁Ｗａは、図７に示すように、第１スリットＳａ及び第２スリットＳｂの間に配置する平坦化膜１９の一部と、その平坦化膜１９の一部上に周辺電極２１ｂを介して設けられ、エッジカバー２２ａと同一層に同一材料により形成された樹脂層２２ｂとを備えている。
The first dam wall Wa is provided in a frame shape so as to surround the display area D, as shown in FIG. 7, and is configured to suppress the spread of the organic film 27 of the sealing film 30. Here, as shown in FIG. 7, the first dam wall Wa is formed on a part of the flattening film 19 disposed between the first slit Sa and the second slit Sb, and on a part of the flattening film 19. And a resin layer 22b formed of the same material on the same layer as the edge cover 22a.
第２堰き止め壁Ｗｂは、図７に示すように、第１堰き止め壁Ｗａを囲むように枠状に設けられている。ここで、第２堰き止め壁Ｗｂは、図７に示すように、第２スリットＳｂの外側に配置する平坦化膜１９の一部と、その平坦化膜１９の一部上に周辺電極２１ｂを介して設けられ、エッジカバー２２ａと同一層に同一材料により形成された樹脂層２２ｃとを備えている。
The second dam wall Wb is provided in a frame shape so as to surround the first dam wall Wa, as shown in FIG. Here, as shown in FIG. 7, the second dam wall Wb includes a part of the flattening film 19 disposed outside the second slit Sb and a peripheral electrode 21 b on a part of the flattening film 19. And a resin layer 22c formed of the same material on the same layer as the edge cover 22a.
封止膜３０を構成する有機膜２７は、図７に示すように、額縁領域Ｆにおいて、第１無機膜２６を介して、第１堰き止め壁Ｗａまで設けられている。なお、本実施形態では、有機膜２７が第１堰き止め壁Ｗａの表示領域Ｄ側の側面で堰き止められた構成を例示したが、有機膜２７は、例えば、第２堰き止め壁Ｗｂの上面まで到達していてもよい。また、封止膜３０を構成して額縁領域Ｆで積層された第１無機膜２７及び第２無機膜２８の積層膜は、図７に示すように、第２堰き止め壁Ｗｂの外側において、第２層間絶縁膜１７に接触し、ＴＦＴ層２０を構成する無機絶縁膜の少なくとも１つに接触している。
(7) The organic film 27 constituting the sealing film 30 is provided in the frame region F through the first inorganic film 26 to the first dam wall Wa, as shown in FIG. In the present embodiment, the configuration in which the organic film 27 is blocked on the side surface of the first blocking wall Wa on the display region D side is exemplified. However, the organic film 27 is, for example, an upper surface of the second blocking wall Wb. May have been reached. Further, as shown in FIG. 7, the stacked film of the first inorganic film 27 and the second inorganic film 28 stacked in the frame region F as a part of the sealing film 30 is formed outside the second dam wall Wb. It is in contact with the second interlayer insulating film 17 and is in contact with at least one of the inorganic insulating films constituting the TFT layer 20.
上述した有機ＥＬ表示装置５０は、各サブ画素Ｐにおいて、ゲート線１４を介して第１ＴＦＴ９ａにゲート信号を入力することにより、第１ＴＦＴ９ａをオン状態にし、ソース線１８ｆを介して第２ＴＦＴ９ｂのゲート電極１４ｂ及びキャパシタ９ｃにソース信号に対応する所定の電圧を書き込み、第２ＴＦＴ９ｂのゲート電圧に基づいて規定された大きさの電源線１８ｇからの電流が有機ＥＬ層２３に供給されることにより、有機ＥＬ層２３の発光層３が発光して、画像表示を行うように構成されている。なお、有機ＥＬ表示装置５０では、各サブ画素Ｐにおいて、第１ＴＦＴ９ａがオフ状態になっても、第２ＴＦＴ９ｂのゲート電圧がキャパシタ９ｃによって保持されるので、次のフレームのゲート信号が入力されるまで発光層３による発光が維持される。
In the above-described organic EL display device 50, in each sub-pixel P, a first TFT 9a is turned on by inputting a gate signal to the first TFT 9a via the gate line 14, and the gate electrode of the second TFT 9b is connected via the source line 18f. A predetermined voltage corresponding to the source signal is written to the capacitor 14b and the capacitor 9c, and a current is supplied from the power supply line 18g having a size defined based on the gate voltage of the second TFT 9b to the organic EL layer 23, thereby the organic EL layer 23 is turned off. The light-emitting layer 3 of the layer 23 emits light to display an image. In the organic EL display device 50, in each sub-pixel P, even if the first TFT 9a is turned off, the gate voltage of the second TFT 9b is held by the capacitor 9c, so that the gate signal of the next frame is input. Light emission by the light emitting layer 3 is maintained.
次に、本実施形態の有機ＥＬ表示装置５０の製造方法について説明する。なお、本実施形態の有機ＥＬ表示装置５０の製造方法は、ＴＦＴ層形成工程と、第１電極形成工程、エッジカバー形成工程、有機ＥＬ層形成工程及び第２電極形成工程を含む有機ＥＬ素子形成工程と、封止膜形成工程とを備える。ここで、図１０、図１１及び図１２は、有機ＥＬ表示装置５０の製造方法における有機ＥＬ素子形成工程の第１電極形成工程、エッジカバー形成工程及び有機ＥＬ層形成工程を示す断面図である。
Next, a method for manufacturing the organic EL display device 50 of the present embodiment will be described. The method for manufacturing the organic EL display device 50 according to the present embodiment includes a TFT layer forming step, an organic EL element forming step including a first electrode forming step, an edge cover forming step, an organic EL layer forming step, and a second electrode forming step. And a sealing film forming step. Here, FIGS. 10, 11 and 12 are cross-sectional views showing a first electrode forming step, an edge cover forming step, and an organic EL layer forming step of the organic EL element forming step in the method of manufacturing the organic EL display device 50. .
＜ＴＦＴ層形成工程＞
例えば、ガラス基板上に形成した樹脂基板層１０の表面に、周知の方法を用いて、ベースコート膜１１、第１ＴＦＴ９ａ、第２ＴＦＴ９ｂ、キャパシタ９ｃ及び平坦化膜１９を形成して、ＴＦＴ層２０を形成する。ここで、第１ＴＦＴ９ａ及び第２ＴＦＴ９ｂを形成する際には、額縁領域Ｆにおいて、駆動回路用ＴＦＴ９ｄ及び９ｅを同時に形成する。 <TFT layer forming step>
For example, abase coat film 11, a first TFT 9a, a second TFT 9b, a capacitor 9c, and a planarizing film 19 are formed on a surface of a resin substrate layer 10 formed on a glass substrate by a known method, and a TFT layer 20 is formed. I do. Here, when forming the first TFT 9a and the second TFT 9b, the driver circuit TFTs 9d and 9e are simultaneously formed in the frame region F.
例えば、ガラス基板上に形成した樹脂基板層１０の表面に、周知の方法を用いて、ベースコート膜１１、第１ＴＦＴ９ａ、第２ＴＦＴ９ｂ、キャパシタ９ｃ及び平坦化膜１９を形成して、ＴＦＴ層２０を形成する。ここで、第１ＴＦＴ９ａ及び第２ＴＦＴ９ｂを形成する際には、額縁領域Ｆにおいて、駆動回路用ＴＦＴ９ｄ及び９ｅを同時に形成する。 <TFT layer forming step>
For example, a
＜有機ＥＬ素子形成工程＞
上記ＴＦＴ層形成工程で形成されたＴＦＴ層２０の平坦化膜１９上に、周知の方法を用いて、第１電極２１ａ、エッジカバー２２ａ、有機ＥＬ層２３（正孔注入層１、正孔輸送層２、発光層３、電子輸送層４、電子注入層５）、第２電極２４を形成して、有機ＥＬ素子２５を形成する。 <Organic EL element forming step>
Thefirst electrode 21a, the edge cover 22a, the organic EL layer 23 (the hole injection layer 1, the hole transport layer) are formed on the flattening film 19 of the TFT layer 20 formed in the above-described TFT layer forming step by using a known method. The layer 2, the light emitting layer 3, the electron transport layer 4, and the electron injection layer 5) and the second electrode 24 are formed to form the organic EL element 25.
上記ＴＦＴ層形成工程で形成されたＴＦＴ層２０の平坦化膜１９上に、周知の方法を用いて、第１電極２１ａ、エッジカバー２２ａ、有機ＥＬ層２３（正孔注入層１、正孔輸送層２、発光層３、電子輸送層４、電子注入層５）、第２電極２４を形成して、有機ＥＬ素子２５を形成する。 <Organic EL element forming step>
The
ここで、第１電極２１ａ、エッジカバー２２ａ、有機ＥＬ層２３及び第２電極２４を形成する際には、まず、平坦化膜１９上に、例えば、スパッタリング法により、ＩＴＯ膜／銀合金膜（ＭｇＡｇ膜）／ＩＴＯ膜等の導電膜２１を成膜した後に、フォトリソグラフィ処理、エッチング処理及びレジスト剥離を行って、導電膜２１をパターニングすることにより、図１０に示すように、表示領域Ｄに複数の第１電極２１ａを形成し、額縁領域Ｆに周辺電極２１ｂを形成する（第１電極形成工程）。
Here, when forming the first electrode 21a, the edge cover 22a, the organic EL layer 23, and the second electrode 24, first, an ITO film / silver alloy film ( After forming a conductive film 21 such as a (MgAg film) / ITO film, a photolithography process, an etching process, and a resist removal are performed, and the conductive film 21 is patterned, so that the display region D is formed as shown in FIG. A plurality of first electrodes 21a are formed, and a peripheral electrode 21b is formed in the frame region F (first electrode forming step).
続いて、各第１電極２１ａ及び周辺電極２１ｂを覆うように、例えば、インクジェット法により、ポリイミド樹脂製の感光性樹脂２２を成膜した後に、ハーフトーンマスクＭｈを用いる露光、現像及び焼成を行って、感光性樹脂２２をパターニングすることにより、表示領域Ｄに複数の第１開口部Ｈａ及び複数の第１柱状スペーサＣａを有し、額縁領域Ｆに複数の第２開口部Ｈｂ及び複数の第２柱状スペーサＣｂを有するエッジカバー２２ａを形成する（エッジカバー形成工程）。ここで、ハーフトーンマスクＭｈは、図１１に示すように、光が透過しない遮蔽部Ｒａと、光の透過量が制御されたハーフ露光部Ｒｂと、光が透過するように開口したフル露光部Ｒｃを備えた多階調マスクである。そして、ハーフトーンマスクＭｈの遮蔽部Ｒａは、図１１に示すように、エッジカバー２２ａの第１柱状スペーサＣａ及び第２柱状スペーサＣｂが形成される領域に配置される。また、ハーフトーンマスクＭｈのフル露光部Ｒｃは、図１１に示すように、エッジカバー２２ａの第１開口部Ｈａ及び第２開口部Ｈｂが形成される領域に配置される。なお、本実施形態では、多階調マスクして、ハーフトーンマスクＭｈを例示したが、多階調マスクは、グレートーンマスクであってもよい。
Subsequently, after a photosensitive resin 22 made of a polyimide resin is formed by, for example, an inkjet method so as to cover the first electrodes 21a and the peripheral electrodes 21b, exposure, development, and baking using a halftone mask Mh are performed. By patterning the photosensitive resin 22, the display region D has a plurality of first openings Ha and a plurality of first columnar spacers Ca, and the frame region F has a plurality of second openings Hb and a plurality of first columnar spacers Ca. The edge cover 22a having the two columnar spacers Cb is formed (edge cover forming step). Here, as shown in FIG. 11, the halftone mask Mh includes a shielding portion Ra through which light does not transmit, a half exposure portion Rb in which the amount of transmitted light is controlled, and a full exposure portion opened so as to transmit light. This is a multi-tone mask provided with Rc. Then, the shielding portion Ra of the halftone mask Mh is arranged in a region of the edge cover 22a where the first columnar spacer Ca and the second columnar spacer Cb are formed, as shown in FIG. Further, as shown in FIG. 11, the full exposure portion Rc of the halftone mask Mh is disposed in a region where the first opening Ha and the second opening Hb of the edge cover 22a are formed. In the present embodiment, the halftone mask Mh is exemplified as the multi-tone mask, but the multi-tone mask may be a gray-tone mask.
さらに、エッジカバー２２ａの第１柱状スペーサＣａ及び第２柱状スペーサＣｂの頂部上に蒸着マスクＭｄを載置した後に、蒸着マスクＭｄを介して、例えば、真空蒸着法により、正孔注入層１、正孔輸送層２、発光層３、電子輸送層４、電子注入層５を順に形成して、各サブ画素Ｐに有機ＥＬ層２３を形成する（有機ＥＬ層形成工程）。
Further, after the deposition mask Md is placed on the tops of the first columnar spacer Ca and the second columnar spacer Cb of the edge cover 22a, the hole injection layer 1 is formed via the deposition mask Md by, for example, a vacuum deposition method. The hole transport layer 2, the light emitting layer 3, the electron transport layer 4, and the electron injection layer 5 are sequentially formed, and the organic EL layer 23 is formed in each sub-pixel P (organic EL layer forming step).
最後に、有機ＥＬ層２３が形成された基板上に、別の蒸着マスクを用いて、例えば、真空蒸着法により、各有機ＥＬ層２３を覆うように銀合金膜（ＭｇＡｇ膜）を成膜して、第２電極２４を形成する（第２電極形成工程）。
Finally, a silver alloy film (MgAg film) is formed on the substrate on which the organic EL layer 23 is formed by using another evaporation mask, for example, by a vacuum evaporation method so as to cover each organic EL layer 23. Thus, the second electrode 24 is formed (second electrode forming step).
＜封止膜形成工程＞
まず、上記有機ＥＬ素子形成工程で有機ＥＬ素子２５が形成された基板表面に、マスクを用いて、例えば、窒化シリコン膜、酸化シリコン膜、酸窒化シリコン膜等の無機絶縁膜をプラズマＣＶＤ法により厚さ１０００ｎｍ程度に成膜して、第１無機膜２６を形成する。 <Sealing film forming step>
First, an inorganic insulating film such as a silicon nitride film, a silicon oxide film, or a silicon oxynitride film is formed on the surface of the substrate on which theorganic EL element 25 is formed in the organic EL element forming step by a plasma CVD method using a mask. The first inorganic film 26 is formed to a thickness of about 1000 nm.
まず、上記有機ＥＬ素子形成工程で有機ＥＬ素子２５が形成された基板表面に、マスクを用いて、例えば、窒化シリコン膜、酸化シリコン膜、酸窒化シリコン膜等の無機絶縁膜をプラズマＣＶＤ法により厚さ１０００ｎｍ程度に成膜して、第１無機膜２６を形成する。 <Sealing film forming step>
First, an inorganic insulating film such as a silicon nitride film, a silicon oxide film, or a silicon oxynitride film is formed on the surface of the substrate on which the
続いて、第１無機膜２６が形成された基板表面に、例えば、インクジェット法により、アクリル樹脂等の有機樹脂材料を厚さ１０μｍ程度に成膜して、有機膜２７を形成する。
Next, an organic resin material such as an acrylic resin is formed to a thickness of about 10 μm on the surface of the substrate on which the first inorganic film 26 is formed, for example, by an inkjet method, thereby forming an organic film 27.
さらに、有機膜２７が形成された基板に対して、マスクを用いて、例えば、窒化シリコン膜、酸化シリコン膜、酸窒化シリコン膜等の無機絶縁膜をプラズマＣＶＤ法により厚さ５００ｎｍ程度に成膜して、第２無機膜２８を形成することにより、封止膜３０を形成する。
Further, an inorganic insulating film such as a silicon nitride film, a silicon oxide film, or a silicon oxynitride film is formed to a thickness of about 500 nm by a plasma CVD method on the substrate on which the organic film 27 is formed, using a mask. Then, the sealing film 30 is formed by forming the second inorganic film 28.
最後に、封止膜３０が形成された基板表面に保護シート（不図示）を貼付した後に、樹脂基板層１０のガラス基板側からレーザー光を照射することにより、樹脂基板層１０の下面からガラス基板を剥離させ、さらに、ガラス基板を剥離させた樹脂基板層１０の下面に保護シート（不図示）を貼付する。
Finally, after attaching a protective sheet (not shown) to the surface of the substrate on which the sealing film 30 is formed, a laser beam is irradiated from the glass substrate side of the resin substrate layer 10 so that the lower surface of the resin substrate layer 10 The substrate is peeled off, and a protective sheet (not shown) is attached to the lower surface of the resin substrate layer 10 from which the glass substrate has been peeled off.
以上のようにして、本実施形態の有機ＥＬ表示装置５０を製造することができる。
有機 As described above, the organic EL display device 50 of the present embodiment can be manufactured.
以上説明したように、本実施形態の有機ＥＬ表示装置５０及びその製造方法によれば、エッジカバー２２ａが、表示領域Ｄにおいて、各第１電極２１ａを露出させる複数の第１開口部Ｈａと、封止膜３０側の表面に突出する複数の第１柱状スペーサＣａとを備え、額縁領域Ｆにおいて、周辺電極２１ｂ上に設けられ、複数の第１開口部Ｈａと同一形状で同一ピッチの複数の第２開口部Ｈｂと、封止膜３０側の表面に突出する複数の第２柱状スペーサＣｂとを備えている。ここで、ＴＦＴ層２０上には、第１電極形成工程で同時に形成された複数の第１電極２１ａ及び周辺電極２１ｂが表示領域Ｄ及び額縁領域Ｆにそれぞれ設けられている。その後、エッジカバー形成工程で各第１電極２１ａの周端部及び周辺電極２１ｂ上に形成されたエッジカバー２２ａにおいて、表示領域Ｄに配置する各第１柱状スペーサＣａの周りの第１開口部Ｈａの形状及びピッチと、額縁領域Ｆに配置する各第２柱状スペーサＣｂの周りの第２開口部Ｈｂの形状及びピッチとが同じになっている。これにより、エッジカバー２２ａとなるパターニングされた感光性樹脂膜を焼成して、各第１柱状スペーサＣａ及び各第２柱状スペーサＣｂに熱だれが発生しても、その熱だれが表示領域Ｄ及び額縁領域Ｆで均一に発生するので、各第１柱状スペーサＣａの高さと、各第２柱状スペーサＣｂの高さとを同じにすることができる。その結果、被蒸着基板に形成された各第１柱状スペーサＣａ及び各第２柱状スペーサＣｂ上に蒸着マスクＭｄを傾けることなく載置させることができるので、蒸着マスクＭｄと各第１柱状スペーサＣａ及び各第２柱状スペーサＣｂとの接触を均一にして、パーティクルの発生を抑制することができる。
As described above, according to the organic EL display device 50 and the method of manufacturing the same according to the present embodiment, the edge cover 22a includes the plurality of first openings Ha that expose the first electrodes 21a in the display region D; A plurality of first columnar spacers Ca protruding from the surface on the side of the sealing film 30; a plurality of first columnar spacers Ca provided on the peripheral electrode 21b in the frame region F; A second opening Hb and a plurality of second columnar spacers Cb protruding from the surface on the side of the sealing film 30 are provided. Here, on the TFT layer 20, a plurality of first electrodes 21a and a plurality of peripheral electrodes 21b simultaneously formed in the first electrode forming step are provided in the display region D and the frame region F, respectively. Thereafter, in the edge cover forming step, the first opening Ha around each first columnar spacer Ca arranged in the display area D is formed on the peripheral end of each first electrode 21a and the edge cover 22a formed on the peripheral electrode 21b. And the shape and pitch of the second openings Hb around the second columnar spacers Cb arranged in the frame region F are the same. Thereby, even if the patterned photosensitive resin film serving as the edge cover 22a is baked and heat dripping occurs in each of the first columnar spacers Ca and each of the second columnar spacers Cb, the heat drooping occurs in the display region D and the display region D. Since it is uniformly generated in the frame region F, the height of each first columnar spacer Ca and the height of each second columnar spacer Cb can be made equal. As a result, the deposition mask Md can be placed on each of the first columnar spacers Ca and each of the second columnar spacers Cb formed on the substrate to be deposited without tilting. In addition, the contact with each of the second columnar spacers Cb can be made uniform to suppress generation of particles.
《その他の実施形態》
上記実施形態では、正孔注入層、正孔輸送層、発光層、電子輸送層及び電子注入層の５層積層構造の有機ＥＬ層を例示したが、有機ＥＬ層は、例えば、正孔注入層兼正孔輸送層、発光層、及び電子輸送層兼電子注入層の３層積層構造であってもよい。 << Other embodiments >>
In the above embodiment, the organic EL layer having a five-layer structure of the hole injection layer, the hole transport layer, the light emitting layer, the electron transport layer, and the electron injection layer is exemplified. It may have a three-layer structure of a hole-transport layer, a light-emitting layer, and an electron-transport layer and an electron-injection layer.
上記実施形態では、正孔注入層、正孔輸送層、発光層、電子輸送層及び電子注入層の５層積層構造の有機ＥＬ層を例示したが、有機ＥＬ層は、例えば、正孔注入層兼正孔輸送層、発光層、及び電子輸送層兼電子注入層の３層積層構造であってもよい。 << Other embodiments >>
In the above embodiment, the organic EL layer having a five-layer structure of the hole injection layer, the hole transport layer, the light emitting layer, the electron transport layer, and the electron injection layer is exemplified. It may have a three-layer structure of a hole-transport layer, a light-emitting layer, and an electron-transport layer and an electron-injection layer.
また、上記実施形態では、第１電極を陽極とし、第２電極を陰極とした有機ＥＬ表示装置を例示したが、本発明は、有機ＥＬ層の積層構造を反転させ、第１電極を陰極とし、第２電極を陽極とした有機ＥＬ表示装置にも適用することができる。
Further, in the above embodiment, the organic EL display device in which the first electrode is used as an anode and the second electrode is used as a cathode is exemplified. However, the present invention inverts the stacked structure of the organic EL layer and uses the first electrode as a cathode. Also, the present invention can be applied to an organic EL display device using the second electrode as an anode.
また、上記実施形態では、第１電極に接続されたＴＦＴの電極をドレイン電極とした有機ＥＬ表示装置を例示したが、本発明は、第１電極に接続されたＴＦＴの電極をソース電極と呼ぶ有機ＥＬ表示装置にも適用することができる。
Further, in the above-described embodiment, the organic EL display device in which the electrode of the TFT connected to the first electrode is used as the drain electrode is exemplified. However, the present invention calls the electrode of the TFT connected to the first electrode a source electrode. The present invention can be applied to an organic EL display device.
また、上記実施形態では、表示装置として有機ＥＬ表示装置を例に挙げて説明したが、本発明は、電流によって駆動される複数の発光素子を備えた表示装置に適用することができる。例えば、量子ドット含有層を用いた発光素子であるＱＬＥＤ（Quantum-dot light emitting diode）を備えた表示装置に適用することができる。
In the above embodiment, the organic EL display device is described as an example of the display device. However, the present invention can be applied to a display device including a plurality of light emitting elements driven by current. For example, the present invention can be applied to a display device provided with a QLED (Quantum-dot-light-emitting-diode) that is a light-emitting element using a quantum dot-containing layer.
以上説明したように、本発明は、フレキシブルな表示装置について有用である。
As described above, the present invention is useful for a flexible display device.
Ｃａ 第１柱状スペーサ
Ｃｂ 第２柱状スペーサ
Ｄ 表示領域
Ｆ 額縁領域
Ｇ，Ｇａ，Ｇｂ トレンチ
Ｈａ 第１開口部
Ｈｂ 第２開口部
Ｍｄ 蒸着マスク
Ｍｈ ハーフトーンマスク（多階調マスク）
Ｓ スリット
Ｓａ 第１スリット
Ｓｂ 第２スリット
１０ 樹脂基板層（ベース基板）
２０ ＴＦＴ層
２１ 導電膜
２１ａ 第１電極
２１ｂ，２１ｃ 周辺電極
２２ 感光性樹脂膜
２２ａ エッジカバー
２３ 有機ＥＬ層（発光素子層）
２４ 第２電極
２５ 有機ＥＬ素子（発光素子）
５０ 有機ＥＬ表示装置 Ca First columnar spacer Cb Second columnar spacer D Display area F Frame area G, Ga, Gb Trench Ha First opening Hb Second opening Md Deposition mask Mh Halftone mask (multi-tone mask)
S slit Sa first slit Sb second slit 10 Resin substrate layer (base substrate)
Reference Signs List 20 TFT layer 21 Conductive film 21a First electrode 21b, 21c Peripheral electrode 22 Photosensitive resin film 22a Edge cover 23 Organic EL layer (light emitting element layer)
24Second electrode 25 Organic EL element (light emitting element)
50 Organic EL display
Ｃｂ 第２柱状スペーサ
Ｄ 表示領域
Ｆ 額縁領域
Ｇ，Ｇａ，Ｇｂ トレンチ
Ｈａ 第１開口部
Ｈｂ 第２開口部
Ｍｄ 蒸着マスク
Ｍｈ ハーフトーンマスク（多階調マスク）
Ｓ スリット
Ｓａ 第１スリット
Ｓｂ 第２スリット
１０ 樹脂基板層（ベース基板）
２０ ＴＦＴ層
２１ 導電膜
２１ａ 第１電極
２１ｂ，２１ｃ 周辺電極
２２ 感光性樹脂膜
２２ａ エッジカバー
２３ 有機ＥＬ層（発光素子層）
２４ 第２電極
２５ 有機ＥＬ素子（発光素子）
５０ 有機ＥＬ表示装置 Ca First columnar spacer Cb Second columnar spacer D Display area F Frame area G, Ga, Gb Trench Ha First opening Hb Second opening Md Deposition mask Mh Halftone mask (multi-tone mask)
S slit Sa first slit Sb second slit 10 Resin substrate layer (base substrate)
24
50 Organic EL display
Claims (13)
- ベース基板と、
上記ベース基板上に設けられたＴＦＴ層と、
上記ＴＦＴ層上に設けられ、表示領域を構成する発光素子と、
上記表示領域の周囲に設けられた額縁領域とを備え、
上記発光素子が、上記ＴＦＴ層上に設けられた複数の第１電極と、該各第１電極の周端部を覆うように複数の第１開口部を有する格子状に設けられたエッジカバーと、該エッジカバーの上記各第１開口部から露出する上記各第１電極上にそれぞれ設けられた複数の発光素子層と、該各発光素子層を覆うように設けられた第２電極とを備え、
上記エッジカバーが、上記表示領域において、上記複数の第１開口部の間で上記ベース基板と反対側の表面に突出するように設けられた複数の第１柱状スペーサとを備えた表示装置であって、
上記額縁領域において、上記ＴＦＴ層上には、上記各第１電極と同一層に同一材料により周辺電極が設けられ、
上記エッジカバーは、上記額縁領域において、上記複数の第１開口部と同一形状で同一ピッチに形成された複数の第２開口部と、該複数の第２開口部の間で上記ベース基板と反対側の表面に突出するように設けられた複数の第２柱状スペーサとを備えていることを特徴とする表示装置。 A base substrate,
A TFT layer provided on the base substrate,
A light emitting element provided on the TFT layer and constituting a display area;
A frame area provided around the display area,
A plurality of first electrodes provided on the TFT layer, and an edge cover provided in a grid shape having a plurality of first openings so as to cover a peripheral end of each first electrode; A plurality of light emitting element layers provided on each of the first electrodes exposed from each of the first openings of the edge cover, and a second electrode provided to cover each of the light emitting element layers. ,
A display device, comprising: a plurality of first columnar spacers provided so that the edge cover projects on a surface opposite to the base substrate between the plurality of first openings in the display area. hand,
In the frame area, a peripheral electrode is provided on the TFT layer in the same layer as the first electrode using the same material,
The edge cover has, in the frame area, a plurality of second openings formed in the same shape and at the same pitch as the plurality of first openings, and opposite to the base substrate between the plurality of second openings. And a plurality of second columnar spacers provided so as to protrude from the surface on the side. - 請求項１に記載された表示装置において、
上記エッジカバーは、上記額縁領域において、上記周辺電極上に設けられていることを特徴とする表示装置。 The display device according to claim 1,
The display device, wherein the edge cover is provided on the peripheral electrode in the frame region. - 請求項１又は２に記載された表示装置において、
上記複数の第２柱状スペーサのピッチは、上記複数の第２開口部のピッチよりも大きくなっていることを特徴とする表示装置。 The display device according to claim 1, wherein
The display device, wherein a pitch of the plurality of second columnar spacers is larger than a pitch of the plurality of second openings. - 請求項１～３の何れか１つに記載された表示装置において、
上記複数の第２開口部と上記複数の第２柱状スペーサとの位置関係は、上記複数の第１開口部と上記複数の第１柱状スペーサとの位置関係と等しくなっていることを特徴とする表示装置。 The display device according to any one of claims 1 to 3,
The positional relationship between the plurality of second openings and the plurality of second columnar spacers is equal to the positional relationship between the plurality of first openings and the plurality of first columnar spacers. Display device. - 請求項１～４の何れか１つに記載された表示装置において、
上記ＴＦＴ層は、上記発光素子側に平坦化膜を有し、
上記額縁領域において、上記平坦化膜には、上記表示領域を囲むように該平坦化膜を貫通するスリット、及び該スリットの表示領域側に該平坦化膜を貫通するトレンチが形成され、
上記第２電極は、上記トレンチを介して上記周辺電極に電気的に接続され、
上記複数の第２開口部及び上記複数の第２柱状スペーサは、上記表示領域と上記トレンチの間に設けられていると共に、上記トレンチと上記スリットとの間に設けられていることを特徴とする表示装置。 The display device according to any one of claims 1 to 4,
The TFT layer has a flattening film on the light emitting element side,
In the frame region, a slit that penetrates the flattening film so as to surround the display region, and a trench that penetrates the flattening film on the display region side of the slit is formed in the flattening film,
The second electrode is electrically connected to the peripheral electrode via the trench,
The plurality of second openings and the plurality of second columnar spacers are provided between the display region and the trench, and are provided between the trench and the slit. Display device. - 請求項５に記載された表示装置において、
上記表示領域と上記トレンチの間に配置された上記複数の第２開口部の配置密度は、上記トレンチと上記スリットとの間に配置された上記複数の第２開口部の配置密度と等しくなっていることを特徴とする表示装置。 The display device according to claim 5,
The arrangement density of the plurality of second openings arranged between the display region and the trench is equal to the arrangement density of the plurality of second openings arranged between the trench and the slit. A display device. - 請求項１～６の何れか１つに記載された表示装置において、
上記第２電極は、上記各第２開口部を介して上記周辺電極と電気的に接続されていることを特徴とする表示装置。 The display device according to any one of claims 1 to 6,
The display device, wherein the second electrode is electrically connected to the peripheral electrode through each of the second openings. - 請求項１～６の何れか１つに記載された表示装置において、
上記周辺電極は、上記各第２開口部から露出していないことを特徴とする表示装置。 The display device according to any one of claims 1 to 6,
The display device, wherein the peripheral electrode is not exposed from each of the second openings. - 請求項１～８の何れか１つに記載された表示装置において、
上記発光素子は、有機ＥＬ素子であることを特徴とする表示装置。 The display device according to any one of claims 1 to 8,
The display device, wherein the light-emitting element is an organic EL element. - ベース基板上にＴＦＴ層を形成するＴＦＴ層形成工程と、
上記ＴＦＴ層上に表示領域を構成する発光素子を形成する発光素子形成工程とを備え、
上記表示領域の周囲に額縁領域が設けられた表示装置を製造する方法であって、
上記発光素子形成工程は、上記ＴＦＴ層上に導電膜を成膜した後に、該導電膜をパターニングして、上記表示領域に複数の第１電極を形成する第１電極形成工程と、上記複数の第１電極を覆うように感光性樹脂膜を成膜した後に、該感光性樹脂膜をパターニングして、上記表示領域において、上記各第１電極の周端部を覆い、該各第１電極をそれぞれ露出させる複数の第１開口部、及び該複数の第１開口部の間で上記ベース基板と反対側の表面に突出する複数の第１柱状スペーサを有し、上記額縁領域において、上記複数の第１開口部と同一形状で同一ピッチに形成された複数の第２開口部、及び該複数の第２開口部の間で上記ベース基板と反対側の表面に突出する複数の第２柱状スペーサを有するエッジカバーを形成するエッジカバー形成工程と、上記複数の第１柱状スペーサ及び上記複数の第２柱状スペーサ上に蒸着マスクを載置した後に、該蒸着マスクを介して、上記エッジカバーから露出する上記複数の第１電極上に複数の発光素子層を蒸着法によりそれぞれ形成する発光素子層形成工程と、上記各発光素子層を覆うように第２電極を形成する第２電極形成工程とを備えることを特徴とする表示装置の製造方法。 A TFT layer forming step of forming a TFT layer on a base substrate;
A light emitting element forming step of forming a light emitting element forming a display region on the TFT layer,
A method of manufacturing a display device provided with a frame region around the display region,
The light emitting element forming step includes a first electrode forming step of forming a plurality of first electrodes in the display region by patterning the conductive film after forming a conductive film on the TFT layer; After forming a photosensitive resin film so as to cover the first electrode, the photosensitive resin film is patterned to cover a peripheral end portion of each of the first electrodes in the display area, and to cover each of the first electrodes. A plurality of first openings to be exposed, and a plurality of first columnar spacers projecting to a surface opposite to the base substrate between the plurality of first openings; A plurality of second openings formed in the same shape and at the same pitch as the first openings, and a plurality of second columnar spacers protruding between the plurality of second openings on a surface opposite to the base substrate. Cover formation to form an edge cover having After a deposition mask is placed on the plurality of first columnar spacers and the plurality of second columnar spacers, a plurality of the plurality of first electrodes are exposed on the plurality of first electrodes exposed from the edge cover via the deposition mask. A light emitting element layer forming step of forming each of the light emitting element layers by a vapor deposition method, and a second electrode forming step of forming a second electrode so as to cover each of the light emitting element layers. Method. - 請求項１０に記載された表示装置の製造方法において、
上記第１電極形成工程では、上記導電膜をパターニングして、上記額縁領域に周辺電極を形成し、
上記エッジカバー形成工程では、上記周辺電極を覆うように上記感光性樹脂膜を成膜することを特徴とする表示装置の製造方法。 The method for manufacturing a display device according to claim 10,
In the first electrode forming step, the conductive film is patterned to form a peripheral electrode in the frame region,
The method of manufacturing a display device, wherein in the edge cover forming step, the photosensitive resin film is formed so as to cover the peripheral electrode. - 請求項１０又は１１に記載された表示装置の製造方法において、
上記エッジカバー形成工程では、上記感光性樹脂膜を多階調マスクにより露光し、該露光した上記感光性樹脂膜を現像し、該現像した上記感光性樹脂膜を焼成して、上記エッジカバーを形成することを特徴とする表示装置の製造方法。 The method for manufacturing a display device according to claim 10,
In the edge cover forming step, the photosensitive resin film is exposed with a multi-tone mask, the exposed photosensitive resin film is developed, and the developed photosensitive resin film is baked to form the edge cover. A method for manufacturing a display device, comprising: - 請求項１０～１２の何れか１つに記載された表示装置の製造方法において、
上記発光素子は、有機ＥＬ素子であることを特徴とする表示装置の製造方法。 A method for manufacturing a display device according to any one of claims 10 to 12,
The method for manufacturing a display device, wherein the light emitting element is an organic EL element.
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