WO2019223333A1 - 一种配置均衡时间的方法、芯片和通信系统 - Google Patents

一种配置均衡时间的方法、芯片和通信系统 Download PDF

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Publication number
WO2019223333A1
WO2019223333A1 PCT/CN2019/070562 CN2019070562W WO2019223333A1 WO 2019223333 A1 WO2019223333 A1 WO 2019223333A1 CN 2019070562 W CN2019070562 W CN 2019070562W WO 2019223333 A1 WO2019223333 A1 WO 2019223333A1
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Prior art keywords
chip
equalization
slave
master
stage
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PCT/CN2019/070562
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English (en)
French (fr)
Inventor
李永耀
朱江
罗飞
李建康
马玉龙
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华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP22175587.9A priority Critical patent/EP4116836A1/en
Priority to ES19806439T priority patent/ES2925375T3/es
Priority to EP19806439.6A priority patent/EP3779711B1/en
Publication of WO2019223333A1 publication Critical patent/WO2019223333A1/zh
Priority to US16/952,350 priority patent/US11347669B2/en
Priority to US17/827,271 priority patent/US11921660B2/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4072—Drivers or receivers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/70—Software maintenance or management
    • G06F8/71—Version control; Configuration management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03878—Line equalisers; line build-out devices

Definitions

  • the present invention relates to the field of chip technology, and in particular, to a method, a chip, and a communication system for configuring equalization time.
  • PCIe Peripheral Component Interconnect Express
  • CCIX Cache Coherent Interconnect for Accelerators
  • FIG. 1 shows a processor system using a PCIe bus.
  • the link between the master chip and the slave chip is taken as an example. After the system is powered on, the master chip and the slave chip first perform link negotiation, and the negotiation is completed. Only after the establishment of high-speed links for business data interaction.
  • link negotiation includes link equalization (referred to as "equalization").
  • Link equalization is implemented through an equalization circuit. The purpose of link equalization is to compensate for transmission on the link due to link loss. Degradation of the signal. See Figure 4 for the four stages of equalization.
  • a fixed equalization time is specified for each phase of the equalization. For example, in the third phase (Phase 2), the equalization time of the slave chip is 24ms and the equalization time of the master chip is 32ms. If the master chip (or slave chip) does not complete the corresponding equalization operation within the specified equalization time, the master chip (or slave chip) will exit the equalization, resulting in a link between the master chip and the slave chip Negotiation failed.
  • This application provides a method for configuring the equalization time, which is used to flexibly configure the equalization time to reduce to a certain extent the situation that link negotiation fails due to insufficient equalization time. Further, the present application also provides a device and a communication system for performing the method, and a chip used in performing the method.
  • the present application provides a method for configuring an equalization time.
  • the method includes the following steps.
  • the port number of the master chip and the identifier of the slave chip are acquired, and the type of the channel between the port of the master chip and the slave chip is determined by looking up the channel type table.
  • the determined channel type is a long-distance LR or a short-distance SR.
  • the PHY type supported by the master chip and the slave chip is one of three types: long distance (LR, Long Reach) and short distance (SR, Short Reach), LR or SR.
  • Determining the working PHY type of the master chip and the slave chip when both the PHY type supported by the master chip and the PHY type supported by the slave chip include the determined channel type, wherein the master chip And the working PHY type of the slave chip is the same as the determined channel type.
  • the working PHY type of the slave chip configure an equalization time of the master chip in the third stage of the equalization. And, according to a working PHY type of the master chip, configuring an equalization time of the slave chip in the fourth stage of the equalization.
  • a type of a channel located between a specific port of the master chip and the slave chip is determined. Then, it is determined whether the PHY type supported by the master chip and the PHY type supported by the slave chip both include the determined channel type. If both are included, determine the working PHY type of the master chip and the slave chip. The working PHY types of the master chip and the slave chip are the same as the determined channel type. Finally, according to the working PHY type of the master chip, configure the equalization time of the slave chip in the fourth phase of equalization, and according to the working PHY type of the slave chip, configure the equalization time of the master chip in the third phase of equalization.
  • the equalization time of the slave chip in the fourth stage of equalization is configured according to the working PHY type of the master chip
  • the equalization time of the master chip in the third stage of equalization is configured according to the working PHY type of the slave chip of. Since the working PHY type of the master chip is determined, the equalization time of the slave chip in this fourth stage will be configured sufficiently. Furthermore, its operation in this stage can be successfully completed without exiting due to insufficient time. Similarly, since the working PHY type of the slave chip is determined, the equalization time of the master chip in this third stage will also be configured adequately. Furthermore, its operation in this third stage will not be exited due to insufficient time. .
  • the chip when the chip is a master chip, the opposite chip is a slave chip.
  • the peer chip when the chip is a slave chip, the peer chip is a master chip.
  • the master chip and the slave chip are connected through a PCIe bus or a CCIX bus. It can be known that the method for configuring the equalization time provided in this embodiment is applied to a processor system using a PCIe bus or a CCIX bus.
  • the master chip is a root component (RC) or a switch chip
  • the slave chip is an endpoint device (Endpoint) independent of the master chip.
  • the switching chip may be a master chip in some cases, and may be a slave chip in other cases.
  • the channel type table includes a port number of the master chip, an identifier of the slave chip, and a channel type. It should be noted that, according to the port number of the master chip and the identifier of the slave chip, the type of the channel between the port of the master chip and the slave chip can be uniquely determined.
  • the channel type is determined according to the loss of the channel, where the channel loss corresponding to LR is greater than the channel loss corresponding to SR.
  • the type of PHY supported by the chip is determined according to the channel loss that the chip can drive. Specifically, the channel loss that can be driven by a chip that supports a PHY type of LR is greater than the channel loss that can be driven by a chip that supports a PHY type of SR.
  • the so-called “configuration of the equalization time of the master chip in the third stage of equalization according to the working PHY type of said slave chip” is implemented in the following manner. First, an equalization circuit of the slave chip is configured according to a working PHY type of the slave chip. Then, an equalization time required by the slave chip in the third stage is determined according to the equalization circuit. Finally, the equalization time of the master chip in the third stage is configured according to the equalization time required by the slave chip in the third stage.
  • a more reasonable equalization circuit can be configured for the slave chip.
  • the equalization circuit of the slave chip can balance the equalization effect and efficiency. According to the equalization circuit of the slave chip, it is possible to relatively accurately estimate the equalization time required by the slave chip in the third stage of equalization. Further, according to the equalization time required by the slave chip in the third stage of equalization, the equalization time of the master chip in the third stage of equalization can be configured relatively accurately. In short, with this embodiment, the equalization time of the main chip in the third phase of the equalization can be configured relatively accurately.
  • the so-called “configuration of the equalization circuit of the slave chip” is to configure the equalization circuit of the slave chip by turning on or off.
  • a total equalization circuit is pre-configured in the slave chip.
  • the equalization circuit includes at least two equalizers.
  • the at least two equalizers may be the same equalizer or different equalizers.
  • an equalization circuit that the slave chip actually works can be configured. It is easy to know that the “equalization circuit of the slave chip” described in this embodiment refers to an equalization circuit that the slave chip actually works. With this solution, the equalization circuit of the slave chip can be configured simply and efficiently.
  • the so-called “configure the slave chip in the fourth stage of the equalization time according to the working PHY type of the master chip" "Is achieved by the following means.
  • an equalization circuit of the main chip is configured according to a working PHY type of the main chip.
  • an equalization time required by the main chip in the fourth stage is determined according to the equalization circuit.
  • the equalization time of the slave chip in the fourth stage is configured according to the equalization time required by the master chip in the fourth stage.
  • a more reasonable equalization circuit can be configured for the main chip.
  • the equalization circuit of the main chip can balance the equalization effect and efficiency.
  • the equalization time required by the main chip in the fourth stage of the equalization can be relatively accurately estimated.
  • the equalization time of the slave chip in the fourth stage of equalization can be configured relatively accurately. In short, with this embodiment, the equalization time of the slave chip in the fourth stage of the equalization can be configured relatively accurately.
  • the so-called “equalization circuit configuring the main chip” refers to configuring the equalization circuit of the main chip by turning on or off. It should be noted that a total equalization circuit is pre-configured in the main chip.
  • the equalization circuit includes at least two equalizers. The at least two equalizers may be the same equalizer or different equalizers. The way of turning on all or part of the equalizer or turning off all or part of the equalizer can configure the equalization circuit that the main chip actually works. It is easy to know that the “equalization circuit of the main chip” described in this embodiment refers to an equalization circuit that the main chip actually works. With this solution, the equalization circuit of the main chip can be configured simply and efficiently.
  • the equalization time of the master chip in the third stage of the equalization is configured as T2. It should be noted that the value of T2 is greater than the value of T1.
  • the equalization time of the master chip in the third stage of the equalization is flexibly configured according to the working PHY type of the slave chip. Specifically, if the working PHY type of the slave chip is SR, the equalization time is configured to be shorter, and if the working PHY type of the slave chip is LR, the equalization time is configured to be longer, which not only reduces link negotiation Risk of failure and increased configuration flexibility. Further, when the working PHY type of the slave chip is SR, the equalization time can be configured to be shorter, thereby avoiding the defect that the link negotiation time is too long due to the long equalization time.
  • the slave The equalization time of the chip in the fourth phase of the equalization is configured as T3.
  • the equalization time of the slave chip in the fourth phase of the equalization is configured as T4. Then the value of T4 is greater than the value of T3.
  • the equalization time is configured to be shorter, and if the working PHY type of the main chip is LR, the equalization time is configured to be longer, which not only reduces The risk of failed link negotiation and increased configuration flexibility. Further, when the working PHY type of the main chip is SR, the equalization time can be configured to be shorter, thereby avoiding the defect that the link negotiation time is too long due to the long equalization time.
  • the working PHY type of the master chip and the slave chip When both are SR, the equalization time of the master chip in the third phase of the equalization and the equalization time of the slave chip in the fourth phase of the equalization are configured as default values.
  • the working PHY type of the master chip and the slave chip When both are SR, read the equalization time of the slave chip in the third stage and write it into the master chip as the equalization time of the master chip in the third stage of equalization. And, the equalization time of the master chip in the fourth stage is read and written into the slave chip as the equalization time of the slave chip in the fourth stage of equalization.
  • the equalization time of the master chip in the third stage of the equalization and the equalization time of the slave chip in the fourth stage of the equalization The time is configured as the default.
  • the above two embodiments both provide a method for configuring an equalization time of the master chip in the third stage of equalization and an equalization time of the slave chip in the fourth stage of equalization according to the working PHY types of the master chip and the slave chip.
  • the default value is set by a person skilled in the art according to related standards or experience.
  • the PHY type supported by the main chip is stored in advance in the In the register of the main chip.
  • the type of PHY supported by the slave chip is stored in advance in a register of the slave chip.
  • the present application provides an apparatus for configuring an equalization time, and the apparatus is configured to perform the foregoing method in the first aspect or any implementation manner of the first aspect.
  • the device includes a transceiver and a manager.
  • the transceiver is used to receive the port number of the master chip and the identification of the slave chip.
  • the manager is configured to determine the type of the channel between the port of the master chip and the slave chip by looking up a channel type table according to the port number of the master chip and the identifier of the slave chip.
  • the determined channel type is LR or SR;
  • the transceiver is further configured to receive a PHY type supported by the master chip and the slave chip.
  • the PHY type supported by the master chip and the slave chip is one of three types: LR and SR, LR, or SR.
  • the manager is further configured to determine whether the PHY type supported by the master chip and the PHY type supported by the slave chip both include the determined channel type, and determine the PHY type and address supported by the master chip.
  • the PHY type supported by the slave chip includes the determined channel type
  • the working PHY type of the master chip and the working PHY type of the slave chip are determined. It should be noted that the working PHY types of the master chip and the slave chip are the same as the determined channel type.
  • the manager is further configured to configure an equalization time of the master chip in the third stage of equalization according to the working PHY type of the slave chip, and configure the master chip according to the working PHY type of the master chip. Equalization time from the chip in the fourth stage of the equalization.
  • the method for configuring the equalization time described in the first aspect or any possible implementation manner of the first aspect can be implemented.
  • the device provided in this embodiment can make the equalization time of the main chip in the third phase of the equalization be sufficient. Accordingly, the equalization operation of the main chip in the third phase will not be exited due to insufficient time; And, the equalization time of the slave chip in the fourth stage of equalization is also sufficient. Accordingly, the equalization operation of the slave chip in the fourth stage will not be withdrawn due to insufficient time. Therefore, by adopting the device provided in this embodiment, the risk that the chip exits the equalization operation due to insufficient equalization time can be reduced to a certain extent, and thus the risk of link negotiation failure can be reduced.
  • the manager is specifically configured to configure the master chip in the third phase of the balancing according to the balancing time required by the slave chip in the third phase of balancing Equalization time.
  • the equalization time required by the slave chip in the third stage of equalization is determined by the slave chip according to the equalization circuit of the slave chip.
  • the equalization circuit of the slave chip is configured by the slave chip according to a working PHY type of the slave chip.
  • the equalization circuit of the slave chip is configured by the slave chip in an on or off manner according to a working PHY type of the slave chip.
  • beneficial effects of this solution refer to the beneficial effects corresponding to the related implementation manners of the first aspect, which will not be repeated here.
  • the manager is specifically configured to configure an IP address according to the equalization time required by the main chip in the fourth phase of equalization.
  • the equalization time of the slave chip in the fourth phase of the equalization is described.
  • the equalization time required by the main chip in the fourth stage of the equalization is determined by the main chip according to the equalization circuit of the main chip.
  • the equalization circuit of the main chip is configured by the main chip according to a working PHY type of the main chip.
  • the equalization circuit of the main chip is configured by the main chip in an on or off manner according to a working PHY type of the main chip.
  • beneficial effects of this solution refer to the beneficial effects corresponding to the related implementation manners of the first aspect, which will not be repeated here.
  • the manager when the working PHY types of the master chip and the slave chip are both SR, the manager is specifically configured to place the master chip in the equalization.
  • the equalization time of the third stage of the VC and the equalization time of the slave chip in the fourth stage of the equalization are both configured as default values.
  • the manager is specifically configured to read the equalization time of the slave chip in the third stage of the equalization, and write it to all In the master chip, an equalization time of the main chip in the third phase of the equalization is used, and the equalization time of the main chip in the fourth phase of the equalization is read, and written into the The slave chip is used as an equalization time of the slave chip in the fourth stage of the equalization.
  • the manager when the working PHY types of the master chip and the slave chip are both SR, the manager is specifically configured to read the slave chip in the Equalization time of the third stage of equalization and writing it into the main chip as the equalization time of the main chip at the third stage of equalization, and reading the main chip at the equalization time An equalization time of the fourth stage of the equalization time, and write it into the slave chip as the equalization time of the slave chip in the fourth stage of the equalization.
  • the manager is specifically configured to balance the master chip in the third stage of the equalization time and the slave chip in the equalization time.
  • the equalization time of the fourth phase of the equalization is configured as the default value.
  • the present application provides another apparatus for configuring an equalization time, and the apparatus is also configured to execute the method for configuring the equalization time according to the foregoing first aspect or any implementation manner of the first aspect.
  • the device includes an acquisition unit, a determination unit, and a configuration unit.
  • the obtaining unit is used to obtain the port number of the master chip and the identifier of the slave chip.
  • the determining unit is configured to determine a type of a channel between the port of the master chip and the slave chip by searching a channel type table.
  • the determined channel type is a long-distance LR or a short-distance SR.
  • the acquiring unit is further configured to acquire a physical layer PHY type supported by the master chip and a PHY type supported by the slave chip.
  • the PHY type supported by the master chip and the PHY type supported by the slave chip are both LR, SR, LR, or SR.
  • the determining unit is further configured to determine whether the PHY type supported by the master chip and the PHY type supported by the slave chip both include the PHY type supported by the master chip and the PHY type supported by the slave chip. Determined channel type.
  • the determining unit is further configured to determine a working PHY type of the master chip and a work of the slave chip PHY type.
  • the working PHY type of the master chip and the working PHY type of the slave chip are the same as the determined channel type.
  • the configuration unit is configured to configure an equalization time of the master chip in the third stage of equalization according to the working PHY type of the slave chip; and configure the slave chip to be in the equalization according to the working PHY type of the master chip.
  • the fourth phase of the equilibrium time is configured to configure an equalization time of the master chip in the third stage of equalization according to the working PHY type of the slave chip; and configure the slave chip to be in the equalization according to the working PHY type of the master chip.
  • the apparatus provided in this embodiment is configured to execute the method according to the first aspect or any possible implementation manner of the first aspect.
  • the equalization time of the main chip in the third stage of the equalization is sufficient, that is, the equalization operation of the main chip in the third stage will not be exited due to insufficient time; and
  • the equalization time of the slave chip in the fourth stage of the equalization is also sufficient, that is, the equalization operation of the slave chip in the fourth stage will not be withdrawn due to insufficient time. Therefore, by adopting the device provided in this embodiment, the risk that the chip exits the equalization operation due to insufficient equalization time can be reduced to a certain extent, and thus the risk of link negotiation failure can be reduced.
  • the configuration unit is specifically configured to configure the master chip in the equalized first time according to the equalization time required by the slave chip in the third phase of the equalization.
  • Three-phase equilibrium time The equalization time required by the slave chip in the third stage of the equalization is determined by the slave chip according to the equalization circuit of the slave chip.
  • the equalization circuit of the slave chip is configured by the slave chip according to a working PHY type of the slave chip.
  • the equalization circuit of the slave chip is configured by the slave chip in an on or off manner according to the working PHY type of the slave chip.
  • the configuration unit is specifically configured to perform an equalization time required by the main chip in the fourth phase of the equalization. And configuring an equalization time of the slave chip in the fourth phase of the equalization.
  • the equalization time required by the main chip in the fourth stage of the equalization is determined by the main chip according to the equalization circuit of the main chip.
  • the equalization circuit of the main chip is configured by the main chip according to a working PHY type of the main chip.
  • the equalization circuit of the main chip is configured by the main chip in an on or off manner according to a working PHY type of the main chip.
  • the configuration unit is specifically configured to place the master chip in the equalization.
  • the equalization time of the third stage of the VC and the equalization time of the slave chip in the fourth stage of the equalization are both configured as default values.
  • the configuration unit is specifically configured to read the equalization time of the slave chip in the third stage of the equalization and write it into the In the master chip, an equalization time of the main chip in the third phase of the equalization is used, and the equalization time of the main chip in the fourth phase of the equalization is read, and written into the The slave chip is used as an equalization time of the slave chip in the fourth stage of the equalization.
  • the configuration unit is specifically configured to read the slave chip in the
  • the equalization time of the third stage of equalization is written into the main chip as the equalization time of the main chip at the third stage of equalization, and the main chip is read at the equalization time.
  • An equalization time of the fourth stage of the equalization time and write it into the slave chip as the equalization time of the slave chip in the fourth stage of the equalization.
  • the configuration unit is specifically configured to set an equalization time of the master chip in the third stage of the equalization and the slave chip in the The equalization time of the fourth phase of the equalization is configured as the default value.
  • the present application provides another apparatus for configuring an equalization time, and the apparatus is also configured to execute the method for configuring the equalization time according to the foregoing first aspect or any implementation manner of the first aspect.
  • the device includes a central processing unit (CPU, Central Processor) and a memory, and the CPU is configured to execute code stored in the memory according to the functions of the device described in this embodiment.
  • the memory is used to store the channel type table.
  • the CPU is used to obtain the port number of the master chip and the identifier of the slave chip, and then according to the port number of the master chip and the identifier of the slave chip, by looking up the channel type table, determine the port located on the master chip and the slave chip.
  • the type of the determined channel is LR or SR.
  • the CPU501 is further configured to obtain a PHY type supported by the master chip and a PHY type supported by the slave chip, and when the determined channel type is included in both the PHY type supported by the master chip and the PHY type supported by the slave chip, determine the The working PHY type of the master chip and the working PHY type of the slave chip.
  • the working PHY type of the master chip and the working PHY type of the slave chip are the same as the determined channel type.
  • the PHY type supported by the master chip and the PHY type supported by the slave chip are both LR and SR, LR or SR.
  • the CPU After determining the working PHY type of the master chip and the working PHY type of the slave chip, the CPU is further configured to configure the equalization time of the slave chip in the fourth stage of the equalization according to the working PHY type of the master chip, and according to the The working PHY type of the slave chip configures the equalization time of the master chip in the third stage of the equalization. Similar to the devices described in the foregoing implementation manners, the device described in this embodiment can reduce the risk of the system exiting the equalization operation due to insufficient equalization time, thereby causing the link negotiation to fail.
  • a chip is provided in the present application, and the chip may be the foregoing first aspect or any implementation manner thereof, the second aspect or any implementation manner thereof, or the third aspect or any implementation manner thereof Mentioned master or slave chip.
  • the chip includes a first register, a transceiver, a second register, and a manager.
  • the first register is used to store a physical layer PHY type supported by the chip, and the PHY type supported by the chip is one of long-range LR and short-range SR, LR, or SR;
  • a transceiver for sending a PHY type supported by the chip and receiving a working PHY type of the chip, the working PHY type of the chip is determined according to a type of a channel between the chip and another chip, where , And the PHY type supported by the chip and the another other chip includes the type of the determined channel, the type of the determined channel is LR or SR, and the type of the working PHY and the type of the determined channel the same;
  • a second register for storing a working PHY type of the chip
  • the manager is configured to configure an equalization circuit of the chip according to a working PHY type of the chip, and determine an equalization time of the chip according to the equalization circuit of the chip.
  • the method described in the first aspect or any possible implementation manner of the first aspect can be implemented to further reduce the system from exiting the equalization operation due to insufficient equalization time, thereby causing link negotiation. Risk of failure.
  • the second register is further configured to store an equilibrium time of the chip.
  • the present application further provides a communication system, which includes system software, a master chip, and a slave chip.
  • the master chip and the slave chip communicate through a bus or a CCIX bus.
  • the system software is configured to obtain a port number of the master chip and an identifier of the slave chip, and determine a type of a channel between the port of the master chip and the slave chip by looking up a channel type table.
  • the determined channel type is a long-distance LR or a short-distance SR.
  • the system software is further configured to obtain a physical layer PHY type supported by the master chip and a PHY type supported by the slave chip, and determine whether both the PHY type supported by the master chip and the PHY type supported by the slave chip include The determined channel type.
  • the PHY type supported by the master chip and the PHY type supported by the slave chip are both LR, SR, LR, or SR.
  • the system software is further configured to determine a working PHY type of the master chip and the slave chip Working PHY type.
  • the working PHY type of the master chip and the working PHY type of the slave chip are the same as the determined channel type.
  • the system software is further configured to configure an equalization time of the master chip in the third phase of the equalization according to the working PHY types of the slave chip; and And, according to a working PHY type of the master chip, configuring an equalization time of the slave chip in the fourth stage of the equalization.
  • the equalization time of the main chip in the third phase of the equalization is sufficient. Accordingly, the equalization operation of the main chip in the third phase will not be withdrawn due to insufficient time; and Therefore, the equalization time of the slave chip in the fourth phase of the equalization is also sufficient. Accordingly, the equalization operation of the slave chip in the fourth phase will not be withdrawn due to insufficient time. Therefore, by adopting the system provided by this embodiment, the risk of the chip exiting the equalization operation due to insufficient equalization time can be reduced to a certain extent, and the risk of failure of the link negotiation between the chip and the opposite chip can be reduced.
  • the memory is configured to store the channel type table.
  • the system software is specifically configured to acquire a PHY supported by the main chip and sent by the main chip. Type, and the type of PHY supported by the slave chip that is read and sent by the slave chip.
  • the system software does not directly read the PHY types supported by the master chip and the slave chip.
  • the PHY type supported by the master chip is read by the master chip and sent to the system software
  • the PHY type supported by the slave chip is read by the slave chip and sent to the system software. In this way, the system software only needs to obtain the relevant information sent by the master chip and the slave chip, so the operation of the system software will be relatively simple.
  • the system software directly reads a PHY type supported by the master chip and a PHY type supported by the slave chip.
  • the master chip and the slave chip do not need to do any operation.
  • the slave chip is configured to work according to the work of the slave chip.
  • the PHY type configures an equalization circuit of the slave chip, and determines an equalization time required by the slave chip in the third stage of the equalization according to the equalization circuit of the slave chip.
  • the system software is specifically configured to configure an equalization time of the master chip in the third phase of the equalization according to an equalization time required by the slave chip in the third phase of the equalization.
  • the slave chip is specifically configured to configure the slave by turning on or off according to a working PHY type of the slave chip.
  • the chip's equalization circuit is specifically configured to configure the slave by turning on or off according to a working PHY type of the slave chip.
  • the main chip is configured to work according to the working PHY of the main chip.
  • Type configure the equalization circuit of the main chip, and determine the equalization time required by the main chip in the fourth stage of the equalization according to the equalization circuit of the main chip.
  • the system software is specifically configured to configure an equalization time of the slave chip in the fourth stage of the equalization according to an equalization time required by the master chip in the fourth stage of the equalization.
  • the master chip is specifically configured to configure the master by turning on or off according to a working PHY type of the master chip.
  • the chip's equalization circuit is specifically configured to configure the master by turning on or off according to a working PHY type of the master chip.
  • the working PHY types of the master chip and the slave chip When both are SR, the system software is specifically configured to configure the equalization time of the master chip in the third phase of the equalization and the equalization time of the slave chip in the fourth phase of the equalization to the default values. .
  • the system software is specifically configured to read the equalization time of the slave chip in the third stage of the equalization and write it into the In the master chip, an equalization time of the main chip in the third phase of the equalization is used, and the equalization time of the main chip in the fourth phase of the equalization is read, and written into the The slave chip is used as an equalization time of the slave chip in the fourth stage of the equalization.
  • the working PHY type of the master chip and the slave chip When both are SR, the system software is specifically used to read the equalization time of the slave chip in the third stage of the equalization and write it into the master chip as the master chip in the The equalization time of the third stage of the equalization, and reading the equalization time of the master chip in the fourth stage of the equalization and writing it into the slave chip as the slave chip in the equalization The fourth phase of the equilibrium time.
  • the system software is specifically configured to balance the master chip in the third stage of the equalization time and the slave chip in the
  • the equalization time of the fourth phase of the equalization is configured as the default value.
  • FIG. 1 is a schematic structural diagram of a processor system using a PCIe bus provided in this application.
  • FIG. 2 is a schematic diagram of a signal channel between an RC and a graphics card provided by the present application.
  • FIG. 3 is a flowchart of establishing a chain according to the PCIe standard.
  • Figure 4 is a flowchart of the four stages of equalization.
  • FIG. 5 is a channel type table provided by the present application.
  • FIG. 6 is a flowchart of a method for configuring an equalization time provided by the present application.
  • FIG. 7 is a method for expressing a PHY type supported by a chip provided by the present application.
  • FIG. 8 is a correspondence table between PHY types and bit values supported by the chip provided by the present application.
  • FIG. 9A is a correspondence table between an identifier of a chip provided by the present application and a PHY type supported by the chip.
  • FIG. 9B is a manner for indicating a working PHY type of a chip provided by the present application.
  • FIG. 10 is a schematic diagram of an apparatus for configuring an equilibrium time provided by the present application.
  • FIG. 11 is a schematic diagram of another apparatus for configuring an equilibrium time provided by the present application.
  • FIG. 12 is a schematic diagram of another apparatus for configuring an equilibrium time provided by the present application.
  • FIG. 13 is a schematic structural diagram of a chip provided by this application.
  • FIG. 14 is a schematic structural diagram of a communication system provided by the present application.
  • FIG. 15 is a link structure diagram including a master chip, a slave chip, and a PCIe bus between them.
  • PCIe is a high-speed serial computer expansion bus standard. It is a type of computer bus standard PCI. It inherits the existing PCI bus programming concepts and communication standards.
  • the PCIe bus uses a high-speed serial point-to-point dual-channel high-bandwidth transmission method, so it has a faster transmission rate than the PCI bus.
  • the CCIX bus is based on the same physical architecture as the PCIe bus. The physical architecture includes an electrical sub-block and a logical sub-block.
  • the CCIX bus supports PCIe 1.0, PCIe 2.0, and PCIe 3.0. And PCIe4.0 transmission rate. .
  • PCIe / CCIX bus can be used not only for internal interconnection but also for external interconnection. It is worth noting that in this application, the PCIe / CCIX bus refers to a PCIe bus or a CCIX bus.
  • FIG. 1 shows a processor system using a PCIe bus.
  • the system includes a root component (RC), a switch chip (Switch), and a PCIe-to-PCI bridge.
  • RC root component
  • Switch switch chip
  • PCIe-to-PCI bridge PCIe-to-PCI bridge
  • the RC is also referred to as the root controller of the system, and is usually integrated on a central processing unit (CPU, Central Processor).
  • RC usually has multiple ports.
  • the RC can communicate with a component through each of the multiple ports.
  • the multiple ports may include multiple ports (referred to as PCIe ports) for connecting the PCIe bus.
  • PCIe ports multiple ports for connecting the PCIe bus.
  • the RC can be connected to an endpoint (Endpoint).
  • the Endpoint may be a graphics card, a network card, an optical channel card, a Switch, or an ASIC (Application Specific Integrated Circuit).
  • RC and DDR are connected through a DDR bus, so the port connected to DDR on the RC is not a PCIe port. Therefore, the multiple ports of the RC may be all PCIe ports or part of them may be PCIe ports.
  • the Switch is used to perform link extension on the RC. Specifically, on the one hand, the Switch and the RC are connected through a PCIe bus; on the other hand, the Switch has multiple ports. Through one port, the Switch can communicate with an EP through the PCIe bus. Therefore, based on the Switch, the RC can communicate with multiple endpoints through one port. As shown in Figure 1, the Switch has three ports, and the Switch can communicate with an ASIC through a PCIe bus through any one of the three ports.
  • the role of the PCIe-to-PCI bridge is bridging, which is used to implement the conversion between the PCIe bus and the PCI bus, so that it can be compatible with the original endpoints that support the PCI bus.
  • one end of the PCIe-to-PCI bridge is connected to the Switch through the PCIe bus, and the other end is connected to the PCI bus.
  • FIG. 1 also shows a plurality of PCI slots supporting the PCI bus standard. Chips or cards inserted in the PCI slots can be connected to the PCIe-to-PCI bridge through the PCI bus, and then connected through the Switch To the CPU.
  • the RC and the Endpoint can be directly connected through the PCIe bus, or can be connected through the PCIe bus and the connector. As shown in FIG. 2, the RC and the graphics card are connected in sequence through a PCIe bus, a connector, a PCIe bus, a connector, and a PCIe bus. It should be known that the lengths of multiple PCIe buses located between the RC and the Endpoint may be the same or different.
  • the PCIe / CCIX system may include a central processing unit CPU and its peripheral devices, wherein at least one of the channels between the CPU and its peripheral devices uses a PCIe / CCIX bus.
  • the PCIe / CCIX system may further include multiple CPUs and peripheral devices thereof, wherein at least one of the channels between the multiple CPUs uses a PCIe / CCIX bus, or a channel between one of the CPUs and peripheral devices At least one of the lanes uses a PCIe / CCIX bus.
  • FIG. 3 it shows a flowchart of the PCIe system from power-on to establishing a communication connection.
  • the link state machine in the main chip sequentially enters the control link: detection-polling-configuration-linkup-recovery .
  • the master chip detects whether the slave chip is in place.
  • the slave chip enters the Polling stage to perform bit and symbol lock and channel polarity determination.
  • the configuration phase determine the link bandwidth and link number, and perform channel-to-channel phase compensation.
  • the Linkup phase After completing the configuration, enter the Linkup phase, and the link runs to Linkup at a low speed, that is, the master chip and the slave chip establish a connection.
  • the system enters the recovery phase, performs equalization time and speed change, and after the speed change is completed and the speed is increased to a high speed, the system returns to the connected state to realize business data transmission.
  • the main chip described in this application refers to a chip including a downstream port (DSP, Downstream Port). Sometimes, the main chip is also referred to as the downlink port.
  • the slave chip described in this application refers to a chip including an upstream port (USP, Upstream Port). Sometimes the slave chip is also referred to as the uplink port for short.
  • the main chip may be an RC or a switch chip.
  • the slave chip may be an endpoint device (Endpoint) or a switch chip (Switch).
  • the master chip is a switch chip
  • the slave chip may be an endpoint device.
  • the endpoint device may be a graphics card, a network card, an optical channel card, a memory card, or a switch chip.
  • the purpose of the equalization implemented in the foregoing recovery phase is to achieve a stable increase in link rate, thereby achieving variable speed.
  • the equalization is explained here.
  • the transmission signal in the communication system undergoes distortion changes, that is, the channel is a non-ideal channel.
  • the technique of compensating and correcting these characteristics in the channel is called equalization.
  • the time required for this equalization process is equalization time.
  • the equilibrium consists of four stages. Referring to FIG. 4, the four stages may be a first stage (Phase 0), a second stage (Phase 1), a third stage (Phase 2), and a fourth stage (Phase 3).
  • the master chip and the slave chip may be located in the same processor system, or may be located in different processor systems, wherein the master chip and the slave chip are connected through a PCIe / CCIX bus.
  • the method will be described below with reference to the RC and Endpoint in FIG. 1.
  • RC in FIG. 1 corresponds to the master chip
  • Endpoint corresponds to the slave chip.
  • the RC sends the initial parameters needed by the Endpoint to the Endpoint.
  • the maximum dwell time of the Endpoint at this stage is 12 ms.
  • the maximum stay time of the RC (or Endpoint) in any one of the four stages is the equilibrium time of the RC (or Endpoint) in this stage.
  • the maximum dwell time of RC in Phase3 is equalized by RC in Phase3.
  • the maximum staying time of the Endpoint in the balanced Phase 2 is the equilibrium time of the Endpoint in the Phase 2.
  • the data is transmitted and received between the RC and the Endpoint at a higher rate after the speed change, and the set initial parameters are used for this transmission and reception operation. Specifically, at this stage, the RC sends data to the Endpoint first, and the Endpoint stays for a while after receiving the data.
  • the Endpoint After determining that the bit error rate of the data is less than 10E-4, the Endpoint enters the next stage—Phase 2. Before the Endpoint enters the next stage, the Endpoint feeds back a message to the RC to indicate that it will enter the next stage, and the RC will enter the next stage after receiving the information.
  • the maximum stay time of the Endpoint in Phase 1 is 12 ms
  • the maximum stay time of the RC in Phase 1 is 24 ms.
  • the Endpoint adjusts the RC's transmit (Tx) parameters and adjusts its own receive (Rx) parameters accordingly, in order to expect the bit error rate of the link between the Endpoint and the RC to be less than 10E-12. It should be known that if the bit error rate between the two does not meet the above requirements, Endpoint will repeat the above adjustment operation, and after the link bit error rate is less than 10E-12, both Endpoint and RC enter the next stage ——Phase 3. Optionally, at this stage, the maximum time for the RC stay is 32ms, and the maximum time for the Endpoint stay is 24ms.
  • the RC adjusts the transmit (Tx) parameters of the Endpoint and adjusts its own receive (Rx) parameters accordingly in order to expect the bit error rate of the link between the Endpoint and the RC to be less than 10E-12. It should be known that if the bit error rate between the two is not less than 10E-12, the RC will repeat the above adjustment operation until the bit error rate of the link is less than 10E-12 and after Phase 3 ends. At this point, the equilibrium time negotiation is also over. Under normal circumstances, the link rate will be increased to a higher level, that is, the link reaches a high-speed connection state.
  • the channel type table includes at least the port number of the master chip, the identifier of the slave chip, and the channel type. It is worth noting that the port number of the master chip can uniquely mark a specific port of a specific master chip, and the identifier of the slave chip can uniquely mark a specific slave chip. According to the port number of the master chip and the identification of the slave chip, the type of the channel between the port of the master chip and the slave chip can be uniquely determined.
  • the channel type table is stored in the PCIe system, powering on, powering down, and resetting the system will not cause the channel type table to be lost.
  • the channel type table is stored in a memory in the PCIe system.
  • the channel types include long distance (LR, Long Reach) and short distance (SR, Short Reach). This distinction is based on the magnitude of the channel loss. It should be clear that the channel loss corresponding to LR is greater than the channel loss corresponding to SR. Optionally, the channel loss corresponding to LR is greater than or equal to 22 dB and less than 32 dB, and the channel loss corresponding to SR is less than 22 dB.
  • the channel type is related to the magnitude of the channel loss. It should be known that the channel type can also be related to parameters in other dimensions, such as the bandwidth of the channel, whether the time period of the channel is idle or busy, and so on. Further, in this application, the channel types are divided into LR and SR according to the magnitude of the channel loss. It should be known that the channel type can also be divided into finer granularity. For example, the channel type can be divided into LR, Middle Distance (MR) and SR, and it can also be divided into XLR , Extra Long Long), LR, MR, SR, and Ultra Short Distance (XSR, Extra Short Distance).
  • MR Middle Distance
  • SR Ultra Short Distance
  • the physical layer (PHY) type supported by the master chip and the PHY type supported by the slave chip need to be configured in advance.
  • the type of PHY supported by the chip is related to the channel loss that the chip can drive.
  • the type of PHY supported by the main chip may only support LR, or only SR, or both LR and SR.
  • the PHY type supported by the slave chip may also support only LR, or only SR, or both LR and SR. It should be noted that the channel loss that can be driven by a chip that supports a PHY type of LR is greater than the channel loss that can be driven by a chip that supports a PHY type of SR.
  • the PHY types supported by the chip are stored in the register of the chip. Specifically, the PHY type supported by the master chip is stored in a register of the master chip, and the PHY type supported by the slave chip is stored in a register of the slave chip.
  • the type of PHY supported by the chip may also be related to the power consumption, cost, and application scenario of the chip.
  • the PHY type supported by the master chip or the slave chip is a subset or the full set of the set Q.
  • the set Q includes LR and SR
  • the PHY type supported by the master chip may be only LR, or only SR, or both LR and SR
  • the PHY type supported by the slave chip may also be LR , Or only SR, or both LR and SR.
  • BIOS Basic Input Output System
  • the method provided in this application includes the following steps.
  • the determined channel type is a long-distance LR or a short-distance SR.
  • the channel type table is stored in the memory of the PCIe / CCIX system in advance.
  • the memory may be a flash memory or an electronic erasable programmable read-only memory (EEPROM).
  • the channel type table includes at least three columns: the port number of the master chip, the identifier of the slave chip, and the channel type. The type of the channel between the master chip and the slave chip can be uniquely determined according to the port number of the master chip and the identifier of the slave chip.
  • the channel type may be LR or SR.
  • the classification is performed from the dimension of channel loss.
  • the loss of a channel of type LR is greater than the loss of a channel of type SR.
  • the PHY type supported by the main chip can be only LR, or only SR, or LR and SR.
  • the PHY type supported by the slave chip can also be LR only, or only SR, or LR and SR.
  • the type of PHY supported by a chip is related to the amount of channel loss that the chip can drive. It should be noted that the channel loss that can be driven by a chip that supports a PHY type of LR is greater than the channel loss that can be driven by a chip that supports a PHY type of SR.
  • the system software can directly obtain the PHY type supported by the master chip and the PHY type supported by the slave chip.
  • the master chip first obtains the PHY types supported by the master chip, and then sends the PHY types supported by the master chip to the system software
  • the slave chip first obtains the PHY types supported by the slave chip, and then supports the slave chip.
  • the PHY type is sent to the system software.
  • the type of PHY supported by the main chip is stored in a register of the main chip in advance.
  • This register can be a status register.
  • the PHY type supported by the main chip may be represented by at least one bit.
  • the PHY type supported by the chip is represented by two bits, the two bits are 1 and 2, and the values of the two bits can be 00, 01 or 10.
  • FIG. 8 in the case where the chip in FIG. 8 is the main chip described in this application, it is easy to know that 00 indicates that the PHY type supported by the main chip is SR, and 01 indicates that the PHY type supported by the main chip is LR, 10 means that the PHY types supported by the main chip are SR and LR.
  • the type of PHY supported by the slave chip is stored in advance in a register of the slave chip.
  • the PHY type supported by the slave chip is also stored in a register of the slave chip in advance.
  • This register can be a status register.
  • the PHY type supported by the slave chip may also be represented by at least one bit.
  • the PHY type supported by the slave chip is represented by two bits.
  • FIG. 8 In the case where the chip in FIG. 8 is the slave chip, it is easy to know that 00 represents the PHY type supported by the slave chip as SR, and 01 represents the PHY type supported by the slave chip as LR. , 10 indicates that the PHY types supported by the slave chip are SR and LR.
  • the meaning of “the type of PHY supported by the master chip and the type of PHY supported by the slave chip includes the determined channel type” is described in detail below.
  • the determined channel type is SR
  • the master chip and The PHY types supported by the slave chip all include the determined channel type.
  • the master chip and The PHY types supported by the slave chip all include the determined channel type.
  • the identification of the chip and the type of PHY supported by the chip may be stored.
  • the chip corresponds to a master chip and a slave chip in the present application.
  • the above content may be stored in a register of a corresponding chip. Further, the above contents can be stored in the form of a table (as shown in FIG. 9A). Then the table includes at least two columns, one of which is the identification of the chip, and the other is the PHY type supported by the corresponding chip. The identification of the chip may be represented by at least one bit.
  • step S1 it is determined that the type of the channel between the master chip and the slave chip is SR, and in step S2, it is determined that the PHY types supported by the master chip are LR and SR, and the PHY types supported by the slave chip are SR.
  • both the PHY type supported by the master chip and the PHY type supported by the slave chip include the determined channel type.
  • the working PHY type of the master chip and the working PHY of the slave chip can be determined.
  • Type The working PHY type of the master chip and the working PHY type of the slave chip are both SR, that is, the same as the channel type determined in step S1.
  • the so-called "working PHY type of the master chip” means that after a channel between the port of the master chip and the slave chip is established, between the master chip and the slave chip
  • the type of PHY that the main chip actually works when transferring service data It should be known that although the PHY type supported by the main chip may be one or multiple. But the main chip has only one working PHY type. Conventionally, multiple means more than two. Optionally, the plurality is two.
  • the so-called “working PHY type of the slave chip” refers to the transfer of services between the master chip and the slave chip after the channel between the port of the master chip and the slave chip is established. Data, the type of PHY that this slave chip actually works.
  • the PHY type supported by the slave chip may be one or multiple. But there is only one working PHY type for this slave chip.
  • the method provided in this application may further include the following steps:
  • the actual working PHY type of the master chip and the slave chip are the same as the channel type determined by S1.
  • the actual working PHY type of the master chip and the slave chip refers to the PHY type of the master chip and the slave chip when transmitting service data.
  • the value of bit 24 may be 0 or 1. This value is used to indicate the actual working PHY type of the master chip or the slave chip when transmitting service data between the master chip and the slave chip. Specifically, if the value of bit 24 is 0, it means that the working PHY type of the master chip or the slave chip is SR; if the value of bit 24 is 1, it means that the working PHY type of the master chip or the slave chip is Is LR.
  • the method provided in this application further includes:
  • the configuration method provided in the present application may further include: writing an equalization time of the master chip in a third stage of equalization into a register of the master chip; and The horizontal equalization time of the fourth stage is written into a register of the slave chip.
  • the values of bits 22 to 20 are used to indicate the chip's equalization time in the fourth stage of the equalization.
  • the values of bits 18 to 16 are used to indicate the chip's equalization time in the third phase of the equalization.
  • the slave chip will configure the equalization circuit of the slave chip accordingly, and determine that the slave chip is in the third stage of equalization according to the equalization circuit of the slave chip. (Phase 2) Equilibrium time. Then, the system software configures the equalization time of the master chip in the third stage according to the equalization time required by the slave chip in the third stage of equalization.
  • the equalization time of the slave chip in Phase 2 and the equalization time of the master chip in Phase 2 are related. Therefore, the system software can further configure the master chip to configure the master chip in Phase 2 Equilibrium time in Phase 2. It should be known that the equalization time of the main chip in Phase 2 determined by the system software is greater than or equal to the actual equalization time of the main chip in Phase 2. Therefore, the equalization operation of the main chip in Phase 2 will not be due to the equalization time. It is too short to exit, which causes the link negotiation between the master chip and the slave chip to fail. That is, the equalization operation of the main chip in Phase 2 can be successfully completed.
  • the total equalization circuit of the slave chip is set in advance.
  • a logic diagram including a master chip, a slave chip, and a PCIe bus between them is provided for the present application.
  • the total equalization circuit of the slave chip includes a continuous time linear equalizer (CTLE, Continuous Time Linear Equalizer) and a third-order decision feedback equalizer (DFE, Decision Backed Equalizer). Select the actual working equalization circuit by turning it on or off. For example, when the working PHY type of the slave chip is LR, the actual working equalization circuit is CTLE and the third-order DFE are connected in series, and when the working PHY type of the slave chip is SR, the actual working equalization circuit is only CTLE.
  • CTLE Continuous Time Linear Equalizer
  • DFE Decision Backed Equalizer
  • the slave chip will configure the equalization circuit of the slave chip accordingly", in fact, the slave chip selects the actual work from the total equalization circuit of the slave chip by turning on or off accordingly. Equalization circuit.
  • the equalization time of the master chip in the third stage is configured as T1
  • the working PHY type of the slave chip is LR
  • the master chip The equalization time in the third stage is configured as T2, and then the value of T2 is greater than the value of T1.
  • the main chip when the working PHY type of the main chip is determined, the main chip will configure the equalization circuit of the main chip accordingly, and determine that the main chip is in the fourth phase of the equalization (Phase) according to the equalization circuit of the main chip. 3) The required equilibrium time. Then, the system software configures the equalization time of the slave chip in the fourth phase of the equalization according to the equalization time required by the master chip in the fourth phase of the equalization.
  • the equalization time of the master chip in Phase 3 and the equalization time of the slave chip in Phase 3 are related. Therefore, the system software can further configure the equalization time of the master chip in Phase 3 in the master chip. It should be known that the equalization time of the slave chip in Phase 3 configured by the system software is greater than or equal to the actual dwell time of the slave chip in Phase 3. Therefore, the equalization operation of the slave chip in Phase 3 will not be caused by the equalization time. Short-term exit, resulting in system link negotiation failure. That is, the equalization operation of the slave chip in Phase 3 can be successfully completed.
  • the total equalization circuit of the main chip is also set in advance.
  • the total equalization circuit of the main chip includes a third-order forward feedback equalizer (FFE, Feed Forward Equalizer), and then the main chip can select an actual working equalization circuit by turning on or off.
  • FFE Feed Forward Equalizer
  • the main chip can select an actual working equalization circuit by turning on or off.
  • the main chip can select the actual working equalization circuit by turning on or off.
  • the equalization time of the slave chip in the fourth stage is configured as T3, and when the working PHY type of the master chip is LR, the slave chip The equalization time in the fourth stage is configured as T4, and then the value of T4 is greater than the value of T3.
  • the system software when the working PHY types of the master chip and the slave chip are both SR, the system software will balance the master chip in the third stage and the slave chip in the
  • the equalization time in the fourth stage is configured as the default value.
  • the default value may be set in advance according to a design document of a chip manufacturer or a chip manufacturer ’s test of the chip, or may be a standard value commonly used in the industry.
  • the system software reads the equalization time of the slave chip in the third stage and writes it into the master chip to As the equalization time of the master chip in the third stage, and reading the equalization time of the master chip in the fourth stage and writing it into the slave chip as the slave chip Equilibrium time in the fourth stage.
  • the system software when the working PHY types of the master chip and the slave chip are both SR, the system software reads the equalization time of the slave chip in the third stage, and Write to the master chip as the equalization time of the master chip in the third stage, and read the equalization time of the master chip in the fourth stage and write it to the slave In the chip, the equalization time of the slave chip in the fourth stage is used.
  • the system software sets the equalization time of the master chip in the third stage and the equalization time of the slave chip in the fourth stage Both are configured as defaults.
  • the default value may be set in advance according to a design document of a chip manufacturer or a chip manufacturer's test of the chip, or may be a general standard value in the industry.
  • the master chip has a reference value in the third stage of the equalization time; corresponding to the working PHY type of the master chip, the slave chip is in the fourth stage There is also a reference value for the equalization time.
  • These reference values can come from the design documents of the chip manufacturer, the test of the chip by the chip manufacturer, or the industry standard values.
  • the link state opportunity completes the chain establishment according to the process shown in FIG. 3 according to the negotiation process stipulated by the PCIe bus standard.
  • This application also provides a device for configuring an equalization time.
  • the device can be used to perform the foregoing method for configuring the equalization time. Therefore, for the device described in this embodiment, reference may be made to related limitations and descriptions of the foregoing method embodiments, in order to save space. The same or similar parts are not repeated in this embodiment. It should be noted that the device described in this embodiment may be a management chip of the system.
  • the device 300 includes a transceiver 301 and a manager 303.
  • the transceiver 301 is configured to receive a port number of a master chip and an identifier of a slave chip.
  • the manager is used to determine the type of the channel between the port of the master chip and the slave chip by looking up the channel type table according to the port number of the master chip and the identifier of the slave chip.
  • the type of the determined channel (or "the determined channel type") is LR or SR.
  • the port number of the main chip received by the transceiver 301 may be sent by the main chip.
  • the identification of the slave chip received by the transceiver 301 may be sent by the slave chip.
  • the transceiver 301 is further configured to receive a PHY type supported by the master chip and a PHY type supported by the slave chip.
  • the PHY type supported by the master chip may be LR, or SR, or LR and SR; and the PHY type supported by the slave chip may be LR, or SR, or LR and SR.
  • the manager 302 is further configured to determine whether the PHY type supported by the master chip and the PHY type supported by the slave chip both include the determined channel type, and if both are included, determine the Working PHY type and the PHY working type of the slave chip. It should be noted that the working PHY type of the master chip and the working PHY type of the slave chip are the same as the determined channel type.
  • the type of PHY supported by the main chip received by the transceiver 301 may be sent by the main chip.
  • the type of PHY supported by the slave chip received by the transceiver 301 may be sent by the slave chip.
  • manager 302 is further configured to configure the equalization time of the master chip in the third phase of the equalization and the slave chip in the fourth phase of the equalization according to the working PHY type of the master chip and the working PHY type of the slave chip. Equalization time.
  • the slave chip configures the equalization circuit of the slave chip according to the working PHY type of the slave chip, and determines the equalization time required by the slave chip in the third stage of equalization according to the equalization circuit of the slave chip. . Then, the manager 302 configures the equalization time of the master chip in the third stage of equalization according to the equalization time required by the slave chip in the third stage of equalization.
  • the main chip configures the equalization circuit of the main chip according to the working PHY type of the main chip, and determines the equalization time required by the main chip in the fourth stage of equalization according to the equalization circuit of the main chip. . Then, the manager 302 configures the equalization time of the slave chip in the fourth stage of equalization according to the equalization time required by the master chip in the fourth stage of equalization.
  • the manager 302 when the working PHY type of the master chip and the working PHY type of the slave chip are both SR, the manager 302 is specifically configured to equalize the master chip in the third stage of the equalization time. And the equalization time of the slave chip in the fourth stage is configured as a default value.
  • the manager 302 is specifically configured to read the equalization time of the slave chip in the third stage and write it to the master chip To use as the master chip's equalization time in the third stage, and read the master chip's equalization time in the fourth stage and write it to the slave chip as the slave chip in The equalization time of the fourth stage.
  • the manager 302 when the working PHY type of the master chip and the working PHY type of the slave chip are both SR, the manager 302 is specifically configured to read the balance of the slave chip in the third stage. Time, and write it into the main chip as the equalization time of the main chip in the third stage, and read the equalization time of the main chip in the fourth stage and write it into the The slave chip is used as the equalization time of the slave chip in the fourth stage.
  • the manager 302 is specifically configured to equalize the master chip in the third stage and the slave chip in the fourth stage Are set to the default value.
  • This application also provides a second device for configuring an equalization time.
  • the device can also be used to implement the foregoing method for configuring an equalization time. Therefore, the device described in this embodiment can also refer to the related limitations and descriptions of the foregoing method embodiments. It should be noted that the device described in this embodiment may be a BIOS.
  • this embodiment provides an apparatus 400 for configuring an equilibrium time.
  • the apparatus includes an obtaining unit 401, a determining unit 403, and a configuration unit 405.
  • the obtaining unit 401 is configured to obtain the port number of the master chip and the identifier of the slave chip.
  • the determining unit 403 is configured to determine the type of the channel between the port of the master chip and the slave chip by looking up the channel type table.
  • the type of the determined channel (or "the determined channel type") is LR or SR.
  • the obtaining unit 401 is further configured to obtain a PHY type supported by the master chip and a PHY type supported by the slave chip.
  • the PHY type supported by the master chip may be LR, or SR, or LR and SR; and the PHY type supported by the slave chip may also be LR, or SR, or LR and SR.
  • the determining unit 403 is further configured to determine whether the PHY type supported by the master chip and the PHY type supported by the slave chip both include the foregoing determined channel types.
  • Both the PHY type supported by the master chip and the PHY type supported by the slave chip include In the foregoing determined channel type, the working PHY type of the master chip and the working PHY type of the slave chip are determined.
  • the working PHY type of the master chip and the working PHY type of the slave chip are the same as the previously determined channel types.
  • the configuration unit 405 is configured to configure an equalization time of the slave chip in the fourth stage (or Phase 3) of the equalization according to the working PHY type of the master chip, and configure the master chip according to the working PHY type of the slave chip. Equilibrium time in the third phase (or Phase 2).
  • the so-called “configuration unit 405 configures the equalization time of the slave chip in the fourth stage (or Phase 3) of the equalization according to the working PHY type of the master chip", specifically, the master chip is based on the working PHY type of the master chip. Configure the equalization circuit of the main chip, and determine the equalization time required by the main chip in the fourth stage of equalization according to the equalization circuit of the main chip; and then configure the unit 405 according to the equalization time required by the main chip in the fourth stage of equalization Configure the equalization time of the slave chip in the fourth stage of equalization.
  • the so-called “configuration unit 405 configures the master chip's equalization time in the third stage (or Phase 2) of the equalization according to the working PHY type of the slave chip", specifically, the slave chip according to the working PHY type of the slave chip, Configure the equalization circuit of the slave chip, and determine the equalization time required by the slave chip in the third stage of equalization according to the equalization circuit of the slave chip; and then configure the unit 405 according to the equalization time required by the slave chip in the third stage of equalization, Configure the equalization time of the master chip in the third phase of the equalization.
  • the configuration unit 405 when the working PHY type of the master chip and the working PHY type of the slave chip are both SR, the configuration unit 405 is specifically configured to equalize the master chip in the third stage of the equalization time And the equalization time of the slave chip in the fourth stage is configured as a default value.
  • the configuration unit 405 is specifically configured to read the equalization time of the slave chip in the third stage and write it to the master chip To use as the master chip's equalization time in the third stage, and read the master chip's equalization time in the fourth stage and write it to the slave chip as the slave chip in The equalization time of the fourth stage.
  • the configuration unit 405 when the working PHY type of the master chip and the working PHY type of the slave chip are both SR, the configuration unit 405 is specifically configured to read the equalization of the slave chip in the third stage. Time, and write it into the main chip as the equalization time of the main chip in the third stage, and read the equalization time of the main chip in the fourth stage and write it into the The slave chip is used as the equalization time of the slave chip in the fourth stage.
  • the configuration unit 405 is specifically configured to equalize the master chip in the third stage and the slave chip in the fourth stage Are set to the default value.
  • the apparatus 500 includes a central processing unit (CPU, Central Processor) 501 and a memory 502.
  • the memory 502 is used to store code, and the CPU 501 is used to The code stored in the memory 502 is executed to implement the functions of the device described in this embodiment.
  • the CPU is a CPU of a processor system to which the PCIe bus is applied.
  • the memory 502 is further configured to store a channel type table.
  • the CPU501 is used to obtain the port number of the master chip and the identifier of the slave chip, and then, according to the port number of the master chip and the identifier of the slave chip, determine the location between the port of the master chip and the slave chip by looking up the channel type table.
  • the type of channel It should be noted that the type of the determined channel (or "the determined channel type") may be LR or SR.
  • the CPU501 is further configured to obtain a PHY type supported by the master chip and a PHY type supported by the slave chip, and when the determined channel type is included in both the PHY type supported by the master chip and the PHY type supported by the slave chip, determine the The working PHY type of the master chip and the working PHY type of the slave chip.
  • the working PHY type of the master chip and the working PHY type of the slave chip are the same as the determined channel type.
  • the PHY type supported by the master chip may be only LR, or only SR, or LR and SR.
  • the PHY type supported by the slave chip may also be LR, or only SR, or For LR and SR.
  • the CPU 501 is further configured to configure an equalization time of the slave chip in the fourth stage of equalization according to the working PHY type of the master chip, and according to the The working PHY type of the slave chip configures the equalization time of the master chip in the third stage of the equalization.
  • the so-called "CPU501 configures the equalization time of the slave chip in the fourth phase (or Phase 3) of the equalization according to the working PHY type of the master chip"
  • the master chip configures the The equalization circuit of the main chip, and according to the equalization circuit of the main chip, determine the equalization time required by the main chip in the fourth stage of equalization; then the CPU 501 configures the slave according to the equalization time required by the main chip in the fourth stage of equalization The equalization time of the chip in the fourth stage of equalization.
  • the so-called "CPU501 configures the master chip's equalization time in the third stage (or Phase 2) of the equalization according to the working PHY type of the slave chip" specifically refers to: the slave chip configures the The equalization circuit of the slave chip determines the equalization time required by the slave chip in the third stage of equalization according to the equalization circuit of the slave chip; then the CPU 501 configures the master according to the equalization time required by the slave chip in the third stage of equalization. The equalization time of the chip in the third phase of the equalization.
  • the CPU 501 when the working PHY type of the master chip and the working PHY type of the slave chip are both SR, the CPU 501 is specifically configured to equalize the master chip in the third stage with the equalization time and the The slave chip's equalization time in the fourth stage is configured as a default value.
  • the CPU 501 is specifically configured to read the equalization time of the slave chip in the third stage and write it into the master chip, Taking the equalization time of the master chip in the third stage, and reading the equalization time of the master chip in the fourth stage and writing it into the slave chip as the slave chip in the Equilibrium time for the fourth stage.
  • the CPU 501 when the working PHY type of the master chip and the working PHY type of the slave chip are both SR, the CPU 501 is specifically configured to read the equalization time of the slave chip in the third stage And write it into the master chip as the equilibration time of the master chip in the third stage, and read the equilibration time of the master chip in the fourth stage and write it into the slave The chip is used as the equalization time of the slave chip in the fourth stage.
  • the CPU 501 is specifically configured to equalize the master chip in the third stage and the slave chip in the fourth stage. The time is configured as the default.
  • the present application further provides a chip, which is the master chip or the slave chip described in the foregoing embodiment.
  • a chip 600 provided by the present application, the chip 600 includes a first register 601, a transceiver 603, a second register 605, and a manager 607.
  • the first register 601 is used to store a PHY type supported by the chip 600. It is easy to know from the foregoing that the PHY type supported by the chip 600 may be LR, or SR, or LR and SR.
  • the transceiver 603 is configured to send the PHY type supported by the chip 600 to the system software or the management chip of the system, and receive the working PHY type of the chip 600 sent by the system software or the management chip of the system. It should be noted that the working PHY type of the chip 600 is determined according to the type of the channel between the chip 600 and another chip.
  • the type of PHY supported by chip 600 and the type of PHY supported by another chip include the type of the channel between chip 600 and another chip, and the type of the channel between chip 600 and another chip may be LR Or SR. It is worth noting that the type of the channel between the chip 600 and another chip is the same as the working PHY type of the chip 600.
  • the second register 605 is also used for the working PHY type of the memory chip 600.
  • the manager 607 is configured to configure the equalization circuit of the chip 600 according to the working PHY type of the chip 600, and then determine the equalization time of the chip 600 according to the equalization circuit of the chip 600.
  • the second register 605 is also used for storing the equalization time of the chip 600.
  • first register 601 and the second register 605 described in this embodiment may be the same register or different registers. And in an actual product form, one register may be used to implement the functions of the first register 601 or the second register 605, or more than two registers may be used. Therefore, the first register 601 and the second register 605 described in this embodiment are distinguished from functions, and their corresponding functions are different, instead of being distinguished from the actual form of the product.
  • FIG. 14 is a communication system 700 provided by the present application.
  • the communication system 700 includes system software 701, a master chip 703, and a slave chip 705. Among them, the master chip 703 and the slave chip 705 pass a PCIe / CCIX bus. Connected. It should be noted that the system software 701 may be a BIOS.
  • the system software 701 obtains the port number of the master chip 703 and the identifier of the slave chip 705, and determines the type of the channel between the port of the master chip 703 and the slave chip 705 by looking up the channel type table.
  • the determined channel type may be LR or SR.
  • system software 701 obtains the PHY types supported by the master chip 703 and the PHY types supported by the slave chip 705, and determines whether both the PHY types supported by the master chip 703 and the PHY types supported by the slave chip 705 include the determined channel type.
  • system software 701 can directly read the PHY types supported by the master chip 703 and the PHY types supported by the slave chip 705.
  • the main chip 703 reads the PHY types supported by the main chip 703, and sends the PHY types supported by the main chip 703 to the system software 701, and reads from the chip 705 the PHY type, and sends the PHY type supported from the chip 705 to the system software 701. That is, the PHY type supported by the master chip 703 acquired by the system software 701 is sent by the master chip 703, and the PHY type supported by the acquired slave chip 705 is sent by the slave chip 705.
  • the PHY type supported by the master chip 703 may be LR, or SR, or LR and SR
  • the PHY type supported by the slave chip 705 may also be LR, or SR, or LR and SR.
  • the system software 701 determines the working PHY type of the master chip 703 and the slave 705 based on the determined channel type.
  • the working PHY type where the working PHY type of the master chip 703 and the working PHY type of the slave chip 705 are the same as the determined channel type.
  • the system software 701 will also determine the equalization time of the slave chip 705 in the fourth stage of the equalization according to the working PHY type of the master chip 703.
  • the system software 701 will also determine the equalization time of the master chip 703 in the third phase of the equalization according to the working PHY type of the slave chip 705.
  • the communication system may further include a memory 702.
  • the memory 702 is configured to store the channel type table.
  • system software 701 will also determine the equalization time of the slave chip 705 in the fourth stage of equalization according to the working PHY type of the master chip 703", specifically, the master chip 703 configures the master
  • the equalization circuit of the chip 703 determines the equalization time required by the main chip 703 according to the equalization circuit of the main chip 703; then, the system software 701 configures the slave chip 705 in the Equilibrium time for the fourth stage.
  • the so-called "system software 701 will also determine the equalization time of the master chip 703 in the third stage of equalization according to the working PHY type of the slave chip 705", specifically: the slave chip 705 configures the slave chip according to the working PHY type of the slave chip 705
  • the equalization circuit of the chip 705, and the equalization time required by the slave chip 705 is determined according to the equalization circuit of the slave chip 705; then, the system software 701 configures the master chip 703 to Equilibrium time of the third stage.
  • the system software 701 can set the equalization time of the master chip 703 at the third stage of the equalization and the slave chip 705 at an The equalization time in the fourth stage is configured as the default value.
  • the system software 701 can read the equalization time of the slave chip 705 in the third stage of the equalization and write it into the master chip 703.
  • the system software 701 can read the equalization time of the slave chip 705 in the third stage of equalization. And write it into the master chip 703 as the equalization time of the master chip 703 in the third stage of the equalization, and read the equalization time of the master chip 703 in the fourth stage of the equalization and write it into the slave chip 705 In this example, the equalization time is taken as the slave chip 705 in the fourth phase of the equalization.
  • the system software 701 can balance the equalization time of the master chip 703 in the third stage of equalization and the equalization time of the slave chip 705 in the fourth stage of equalization.
  • the time is configured as the default.

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Abstract

本申请提供一种配置均衡时间的方法，应用于使用PCIe或CCIX总线的处理器系统。该方法是先确定主芯片的工作PHY类型和从芯片的工作PHY类型，然后根据主芯片的工作PHY类型确定从芯片在均衡的第四阶段的均衡时间，以及根据从芯片的工作PHY类型确定主芯片在均衡的第三阶段的均衡时间。采用该方案，能够减少由于均衡时间不充足而导致的链路协商失败的情况。进一步地，本申请还提供了执行该方法的装置、通信系统以及在执行该方法中提及的芯片。

Description

一种配置均衡时间的方法、芯片和通信系统
本申请要求于2018年05月23日提交中国国家知识产权局、申请号为201810503737.3、申请名称为“一种配置均衡时间的方法、芯片和通信系统”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及芯片技术领域，尤其涉及一种配置均衡时间的方法、芯片和通信系统。
背景技术
按照外围组件快速互连(PCIe，Peripheral Component Interconnect Express)总线标准或加速器的高速互联内存一致性(CCIX，Cache Coherent Interconnect for Accelerators)总线标准的规定，系统上电后先进行链路协商，然后才建立高速链路进行业务数据的收发。参见附图1，它示出了一个应用PCIe总线的处理器系统，以主芯片与从芯片之间的链路为例，系统上电后，主芯片和从芯片先进行链路协商，协商完成后才建立高速链路进行业务数据的交互。
需要说明的是，链路协商包含链路均衡(简称为“均衡”)，链路均衡是通过均衡电路实现的，链路均衡的目的是为了补偿因为链路损耗而造成的该链路上传输的信号的劣化。参见附图4，它示出了均衡的四个阶段。当前，均衡的每一阶段都规定了固定的均衡时间，比如在第三阶段(Phase 2)，从芯片的均衡时间为24ms，主芯片的均衡时间为32ms。如果该主芯片(或从芯片)在规定的均衡时间内没有完成对应的均衡操作，则该主芯片(或从芯片)会退出均衡，从而导致位于该主芯片和该从芯片之间的链路协商失败。
发明内容
本申请提供一种配置均衡时间的方法，用于灵活地配置均衡时间，以在一定程度上降低因为均衡时间不够而导致链路协商失败的情况。进一步地，本申请还提供了执行该方法的装置和通信系统，以及在执行该方法中用到的一种芯片。
第一方面，本申请提供了一种配置均衡时间的方法。该方法包括下述步骤。
获取主芯片的端口号和从芯片的标识，通过查找通道类型表，确定位于所述主芯片的端口和所述从芯片之间的通道的类型。其中，所述确定的通道类型为长距LR或短距SR。
获取所述主芯片支持的物理层(PHY，Physical Layer)类型和所述从芯片支持的PHY类型，并判断所述主芯片支持的PHY类型和所述从芯片支持的PHY类型是否均包括所述确定的通道类型。其中，所述主芯片和所述从芯片支持的PHY类型均为长距(LR，Long Reach)和短距(SR，Short Reach)、LR或SR三种的一种。
在所述主芯片支持的PHY类型和所述从芯片支持的PHY类型中均包括所述确定的通道类型时，确定所述主芯片以及所述从芯片的工作PHY类型，其中，所述主芯片以及所述从芯片的工作PHY类型均与所述确定的通道类型相同。
根据所述从芯片的工作PHY类型，配置所述主芯片在均衡的第三阶段的均衡时间。以及，根据所述主芯片的工作PHY类型，配置所述从芯片在所述均衡的第四阶段的均衡时间。
在本实施例中，首先，确定位于该主芯片的特定端口和该从芯片之间的通道的类型。然后，判断该主芯片支持的PHY类型和该从芯片支持的PHY类型是否均包括该确定的通道类型。并在均包括的情况下，确定该主芯片和该从芯片的工作PHY类型。其中，该主芯片和该从芯片的工作PHY类型均与该确定的通道类型相同。最后，根据主芯片的工作PHY类型，配置从芯片在均衡的第四阶段的均衡时间，以及根据从芯片的工作PHY类型，配置该主芯片在均衡的第三阶段的均衡时间。也即，在本申请中，从芯片在均衡的第四阶段的均衡时间是根据主芯片的工作PHY类型配置的，主芯片在均衡的第三阶段的均衡时间是根据从芯片的工作PHY类型配置的。由于主芯片的工作PHY类型是确定的，所以从芯片在该第四阶段的均衡时间会被配置的比较充足，进而，其在该阶段的操作能够顺利完成，不会由于时间不充裕而退出。类似的，由于从芯片的工作PHY类型是确定的，主芯片在该第三阶段的均衡时间也将被配置的比较充足，进而，其在该第三阶段的操作也不会因为时间不够而退出。已知的，在均衡的各个阶段，如果芯片的均衡操作不能在均衡时间内完成，则该芯片将会退出均衡，进而导致该芯片和对端芯片之间的链路协商失败。因此，本申请提供的方法能够在一定程度上降低链路协商失败的风险。
需要说明的是，在该芯片为主芯片时，所述对端芯片为从芯片。在该芯片为从芯片时，所述对端芯片为主芯片。
可选的，该主芯片和该从芯片之间通过PCIe总线或CCIX总线连通。可知，本实施例提供的配置均衡时间的方法应用在使用PCIe总线或CCIX总线的处理器系统内。
可选的，在应用PCIe总线的处理器系统中，该主芯片为根组件(RC，Root Complex)或交换芯片，该从芯片是独立于该主芯片的端点设备(Endpoint)。应当知道的是，交换芯片在一些情况下可以为主芯片，在另一些情况下可以为从芯片。
可选的，该通道类型表包括该主芯片的端口号、该从芯片的标识和通道类型。需要说明的是，根据该主芯片的端口号和该从芯片的标识，能够唯一地确定位于该主芯片的端口和该从芯片之间的通道的类型。
可选的，所述通道类型是根据该通道的损耗确定的，其中，LR对应的通道损耗大于SR对应的通道损耗。
可选的，芯片支持的PHY类型是根据该芯片能够驱动的通道损耗确定。具体的，支持的PHY类型为LR的芯片能够驱动的通道损耗大于支持的PHY类型为SR的芯片能够驱动的通道损耗。
结合第一方面，在第一种可能的实现方式下，所谓“根据所述从芯片的工作PHY类型，配置主芯片在均衡的第三阶段的均衡时间”是按照下述方式实现的。首先，根据所述从芯片的工作PHY类型，配置所述从芯片的均衡电路。然后，根据所述均衡电路确定所述从芯片在所述第三阶段所需要的均衡时间。最后，根据所述从芯片在所述第三阶段所需要的均衡时间配置所述主芯片在所述第三阶段的均衡时间。
在本实施例中，根据该从芯片的工作PHY类型，能够为该从芯片配置一个比较合理的均衡电路。该从芯片的均衡电路能够兼顾均衡效果和效率。根据该从芯片的均衡电路，能够比较准确的估计出该从芯片在均衡的第三阶段需要的均衡时间。进一步地，根据该从芯 片在均衡的第三阶段需要的均衡时间，能够比较准确的配置出该主芯片在均衡的第三阶段的均衡时间。简而言之，采用本实施例，能够比较准确的配置出该主芯片在均衡的第三阶段的均衡时间。
可选的，所谓“配置所述从芯片的均衡电路”，是通过开通或关断的方式配置该从芯片的均衡电路。换句话说，该从芯片内预先配置有总的均衡电路，该均衡电路包括至少两个均衡器，该至少两个均衡器可以是相同的均衡器，也可以是不同的均衡器，则通过开通全部或者部分均衡器的方式，或，通过关断全部或者部分均衡器的方式，能够配置出该从芯片实际工作的均衡电路。容易知道，本实施例所述的“从芯片的均衡电路”是指该从芯片实际工作的均衡电路。运用本方案，能够简单且高效的配置该从芯片的均衡电路。
结合第一方面或第一方面的第一种可能实现方式，在第二种可能的实现方式下，所谓“根据所述主芯片的工作PHY类型，配置从芯片在均衡的第四阶段的均衡时间”是通过下述手段实现的。首先，根据所述主芯片的工作PHY类型，配置所述主芯片的均衡电路。然后，根据所述均衡电路确定所述主芯片在所述第四阶段所需要的均衡时间。最后，根据所述主芯片在所述第四阶段所需要的均衡时间配置所述从芯片在所述第四阶段的均衡时间。
在本实施例中，根据该主芯片的工作PHY类型，能够为该主芯片配置一个比较合理的均衡电路。该主芯片的均衡电路能够兼顾均衡效果和效率。根据该主芯片的均衡电路，能够比较准确的估计出该主芯片在均衡的第四阶段需要的均衡时间。进一步地，根据该主芯片在均衡的第四阶段需要的均衡时间，能够比较准确的配置出该从芯片在均衡的第四阶段的均衡时间。简而言之，采用本实施例，能够比较准确的配置出该从芯片在均衡的第四阶段的均衡时间。
可选的，所谓“配置所述主芯片的均衡电路”，是通过开通或关断的方式配置所述主芯片的均衡电路。需要说明的是，该主芯片内预先配置有总的均衡电路，该均衡电路包括至少两个均衡器，该至少两个均衡器可以是相同的均衡器，也可以是不同的均衡器，则通过开通全部或者部分均衡器，或关断全部或者部分均衡器的方式，能够配置出该主芯片实际工作的均衡电路。容易知道，本实施例所述的“主芯片的均衡电路”是指该主芯片实际工作的均衡电路。运用本方案，能够简单且高效的配置该主芯片的均衡电路。
结合第一方面、第一方面的第一种可能实现方式或第一方面的第二种可能实现方式，在第三种可能的实现方式下，在该从芯片的工作PHY类型为SR时，该主芯片在所述均衡的第三阶段的均衡时间被配置为T1。在该从芯片的工作PHY类型为LR时，该主芯片在所述均衡的第三阶段的均衡时间被配置为T2。需要说明的是，T2的值大于T1的值。
在本实施例中，主芯片在均衡的第三阶段的均衡时间是根据从芯片的工作PHY类型灵活配置的。具体的，如果从芯片的工作PHY类型为SR，则该均衡时间被配置的短一点，如果从芯片的工作PHY类型为LR，则该均衡时间被配置的长一点，这样不仅降低了链路协商失败的风险，而且增加了配置的灵活性。进一步地，在从芯片的工作PHY类型为SR时，可以将该均衡时间配置的短一点，从而避免了该均衡时间过长而导致的链路协商时间过长的缺陷。
结合第一方面或第一方面的第一种至第三种可能实现方式中任一种实现方式，在第四种可能的实现方式下，在该主芯片的工作PHY类型为SR时，该从芯片在所述均衡的第四 阶段的均衡时间被配置为T3.在该主芯片的工作PHY类型为LR时，该从芯片在所述均衡的第四阶段的均衡时间被配置为T4。则T4的值大于T3的值。
在该实施例中，如果主芯片的工作PHY类型为SR，则该均衡时间被配置的短一点，如果主芯片的工作PHY类型为LR，则该均衡时间被配置的长一点，这样不仅降低了链路协商失败的风险，而且增加了配置的灵活性。进一步地，在主芯片的工作PHY类型为SR时，可以将该均衡时间配置的短一点，从而避免了该均衡时间过长而导致的链路协商时间过长的缺陷。
结合第一方面或第一方面的第三种至第四种可能实现方式中任一种实现方式，在第五种可能的实现方式下，在所述主芯片和所述从芯片的工作PHY类型均为SR时，将所述主芯片在所述均衡的第三阶段的均衡时间和所述从芯片在所述均衡的第四阶段的均衡时间均配置为缺省值。
在所述主芯片和所述从芯片的工作PHY类型均为LR时，读取所述从芯片在所述第三阶段的均衡时间，并将其写入所述主芯片中，以作为所述主芯片在所述均衡的第三阶段的均衡时间；以及，读取所述主芯片在所述第四阶段的均衡时间，并将其写入所述从芯片中，以作为所述从芯片在所述均衡的第四阶段的均衡时间。
结合第一方面或第一方面的第三种至第四种可能实现方式中任一种实现方式，在第六种可能的实现方式下，在所述主芯片和所述从芯片的工作PHY类型均为SR时，读取所述从芯片在所述第三阶段的均衡时间，并将其写入所述主芯片中，以作为所述主芯片在所述均衡的第三阶段的均衡时间，以及，读取所述主芯片在所述第四阶段的均衡时间，并将其写入所述从芯片中，以作为所述从芯片在所述均衡的第四阶段的均衡时间。
在所述主芯片和所述从芯片的工作PHY类型均为LR时，将所述主芯片在所述均衡的第三阶段的均衡时间和所述从芯片在所述均衡的第四阶段的均衡时间均配置为缺省值。
上述两个实施例均提供了一种根据主芯片和从芯片的工作PHY类型，配置该主芯片在均衡的第三阶段的均衡时间以及该从芯片在均衡的第四阶段的均衡时间的方法。其中，该缺省值是本领域技术人员根据相关标准或经验设定的。
结合第一方面或第一方面的第一种至第六种可能实现方式中任一种实现方式，在第七种可能的实现方式下，所述主芯片支持的PHY类型被预先存储在所述主芯片的寄存器内。所述从芯片支持的PHY类型被预先存储在所述从芯片的寄存器内。在用到该主芯片支持的PHY类型或该从芯片支持的PHY类型时，可以直接到对应芯片的寄存器中读取，节约时间。
第二方面，本申请提供一种配置均衡时间的装置，该装置用于执行前述第一方面或第一方面任一实现方式所述的方法。该装置包括收发器和管理器。
收发器用于接收主芯片的端口号和从芯片的标识。对应的，管理器用于根据所述主芯片的端口号和所述从芯片的标识，通过查找通道类型表，确定位于所述主芯片的端口和所述从芯片之间的通道的类型。其中，所述确定的通道类型为LR或SR；
所述收发器还用于接收所述主芯片和所述从芯片支持的PHY类型。其中，所述主芯片和所述从芯片支持的PHY类型均为LR和SR、LR或SR三种的一种。对应的，所述管理器还用于判断所述主芯片支持的PHY类型和所述从芯片支持的PHY类型是否均包括所述确定的通道类型，并在所述主芯片支持的PHY类型和所述从芯片支持的PHY类型均包括所述确定的通道类型时，确定所述主芯片的工作PHY类型和所述从芯片的工作PHY类型。需要说 明的是，所述主芯片和所述从芯片的工作PHY类型均与所述确定的通道类型相同。
进一步地，所述管理器还用于根据所述从芯片的工作PHY类型，配置所述主芯片在均衡的第三阶段的均衡时间，以及，根据所述主芯片的工作PHY类型，配置所述从芯片在所述均衡的第四阶段的均衡时间。
采用本实施例提供的装置，能够实现第一方面或第一方面任一种可能的实现方式所述的配置均衡时间的方法。可知，采用本实施例提供的装置，能够使得该主芯片在均衡的第三阶段的均衡时间是充足的，相应的，该主芯片在该第三阶段的均衡操作不会因为时间不够而退出；以及，使得该从芯片在均衡的第四阶段的均衡时间也是充足的，相应的，该从芯片在该第四阶段的均衡操作也不会因为时间不够而退出。因此，采用本实施例提供的装置，能够在一定程度上降低因为均衡时间不够而导致芯片退出均衡操作，进而导致链路协商失败的风险。
结合第二方面，在第一种可能的实现方式下，所述管理器具体用于根据所述从芯片在均衡的第三阶段需要的均衡时间配置所述主芯片在所述均衡的第三阶段的均衡时间。其中，所述从芯片在均衡的第三阶段需要的均衡时间是所述从芯片根据所述从芯片的均衡电路确定的。所述从芯片的均衡电路是所述从芯片根据所述从芯片的工作PHY类型配置的。采用本实施例提供的装置，能够比较准确的配置出该主芯片在均衡的第三阶段的均衡时间。
可选的，所述从芯片的均衡电路是所述从芯片根据所述从芯片的工作PHY类型通过开通或关断的方式配置的。该方案的有益效果可以参见第一方面的相关实现方式对应的有益效果，此处不再赘述。
结合第二方面或第二方面的第一种可能实现方式，在第二种可能的实现方式下，所述管理器具体用于根据所述主芯片在均衡的第四阶段需要的均衡时间配置所述从芯片在所述均衡的第四阶段的均衡时间。其中，所述主芯片在均衡的第四阶段需要的均衡时间是所述主芯片根据所述主芯片的均衡电路确定的。所述主芯片的均衡电路是所述主芯片根据所述主芯片的工作PHY类型配置的。采用本实施例提供的装置，能够比较准确的配置出该从芯片在均衡的第四阶段的均衡时间。
可选的，所述主芯片的均衡电路是所述主芯片根据所述主芯片的工作PHY类型通过开通或关断的方式配置的。该方案的有益效果可以参见第一方面的相关实现方式对应的有益效果，此处不再赘述。
结合第二方面，在第三种可能的实现方式下，在所述主芯片和所述从芯片的工作PHY类型均为SR时，所述管理器具体用于将所述主芯片在所述均衡的第三阶段的均衡时间和所述从芯片在所述均衡的第四阶段的均衡时间均配置为缺省值。
在所述主芯片和所述从芯片的工作PHY类型均为LR时，所述管理器具体用于读取所述从芯片在所述均衡的第三阶段的均衡时间，并将其写入所述主芯片中，以作为所述主芯片在所述均衡的第三阶段的均衡时间，以及，读取所述主芯片在所述均衡的第四阶段的均衡时间，并将其写入所述从芯片中，以作为所述从芯片在所述均衡的第四阶段的均衡时间。
结合第二方面，在第四种可能的实现方式下，在所述主芯片和所述从芯片的工作PHY类型均为SR时，所述管理器具体用于读取所述从芯片在所述均衡的第三阶段的均衡时间，并将其写入所述主芯片中，以作为所述主芯片在所述均衡的第三阶段的均衡时间，以及， 读取所述主芯片在所述均衡的第四阶段的均衡时间，并将其写入所述从芯片中，以作为所述从芯片在所述均衡的第四阶段的均衡时间。
在所述主芯片和所述从芯片的工作PHY类型均为LR时，所述管理器具体用于将所述主芯片在所述均衡的第三阶段的均衡时间和所述从芯片在所述均衡的第四阶段的均衡时间均配置为缺省值。
如前文所述，前述两个实施例中的缺省值，是本领域技术人员根据相关标准或者经验设定的。
第三方面，本申请提供另一种配置均衡时间的装置，该装置也用于执行前述第一方面或第一方面任一实现方式所述的配置均衡时间的方法。该装置包括获取单元、确定单元和配置单元。
获取单元用于获取主芯片的端口号和从芯片的标识。对应的，确定单元用于通过查找通道类型表，确定位于所述主芯片的端口和所述从芯片之间的通道的类型。其中，所述确定的通道类型为长距LR或短距SR。
所述获取单元还用于获取所述主芯片支持的物理层PHY类型和所述从芯片支持的PHY类型。其中，所述主芯片支持的PHY类型以及所述从芯片支持的PHY类型均为LR和SR、LR或SR三种的一种。对应的，确定单元还用于根据所述主芯片支持的PHY类型和所述从芯片支持的PHY类型，判断所述主芯片支持的PHY类型和所述从芯片支持的PHY类型是否均包括所述确定的通道类型。
在所述主芯片支持的PHY类型和所述从芯片支持的PHY类型中均包括所述确定的通道类型时，确定单元还用于确定所述主芯片的工作PHY类型以及所述从芯片的工作PHY类型。其中，所述主芯片的工作PHY类型以及所述从芯片的工作PHY类型均与所述确定的通道类型相同。
配置单元用于根据所述从芯片的工作PHY类型，配置所述主芯片在均衡的第三阶段的均衡时间；以及，根据所述主芯片的工作PHY类型，配置所述从芯片在所述均衡的第四阶段的均衡时间。
本实施例提供的装置用于执行第一方面或第一方面任一种可能的实现方式所述的方法。采用本实施例提供的装置，能够使得该主芯片在均衡的第三阶段的均衡时间是充足的，也即该主芯片在该第三阶段的均衡操作不会因为时间不够而退出；以及，使得该从芯片在均衡的第四阶段的均衡时间也是充足的，也即该从芯片在该第四阶段的均衡操作也不会因为时间不够而退出。因此，采用本实施例提供的装置，能够在一定程度上降低因为均衡时间不够而导致芯片退出均衡操作，进而导致链路协商失败的风险。
结合第三方面，在第一种可能的实现方式下，所述配置单元具体用于根据所述从芯片在所述均衡的第三阶段需要的均衡时间配置所述主芯片在所述均衡的第三阶段的均衡时间。所述从芯片在所述均衡的第三阶段需要的均衡时间是所述从芯片根据所述从芯片的均衡电路确定的。所述从芯片的均衡电路是所述从芯片根据所述从芯片的工作PHY类型配置的。采用本实施例提供的装置，能够比较准确的配置出该主芯片在均衡的第三阶段的均衡时间。
可选的，该从芯片的均衡电路是所述从芯片根据所述从芯片的工作PHY类型通过开通或关断的方式配置的。
结合第三方面或第三方面的第一种可能实现方式，在第二种可能的实现方式下，所述配置单元具体用于根据所述主芯片在所述均衡的第四阶段需要的均衡时间配置所述从芯片在所述均衡的第四阶段的均衡时间。所述主芯片在所述均衡的第四阶段需要的均衡时间是所述主芯片根据所述主芯片的均衡电路确定的。所述主芯片的均衡电路是所述主芯片根据所述主芯片的工作PHY类型配置的。采用本实施例提供的装置，能够比较准确的配置出该从芯片在均衡的第四阶段的均衡时间。
可选的，所述主芯片的均衡电路是所述主芯片根据所述主芯片的工作PHY类型通过开通或关断的方式配置的。
结合第三方面，在第三种可能的实现方式下，在所述主芯片和所述从芯片的工作PHY类型均为SR时，所述配置单元具体用于将所述主芯片在所述均衡的第三阶段的均衡时间和所述从芯片在所述均衡的第四阶段的均衡时间均配置为缺省值。
在所述主芯片和所述从芯片的工作PHY类型均为LR时，所述配置单元具体用于读取所述从芯片在所述均衡的第三阶段的均衡时间，并将其写入所述主芯片中，以作为所述主芯片在所述均衡的第三阶段的均衡时间，以及，读取所述主芯片在所述均衡的第四阶段的均衡时间，并将其写入所述从芯片中，以作为所述从芯片在所述均衡的第四阶段的均衡时间。
结合第三方面，在第四种可能的实现方式下，在所述主芯片和所述从芯片的工作PHY类型均为SR时，所述配置单元具体用于读取所述从芯片在所述均衡的第三阶段的均衡时间，并将其写入所述主芯片中，以作为所述主芯片在所述均衡的第三阶段的均衡时间，以及，读取所述主芯片在所述均衡的第四阶段的均衡时间，并将其写入所述从芯片中，以作为所述从芯片在所述均衡的第四阶段的均衡时间。
在所述主芯片和所述从芯片的工作PHY类型均为LR时，所述配置单元具体用于将所述主芯片在所述均衡的第三阶段的均衡时间和所述从芯片在所述均衡的第四阶段的均衡时间均配置为缺省值。
第四方面，本申请提供了再一种配置均衡时间的装置，该装置也用于执行前述第一方面或第一方面任一实现方式所述的配置均衡时间的方法。该装置包括中央处理器(CPU，Central Processor Unit)和存储器，CPU用于执行存储在存储器内的代码以本实施例所述的装置的功能。
存储器用于存储通道类型表。对应的，CPU用于获取主芯片的端口号和从芯片的标识，然后根据该主芯片的端口号和该从芯片的标识，通过查找该通道类型表，确定位于该主芯片的端口和该从芯片之间的通道的类型。其中，所述确定的通道的类型为LR或SR。
CPU501还用于获取该主芯片支持的PHY类型和该从芯片支持的PHY类型，并在该主芯片支持的PHY类型和该从芯片支持的PHY类型中均包括该确定的通道类型时，确定该主芯片的工作PHY类型和该从芯片的工作PHY类型。其中，该主芯片的工作PHY类型和该从芯片的工作PHY类型均和所述确定的通道类型相同。该主芯片支持的PHY类型和该从芯片支持的PHY类型均为LR和SR，LR或SR三种中的一种。
在确定了该主芯片的工作PHY类型和该从芯片的工作PHY类型之后，CPU还用于根据该主芯片的工作PHY类型，配置该从芯片在均衡的第四阶段的均衡时间，以及根据该从芯片的工作PHY类型，配置该主芯片在均衡的第三阶段的均衡时间。与前述各个实现方式所述 的装置类似，采用本实施例所述的装置，能够在一定程度上降低由于均衡时间不够而导致系统退出均衡操作，进而导致链路协商失败的风险。
第五方面，本申请提供了一种芯片，该芯片可以为前述第一方面或其任一种实现方式、第二方面或其任一种实现方式、或第三方面或其任一种实现方式提及的主芯片或从芯片。该芯片包括第一寄存器、收发器、第二寄存器和管理器。
第一寄存器，用于存储所述芯片支持的物理层PHY类型，所述芯片支持的PHY类型为长距LR和短距SR、LR或SR三种的一种；
收发器，用于发送所述芯片支持的PHY类型以及接收所述芯片的工作PHY类型，所述芯片的工作PHY类型是根据所述芯片与另一个其他芯片之间的通道的类型确定的，其中，所述芯片和所述另一个其他芯片支持的PHY类型均包括所述确定的通道的类型，所述确定的通道的类型为LR或SR，所述工作PHY类型与所述确定的通道的类型相同；
第二寄存器，用于存储所述芯片的工作PHY类型，
管理器，用于根据所述芯片的工作PHY类型配置所述芯片的均衡电路，并根据所述芯片的均衡电路确定所述芯片的均衡时间。
应用本实施例所述的芯片，能够实现第一方面或第一方面的任一种可能的实现方式所述的方法，进而实现降低因均衡时间不够而导致系统退出均衡操作，进而导致链路协商失败的风险。
结合第五方面，在第一种可能的实现方式下，所述第二寄存器还用于存储所述芯片的均衡时间。
第六方面，本申请还提供一种通信系统，该通信系统包括系统软件、主芯片和从芯片。所述主芯片和所述从芯片之间通过总线或CCIX总线连通。
所述系统软件用于获取所述主芯片的端口号和所述从芯片的标识，通过查找通道类型表，确定位于所述主芯片的端口和所述从芯片之间的通道的类型。其中，所述确定的通道类型为长距LR或短距SR。
所述系统软件还用于获取所述主芯片支持的物理层PHY类型和所述从芯片支持的PHY类型，并判断所述主芯片支持的PHY类型和所述从芯片支持的PHY类型是否均包括所述确定的通道类型。其中，所述主芯片支持的PHY类型以及所述从芯片支持的PHY类型均为LR和SR、LR或SR三种的一种。
在所述主芯片支持的PHY类型和所述从芯片支持的PHY类型中均包括所述确定的通道类型时，所述系统软件还用于确定所述主芯片的工作PHY类型以及所述从芯片的工作PHY类型。其中，所述主芯片的工作PHY类型以及所述从芯片的工作PHY类型均与所述确定的通道类型相同。
在确定所述主芯片和所述从芯片的工作PHY类型之后，所述系统软件还用于根据所述从芯片的工作PHY类型，配置所述主芯片在均衡的第三阶段的均衡时间；以及，根据所述主芯片的工作PHY类型，配置所述从芯片在所述均衡的第四阶段的均衡时间。
采用本实施例提供的通信系统，能够使得该主芯片在均衡的第三阶段的均衡时间是充足的，相应的，该主芯片在该第三阶段的均衡操作不会因为时间不够而退出；以及，使得该从芯片在均衡的第四阶段的均衡时间也是充足的，相应的，该从芯片在该第四阶段的均衡操作也不会因为时间不够而退出。因此，采用本实施例提供的系统，能够在一定程度上 降低因为均衡时间不够而导致芯片退出均衡操作，进而导致位于该芯片和对端芯片之间的链路协商失败的风险。
结合第六方面，在第一种可能的实现方式下，存储器，用于存储所述通道类型表。
结合第六方面或第六方面的第一种可能实现方式，在第二种可能的实现方式下，所述系统软件具体用于获取所述主芯片读取并发送的所述主芯片支持的PHY类型，以及，所述从芯片读取并发送的所述从芯片支持的PHY类型。在本实施例中，系统软件不是直接读取该主芯片和该从芯片支持的PHY类型的。其中，该主芯片支持的PHY类型是该主芯片读取并发送给该系统软件的，该从芯片支持的PHY类型是该从芯片读取并发送给该系统软件的。这样，该系统软件只需要获取该主芯片和该从芯片发送的相关信息就好了，因此该系统软件的操作会比较简单。
可选的，所述系统软件直接读取所述主芯片支持的PHY类型以及所述从芯片支持的PHY类型。这种情况下，由于是该系统软件直接读取的，因此该主芯片和该从芯片不需要做任何操作。
结合第六方面、第六方面的第一种可能实现方式或第六方面的第二种可能实现方式，在第三种可能的实现方式下，所述从芯片用于根据所述从芯片的工作PHY类型，配置所述从芯片的均衡电路，并根据所述从芯片的均衡电路确定所述从芯片在所述均衡的第三阶段需要的均衡时间。所述系统软件具体用于根据所述从芯片在所述均衡的第三阶段需要的均衡时间配置所述主芯片在所述均衡的第三阶段的均衡时间。
结合第六方面的第三种可能实现方式，在第四种可能的实现方式下，所述从芯片具体用于根据所述从芯片的工作PHY类型，通过开通或关断的方式配置所述从芯片的均衡电路。
结合第六方面或第六方面的第一种至第四种可能实现方式中任一种实现方式，在第五种可能的实现方式下，所述主芯片用于根据所述主芯片的工作PHY类型，配置所述主芯片的均衡电路，并根据所述主芯片的均衡电路确定所述主芯片在所述均衡的第四阶段需要的均衡时间。所述系统软件具体用于根据所述主芯片在所述均衡的第四阶段需要的均衡时间配置所述从芯片在所述均衡的第四阶段的均衡时间。
结合第六方面的第五种可能实现方式，在第六种可能的实现方式下，所述主芯片具体用于根据所述主芯片的工作PHY类型，通过开通或关断的方式配置所述主芯片的均衡电路。
结合第六方面或第六方面的第一种至第二种可能实现方式中任一种实现方式，在第七种可能的实现方式下，在所述主芯片和所述从芯片的工作PHY类型均为SR时，所述系统软件具体用于将所述主芯片在所述均衡的第三阶段的均衡时间和所述从芯片在所述均衡的第四阶段的均衡时间均配置为缺省值。
在所述主芯片和所述从芯片的工作PHY类型均为LR时，所述系统软件具体用于读取所述从芯片在所述均衡的第三阶段的均衡时间，并将其写入所述主芯片中，以作为所述主芯片在所述均衡的第三阶段的均衡时间，以及，读取所述主芯片在所述均衡的第四阶段的均衡时间，并将其写入所述从芯片中，以作为所述从芯片在所述均衡的第四阶段的均衡时间。
结合第六方面或第六方面的第一种至第二种可能实现方式中任一种实现方式，在第八 种可能的实现方式下，在所述主芯片和所述从芯片的工作PHY类型均为SR时，所述系统软件具体用于读取所述从芯片在所述均衡的第三阶段的均衡时间，并将其写入所述主芯片中，以作为所述主芯片在所述均衡的第三阶段的均衡时间，以及，读取所述主芯片在所述均衡的第四阶段的均衡时间，并将其写入所述从芯片中，以作为所述从芯片在所述均衡的第四阶段的均衡时间。
在所述主芯片和所述从芯片的工作PHY类型均为LR时，所述系统软件具体用于将所述主芯片在所述均衡的第三阶段的均衡时间和所述从芯片在所述均衡的第四阶段的均衡时间均配置为缺省值。
需要说明的是，第六方面或其各个可能实现方式的有益效果可以参见前述各个关联实施例的有益效果，由于高度类似，因此不再赘述。
附图说明
图1为本申请提供的一种应用PCIe总线的处理器系统的结构示意图。
图2为本申请提供的位于RC和显卡之间的信号通道的示意图。
图3为PCIe标准规定的建链流程图。
图4为均衡的四个阶段的流程图。
图5为本申请提供的通道类型表。
图6为本申请提供的一种配置均衡时间的方法的流程图。
图7为本申请提供的一种用于表达芯片支持的PHY类型的方式。
图8为本申请提供的芯片支持的PHY类型和比特位的值之间的对应关系表。
图9A为本申请提供的芯片的标识与该芯片所支持的PHY类型的对应关系表。
图9B为本申请提供的一种用于指示芯片的工作PHY类型的方式。
图10为本申请提供的一种配置均衡时间的装置的示意图。
图11为本申请提供的另一种配置均衡时间的装置的示意图。
图12为本申请提供的再一种配置均衡时间的装置的示意图。
图13为本申请提供的一种芯片的结构示意图。
图14为本申请提供的一种通信系统的结构示意图。
图15为本申请提供的一种包含主芯片、从芯片以及它们之间的PCIe总线的链路结构图。
具体实施方式
PCIe是一种高速串行计算机扩展总线标准，是电脑总线标准PCI的一种，它沿用现有PCI总线的编程概念和通信标准。PCIe总线采用的是高速串行点对点双通道高带宽的传输方式，因此相对于PCI总线来说具有更快的传输速率。CCIX总线基于与PCIe总线相同的物理架构，该物理架构包括电气子层(Electrical Sub-block)和逻辑子层(Logical Sub-block)，且CCIX总线支持PCIe1.0、PCIe2.0、PCIe3.0和PCIe4.0的传输速率。.
需要说明的是，PCIe/CCIX总线不仅可以应用于内部互连，也可以应用于外部互连。值得注意的是，在本申请中，PCIe/CCIX总线是指PCIe总线或者CCIX总线。
下面仅以应用PCIe总线的处理器系统(也可以简称为“PCIe系统”)为例以说明本申请涉及的方案。应当知道的是，应用CCIX总线的处理器系统也具有相同或相似的特征， 具体参见下文关于应用PCIe总线的处理器系统的描述就能够理解应用CCIX总线的处理器系统了，因此不再重复赘述。
参见附图1，它示出了一个应用PCIe总线的处理器系统。该系统包括根组件(RC，Root Complex)、交换芯片(Switch)和PCIe-to-PCI桥等。
具体的，RC也被称为该系统的根控制器，通常被集成在中央处理器(CPU，Central Processor Unit)上。RC通常具有多个端口。通过该多个端口中的每一个端口，该RC可以和一个部件连通。该多个端口可以包括多个用于连接PCIe总线的端口(简称PCIe端口)。通过一个PCIe端口，该RC可以连接一个端点(Endpoint)，自然，该RC和该Endpoint之间是通过PCIe总线实现连接的。需要说明的是，如图1所示，该Endpoint可以为显卡、网卡、光通道卡、Switch或准用集成电路(ASIC，Application Specific Integrated Circuit)等。在图1所示的处理器系统中，RC和DDR之间通过DDR总线连通，所以RC上与DDR连接的端口不是PCIe端口。因此，该RC的多个端口可以全是PCIe端口，也可以部分是PCIe端口。
Switch用于对该RC进行链路扩展。具体的，一方面，该Switch和RC之间通过PCIe总线实现连通；另一方面，该Switch具有多个端口，通过一个端口，该Switch可以和一个EP通过PCIe总线连通。因此，基于该Switch，该RC可以通过一个端口和多个Endpoint实现连通。如图1所示，该Switch具有3个端口，该Switch通过该3个端口中的任意一个端口可以和一个ASIC，通过PCIe总线连通。
PCIe-to-PCI桥的作用是桥接，用于实现PCIe总线和PCI总线的转换，从而能够兼容原来的支持PCI总线的Endpoint。如图1所示，PCIe-to-PCI桥的一端通过PCIe总线连接到Switch，另一端连接到PCI总线上。进一步地，图1中还示出了多个支持PCI总线标准的PCI插槽，插在该PCI插槽内的芯片或卡能够通过PCI总线连接到该PCIe-to-PCI桥，进而通过Switch连接到CPU。
需要说明的是，RC和Endpoint之间可以通过PCIe总线直接连通，也可以通过PCIe总线和连接器后实现连通。如图2所示，RC和显卡之间依次通过PCIe总线、连接器、PCIe总线、连接器和PCIe总线后实现连通。应当知道的是，位于RC和Endpoint之间的多条PCIe总线的长度可以是相同，也可以是不同。
为了便于理解，此处对本申请中多次提及的“系统”进行说明。本申请所述的系统是指应用PCIe/CCIX总线的系统(简称为“PCIe/CCIX系统”)。该PCIe/CCIX系统可以包括一个中央处理器CPU和其外围设备，其中，该CPU和其外围设备之间的通道中至少有一个通道使用的是PCIe/CCIX总线。该PCIe/CCIX系统还可以包括多个CPU和其外围设备，其中，该多个CPU之间的通道中至少有一个通道使用的是PCIe/CCIX总线，或其中一个CPU和外围设备之间的通道中至少有一个通道使用的是PCIe/CCIX总线。
参见附图3，它示出了PCIe系统从上电到建立通信连接的流程图。根据PCIe标准的规定，当开机或复位后，主芯片中的链路状态机将控制链路依次进入：检测——轮询(Polling)——配置(Configuration)——连接(Linkup)——恢复。具体的，在检测阶段，主芯片检测从芯片是否在位。当检测到从芯片在位后，进入到Polling阶段，进行比特和符号锁定以及通道极性确定。然后进入到配置阶段，进行链路带宽和链路号的确定，执行通道到通道的相位补偿等。完成配置后，进入Linkup阶段，链路以低速运行到Linkup， 也即主芯片和从芯片建立连接。然后，系统进入到恢复阶段，进行均衡时间以及变速，完成变速且速率提升到高速后，返回到连接状态，以实现业务数据传输。
需要说明的是，本申请中所述的主芯片是指包含下行口(DSP，Downstream Port)的芯片。有时，该主芯片也被简称为下行口。本申请中所述的从芯片是指包含上行口(USP，Upstream Port)的芯片。有时，该从芯片也被简称为上行口。
进一步地，结合图1可知，在本申请中，所述主芯片可以为RC，也可以为交换芯片(Switch)。在该主芯片为RC时，该从芯片可以为端点设备(Endpoint)，也可以为交换芯片(Switch)。在该主芯片为交换芯片时，该从芯片可以为端点设备。其中，该端点设备可以为显卡、网卡、光通道卡、存储卡或交换芯片等。
值得注意的是，前述恢复阶段实施的均衡的目的是实现链路速率稳定提升，进而实现变速。为了容易理解，此处对均衡进行说明。在通信系统中，由于各种噪声和干扰的存在，使得通信系统中的传输信号发生失真的变化，也就是信道是非理想信道，对信道中这些特性进行补偿和校正的技术就称之为均衡。该均衡过程所需要的时间就是均衡时间。通常，均衡包括四个阶段。参见图4，这四个阶段可以为第一阶段(Phase 0)，第二阶段(Phase1)，第三阶段(Phase 2)和第四阶段(Phase 3)。
值得注意的是，关于均衡时间的操作发生在主芯片和从芯片之间。在本申请中，该主芯片和从芯片可以位于同一处理器系统中，也可以位于不同的处理器系统中，其中，该主芯片和从芯片之间通过PCIe/CCIX总线连通。下面将结合图1中的RC和Endpoint对该方法进行说明。其中，图1中的RC对应于主芯片，Endpoint对应于从芯片。
在Phase 0，RC将Endpoint需要用的初始参数发送给Endpoint。作为本申请的一个实施例，Endpoint在该阶段的最大停留时间为12ms。
需要说明的是，在均衡的四个阶段，RC(或Endpoint)在该四个阶段中的任意一个阶段的最大停留时间为RC(或Endpoint)在该阶段的均衡时间。比如，RC在均衡的Phase3的最大停留时间为RC在该Phase 3的均衡时间。Endpoint在均衡的Phase 2的最大停留时间为Endpoint在该Phase 2的均衡时间。在Phase 1，RC和Endpoint之间以变速之后的较高速率进行数据收发，且该收发操作使用的是设定的初始参数。具体的，在该阶段，RC先向Endpoint发送数据，Endpoint接收到该数据后停留一会，在确定该数据的误码率小于10E-4后，该Endpoint进入下一阶段——Phase 2。在该Endpoint进入下一阶段之前，该Endpoint向RC反馈一个信息用于说明自己将进入下一阶段，RC收到该信息后也将进入下一阶段。可选的，Endpoint在Phase 1的最大停留时间为12ms，RC在Phase 1的最大停留时间为24ms。
在Phase 2，Endpoint调整RC的发送(Tx)参数，并对应的调整自己的接收(Rx)参数，以期望Endpoint和RC之间的链路的误码率小于10E-12。应当知道的是，如果该两者之间的误码率没有达到上述要求，则Endpoint会重复进行上述调整操作，并在链路误码率小于10E-12后，Endpoint和RC均进入下一阶段——Phase 3。可选的，在该阶段，RC停留的最大时间为32ms，Endpoint停留的最大时间为24ms。
在Phase 3，RC调整Endpoint的发送(Tx)参数，并对应的调整自己的接收(Rx)参数，以期望Endpoint和RC之间的链路的误码率小于10E-12。应当知道的是，如果该两者之间的误码率没有小于10E-12，则RC会重复进行上述调整操作，直到该链路误码率 小于10E-12后，Phase 3结束后。至此，均衡时间协商也结束了，正常情况下，链路速率会提升到高一级的速率，也即链路达到高速连接状态。
需要说明的是，前述关于均衡时间的操作不仅可以发生在恢复阶段，也可以发生在芯片上电之后以及PCIe/CCIX状态机启动之前。
本申请提供的协商均衡时间的方法中协商的是Phase 2和Phase 3两个阶段所需要的时间。
在执行本申请所述的方法之前，还需要对该PCIe系统做如下的配置。
首先，需要在该PCIe系统内建立并存储一张如图5所示的通道类型表，该通道类型表至少包括主芯片的端口号、从芯片的标识和通道类型。值得注意的是，该主芯片的端口号能够唯一标注一个特定主芯片的一个特定的端口，该从芯片的标识能够唯一标注一个特定的从芯片。根据该主芯片的端口号和该从芯片的标识，能够唯一地确定出位于该主芯片的端口和该从芯片之间的通道的类型。
需要说明的是，该通道类型表被存储在该PCIe系统中之后，该系统上电、下电以及复位，均不会造成该通道类型表丢失。具体的，该通道类型表被存储在该PCIe系统内的存储器中。
在本申请中，通道类型包括长距(LR，Long Reach)和短距(SR，Short Reach)。该区分是根据通道损耗的大小确定的。需要明确的是，LR对应的通道损耗大于SR对应的通道损耗。可选的，LR对应的通道损耗大于或等于22dB且小于32dB，SR对应的通道损耗小于22dB。
在本申请中，通道类型与通道损耗的大小有关。应当知道的是，通道类型还可以与其他维度的参数相关，比如通道的带宽大小、通道工作的时间段是闲时还是忙时等。进一步地，在本申请中，根据通道损耗的大小，通道类型被分为LR和SR。应当知道的是，该通道类型还可以被划分成更细的粒度，比如通该道类型可以被划分为LR、中距(MR，Middle Reach)以及SR，还可以被划分为超长距(XLR，Extra Long Reach)、LR、MR、SR以及超短距(XSR，Extra Short Reach)。
其次，还需要预先配置主芯片支持的物理层(PHY)类型和从芯片支持的PHY类型。具体的，芯片支持的PHY类型与根据该芯片能够驱动的通道损耗的大小有关。在本申请中，该主芯片支持的PHY类型可以仅支持LR，或者仅支持SR，或者同时支持LR和SR。类似地，该从芯片支持的PHY类型也可以仅支持LR，或者仅支持SR，或者同时支持LR和SR。需要说明的是，支持的PHY类型为LR的芯片能够驱动的通道损耗大于支持的PHY类型为SR的芯片能够驱动的通道损耗。
值得注意的是，在本申请中，芯片支持的PHY类型被存储在该芯片的寄存器内。具体的，该主芯片支持的PHY类型被存储在该主芯片的寄存器内，该从芯片支持的PHY类型被存储在该从芯片的寄存器内。
可选的，芯片支持的PHY类型还可以与该芯片的功耗、成本以及应用场景等有关。
结合前述描述可以得知，假设位于该主芯片的端口和从芯片之间的通道的类型位于集合Q中，则主芯片或从芯片各自支持的PHY类型为集合Q的子集或全集。比如，在本申请中，该集合Q包括LR和SR，则主芯片支持的PHY类型可以仅为LR，或仅为SR，或同时为LR和SR，从芯片支持的PHY类型也可以仅为LR，或仅为SR，或同时为LR和SR。
一
在完成上述配置且该系统被上电之后，本申请提供的一种配置均衡时间的方法将会被执行。该方法的执行主体可以为系统软件或系统的管理芯片。该系统软件可以为基本输入输出系统(BIOS，Basic Input Output System)。应当知道的是，BIOS是设备上电后加载的第一个软件，BIOS加载完成后会引导启动上层操作系统(OS,Operating System)。在BIOS运行阶段，BIOS可以执行本申请提供的配置均衡时间的方法。
如图6所示，本申请提供的方法包括下述步骤。
S101、获取主芯片的端口号和从芯片的标识，通过查找通道类型表，确定位于该主芯片的端口和该从芯片之间的通道的类型.
其中，所述确定的通道类型为长距LR或短距SR。
其中，该通道类型表被预先存储在PCIe/CCIX系统的存储器内。具体的，该存储器可以为闪存或电子可擦可编程序只读存储器EEPROM等。正如前文所述，该通道类型表至少包括该主芯片的端口号、该从芯片的标识以及通道类型三列。其中，根据主芯片的端口号和从芯片的标识，能够唯一确定出位于该主芯片和该从芯片之间的通道的类型。
在本申请中，通道类型可以为LR或SR，该分类是从通道损耗的维度进行的，类型为LR的通道的损耗大于类型为SR的通道的损耗。
S103、获取该主芯片支持的PHY类型和该从芯片支持的PHY类型，判断该主芯片支持的PHY类型和该从芯片支持的PHY类型是否均包括步骤S1确定的通道类型。
其中，主芯片支持的PHY类型可以仅为LR，或仅为SR，或为LR和SR。从芯片支持的PHY类型也可以仅为LR，或仅为SR，或为LR和SR。
正如前述所述，在本申请中，芯片支持的PHY类型与该芯片能够驱动的通道损耗的大小相关。需要说明的是，支持的PHY类型为LR的芯片能够驱动的通道损耗大于支持的PHY类型为SR的芯片能够驱动的通道损耗。
可选的，系统软件可以直接获取该主芯片支持的PHY类型和该从芯片支持的PHY类型。也可以是该主芯片先获取该主芯片支持的PHY类型，然后将该主芯片支持的PHY类型发送给系统软件，以及该从芯片先获取该从芯片支持的PHY类型，然后将该从芯片支持的PHY类型发送给系统软件。
需要说明的是，该主芯片支持的PHY类型被预先存储在该主芯片的寄存器内。该寄存器可以均为状态寄存器。作为本申请的一个实施例，该主芯片支持的PHY类型可以用至少一个比特表示。请参阅附图7，芯片支持的PHY类型用两个比特表示，该两个比特位为1和2，且该两个比特的值可以为00，01或10。进一步参阅附图8，在图,8中的芯片为本申请所述的主芯片的情况下，容易知道，00代表该主芯片支持的PHY类型为SR，01代表该主芯片支持的PHY类型为LR，10代表该主芯片支持的PHY类型为SR和LR。
类似地，该从芯片支持的PHY类型被预先存储在该从芯片的寄存器内。其中，该从芯片支持的PHY类型也被预先存储在该从芯片的寄存器内。该寄存器可以为状态寄存器。其中，在该寄存器内，该从芯片支持的PHY类型也可以用至少一个比特表示。作为本申请的一个实施例，该从芯片支持的PHY类型用两个比特表示。类似的，请参考附图8，在图8中的芯片为该从芯片的情况下，则容易知道，00代表该从芯片支持的PHY类型为SR，01代表该从芯片支持的PHY类型为LR，10代表该从芯片支持的PHY类型为SR和LR。
下面对“主芯片支持的PHY类型和从芯片支持的PHY类型均包括所述确定的通道类型”在本申请中的含义进行详细说明。在所述确定的通道类型为SR的情况下，如果主芯片支持的PHY类型为SR，或为SR和LR，且从芯片支持的PHY类型为SR，或为SR和LR，则说明主芯片和从芯片支持的PHY类型均包括所述确定的通道类型。在所述确定的通道类型为LR的情况下，如果主芯片支持的PHY类型为LR，或为SR和LR，且从芯片支持的PHY类型为LR，或为SR和LR，则说明主芯片和从芯片支持的PHY类型均包括所述确定的通道类型。
需要说明的是，在执行本申请所述的配置方法之前，可以存储芯片的标识和该芯片支持的PHY类型。其中，该芯片对应于本申请中的主芯片和从芯片。
具体的，可以将上述内容存储在对应芯片的寄存器内。进一步地，可以以表格的形式存储上述内容(如图9A所示)。则该表格至少包括两列，其中一列是芯片的标识，另一列是对应芯片支持的PHY类型。其中，芯片的标识可以用至少一个比特位表示。
S105、在所述主芯片和所述从芯片支持的PHY类型中均包括所述确定的通道类型时，确定所述主芯片以及所述从芯片的工作PHY类型。
值得注意的是，所述主芯片以及所述从芯片的工作PHY类型均与所述确定的通道类型相同。
例如，在步骤S1中确定位于该主芯片和该从芯片之间的通道的类型为SR，在步骤S2中确定该主芯片支持的PHY类型为LR和SR，该从芯片支持的PHY类型为SR，则能够知道该主芯片支持的PHY类型和该从芯片支持的PHY类型均包括所述确定的通道类型，这种情况下，就能够确定该主芯片的工作PHY类型和该从芯片的工作PHY类型了。其中，该主芯片的工作PHY类型和该从芯片的工作PHY类型均为SR，也即与步骤S1中确定的通道类型相同。
需要说明的是，在本申请中，所谓的“主芯片的工作PHY类型”是指位于该主芯片的端口和该从芯片之间的通道被建立后，在该主芯片和该从芯片之间传递业务数据时，该主芯片实际工作的PHY类型。应当知道的是，虽然该主芯片支持的PHY类型可以为一个，也可以为多个。但是该主芯片的工作PHY类型只有一个。常规的，多个是指两个以上。可选的，该多个为两个。
类似的，在本申请中，所谓的“从芯片的工作PHY类型”是指位于该主芯片的端口和该从芯片之间的通道被建立后，在该主芯片和该从芯片之间传递业务数据时，该从芯片实际工作的PHY类型。虽然在本申请中，该从芯片支持的PHY类型可以为一个，也可以为多个。但是该从芯片的工作PHY类型只有一个。
在确定该主芯片的工作PHY类型和该从芯片的工作PHY类型之后，本申请提供的方法还可以包括下述步骤：
S106、将该主芯片的工作PHY类型写入该主芯片的寄存器内，以及将该从芯片的工作PHY类型写入该从芯片的寄存器内。
需要说明的是，该主芯片和该从芯片实际的工作PHY类型均与S1确定的通道类型相同。该主芯片和该从芯片实际的工作PHY类型是指在传输业务数据时，该主芯片和该从芯片的PHY类型。
请参见附图9B，它用于表示该主芯片的寄存器或该从芯片的寄存器中存储的内容。 在图9B中，比特位24的值可以为0或1，该值用于表示该主芯片和该从芯片之间传输业务数据时，该主芯片或该从芯片实际的工作PHY类型。具体的，如果比特位24的值为0，则表示该主芯片或该从芯片的工作PHY类型为SR；如果比特位24的值为1，则表示该主芯片或该从芯片的工作PHY类型为LR。
在主芯片和从芯片实际的工作PHY类型分别被写入对应芯片的寄存器之后，本申请提供方法还包括：
S107、根据所述从芯片的工作PHY类型，配置所述主芯片在均衡的第三阶段的均衡时间；以及，根据所述主芯片的工作PHY类型，配置所述从芯片在均衡的第四阶段的均衡时间。
需要说明的是，在S107之后，本申请提供的配置方法还可以包括:将所述主芯片在均衡的第三阶段的均衡时间写入该主芯片的寄存器内；以及，将该从芯片在均横的第四阶段的均衡时间写入该从芯片的寄存器内。可选的，如图9B所示，比特位22至20的值用于表示该芯片在均衡的第四阶段的均衡时间。进一步可选的，如图9B所示，比特位18至16的值用于表示该芯片在均衡的第三阶段的均衡时间。
值得注意的是，在该从芯片的工作PHY类型确定的情况下，该从芯片会据此配置该从芯片的均衡电路，并根据该从芯片的均衡电路确定该从芯片在均衡的第三阶段(Phase 2)的均衡时间。然后，系统软件会根据该从芯片在均衡的第三阶段需要的均衡时间配置该主芯片在第三阶段的均衡时间。
根据前文已经知道的是，该从芯片在Phase 2的均衡时间和该主芯片在Phase 2的均衡时间是相关的，因此，系统软件还进一步能够该从芯片在Phase 2的均衡时间配置该主芯片在Phase 2的均衡时间。应当知道的是，系统软件确定出的该主芯片在Phase 2的均衡时间是大于或等于该主芯片在Phase 2的实际均衡时间的，因此该主芯片在Phase 2的均衡操作不会因为均衡时间太短而退出，从而导致该主芯片和该从芯片之间的链路协商失败。也即该主芯片在Phase 2的均衡操作能够顺利完成。
需要说明的是，该从芯片的总的均衡电路是预先设置好的。如图15所示，为本申请提供的一种包含主芯片、从芯片以及它们之间的PCIe总线的逻辑图。参阅附图15，它示出了从芯片的总的均衡电路包括连续时间线性均衡器(CTLE，Continuous Time Linear Equalizer)和三阶判决反馈均衡器(DFE，Decision Feedback Equalizer)，则该从芯片可以通过开通或关断的方式选择实际工作的均衡电路。例如，在该从芯片的工作PHY类型为LR时，实际工作的均衡电路为CTLE和三阶DFE串联，而在该从芯片的工作PHY类型为SR时，该实际工作的均衡电路仅为CTLE，或为CTLE和一阶DFE串联。因此前文所述的“该从芯片会据此配置该从芯片的均衡电路”，实际上是该从芯片据此通过开通或关断的方式从该从芯片总的均衡电路中选择出实际工作的均衡电路。
需要说明的是，若在该从芯片的工作PHY类型为SR时，所述主芯片在第三阶段的均衡时间被配置为T1，在该从芯片的工作PHY类型为LR时，所述主芯片在第三阶段的均衡时间被配置为T2，则T2的值大于T1的值。
类似的，在该主芯片的工作PHY类型确定的情况下，该主芯片会据此配置该主芯片的均衡电路，并根据该主芯片的均衡电路确定该主芯片在均衡的第四阶段(Phase 3)所需要的均衡时间。然后，系统软件会根据该主芯片在均衡的第四阶段需要的均衡时间配置该 从芯片在该均衡的第四阶段的均衡时间。
该主芯片在Phase 3的均衡时间和该从芯片在Phase 3的均衡时间是相关的，因此，系统软件还进一步能够该主芯片在Phase 3的均衡时间配置该从芯片在Phase 3的均衡时间。应当知道的是，系统软件配置的该从芯片在Phase 3的均衡时间是大于或等于该从芯片在Phase 3的实际停留时间的，因此该从芯片在Phase 3的均衡操作不会因为均衡时间太短而退出，从而导致系统的链路协商失败。也即该从芯片在Phase 3的均衡操作能够顺利完成。
需要说明的是，该主芯片的总的均衡电路也是预先设置好的。如图15所示，主芯片的总的均衡电路包括三阶前反馈均衡器(FFE,Feed Forward Equalizer)，则该主芯片可以通过开通或关断的方式选择实际工作的均衡电路。例如，在该主芯片的工作PHY类型为LR时，实际工作的均衡电路为三阶FFE，而在该主芯片的工作PHY类型为SR时，该实际工作的均衡电路为两阶FFE或一阶FFE。因此前文所述的“该主芯片可以通过开通或关断的方式选择实际工作的均衡电路”，是指该主芯片可以通过开通或关断的方式从该主芯片的总的均衡电路中选择实际工作的均衡电路。
需要说明的是，若在该主芯片的工作PHY类型为SR时，所述从芯片在第四阶段的均衡时间被配置为T3，在该主芯片的工作PHY类型为LR时，所述从芯片在第四阶段的均衡时间被配置为T4，则T4的值大于T3的值。
作为本申请的一个实施例，在该主芯片和该从芯片的工作PHY类型均为SR时，系统软件会将所述主芯片在所述第三阶段的均衡时间和所述从芯片在所述第四阶段的均衡时间均配置为缺省值。其中，所述缺省值可以是根据芯片厂家的设计文档或芯片厂家对芯片的测试预先设置的，也可以是业界的通用标准值等。
在所述主芯片和所述从芯片的工作PHY类型均为LR时，系统软件会读取所述从芯片在所述第三阶段的均衡时间，并将其写入所述主芯片中，以作为所述主芯片在所述第三阶段的均衡时间，以及，读取所述主芯片在所述第四阶段的均衡时间，并将其写入所述从芯片中，以作为所述从芯片在所述第四阶段的均衡时间。
作为本申请的另一个实施例，在所述主芯片和所述从芯片的工作PHY类型均为SR时，系统软件会读取所述从芯片在所述第三阶段的均衡时间，并将其写入所述主芯片中，以作为所述主芯片在所述第三阶段的均衡时间，以及，读取所述主芯片在所述第四阶段的均衡时间，并将其写入所述从芯片中，以作为所述从芯片在所述第四阶段的均衡时间。
在所述主芯片和所述从芯片的工作PHY类型均为LR时，系统软件会将所述主芯片在所述第三阶段的均衡时间和所述从芯片在所述第四阶段的均衡时间均配置为缺省值。类似的，该缺省值可以是根据芯片厂家的设计文档或芯片厂家对芯片的测试预先设置的，也可以是业界的通用标准值等。
作为本申请的再一个实施例，对应于该从芯片的工作PHY类型，该主芯片在第三阶段的均衡时间有参考值；对应于该主芯片的工作PHY类型，该从芯片在第四阶段的均衡时间也有参考值。这些参考值可以来自于芯片厂家的设计文档、芯片厂家对芯片的测试或业界的通用标准值等。
应当知道的是，在完成前述均衡时间的配置之后，按照PCIe总线标准规定的协商流程，链路状态机会按照图3所示的过程完成建链。
二
本申请还提供了一种配置均衡时间的装置，该装置可以用来执行前述的配置均衡时间的方法，因此本实施例所述的装置可以参见前述方法实施例的相关限定和描述，为了节约篇幅，相同或者相似部分，本实施例不再赘述。需要说明的是，本实施例所述的装置可以为系统的管理芯片。
如图10所示，为本实施例提供的一种配置均衡时间的装置300。该装置300包括收发器301和管理器303.
具体的，该收发器301用于接收主芯片的端口号和从芯片的标识。对应的，该管理器用于根据该主芯片的端口号和该从芯片的标识，通过查找通道类型表，确定位于该主芯片的端口和该从芯片之间的通道的类型。在本实施例中，所述确定的通道的类型(或“所述确定的通道类型”)为LR或SR.
值得注意的是，收发器301接收的主芯片的端口号可以是该主芯片发送的。收发器301接收的从芯片的标识可以是该从芯片发送的。
收发器301还用于接收该主芯片支持的PHY类型以及该从芯片支持的PHY类型。其中，该主芯片支持的PHY类型可以为LR，或为SR，或为LR和SR；该从芯片支持的PHY类型可以为LR，或为SR，或为LR和SR。对应的，该管理器302还用于判断该主芯片支持的PHY类型和该从芯片支持的PHY类型中是否均包括所述确定的通道类型，并在均包括的情况下，确定该主芯片的工作PHY类型以及该从芯片的PHY工作类型。需要说明的是，该主芯片的工作PHY类型和该从芯片的工作PHY类型均与所述确定的通道类型相同。
需要说明的是，收发器301接收的该主芯片支持的PHY类型可以是由该主芯片发送的。收发器301接收的该从芯片支持的PHY类型可以是由该从芯片发送的。
进一步地，该管理器302还用于根据该主芯片的工作PHY类型和该从芯片的工作PHY类型，配置该主芯片在均衡的第三阶段的均衡时间和该从芯片在均衡的第四阶段的均衡时间。
作为本申请的一个实施例，该从芯片根据该从芯片的工作PHY类型，配置该从芯片的均衡电路，并根据该从芯片的均衡电路确定该从芯片在均衡的第三阶段需要的均衡时间。然后，管理器302根据该从芯片在均衡的第三阶段需要的均衡时间配置该主芯片在均衡的第三阶段的均衡时间。
作为本申请的另一个实施例，该主芯片根据该主芯片的工作PHY类型配置该主芯片的均衡电路，并根据该主芯片的均衡电路确定该主芯片在均衡的第四阶段需要的均衡时间。然后，管理器302根据该主芯片在均衡的第四阶段需要的均衡时间，配置该从芯片在均衡的第四阶段的均衡时间。
作为本申请的再一种实施例，在该主芯片的工作PHY类型和该从芯片的工作PHY类型均为SR时，管理器302具体用于将该主芯片在所述第三阶段的均衡时间和该从芯片在所述第四阶段的均衡时间均配置为缺省值。在该主芯片的工作PHY类型和该从芯片的工作PHY类型均为LR时，管理器302具体用于读取该从芯片在所述第三阶段的均衡时间，并将其写入该主芯片中，以作为该主芯片在所述第三阶段的均衡时间，以及，读取该主芯片在所述第四阶段的均衡时间，并将其写入该从芯片中，以作为该从芯片在所述第四阶段的均衡时间。
作为本申请的再一种实施例，在该主芯片的工作PHY类型和该从芯片的工作PHY类型均为SR时，管理器302具体用于读取该从芯片在所述第三阶段的均衡时间，并将其写入该主芯片中，以作为该主芯片在所述第三阶段的均衡时间，以及，读取该主芯片在所述第四阶段的均衡时间，并将其写入该从芯片中，以作为该从芯片在所述第四阶段的均衡时间。在该主芯片的工作PHY类型和该从芯片的工作PHY类型均为LR时，管理器302具体用于将该主芯片在所述第三阶段的均衡时间和该从芯片在所述第四阶段的均衡时间均配置为缺省值。
三
本申请还提供了第二种配置均衡时间的装置，该装置也可以用来执行前述的配置均衡时间的方法，因此本实施例所述的装置也可以参见前述方法实施例的相关限定和描述。需要说明的是，本实施例所述的装置可以为BIOS。
如图11所示，为本实施例提供的一种配置均衡时间的装置400.该装置包括获取单元401，确定单元403和配置单元405。
其中，获取单元401用于获取主芯片的端口号和从芯片的标识。对应的，确定单元403用于通过查找通道类型表，确定位于该主芯片的端口和该从芯片之间的通道的类型。在本实施例中，所述确定的通道的类型(或“所述确定的通道类型”)为LR或SR。
获取单元401还用于获取该主芯片支持的PHY类型和该从芯片支持的PHY类型。其中，该主芯片支持的PHY类型可以为LR，或为SR，或为LR和SR；该从芯片支持的PHY类型也可以为LR，或为SR，或为LR和SR。相应的，确定单元403还用于判断主芯片支持的PHY类型和从芯片支持的PHY类型是否均包括前述确定的通道类型，在该主芯片支持的PHY类型和该从芯片支持的PHY类型均包括前述确定的通道类型时，确定该主芯片的工作PHY类型以及该从芯片的工作PHY类型。其中，该主芯片的工作PHY类型和该从芯片的工作PHY类型均与前述确定的通道类型相同。
进一步地，配置单元405用于根据该主芯片的工作PHY类型，配置该从芯片在均衡的第四阶段(或Phase 3)的均衡时间，以及根据该从芯片的工作PHY类型，配置该主芯片在均衡的第三阶段(或Phase 2)的均衡时间。
所谓“配置单元405根据该主芯片的工作PHY类型，配置该从芯片在均衡的第四阶段(或Phase 3)的均衡时间”，具体是指：该主芯片根据该主芯片的工作PHY类型，配置该主芯片的均衡电路，并根据该主芯片的均衡电路确定该主芯片在均衡的第四阶段需要的均衡时间；然后配置单元405根据该主芯片在均衡的第四阶段需要的均衡时间，配置出该从芯片在均衡的第四阶段的均衡时间。
所谓“配置单元405根据该从芯片的工作PHY类型，配置该主芯片在均衡的第三阶段(或Phase 2)的均衡时间”，具体是指：该从芯片根据该从芯片的工作PHY类型，配置该从芯片的均衡电路，并根据该从芯片的均衡电路确定该从芯片在均衡的第三阶段需要的均衡时间；然后配置单元405根据该从芯片在均衡的第三阶段需要的均衡时间，配置出该主芯片在均衡的第三阶段的均衡时间。
作为本申请的再一种实施例，在该主芯片的工作PHY类型和该从芯片的工作PHY类型均为SR时，配置单元405具体用于将该主芯片在所述第三阶段的均衡时间和该从芯片在所述第四阶段的均衡时间均配置为缺省值。在该主芯片的工作PHY类型和该从芯片的工 作PHY类型均为LR时，配置单元405具体用于读取该从芯片在所述第三阶段的均衡时间，并将其写入该主芯片中，以作为该主芯片在所述第三阶段的均衡时间，以及，读取该主芯片在所述第四阶段的均衡时间，并将其写入该从芯片中，以作为该从芯片在所述第四阶段的均衡时间。
作为本申请的再一种实施例，在该主芯片的工作PHY类型和该从芯片的工作PHY类型均为SR时，配置单元405具体用于读取该从芯片在所述第三阶段的均衡时间，并将其写入该主芯片中，以作为该主芯片在所述第三阶段的均衡时间，以及，读取该主芯片在所述第四阶段的均衡时间，并将其写入该从芯片中，以作为该从芯片在所述第四阶段的均衡时间。在该主芯片的工作PHY类型和该从芯片的工作PHY类型均为LR时，配置单元405具体用于将该主芯片在所述第三阶段的均衡时间和该从芯片在所述第四阶段的均衡时间均配置为缺省值。
四
本申请还提供了第三种配置均衡时间的装置，该装置也可以用于执行前述配置均衡时间的方法，相应的，该装置也可以参见前述方法实施例的相关限定，相同或相似部分，本实施例不再赘述。请参见附图12，为本实施例提供的配置均衡时间的装置500，该装置500包括中央处理器(CPU，Central Processor Unit)501和存储器502.其中，存储器502用于存储代码，CPU501用于执行存储器502存储的代码以实现本实施例所述的装置的功能。应当知道的是，该CPU为应用该PCIe总线的处理器系统的CPU。
具体的，存储器502还用于存储通道类型表。CPU501用于获取主芯片的端口号和从芯片的标识，然后根据该主芯片的端口号和该从芯片的标识，通过查找该通道类型表，确定位于该主芯片的端口和该从芯片之间的通道的类型。需要说明的是，所述确定的通道的类型(或“所述确定的通道类型”)可以为LR或SR。
CPU501还用于获取该主芯片支持的PHY类型和该从芯片支持的PHY类型，并在该主芯片支持的PHY类型和该从芯片支持的PHY类型中均包括该确定的通道类型时，确定该主芯片的工作PHY类型和该从芯片的工作PHY类型。其中，该主芯片的工作PHY类型和该从芯片的工作PHY类型均和所述确定的通道类型相同。需要说明的是，该主芯片支持的PHY类型可以仅仅为LR，或仅仅为SR，或为LR和SR，类似的，该从芯片支持的PHY类型也可以仅仅为LR，或仅仅为SR，或为LR和SR。
在确定了该主芯片的工作PHY类型和该从芯片的工作PHY类型之后，CPU501还用于根据该主芯片的工作PHY类型，配置该从芯片在均衡的第四阶段的均衡时间，以及根据该从芯片的工作PHY类型，配置该主芯片在均衡的第三阶段的均衡时间。
所谓“CPU501根据该主芯片的工作PHY类型，配置该从芯片在均衡的第四阶段(或Phase 3)的均衡时间”，具体是指：该主芯片根据该主芯片的工作PHY类型，配置该主芯片的均衡电路，并根据该主芯片的均衡电路确定该主芯片在均衡的第四阶段需要的均衡时间；然后CPU501根据该主芯片在均衡的第四阶段需要的均衡时间，配置出该从芯片在均衡的第四阶段的均衡时间。
所谓“CPU501根据该从芯片的工作PHY类型，配置该主芯片在均衡的第三阶段(或Phase 2)的均衡时间”，具体是指：该从芯片根据该从芯片的工作PHY类型，配置该从芯片的均衡电路，并根据该从芯片的均衡电路确定该从芯片在均衡的第三阶段需要的均衡时 间；然后CPU501根据该从芯片在均衡的第三阶段需要的均衡时间，配置出该主芯片在均衡的第三阶段的均衡时间。
作为本实施例的一种实现方式，在该主芯片的工作PHY类型和该从芯片的工作PHY类型均为SR时，CPU501具体用于将该主芯片在所述第三阶段的均衡时间和该从芯片在所述第四阶段的均衡时间均配置为缺省值。在该主芯片的工作PHY类型和该从芯片的工作PHY类型均为LR时，CPU501具体用于读取该从芯片在所述第三阶段的均衡时间，并将其写入该主芯片中，以作为该主芯片在所述第三阶段的均衡时间，以及，读取该主芯片在所述第四阶段的均衡时间，并将其写入该从芯片中，以作为该从芯片在所述第四阶段的均衡时间。
作为本实施例的另一种实现方式，在该主芯片的工作PHY类型和该从芯片的工作PHY类型均为SR时，CPU501具体用于读取该从芯片在所述第三阶段的均衡时间，并将其写入该主芯片中，以作为该主芯片在所述第三阶段的均衡时间，以及，读取该主芯片在所述第四阶段的均衡时间，并将其写入该从芯片中，以作为该从芯片在所述第四阶段的均衡时间。在该主芯片的工作PHY类型和该从芯片的工作PHY类型均为LR时，CPU501具体用于将该主芯片在所述第三阶段的均衡时间和该从芯片在所述第四阶段的均衡时间均配置为缺省值。
五
本申请还提供了一种芯片，该芯片为前述实施例所述的主芯片或从芯片。请参见附图13，为本申请提供的芯片600，该芯片600包括第一寄存器601，收发器603，第二寄存器605和管理器607.
第一寄存器601用于存储芯片600支持的PHY类型。结合前文容易知道，芯片600支持的PHY类型可以为LR，或为SR，或为LR和SR。收发器603用于向系统软件或系统的管理芯片发送芯片600支持的PHY类型，以及，接收系统软件或系统的管理芯片发送的芯片600的工作PHY类型。需要说明的是，芯片600的工作PHY类型是根据芯片600和另一个其他芯片之间的通道的类型确定的。其中，芯片600支持的PHY类型和另一个其他芯片支持的PHY类型均包括芯片600和另一个其他芯片之间的通道的类型，且芯片600和另一个其他芯片之间的通道的类型可以为LR或SR。值得注意的是，芯片600和另一个其他芯片之间的通道的类型和芯片600的工作PHY类型相同的。
应道知道的是，在芯片600为本申请所述的主芯片的情况下，另一个其他芯片为从芯片。在芯片600为本申请所述的从芯片的情况下，另一个其他芯片为主芯片。
进一步地，第二寄存器605还用于存储芯片600的工作PHY类型。管理器607用于根据芯片600的工作PHY类型配置芯片600的均衡电路，然后根据芯片600的均衡电路确定芯片600的均衡时间。对应的，该第二寄存器605还用于存储芯片600的均衡时间。
需要说明的是，本实施例中所述的第一寄存器601和第二寄存器605可以是同一个寄存器，也可以是不同的寄存器。且在实际的产品形态中，用于实现第一寄存器601或第二寄存器605的功能的可以是一个寄存器，也可以是两个以上的寄存器。因此，本实施例中所述的第一寄存器601和第二寄存器605是从功能上做的区分，它们对应的功能是不同的，而不是从产品的实际形态上做的区分。
六
请参阅附图14，为本申请提供的一种通信系统700.该通信系统700包括系统软件701、 主芯片703和从芯片705.其中，主芯片703和从芯片705之间通过PCIe/CCIX总线连通。需要说明的是，该系统软件701可以为BIOS。
具体的，系统软件701获取主芯片703的端口号和从芯片705的标识，通过查找通道类型表，确定位于主芯片703的端口和从芯片705之间的通道的类型。结合前述实施例，应当知道的是，该确定的通道类型可以为LR或SR。
进一步地，系统软件701获取主芯片703支持的PHY类型和从芯片705支持的PHY类型，并判断主芯片703支持的PHY类型和从芯片705支持的PHY类型是否均包括所述确定的通道类型。
可选的，系统软件701可以直接读取主芯片703支持的PHY类型和从芯片705支持的PHY类型。
作为本实施例的另一种实现，主芯片703读取主芯片703支持的PHY类型，并将主芯片703支持的PHY类型发送给系统软件701，以及，从芯片705读取从芯片705支持的PHY类型，并将从芯片705支持的PHY类型发送给系统软件701。也即，系统软件701获取的主芯片703支持的PHY类型是由主芯片703发送的，获取的从芯片705支持的PHY类型是由从芯片705发送的。
结合前述实施例，应当知道的是，主芯片703支持的PHY类型可以为LR，或为SR，或为LR和SR，且从芯片705支持的PHY类型也可以为LR，或为SR，或为LR和SR。
在主芯片703支持的PHY类型和从芯片705支持的PHY类型均包括所述确定的通道类型时，系统软件701根据所述确定的通道类型，确定主芯片703的工作PHY类型和从芯片705的工作PHY类型，其中，主芯片703的工作PHY类型和从芯片705的工作PHY类型均与所述确定的通道类型相同。在主芯片703的工作PHY类型确定的情况下，系统软件701还将根据主芯片703的工作PHY类型，确定从芯片705在均衡的第四阶段的均衡时间。相应的，在从芯片705的工作PHY类型确定的情况下，系统软件701还将根据从芯片705的工作PHY类型，确定主芯片703在均衡的第三阶段的均衡时间。
需要说明的是，该通信系统还可以包括存储器702。该存储器702用于存储该通道类型表。
所谓的“系统软件701还将根据主芯片703的工作PHY类型，确定从芯片705在均衡的第四阶段的均衡时间”，具体是指：主芯片703根据主芯片703的工作PHY类型，配置主芯片703的均衡电路，并根据主芯片703的均衡电路确定主芯片703需要的均衡时间；然后，系统软件701根据主芯片703在均衡的第四阶段需要的均衡时间，配置从芯片705在均衡的第四阶段的均衡时间。
所谓的“系统软件701还将根据从芯片705的工作PHY类型，确定主芯片703在均衡的第三阶段的均衡时间”，具体是指：从芯片705根据从芯片705的工作PHY类型，配置从芯片705的均衡电路，并根据从芯片705的均衡电路确定从芯片705需要的均衡时间；然后，系统软件701根据从芯片705在均衡的第三阶段需要的均衡时间，配置主芯片703在均衡的第三阶段的均衡时间。
值得注意的是，在主芯片703的工作PHY类型和从芯片705的工作PHY类型均为SR时，系统软件701可以将主芯片703在均衡的第三阶段的均衡时间和从芯片705在均衡的第四阶段的均衡时间均配置为缺省值。在主芯片703的工作PHY类型和从芯片705的工作 PHY类型均为LR时，系统软件701可以读取从芯片705在均衡的第三阶段的均衡时间，并将其写入主芯片703中，以作为主芯片703在均衡的第三阶段的均衡时间，以及，读取主芯片703在均衡的第四阶段的均衡时间，并将其写入从芯片705中，以作为从芯片705在均衡的第四阶段的均衡时间。
作为本实施例的另一种实现，在主芯片703的工作PHY类型和从芯片705的工作PHY类型均为SR时，系统软件701可以读取从芯片705在均衡的第三阶段的均衡时间，并将其写入主芯片703中，以作为主芯片703在均衡的第三阶段的均衡时间，以及，读取主芯片703在均衡的第四阶段的均衡时间，并将其写入从芯片705中，以作为从芯片705在均衡的第四阶段的均衡时间。在主芯片703的工作PHY类型和从芯片705的工作PHY类型均为LR时，系统软件701可以将主芯片703在均衡的第三阶段的均衡时间和从芯片705在均衡的第四阶段的均衡时间均配置为缺省值。
值得注意的是，上述的装置、芯片以及通信系统均可以参见方法实施例中的有关描述。由于本申请保护的主体之间具有单一性，因此这些主体的描述部分有很多相同或相似的部分，为了节约篇幅，本申请文件中对方法实施例做了全面丰富的描述，其他实施例均比较简约。
应当知道的是，前述实施例仅为本发明的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应该以权利要求的保护范围为准。

Claims (31)

  1. 一种配置均衡时间的方法，其特征在于：
    获取主芯片的端口号和从芯片的标识，通过查找通道类型表，确定位于所述主芯片的端口和所述从芯片之间的通道的类型，其中，所述确定的通道类型为长距LR或短距SR；
    获取所述主芯片支持的物理层PHY类型和所述从芯片支持的PHY类型，并判断所述主芯片支持的PHY类型和所述从芯片支持的PHY类型是否均包括所述确定的通道类型，所述主芯片支持的PHY类型以及所述从芯片支持的PHY类型均为LR和SR、LR或SR三种的一种；
    在所述主芯片支持的PHY类型和所述从芯片支持的PHY类型中均包括所述确定的通道类型时，确定所述主芯片以及所述从芯片的工作PHY类型，所述主芯片以及所述从芯片的工作PHY类型均与所述确定的通道类型相同，
    根据所述从芯片的工作PHY类型，配置所述主芯片在均衡的第三阶段的均衡时间；以及，根据所述主芯片的工作PHY类型，配置所述从芯片在所述均衡的第四阶段的均衡时间。
  2. 根据权利要求1所述的方法，其特征在于，根据所述从芯片的工作PHY类型，配置主芯片在均衡的第三阶段的均衡时间，包括：
    根据所述从芯片的工作PHY类型，配置所述从芯片的均衡电路；根据所述均衡电路确定所述从芯片在所述第三阶段所需要的均衡时间；根据所述从芯片在所述第三阶段所需要的均衡时间配置所述主芯片在所述第三阶段的均衡时间。
  3. 根据权利要求1所述的方法，其特征在于，根据所述主芯片的工作PHY类型，配置从芯片在均衡的第四阶段的均衡时间，包括：
    根据所述主芯片的工作PHY类型，配置所述主芯片的均衡电路，根据所述均衡电路确定所述主芯片在所述第四阶段所需要的均衡时间，根据所述主芯片在所述第四阶段所需要的均衡时间配置从芯片在所述第四阶段的均衡时间。
  4. 根据权利要求1所述的方法，其特征在于，在所述从芯片的工作PHY类型为SR时，所述主芯片在所述均衡的第三阶段的均衡时间被配置为T1，在所述从芯片的工作PHY类型为LR时，所述主芯片在所述均衡的第三阶段的均衡时间被配置为T2，则T2的值大于T1的值。
  5. 根据权利要求1所述的方法，其特征在于，在所述主芯片的工作PHY类型为SR时，所述从芯片在所述均衡的第四阶段的均衡时间被配置为T3，在所述主芯片的工作PHY类型为LR时，所述从芯片在所述均衡的第四阶段的均衡时间被配置为T4，则T4的值大于T3的值。
  6. 根据权利要求1所述的方法，其特征在于，根据所述从芯片的工作PHY类型，配置所述主芯片在均衡的第三阶段的均衡时间；以及，根据所述主芯片的工作PHY类型，配置所述从芯片在所述均衡的第四阶段的均衡时间，包括：
    在所述主芯片和所述从芯片的工作PHY类型均为SR时，将所述主芯片在所述均衡的第三阶段的均衡时间和所述从芯片在所述均衡的第四阶段的均衡时间均配置为缺省值；
    在所述主芯片和所述从芯片的工作PHY类型均为LR时，读取所述从芯片在所述第三阶段的均衡时间，并将其写入所述主芯片中，以作为所述主芯片在所述均衡的第三阶段的 均衡时间，以及，读取所述主芯片在所述第四阶段的均衡时间，并将其写入所述从芯片中，以作为所述从芯片在所述均衡的第四阶段的均衡时间。
  7. 根据权利要求1所述的方法，其特征在于，根据所述从芯片的工作PHY类型，配置所述主芯片在均衡的第三阶段的均衡时间；以及，根据所述主芯片的工作PHY类型，配置所述从芯片在所述均衡的第四阶段的均衡时间，包括：
    在所述主芯片和所述从芯片的工作PHY类型均为SR时，读取所述从芯片在所述第三阶段的均衡时间，并将其写入所述主芯片中，以作为所述主芯片在所述均衡的第三阶段的均衡时间，以及，读取所述主芯片在所述第四阶段的均衡时间，并将其写入所述从芯片中，以作为所述从芯片在所述均衡的第四阶段的均衡时间；
    在所述主芯片和所述从芯片的工作PHY类型均为LR时，将所述主芯片在所述均衡的第三阶段的均衡时间和所述从芯片在所述均衡的第四阶段的均衡时间均配置为缺省值。
  8. 根据权利要求1至7任一项所述的方法，其特征在于：所述主芯片和所述从芯片之间通过外围组件快速互连PCIe总线或者加速器的高速互连内存一致性CCIX总线连通，所述主芯片为根组件或交换芯片，所述从芯片是独立于所述主芯片的端点设备。
  9. 根据权利要求1至8任一项所述的方法，其特征在于：所述通道类型表包括所述主芯片的端口号、所述从芯片的标识和通道类型，根据所述主芯片的端口号和所述从芯片的标识，能够唯一地确定位于所述主芯片的端口和所述从芯片之间的通道的类型。
  10. 根据权利要求1至9任一项所述的方法，其特征在于：所述通道类型是根据所述通道的损耗确定的，其中，LR对应的通道损耗大于SR对应的通道损耗。
  11. 根据权利要求1至10任一项所述的方法，其特征在于：芯片支持的PHY类型是根据所述芯片能够驱动的通道损耗确定的，其中，支持的PHY类型为LR的芯片能够驱动的通道损耗大于支持的PHY类型为SR的芯片能够驱动的通道损耗。
  12. 根据权利要求1至11任一项所述的方法，其特征在于：所述主芯片支持的PHY类型被预先存储在所述主芯片的寄存器内；所述从芯片支持的PHY类型被预先存储在所述从芯片的寄存器内。
  13. 一种配置均衡时间的装置，其特征在于，包括：
    收发器，用于接收主芯片的端口号和从芯片的标识，
    管理器，用于根据所述主芯片的端口号和所述从芯片的标识，通过查找通道类型表，确定位于所述主芯片的端口和所述从芯片之间的通道的类型，其中，所述确定的通道类型为长距LR或短距SR；
    所述收发器还用于接收所述主芯片支持的物理层PHY类型和所述从芯片支持的PHY类型，所述主芯片支持的PHY类型以及所述从芯片支持的PHY类型均为LR和SR、LR或SR三种的一种；
    所述管理器还用于判断所述主芯片支持的PHY类型和所述从芯片支持的PHY类型是否均包括所述确定的通道类型，并在所述主芯片支持的PHY类型和所述从芯片支持的PHY类型均包括所述确定的通道类型时，确定所述主芯片的工作PHY类型和所述从芯片的工作PHY类型，所述主芯片和所述从芯片的工作PHY类型均与所述确定的通道类型相同；
    以及，所述管理器还用于根据所述从芯片的工作PHY类型，配置所述主芯片在均衡的第三阶段的均衡时间，以及，根据所述主芯片的工作PHY类型，配置所述从芯片在所述均 衡的第四阶段的均衡时间。
  14. 根据权利要求13所述的装置，其特征在于：
    所述管理器具体用于根据所述从芯片在所述均衡的第三阶段需要的均衡时间配置所述主芯片在所述均衡的第三阶段的均衡时间，所述从芯片在所述均衡的第三阶段需要的均衡时间是所述从芯片根据所述从芯片的均衡电路确定的，所述从芯片的均衡电路是所述从芯片根据所述从芯片的工作PHY类型配置的。
  15. 根据权利要求13或14所述的装置，其特征在于：
    所述管理器具体用于根据所述主芯片在所述均衡的第四阶段需要的均衡时间配置所述从芯片在所述均衡的第四阶段的均衡时间，所述主芯片在所述均衡的第四阶段需要的均衡时间是所述主芯片根据所述主芯片的均衡电路确定的，所述主芯片的均衡电路是所述主芯片根据所述主芯片的工作PHY类型配置的。
  16. 根据权利要求13所述的装置，其特征在于：
    在所述主芯片和所述从芯片的工作PHY类型均为SR时，所述管理器具体用于将所述主芯片在所述均衡的第三阶段的均衡时间和所述从芯片在所述均衡的第四阶段的均衡时间均配置为缺省值；
    在所述主芯片和所述从芯片的工作PHY类型均为LR时，所述管理器具体用于读取所述从芯片在所述均衡的第三阶段的均衡时间，并将其写入所述主芯片中，以作为所述主芯片在所述均衡的第三阶段的均衡时间，以及，读取所述主芯片在所述均衡的第四阶段的均衡时间，并将其写入所述从芯片中，以作为所述从芯片在所述均衡的第四阶段的均衡时间。
  17. 根据权利要求13所述的装置，其特征在于：
    在所述主芯片和所述从芯片的工作PHY类型均为SR时，所述管理器具体用于读取所述从芯片在所述均衡的第三阶段的均衡时间，并将其写入所述主芯片中，以作为所述主芯片在所述均衡的第三阶段的均衡时间，以及，读取所述主芯片在所述均衡的第四阶段的均衡时间，并将其写入所述从芯片中，以作为所述从芯片在所述均衡的第四阶段的均衡时间；
    在所述主芯片和所述从芯片的工作PHY类型均为LR时，所述管理器具体用于将所述主芯片在所述均衡的第三阶段的均衡时间和所述从芯片在所述均衡的第四阶段的均衡时间均配置为缺省值。
  18. 一种配置均衡时间的装置，其特征在于，包括：
    获取单元，用于获取主芯片的端口号和从芯片的标识；
    确定单元，用于通过查找通道类型表，确定位于所述主芯片的端口和所述从芯片之间的通道的类型，其中，所述确定的通道类型为长距LR或短距SR；
    所述获取单元还用于获取所述主芯片支持的物理层PHY类型和所述从芯片支持的PHY类型，所述主芯片支持的PHY类型以及所述从芯片支持的PHY类型均为LR和SR、LR或SR三种的一种；
    确定单元还用于判断所述主芯片支持的PHY类型和所述从芯片支持的PHY类型是否均包括所述确定的通道类型，并在所述主芯片支持的PHY类型和所述从芯片支持的PHY类型中均包括所述确定的通道类型时，确定所述主芯片的工作PHY类型以及所述从芯片的工作PHY类型，其中，所述主芯片的工作PHY类型以及所述从芯片的工作PHY类型均与所述确定的通道类型相同；
    配置单元用于根据所述从芯片的工作PHY类型，配置所述主芯片在均衡的第三阶段的均衡时间；以及，根据所述主芯片的工作PHY类型，配置所述从芯片在所述均衡的第四阶段的均衡时间。
  19. 根据权利要求18所述的装置，其特征在于：
    所述配置单元具体用于根据所述从芯片在所述均衡的第三阶段需要的均衡时间配置所述主芯片在所述均衡的第三阶段的均衡时间，所述从芯片在所述均衡的第三阶段需要的均衡时间是所述从芯片根据所述从芯片的均衡电路确定的，所述从芯片的均衡电路是所述从芯片根据所述从芯片的工作PHY类型配置的。
  20. 根据权利要求18或19所述的装置，其特征在于：
    所述配置单元具体用于根据所述主芯片在所述均衡的第四阶段需要的均衡时间配置所述从芯片在所述均衡的第四阶段的均衡时间，所述主芯片在所述均衡的第四阶段需要的均衡时间是所述主芯片根据所述主芯片的均衡电路确定的，所述主芯片的均衡电路是所述主芯片根据所述主芯片的工作PHY类型配置的。
  21. 根据权利要求18所述的装置，其特征在于：
    在所述主芯片和所述从芯片的工作PHY类型均为SR时，所述配置单元具体用于将所述主芯片在所述均衡的第三阶段的均衡时间和所述从芯片在所述均衡的第四阶段的均衡时间均配置为缺省值；
    在所述主芯片和所述从芯片的工作PHY类型均为LR时，所述配置单元具体用于读取所述从芯片在所述均衡的第三阶段的均衡时间，并将其写入所述主芯片中，以作为所述主芯片在所述均衡的第三阶段的均衡时间，以及，读取所述主芯片在所述均衡的第四阶段的均衡时间，并将其写入所述从芯片中，以作为所述从芯片在所述均衡的第四阶段的均衡时间。
  22. 根据权利要求18所述的装置，其特征在于：
    在所述主芯片和所述从芯片的工作PHY类型均为SR时，所述配置单元具体用于读取所述从芯片在所述均衡的第三阶段的均衡时间，并将其写入所述主芯片中，以作为所述主芯片在所述均衡的第三阶段的均衡时间，以及，读取所述主芯片在所述均衡的第四阶段的均衡时间，并将其写入所述从芯片中，以作为所述从芯片在所述均衡的第四阶段的均衡时间；
    在所述主芯片和所述从芯片的工作PHY类型均为LR时，所述配置单元具体用于将所述主芯片在所述均衡的第三阶段的均衡时间和所述从芯片在所述均衡的第四阶段的均衡时间均配置为缺省值。
  23. 一种芯片，其特征在于，包括：
    第一寄存器，用于存储所述芯片支持的物理层PHY类型，所述芯片支持的PHY类型为长距LR和短距SR、LR或SR三种的一种；
    收发器，用于发送所述芯片支持的PHY类型以及接收所述芯片的工作PHY类型，所述芯片的工作PHY类型是根据所述芯片与另一个其他芯片之间的通道的类型确定的，其中，所述芯片和所述另一个其他芯片支持的PHY类型均包括所述确定的通道的类型，所述确定的通道的类型为LR或SR，所述工作PHY类型与所述确定的通道的类型相同；
    第二寄存器，用于存储所述芯片的工作PHY类型，
    管理器，用于根据所述芯片的工作PHY类型配置所述芯片的均衡电路，并根据所述芯片的均衡电路确定所述芯片的均衡时间。
  24. 根据权利要求23所述的芯片，其特征在于，
    所述第二寄存器还用于存储所述芯片的均衡时间。
  25. 一种通信系统，其特征在于，包括系统软件、主芯片和从芯片，所述主芯片和所述从芯片之间通过外围组件快速互连PCIe总线或者加速器的高速互连内存一致性CCIX总线连通；
    所述系统软件用于：
    获取所述主芯片的端口号和所述从芯片的标识，通过查找通道类型表，确定位于所述主芯片的端口和所述从芯片之间的通道的类型，所述确定的通道类型为长距LR或短距SR；以及，
    获取所述主芯片支持的物理层PHY类型和所述从芯片支持的PHY类型，并判断所述主芯片支持的PHY类型和所述从芯片支持的PHY类型是否均包括所述确定的通道类型，所述主芯片支持的PHY类型以及所述从芯片支持的PHY类型均为LR和SR、LR或SR三种的一种；
    在所述主芯片支持的PHY类型和所述从芯片支持的PHY类型中均包括所述确定的通道类型时，所述系统软件还用于：
    确定所述主芯片的工作PHY类型以及所述从芯片的工作PHY类型，所述主芯片的工作PHY类型以及所述从芯片的工作PHY类型均与所述确定的通道类型相同，以及，
    根据所述从芯片的工作PHY类型，配置所述主芯片在均衡的第三阶段的均衡时间；以及，根据所述主芯片的工作PHY类型，配置所述从芯片在所述均衡的第四阶段的均衡时间。
  26. 根据权利要求25所述的通信系统，其特征在于，还包括：
    存储器，用于存储所述通道类型表。
  27. 根据权利要求25或26所述的通信系统，其特征在于，
    所述系统软件具体用于获取所述主芯片读取并发送的所述主芯片支持的PHY类型，以及，获取所述从芯片读取并发送的所述从芯片支持的PHY类型。
  28. 根据权利要求25至27任一项所述的通信系统，其特征在于，所述系统软件还用于根据所述从芯片的工作PHY类型，配置所述主芯片在均衡的第三阶段的均衡时间，具体包括：
    所述从芯片用于根据所述从芯片的工作PHY类型，配置所述从芯片的均衡电路，并根据所述从芯片的均衡电路确定所述从芯片在所述均衡的第三阶段需要的均衡时间；
    所述系统软件具体用于根据所述从芯片在所述均衡的第三阶段需要的均衡时间配置所述主芯片在所述均衡的第三阶段的均衡时间。
  29. 根据权利要求25至28任一项所述的通信系统，其特征在于，所述系统软件还用于根据所述主芯片的工作PHY类型，配置所述从芯片在所述均衡的第四阶段的均衡时间，具体包括：
    所述主芯片用于根据所述主芯片的工作PHY类型，配置所述主芯片的均衡电路，并根据所述主芯片的均衡电路确定所述主芯片在所述均衡的第四阶段需要的均衡时间；
    所述系统软件具体用于根据所述主芯片在所述均衡的第四阶段需要的均衡时间配置所述从芯片在所述均衡的第四阶段的均衡时间。
  30. 根据权利要求25至27任一项所述的通信系统，其特征在于，
    在所述主芯片和所述从芯片的工作PHY类型均为SR时，所述系统软件具体用于将所述主芯片在所述均衡的第三阶段的均衡时间和所述从芯片在所述均衡的第四阶段的均衡时间均配置为缺省值；
    在所述主芯片和所述从芯片的工作PHY类型均为LR时，所述系统软件具体用于读取所述从芯片在所述均衡的第三阶段的均衡时间，并将其写入所述主芯片中，以作为所述主芯片在所述均衡的第三阶段的均衡时间，以及，读取所述主芯片在所述均衡的第四阶段的均衡时间，并将其写入所述从芯片中，以作为所述从芯片在所述均衡的第四阶段的均衡时间。
  31. 根据权利要求25至27任一项所述的通信系统，其特征在于，
    在所述主芯片和所述从芯片的工作PHY类型均为SR时，所述系统软件具体用于读取所述从芯片在所述均衡的第三阶段的均衡时间，并将其写入所述主芯片中，以作为所述主芯片在所述均衡的第三阶段的均衡时间，以及，读取所述主芯片在所述均衡的第四阶段的均衡时间，并将其写入所述从芯片中，以作为所述从芯片在所述均衡的第四阶段的均衡时间；
    在所述主芯片和所述从芯片的工作PHY类型均为LR时，所述系统软件具体用于将所述主芯片在所述均衡的第三阶段的均衡时间和所述从芯片在所述均衡的第四阶段的均衡时间均配置为缺省值。
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