WO2019213947A1

WO2019213947A1 - Improved iterative decoder for ldpc codes with weights and biases

Info

Publication number: WO2019213947A1
Application number: PCT/CN2018/086533
Authority: WO
Inventors: Kai Chen; Yu Zhang; Hao Xu
Original assignee: Qualcomm Incorporated
Priority date: 2018-05-11
Filing date: 2018-05-11
Publication date: 2019-11-14

Abstract

Certain aspects of the present disclosure provide techniques for wireless communication. An exemplary method generally includes receiving a low-density parity-check (LDPC) -encoded codeword and decoding the codeword using a tanner base graph comprising a plurality of check nodes and a plurality of variable nodes, wherein decoding the codeword using the tanner graph comprises variably applying at least one of weights or biases to each check-node-to-variable-node connection and variable-node-to-check-node connection in the tanner graph.

Description

IMPROVED ITERATIVE DECODER FOR LDPC CODES WITH WEIGHTS AND BIASES

INTRODUCTION

Field of the Disclosure

Aspects of the present disclosure relate to wireless communications, and more particularly, to techniques for an improved iterative decoder for LDPC codes with weights and biases.

Description of Related Art

Wireless communication systems are widely deployed to provide various telecommunication services such as telephony, video, data, messaging, broadcasts, etc. These wireless communication systems may employ multiple-access technologies capable of supporting communication with multiple users by sharing available system resources (e.g., bandwidth, transmit power, etc. ) . Examples of such multiple-access systems include 3rd Generation Partnership Project (3GPP) Long Term Evolution (LTE) systems, LTE Advanced (LTE-A) systems, code division multiple access (CDMA) systems, time division multiple access (TDMA) systems, frequency division multiple access (FDMA) systems, orthogonal frequency division multiple access (OFDMA) systems, single-carrier frequency division multiple access (SC-FDMA) systems, and time division synchronous code division multiple access (TD-SCDMA) systems, to name a few.

In some examples, a wireless multiple-access communication system may include a number of base stations (BSs) , which are each capable of simultaneously supporting communication for multiple communication devices, otherwise known as user equipments (UEs) . In an LTE or LTE-A network, a set of one or more base stations may define an eNodeB (eNB) . In other examples (e.g., in a next generation, a new radio (NR) , or 5G network) , a wireless multiple access communication system may include a number of distributed units (DUs) (e.g., edge units (EUs) , edge nodes (ENs) , radio heads (RHs) , smart radio heads (SRHs) , transmission reception points (TRPs) , etc. ) in communication with a number of central units (CUs) (e.g., central nodes (CNs) , access node controllers (ANCs) , etc. ) , where a set of one or more distributed units, in communication with a central unit, may define an access node (e.g., which may be referred to as a base station, 5G NB, next generation NodeB (gNB or gNodeB) , TRP, etc. ) . A base station or distributed unit may communicate with a set of UEs on downlink channels (e.g., for transmissions from a base station or to a UE) and uplink channels (e.g., for transmissions from a UE to a base station or distributed unit) .

These multiple access technologies have been adopted in various telecommunication standards to provide a common protocol that enables different wireless devices to communicate on a municipal, national, regional, and even global level. New Radio (NR) (e.g., 5G) is an example of an emerging telecommunication standard. NR is a set of enhancements to the LTE mobile standard promulgated by 3GPP. It is designed to better support mobile broadband Internet access by improving spectral efficiency, lowering costs, improving services, making use of new spectrum, and better integrating with other open standards using OFDMA with a cyclic prefix (CP) on the downlink (DL) and on the uplink (UL) . To these ends, NR supports beamforming, multiple-input multiple-output (MIMO) antenna technology, and carrier aggregation.

However, as the demand for mobile broadband access continues to increase, there exists a need for further improvements in NR and LTE technology. Preferably, these improvements should be applicable to other multi-access technologies and the telecommunication standards that employ these technologies.

BRIEF SUMMARY

The systems, methods, and devices of the disclosure each have several aspects, no single one of which is solely responsible for its desirable attributes. Without limiting the scope of this disclosure as expressed by the claims which follow, some features will now be discussed briefly. After considering this discussion, and particularly after reading the section entitled “Detailed Description” one will understand how the features of this disclosure provide advantages that include improved communications between access points and stations in a wireless network.

Certain aspects provide a method for wireless communication. The method generally includes receiving a low-density parity-check (LDPC) -encoded codeword and decoding the codeword using a tanner base graph comprising a plurality of check nodes and a plurality of variable nodes, wherein decoding the codeword using the tanner graph comprises variably applying at least one of weights or biases to each check-node-to- variable-node connection and variable-node-to-check-node connection in the tanner graph.

Certain aspects provide an apparatus for wireless communication. The apparatus generally includes at least one processor configured to receive a low-density parity-check (LDPC) -encoded codeword and decode the codeword using a tanner base graph comprising a plurality of check nodes and a plurality of variable nodes, wherein decoding the codeword using the tanner graph comprises variably applying at least one of weights or biases to each check-node-to-variable-node connection and variable-node-to-check-node connection in the tanner graph. The apparatus also generally includes a memory coupled with the at least one processor.

Certain aspects provide an apparatus for wireless communication. The apparatus generally includes means for receiving a low-density parity-check (LDPC) -encoded codeword and means for decoding the codeword using a tanner base graph comprising a plurality of check nodes and a plurality of variable nodes, wherein decoding the codeword using the tanner graph comprises variably applying at least one of weights or biases to each check-node-to-variable-node connection and variable-node-to-check-node connection in the tanner graph.

Certain aspects provide a non-transitory computer-readable medium for wireless communication. The non-transitory computer-readable medium generally includes instructions that, when executed by at least one processor, configure the at least one processor to receive a low-density parity-check (LDPC) -encoded codeword and decode the codeword using a tanner base graph comprising a plurality of check nodes and a plurality of variable nodes, wherein decoding the codeword using the tanner graph comprises variably applying at least one of weights or biases to each check-node-to-variable-node connection and variable-node-to-check-node connection in the tanner graph.

To the accomplishment of the foregoing and related ends, the one or more aspects comprise the features hereinafter fully described and particularly pointed out in the claims. The following description and the appended drawings set forth in detail certain illustrative features of the one or more aspects. These features are indicative, however, of but a few of the various ways in which the principles of various aspects may be employed.

BRIEF DESCRIPTION OF THE DRAWINGS

So that the manner in which the above-recited features of the present disclosure can be understood in detail, a more particular description, briefly summarized above, may be had by reference to aspects, some of which are illustrated in the drawings. It is to be noted, however, that the appended drawings illustrate only certain typical aspects of this disclosure and are therefore not to be considered limiting of its scope, for the description may admit to other equally effective aspects.

FIG. 1 is a block diagram conceptually illustrating an example telecommunications system, in accordance with certain aspects of the present disclosure.

FIG. 2 is a block diagram illustrating an example logical architecture of a distributed radio access network (RAN) , in accordance with certain aspects of the present disclosure.

FIG. 3 is a diagram illustrating an example physical architecture of a distributed RAN, in accordance with certain aspects of the present disclosure.

FIG. 4 is a block diagram conceptually illustrating a design of an example base station (BS) and user equipment (UE) , in accordance with certain aspects of the present disclosure.

FIG. 5 is a diagram showing examples for implementing a communication protocol stack, in accordance with certain aspects of the present disclosure.

FIG. 6 illustrates an example of a frame format for a new radio (NR) system, in accordance with certain aspects of the present disclosure.

FIGs. 7-7A show graphical and matrix representations of an exemplary low density parity check (LDPC) code, according to certain aspects of the present disclosure.

FIG. 8 graphically illustrates lifting of the LDPC code of FIG. 4A, according to certain aspects of the present disclosure.

FIG. 9 is an integer representation of a matrix for a quasi-cyclic 802.11 LDPC code.

FIG. 10 illustrates example multi-edge type LDPC codes, according to certain aspects of the present disclosure.

FIG. 11 is a simplified block diagram illustrating a puncturing encoder, according to certain aspects of the present disclosure.

FIG. 12 is a simplified block diagram illustrating a decoder, according to certain aspects of the present disclosure.

FIG. 13 illustrate example operations for wireless communications, according to certain aspects of the present disclosure.

FIG. 14 illustrates an example neural network implementing a machine learning algorithm, according to certain aspects of the present disclosure.

FIG. 15 illustrates a complexity comparison between message passing algorithms, according to certain aspects of the present disclosure.

FIG. 16 illustrates a communications device that may include various components configured to perform operations for the techniques disclosed herein in accordance with aspects of the present disclosure.

To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one aspect may be beneficially utilized on other aspects without specific recitation.

DETAILED DESCRIPTION

Aspects of the present disclosure provide apparatus, methods, processing systems, and computer readable mediums for an improved iterative decoder for LDPC codes with weights and biases.

The following description provides examples, and is not limiting of the scope, applicability, or examples set forth in the claims. Changes may be made in the function and arrangement of elements discussed without departing from the scope of the disclosure. Various examples may omit, substitute, or add various procedures or components as appropriate. For instance, the methods described may be performed in an order different from that described, and various steps may be added, omitted, or combined. Also, features described with respect to some examples may be combined in some other examples. For example, an apparatus may be implemented or a method may be practiced using any number of the aspects set forth herein. In addition, the scope of the disclosure is intended to cover such an apparatus or method which is practiced using other structure, functionality, or structure and functionality in addition to, or other than, the various aspects of the disclosure set forth herein. It should be understood that any aspect of the disclosure disclosed herein may be embodied by one or more elements of a claim. The word “exemplary” is used herein to mean “serving as an example, instance, or illustration. ” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

The techniques described herein may be used for various wireless communication technologies, such as LTE, CDMA, TDMA, FDMA, OFDMA, SC-FDMA and other networks. The terms “network” and “system” are often used interchangeably. A CDMA network may implement a radio technology such as Universal Terrestrial Radio Access (UTRA) , cdma2000, etc. UTRA includes Wideband CDMA (WCDMA) and other variants of CDMA. cdma2000 covers IS-2000, IS-95 and IS-856 standards. A TDMA network may implement a radio technology such as Global System for Mobile Communications (GSM) . An OFDMA network may implement a radio technology such as NR (e.g. 5G RA) , Evolved UTRA (E-UTRA) , Ultra Mobile Broadband (UMB) , IEEE 802.11 (Wi-Fi) , IEEE 802.16 (WiMAX) , IEEE 802.20, Flash-OFDMA, etc. UTRA and E-UTRA are part of Universal Mobile Telecommunication System (UMTS) .

New Radio (NR) is an emerging wireless communications technology under development in conjunction with the 5G Technology Forum (5GTF) . 3GPP Long Term Evolution (LTE) and LTE-Advanced (LTE-A) are releases of UMTS that use E-UTRA. UTRA, E-UTRA, UMTS, LTE, LTE-A and GSM are described in documents from an organization named “3rd Generation Partnership Project” (3GPP) . cdma2000 and UMB are described in documents from an organization named “3rd Generation Partnership Project 2” (3GPP2) . The techniques described herein may be used for the wireless networks and radio technologies mentioned above as well as other wireless networks and radio technologies. For clarity, while aspects may be described herein using terminology commonly associated with 3G and/or 4G wireless technologies, aspects of the present disclosure can be applied in other generation-based communication systems, such as 5G and later, including NR technologies.

New radio (NR) access (e.g., 5G technology) may support various wireless communication services, such as enhanced mobile broadband (eMBB) targeting wide bandwidth (e.g., 80 MHz or beyond) , millimeter wave (mmW) targeting high carrier frequency (e.g., 25 GHz or beyond) , massive machine type communications MTC (mMTC) targeting non-backward compatible MTC techniques, and/or mission critical targeting ultra-reliable low-latency communications (URLLC) . These services may include latency and reliability requirements. These services may also have different transmission time intervals (TTI) to meet respective quality of service (QoS) requirements. In addition, these services may co-exist in the same subframe.

Example Wireless Communications System

FIG. 1 illustrates an example wireless communication network 100 in which aspects of the present disclosure may be performed. For example, the wireless communication network 100 may be a New Radio (NR) or 5G network.

As illustrated in FIG. 1, the wireless network 100 may include a number of base stations (BSs) 110 and other network entities. A BS may be a station that communicates with user equipments (UEs) . Each BS 110 may provide communication coverage for a particular geographic area. In 3GPP, the term “cell” can refer to a coverage area of a Node B (NB) and/or a Node B subsystem serving this coverage area, depending on the context in which the term is used. In NR systems, the term “cell” and next generation NodeB (gNB) , new radio base station (NR BS) , 5G NB, access point (AP) , or transmission reception point (TRP) may be interchangeable. In some examples, a cell may not necessarily be stationary, and the geographic area of the cell may move according to the location of a mobile BS. In some examples, the base stations may be interconnected to one another and/or to one or more other base stations or network nodes (not shown) in wireless communication network 100 through various types of backhaul interfaces, such as a direct physical connection, a wireless connection, a virtual network, or the like using any suitable transport network.

In general, any number of wireless networks may be deployed in a given geographic area. Each wireless network may support a particular radio access technology (RAT) and may operate on one or more frequencies. A RAT may also be referred to as a radio technology, an air interface, etc. A frequency may also be referred to as a carrier, a subcarrier, a frequency channel, a tone, a subband, etc. Each frequency may support a single RAT in a given geographic area in order to avoid interference between wireless networks of different RATs. In some cases, NR or 5G RAT networks may be deployed.

A base station (BS) may provide communication coverage for a macro cell, a pico cell, a femto cell, and/or other types of cells. A macro cell may cover a relatively large geographic area (e.g., several kilometers in radius) and may allow unrestricted access by UEs with service subscription. A pico cell may cover a relatively small geographic area and may allow unrestricted access by UEs with service subscription. A femto cell may cover a relatively small geographic area (e.g., a home) and may allow restricted access by UEs having an association with the femto cell (e.g., UEs in a Closed Subscriber Group (CSG) , UEs for users in the home, etc. ) . A BS for a macro cell may be referred to as a macro BS. A BS for a pico cell may be referred to as a pico BS. A BS for a femto cell may be referred to as a femto BS or a home BS. In the example shown in FIG. 1, the

BSs

110a, 110b and 110c may be macro BSs for the

macro cells

102a, 102b and 102c, respectively. The BS 110x may be a pico BS for a pico cell 102x. The BSs 110y and 110z may be femto BSs for the femto cells 102y and 102z, respectively. A BS may support one or multiple (e.g., three) cells.

Wireless communication network 100 may also include relay stations. A relay station is a station that receives a transmission of data and/or other information from an upstream station (e.g., a BS or a UE) and sends a transmission of the data and/or other information to a downstream station (e.g., a UE or a BS) . A relay station may also be a UE that relays transmissions for other UEs. In the example shown in FIG. 1, a relay station 110r may communicate with the BS 110a and a UE 120r in order to facilitate communication between the BS 110a and the UE 120r. A relay station may also be referred to as a relay BS, a relay, etc.

Wireless network 100 may be a heterogeneous network that includes BSs of different types, e.g., macro BS, pico BS, femto BS, relays, etc. These different types of BSs may have different transmit power levels, different coverage areas, and different impact on interference in the wireless network 100. For example, macro BS may have a high transmit power level (e.g., 20 Watts) whereas pico BS, femto BS, and relays may have a lower transmit power level (e.g., 1 Watt) .

Wireless communication network 100 may support synchronous or asynchronous operation. For synchronous operation, the BSs may have similar frame timing, and transmissions from different BSs may be approximately aligned in time. For asynchronous operation, the BSs may have different frame timing, and transmissions from different BSs may not be aligned in time. The techniques described herein may be used for both synchronous and asynchronous operation.

A network controller 130 may couple to a set of BSs and provide coordination and control for these BSs. The network controller 130 may communicate with the BSs 110 via a backhaul. The BSs 110 may also communicate with one another (e.g., directly or indirectly) via wireless or wireline backhaul.

The UEs 120 (e.g., 120x, 120y, etc. ) may be dispersed throughout the wireless network 100, and each UE may be stationary or mobile. A UE may also be referred to as a mobile station, a terminal, an access terminal, a subscriber unit, a station, a Customer Premises Equipment (CPE) , a cellular phone, a smart phone, a personal digital assistant (PDA) , a wireless modem, a wireless communication device, a handheld device, a laptop computer, a cordless phone, a wireless local loop (WLL) station, a tablet computer, a camera, a gaming device, a netbook, a smartbook, an ultrabook, an appliance, a medical device or medical equipment, a biometric sensor/device, a wearable device such as a smart watch, smart clothing, smart glasses, a smart wrist band, smart jewelry (e.g., a smart ring, a smart bracelet, etc. ) , an entertainment device (e.g., a music device, a video device, a satellite radio, etc. ) , a vehicular component or sensor, a smart meter/sensor, industrial manufacturing equipment, a global positioning system device, or any other suitable device that is configured to communicate via a wireless or wired medium. Some UEs may be considered machine-type communication (MTC) devices or evolved MTC (eMTC) devices. MTC and eMTC UEs include, for example, robots, drones, remote devices, sensors, meters, monitors, location tags, etc., that may communicate with a BS, another device (e.g., remote device) , or some other entity. A wireless node may provide, for example, connectivity for or to a network (e.g., a wide area network such as Internet or a cellular network) via a wired or wireless communication link. Some UEs may be considered Internet-of-Things (IoT) devices, which may be narrowband IoT (NB-IoT) devices.

Certain wireless networks (e.g., LTE) utilize orthogonal frequency division multiplexing (OFDM) on the downlink and single-carrier frequency division multiplexing (SC-FDM) on the uplink. OFDM and SC-FDM partition the system bandwidth into multiple (K) orthogonal subcarriers, which are also commonly referred to as tones, bins, etc. Each subcarrier may be modulated with data. In general, modulation symbols are sent in the frequency domain with OFDM and in the time domain with SC-FDM. The spacing between adjacent subcarriers may be fixed, and the total number of subcarriers (K) may be dependent on the system bandwidth. For example, the spacing of the subcarriers may be 15 kHz and the minimum resource allocation (called a “resource block” (RB) ) may be 12 subcarriers (or 180 kHz) . Consequently, the nominal Fast Fourier Transfer (FFT) size may be equal to 128, 256, 512, 1024 or 2048 for system bandwidth of 1.25, 2.5, 5, 10, or 20 megahertz (MHz) , respectively. The system bandwidth may also be partitioned into subbands. For example, a subband may cover 1.08 MHz (i.e., 6 resource blocks) , and there may be 1, 2, 4, 8, or 16 subbands for system bandwidth of 1.25, 2.5, 5, 10 or 20 MHz, respectively.

While aspects of the examples described herein may be associated with LTE technologies, aspects of the present disclosure may be applicable with other wireless communications systems, such as NR. NR may utilize OFDM with a CP on the uplink and downlink and include support for half-duplex operation using TDD. Beamforming may be supported and beam direction may be dynamically configured. MIMO transmissions with precoding may also be supported. MIMO configurations in the DL may support up to 8 transmit antennas with multi-layer DL transmissions up to 8 streams and up to 2 streams per UE. Multi-layer transmissions with up to 2 streams per UE may be supported. Aggregation of multiple cells may be supported with up to 8 serving cells.

In some examples, access to the air interface may be scheduled, wherein a. A scheduling entity (e.g., a base station) allocates resources for communication among some or all devices and equipment within its service area or cell. The scheduling entity may be responsible for scheduling, assigning, reconfiguring, and releasing resources for one or more subordinate entities. That is, for scheduled communication, subordinate entities utilize resources allocated by the scheduling entity. Base stations are not the only entities that may function as a scheduling entity. In some examples, a UE may function as a scheduling entity and may schedule resources for one or more subordinate entities (e.g., one or more other UEs) , and the other UEs may utilize the resources scheduled by the UE for wireless communication. In some examples, a UE may function as a scheduling entity in a peer-to-peer (P2P) network, and/or in a mesh network. In a mesh network example, UEs may communicate directly with one another in addition to communicating with a scheduling entity.

In FIG. 1, a solid line with double arrows indicates desired transmissions between a UE and a serving BS, which is a BS designated to serve the UE on the downlink and/or uplink. A finely dashed line with double arrows indicates interfering transmissions between a UE and a BS.

FIG. 2 illustrates an example logical architecture of a distributed Radio Access Network (RAN) 200, which may be implemented in the wireless communication network 100 illustrated in FIG. 1. A 5G access node 206 may include an access node controller (ANC) 202. ANC 202 may be a central unit (CU) of the distributed RAN 200. The backhaul interface to the Next Generation Core Network (NG-CN) 204 may terminate at ANC 202. The backhaul interface to neighboring next generation access Nodes (NG-ANs) 210 may terminate at ANC 202. ANC 202 may include one or more transmission reception points (TRPs) 208 (e.g., cells, BSs, gNBs, etc. ) .

The TRPs 208 may be a distributed unit (DU) . TRPs 208 may be connected to a single ANC (e.g., ANC 202) or more than one ANC (not illustrated) . For example, for RAN sharing, radio as a service (RaaS) , and service specific AND deployments, TRPs 208 may be connected to more than one ANC. TRPs 208 may each include one or more antenna ports. TRPs 208 may be configured to individually (e.g., dynamic selection) or jointly (e.g., joint transmission) serve traffic to a UE.

The logical architecture of distributed RAN 200 may support fronthauling solutions across different deployment types. For example, the logical architecture may be based on transmit network capabilities (e.g., bandwidth, latency, and/or jitter) .

The logical architecture of distributed RAN 200 may share features and/or components with LTE. For example, next generation access node (NG-AN) 210 may support dual connectivity with NR and may share a common fronthaul for LTE and NR.

The logical architecture of distributed RAN 200 may enable cooperation between and among TRPs 208, for example, within a TRP and/or across TRPs via ANC 202. An inter-TRP interface may not be used.

Logical functions may be dynamically distributed in the logical architecture of distributed RAN 200. As will be described in more detail with reference to FIG. 5, the Radio Resource Control (RRC) layer, Packet Data Convergence Protocol (PDCP) layer, Radio Link Control (RLC) layer, Medium Access Control (MAC) layer, and a Physical (PHY) layers may be adaptably placed at the DU (e.g., TRP 208) or CU (e.g., ANC 202) .

FIG. 3 illustrates an example physical architecture of a distributed Radio Access Network (RAN) 300, according to aspects of the present disclosure. A centralized core network unit (C-CU) 302 may host core network functions. C-CU 302 may be centrally deployed. C-CU 302 functionality may be offloaded (e.g., to advanced wireless services (AWS) ) , in an effort to handle peak capacity.

A centralized RAN unit (C-RU) 304 may host one or more ANC functions. Optionally, the C-RU 304 may host core network functions locally. The C-RU 304 may have distributed deployment. The C-RU 304 may be close to the network edge.

A DU 306 may host one or more TRPs (Edge Node (EN) , an Edge Unit (EU) , a Radio Head (RH) , a Smart Radio Head (SRH) , or the like) . The DU may be located at edges of the network with radio frequency (RF) functionality.

FIG. 4 illustrates example components of BS 110 and UE 120 (as depicted in FIG. 1) , which may be used to implement aspects of the present disclosure. For example, antennas 452,

processors

466, 458, 464, and/or controller/processor 480 of the UE 120 and/or antennas 434,

processors

420, 460, 438, and/or controller/processor 440 of the BS 110 may be used to perform the various techniques and methods described herein.

At the BS 110, a transmit processor 420 may receive data from a data source 412 and control information from a controller/processor 440. The control information may be for the physical broadcast channel (PBCH) , physical control format indicator channel (PCFICH) , physical hybrid ARQ indicator channel (PHICH) , physical downlink control channel (PDCCH) , group common PDCCH (GC PDCCH) , etc. The data may be for the physical downlink shared channel (PDSCH) , etc. The processor 420 may process (e.g., encode and symbol map) the data and control information to obtain data symbols and control symbols, respectively. The processor 420 may also generate reference symbols, e.g., for the primary synchronization signal (PSS) , secondary synchronization signal (SSS) , and cell-specific reference signal (CRS) . A transmit (TX) multiple-input multiple-output (MIMO) processor 430 may perform spatial processing (e.g., precoding) on the data symbols, the control symbols, and/or the reference symbols, if applicable, and may provide output symbol streams to the modulators (MODs) 432a through 432t. Each modulator 432 may process a respective output symbol stream (e.g., for OFDM, etc. ) to obtain an output sample stream. Each modulator may further process (e.g., convert to analog, amplify, filter, and upconvert) the output sample stream to obtain a downlink signal. Downlink signals from modulators 432a through 432t may be transmitted via the antennas 434a through 434t, respectively.

At the UE 120, the antennas 452a through 452r may receive the downlink signals from the base station 110 and may provide received signals to the demodulators (DEMODs) in transceivers 454a through 454r, respectively. Each demodulator 454 may condition (e.g., filter, amplify, downconvert, and digitize) a respective received signal to obtain input samples. Each demodulator may further process the input samples (e.g., for OFDM, etc. ) to obtain received symbols. A MIMO detector 456 may obtain received symbols from all the demodulators 454a through 454r, perform MIMO detection on the received symbols if applicable, and provide detected symbols. A receive processor 458 may process (e.g., demodulate, deinterleave, and decode) the detected symbols, provide decoded data for the UE 120 to a data sink 460, and provide decoded control information to a controller/processor 480.

On the uplink, at UE 120, a transmit processor 464 may receive and process data (e.g., for the physical uplink shared channel (PUSCH) ) from a data source 462 and control information (e.g., for the physical uplink control channel (PUCCH) from the controller/processor 480. The transmit processor 464 may also generate reference symbols for a reference signal (e.g., for the sounding reference signal (SRS) ) . The symbols from the transmit processor 464 may be precoded by a TX MIMO processor 466 if applicable, further processed by the demodulators in transceivers 454a through 454r (e.g., for SC-FDM, etc. ) , and transmitted to the base station 110. At the BS 110, the uplink signals from the UE 120 may be received by the antennas 434, processed by the modulators 432, detected by a MIMO detector 436 if applicable, and further processed by a receive processor 438 to obtain decoded data and control information sent by the UE 120. The receive processor 438 may provide the decoded data to a data sink 439 and the decoded control information to the controller/processor 440.

The controllers/

processors

440 and 480 may direct the operation at the base station 110 and the UE 120, respectively. The processor 440 and/or other processors and modules at the BS 110 may perform or direct the execution of processes for the techniques described herein. The

memories

442 and 482 may store data and program codes for BS 110 and UE 120, respectively. A scheduler 444 may schedule UEs for data transmission on the downlink and/or uplink.

FIG. 5 illustrates a diagram 500 showing examples for implementing a communications protocol stack, according to aspects of the present disclosure. The illustrated communications protocol stacks may be implemented by devices operating in a wireless communication system, such as a 5G system (e.g., a system that supports uplink-based mobility) . Diagram 500 illustrates a communications protocol stack including a Radio Resource Control (RRC) layer 510, a Packet Data Convergence Protocol (PDCP) layer 515, a Radio Link Control (RLC) layer 520, a Medium Access Control (MAC) layer 525, and a Physical (PHY) layer 530. In various examples, the layers of a protocol stack may be implemented as separate modules of software, portions of a processor or ASIC, portions of non-collocated devices connected by a communications link, or various combinations thereof. Collocated and non-collocated implementations may be used, for example, in a protocol stack for a network access device (e.g., ANs, CUs, and/or DUs) or a UE.

A first option 505-ashows a split implementation of a protocol stack, in which implementation of the protocol stack is split between a centralized network access device (e.g., an ANC 202 in FIG. 2) and distributed network access device (e.g., DU 208 in FIG. 2) . In the first option 505-a, an RRC layer 510 and a PDCP layer 515 may be implemented by the central unit, and an RLC layer 520, a MAC layer 525, and a PHY layer 530 may be implemented by the DU. In various examples the CU and the DU may be collocated or non-collocated. The first option 505-amay be useful in a macro cell, micro cell, or pico cell deployment.

A second option 505-b shows a unified implementation of a protocol stack, in which the protocol stack is implemented in a single network access device. In the second option, RRC layer 510, PDCP layer 515, RLC layer 520, MAC layer 525, and PHY layer 530 may each be implemented by the AN. The second option 505-b may be useful in, for example, a femto cell deployment.

Regardless of whether a network access device implements part or all of a protocol stack, a UE may implement an entire protocol stack as shown in 505-c (e.g., the RRC layer 510, the PDCP layer 515, the RLC layer 520, the MAC layer 525, and the PHY layer 530) .

In LTE, the basic transmission time interval (TTI) or packet duration is the 1 ms subframe. In NR, a subframe is still 1 ms, but the basic TTI is referred to as a slot. A subframe contains a variable number of slots (e.g., 1, 2, 4, 8, 16, …slots) depending on the subcarrier spacing. The NR RB is 12 consecutive frequency subcarriers. NR may support a base subcarrier spacing of 15 KHz and other subcarrier spacing may be defined with respect to the base subcarrier spacing, for example, 30 kHz, 60 kHz, 120 kHz, 240 kHz, etc. The symbol and slot lengths scale with the subcarrier spacing. The CP length also depends on the subcarrier spacing.

FIG. 6 is a diagram showing an example of a frame format 600 for NR. The transmission timeline for each of the downlink and uplink may be partitioned into units of radio frames. Each radio frame may have a predetermined duration (e.g., 10 ms) and may be partitioned into 10 subframes, each of 1 ms, with indices of 0 through 9. Each subframe may include a variable number of slots depending on the subcarrier spacing. Each slot may include a variable number of symbol periods (e.g., 7 or 14 symbols) depending on the subcarrier spacing. The symbol periods in each slot may be assigned indices. A mini-slot, which may be referred to as a sub-slot structure, refers to a transmit time interval having a duration less than a slot (e.g., 2, 3, or 4 symbols) .

Each symbol in a slot may indicate a link direction (e.g., DL, UL, or flexible) for data transmission and the link direction for each subframe may be dynamically switched. The link directions may be based on the slot format. Each slot may include DL/UL data as well as DL/UL control information.

In NR, a synchronization signal (SS) block is transmitted. The SS block includes a PSS, a SSS, and a two symbol PBCH. The SS block can be transmitted in a fixed slot location, such as the symbols 0-3 as shown in FIG. 6. The PSS and SSS may be used by UEs for cell search and acquisition. The PSS may provide half-frame timing, the SS may provide the CP length and frame timing. The PSS and SSS may provide the cell identity. The PBCH carries some basic system information, such as downlink system bandwidth, timing information within radio frame, SS burst set periodicity, system frame number, etc. The SS blocks may be organized into SS bursts to support beam sweeping. Further system information such as, remaining minimum system information (RMSI) , system information blocks (SIBs) , other system information (OSI) can be transmitted on a physical downlink shared channel (PDSCH) in certain subframes.

In some circumstances, two or more subordinate entities (e.g., UEs) may communicate with each other using sidelink signals. Real-world applications of such sidelink communications may include public safety, proximity services, UE-to-network relaying, vehicle-to-vehicle (V2V) communications, Internet of Everything (IoE) communications, IoT communications, mission-critical mesh, and/or various other suitable applications. Generally, a sidelink signal may refer to a signal communicated from one subordinate entity (e.g., UE1) to another subordinate entity (e.g., UE2) without relaying that communication through the scheduling entity (e.g., UE or BS) , even though the scheduling entity may be utilized for scheduling and/or control purposes. In some examples, the sidelink signals may be communicated using a licensed spectrum (unlike wireless local area networks, which typically use an unlicensed spectrum) .

A UE may operate in various radio resource configurations, including a configuration associated with transmitting pilots using a dedicated set of resources (e.g., a radio resource control (RRC) dedicated state, etc. ) or a configuration associated with transmitting pilots using a common set of resources (e.g., an RRC common state, etc. ) . When operating in the RRC dedicated state, the UE may select a dedicated set of resources for transmitting a pilot signal to a network. When operating in the RRC common state, the UE may select a common set of resources for transmitting a pilot signal to the network. In either case, a pilot signal transmitted by the UE may be received by one or more network access devices, such as an AN, or a DU, or portions thereof. Each receiving network access device may be configured to receive and measure pilot signals transmitted on the common set of resources, and also receive and measure pilot signals transmitted on dedicated sets of resources allocated to the UEs for which the network access device is a member of a monitoring set of network access devices for the UE. One or more of the receiving network access devices, or a CU to which receiving network access device (s) transmit the measurements of the pilot signals, may use the measurements to identify serving cells for the UEs, or to initiate a change of serving cell for one or more of the UEs.

Example Error Correction Coding

Many communications systems use error-correcting codes. Specifically, error-correcting codes compensate for the intrinsic unreliability of information transfer in these systems by introducing redundancy into the data stream. Low-density parity check (LDPC) codes are a particular type of error correcting codes which use an iterative coding system. In particular, Gallager codes are an early example of regular LDPC codes. LDPC codes are linear block codes in which most of the elements of its parity check matrix H are set to ‘0’ .

LDPC codes can be represented by bipartite graphs (often referred to as “Tanner graphs” ) , wherein a set of variable nodes corresponds to bits of a code word (e.g., information bits or systematic bits) , and a set of check nodes correspond to a set of parity-check constraints that define the code. Edges in the graph connect variable nodes to check nodes. Thus, the nodes of the graph are separated into two distinctive sets, variable nodes and check nodes, with edges connecting the two different types of nodes.

A lifted graph is created by copying a bipartite base graph (G) , which may also be known as a protograph, a number of times, Z. A variable node and a check node may be considered “neighbors” if they are connected by an “edge” (i.e., the line connecting the variable node and the check node) in the graph. In addition, for each edge (e) of the bipartite base graph (G) , a permutation is applied to the Z copies of edge (e) to interconnect the Z copies of G. A bit sequence having a one-to-one association with the variable node sequence is a valid codeword if, and only if, for each check node, the bits associated with all neighboring variable nodes sum to zero modulo two (i.e., they include an even number of 1’s) . The resulting LDPC code may be quasi-cyclic (QC) if the permutations used are cyclic.

FIGs. 7-7A show graphical and matrix representations of an exemplary LDPC code, in accordance with certain aspects of the present disclosure. For example, FIG. 7 shows a bipartite graph 700 representing an exemplary LDPC code. The bipartite graph 700 includes a set of 5 variable nodes 710 (represented by circles) connected to 4 check nodes 720 (represented by squares) . Edges in the graph 700 connect variable nodes 710 to the check nodes 720 (represented by the lines connecting the variable nodes 710 to the check nodes 720) . This graph consists of |V | = 5 variable nodes and |C| = 4 check nodes, connected by |E| = 12 edges.

The bipartite graph may be represented by a simplified adjacency matrix, which may also be known as a parity check matrix. FIG. 7A shows a matrix representation 700A of the bipartite graph 700. The matrix representation 700A includes a parity check matrix H and a code word vector x, where x1-x5 represent bits of the code word x. The parity matrix H is used for determining whether a received signal was normally decoded. The parity check matrix H has C rows corresponding to j check nodes and V columns corresponding to i variable nodes (i.e., a demodulated symbol) , where the rows represent the equations and the columns represents the bits of the code word. In FIG. 7A, matrix H has 4 rows and 5 columns corresponding to 4 check nodes and 5 variable nodes respectfully. If a j-th check node is connected to an i-th variable node by an edge, i.e., the two nodes are neighbors, then there is a 1 in the i-th column and in the j-th row of the parity check matrix H. That is, the intersection of an i-th row and a j-th column contains a "1" where an edge joins the corresponding vertices and a "0" where there is no edge. The code word vector x represents a valid code word if, and only if, Hx = 0 (e.g., if, for each constraint node, the bits neighboring the constraint (via their association with variable nodes) sum to zero modulo two, i.e., they comprise an even number of ones) . Thus, if the code word is received correctly, then Hx = 0 (mod 2) . When the product of a coded received signal and the parity check matrix H becomes ‘0’ , this signifies that no error has occurred. The parity check matrix is a C row by V column binary matrix. The rows represent the equations and the columns represent the digits in the code word.

The number of demodulated symbols or variable nodes is the LDPC code length. The number of non-zero elements in a row (column) is defined as the row (column) weight dc (dv) .

The degree of a node refers to the number of edges connected to that node. This feature is illustrated in the H matrix shown in FIG. 7A where the number of edges incident to a variable node 710 is equal to the number of 1’s in the corresponding column and is called the variable node degree d (v) . Similarly, the number of edges connected with a check node 720 is equal to the number of ones in a corresponding row and is called the check node degree d (c) .

A regular graph or code is one for which all variable nodes have the same degree, j, and all constraint nodes have the same degree, k. In this case, we say that the code is a (j, k) regular code. On the other hand, an irregular code has constraint nodes and/or variable nodes of differing degrees. For example, some variable nodes may be of degree 4, others of degree 3 and still others of degree 2.

“Lifting” enables LDPC codes to be implemented using parallel encoding and/or decoding implementations while also reducing the complexity typically associated with large LDPC codes. Lifting helps enable efficient parallelization of LDPC decoders while still having a relatively compact description. More specifically, lifting is a technique for generating a relatively large LDPC code from multiple copies of a smaller base code. For example, a lifted LDPC code may be generated by producing Z number of parallel copies of a base graph (e.g., protograph) and then interconnecting the parallel copies through permutations of edge bundles of each copy of the base graph. The base graph defines the (macro) structure of the code and consists of a number (K) of information bit-columns and a number (N) of code bit columns. Lifting the base graph a number (Z) of results in a final block length of KZ.

Thus, a larger graph can be obtained by a “copy and permute” operation where multiple copies of the base graph are made and connected to form a single lifted graph. For the multiple copies, like edges that are a set of copies of a single base edge, are permutated and connected to form a connected graph Z times larger than the base graph.

FIG. 8 graphically illustrates the effect of making three copies 800 of the graph of FIG. 7. Three copies may be interconnected by permuting like edges among the copies. If the permutations are restricted to cyclic permutations, then the resulting graph corresponds to a quasi-cyclic LDPC with lifting Z = 3. The original graph from which three copies were made is referred to herein as the base graph. To obtain derived graphs of different sizes, we can apply the “copy and permute” operation to a base graph.

A corresponding parity check matrix of the lifted graph can be constructed from the parity check matrix of the base graph by replacing each entry in the base parity check matrix with a ZxZ matrix. The 0 entries (those having no base edges) are replaced with the 0 matrix and the 1 entries (indicating a base edge) are replaced with a ZxZ permutation matrix. In the case of cyclic liftings the permutations are cyclic permutations.

A cyclically lifted LDPC code can also be interpreted as a code over the ring of binary polynomials modulo x ^Z+1. In this interpretation, a binary polynomial, (x)= b ₀+ b ₁ x + b ₂ x ² + ... + b _Z-1 x ^Z-1 may be associated to each variable node in the base graph. The binary vector (b ₀, b ₁ , b ₂ , ..., b _Z-1 ) corresponds to the bits associated to Z corresponding variable nodes in the lifted graph, that is, Z copies of a single base variable node. A cyclic permutation by k of the binary vector is achieved by multiplying the corresponding binary polynomial by x ^k where multiplication is taken modulo x ^Z+1. A degree d parity check in the base graph can be interpreted as a linear constraint on the neighboring binary polynomials B ₁ (x) , ..., B _d (x) written as

where the values, k ₁, ..., k _d are the cyclic lifting values associated to the corresponding edges.

This resulting equation is equivalent to the Z parity checks in the cyclically lifted Tanner graph corresponding to the single associated parity check in the base graph. Thus, the parity check matrix for the lifted graph can be expressed using the matrix for the base graph in which 1 entries are replaced with monomials of the form x ^k and 0 entries are lifted as 0, but now the 0 is interpreted as the 0 binary polynomial modulo x ^Z+1. Such a matrix may be written by giving the value k in place of x ^k. In this case the 0 polynomial is sometimes represented as -1 and sometimes as another character in order to distinguish it from x ⁰.

Typically, a square submatrix of the parity check matrix represents the parity bits of the code. The complementary columns correspond to information bits that, at the time of encoding, are set equal to the information bits to be encoded. The encoding may be achieved by solving for the variables in the aforementioned square submatrix in order to satisfy the parity check equations. The parity check matrix H may be partitioned into two parts M and N where M is the square portion. Thus, encoding reduces to solving Mc = s = Nd where c and d comprise x. In the case of quasi-cyclic codes, or cyclically lifted codes, the above algebra can be interpreted as being over the ring of binary polynomials modulo x ^Z+1. In the case of the 802.11 LDPC codes, which are quasi-cyclic, the encoding submatrix M has an integer representation 900 as shown in FIG. 9.

A received LDPC code word can be decoded to produce a reconstructed version of the original code word. In the absence of errors, or in the case of correctable errors, decoding can be used to recover the original data unit that was encoded. Redundant bits may be used by decoders to detect and correct bit errors. LDPC decoder (s) generally operate by iteratively performing local calculations and passing those results by exchanging messages within the bipartite graph 700, along the edges, and updating these messages by performing computations at the nodes based on the incoming messages. These steps may typically be repeated several times and may be referred to as message passing steps. For example, each variable node 710 in the graph 700 may initially be provided with a “soft bit” (e.g., representing the received bit of the code word) that indicates an estimate of the associated bit’s value as determined by observations from the communications channel. Using these soft bits the LDPC decoders may update messages by iteratively reading them, or some portion thereof, from memory and writing an updated message, or some portion thereof, back to, memory. The update operations are typically based on the parity check constraints of the corresponding LDPC code. In implementations for lifted LDPC codes, messages on like edges are often processed in parallel.

LDPC codes designed for high speed applications often use quasi-cyclic constructions with large lifting factors and relatively small base graphs to support high parallelism in encoding and decoding operations. LDPC codes with higher code rates (e.g., the ratio of the message length to the code word length) tend to have relatively fewer parity checks. If the number of base parity checks is smaller than the degree of a variable node (e.g., the number of edges connected to a variable node) , then, in the base graph, that variable node is connected to at least one of the base parity checks by two or more edges (e.g., the variable node may have a “double edge” ) . Or if the number of base parity checks is smaller than the degree of a variable node (e.g., the number of edges connected to a variable node) , then, in the base graph, that variable node is connected to at least one of the base parity checks by two or more edges. Having a base variable node and a base check node connected by two or more edges is generally undesirable for parallel hardware implementation purposes. For example, such double edges may result in multiple concurrent read and write operations to the same memory locations, which in turn may create data coherency problems. A double edge in a base LDPC code may trigger parallel reading of the same soft bit value memory location twice during a single parallel parity check update. Thus, additional circuitry is typically needed to combine the soft bit values that are written back to memory, so as to properly incorporate both updates. However, eliminating double edges in the LDPC code helps to avoid this extra complexity

LDPC code designs based on cyclic lifting can be interpreted as codes over the ring of polynomials modulo may be binary polynomials modulo x ^Z+1, where Z is the lifting size (e.g., the size of the cycle in the quasi-cyclic code) . Thus encoding such codes can often be interpreted as an algebraic operation in this ring.

In the definition of standard irregular LDPC code ensembles (degree distributions) all edges in the Tanner graph representation may be statistically interchangeable. In other words, there exists a single statistical equivalence class of edges. A more detailed discussion of lifted LDPC codes may be found, for example, in the book titled, "Modern Coding Theory, " published Mar. 17, 2008, by Tom Richardson and Ruediger Urbanke.

For multi-edge LDPC codes, multiple equivalence classes of edges may be possible. While in the standard irregular LDPC ensemble definition, nodes in the graph (both variable and constraint) are specified by their degree, i.e., the number of edges they are connected to, in the multi-edge type setting an edge degree is a vector; it specifies the number of edges connected to the node from each edge equivalence class (type) independently. A multi-edge type ensemble is comprised of a finite number of edge types. The degree type of a constraint node is a vector of (non-negative) integers; the i-th entry of this vector records the number of sockets of the i-th type connected to such a node. This vector may be referred to as an edge degree. The degree type of a variable node has two parts although it can be viewed as a vector of (non-negative) integers. The first part relates to the received distribution and will be termed the received degree and the second part specifies the edge degree. The edge degree plays the same role as for constraint nodes. Edges are typed as they pair sockets of the same type. This constraint –that sockets must pair with sockets of like type –characterizes the multi-edge type concept. In a multi-edge type description, different node types can have different received distributions (e.g., the associated bits may go through different channels) .

FIG. 10 illustrates an example of multi-edge type (MET-) LDPC codes, according to certain aspects presented herein. A MET-LDPC code is defined on a graph constructed by applying “copy-and-permutation” operations on a predefined based code, or equivalently base graph. As illustrated, a base code 1000 may have multiple edge types, such as 1002, 1004, 1006, and 1008. Further, multiple copies of the base code 1000 may be made and edges of the same type grouped, as shown at 1020. Additionally, edges of a same type, which corresponding to the same edge in the base graph, may be permuted (e.g., connected to different check nodes) as shown at 1030, and the resulting larger graph (compared to base graph) defines the target LDPC code. This graph representation can be translated into matrix operations: a parity-check matrix representation of the base code and edge types may be seen at 1040. Then, at 1050, non-zero entries in the parity-check matrix of the base code may be replaced with identities matrices or its permutation matrices. According to aspects, the matrix at 1050 is the parity-check matrix of the target LDPC code.

FIG. 11 illustrates a portion of a radio frequency (RF) modem 1114 that may be configured to provide an encoded message for wireless transmission. In one example, an encoder 1106 in a base station (e.g., Node B 102 and/or transmitter system 210) (or wireless node on the reverse path) receives a message 1102 for transmission. The message 1102 may contain data and/or encoded voice or other content directed to the receiving device. The encoder 1106 encodes the message using a suitable modulation and coding scheme (MCS) , typically selected based on a configuration defined by the base station or another network entity. In some cases, the encoder 1106 may encode the message, for example, using techniques described above (e.g., by using a LDPC code) . An encoded bitstream 1108 produced by the encoder 1106 may then be provided to a mapper 1110 that generates a sequence of Tx symbols 1112 that are modulated, amplified and otherwise processed by Tx chain 1114 to produce an RF signal 1116 for transmission through antenna 1118.

FIG. 12 illustrates a portion of a RF modem that may be configured to receive and decode a wirelessly transmitted signal including an encoded message (e.g., a message encoded using a LDPC code as described above) . In various examples, the RF modem receiving the signal may reside at the wireless node (e.g., user equipment 120) , at the base station (e.g., Node B 110) , or at any other suitable apparatus or means for carrying out the described functions (e.g., wireless device 302) . An antenna 1202 receives an RF signal 1116 (i.e., the RF signal 1116 produced in FIG. 11) for a wireless node (e.g., user equipment 120) . An RF chain 1204 processes and demodulates the RF signal 1116 and may provide a sequence of demodulated symbols 1206 to a demapper 1208, which produces a bitstream 1210 representative of the encoded message.

A decoder 1212 may then be used to decode m-bit information strings from a bitstream that has been encoded using a coding scheme (e.g., an LDPC code) . The decoder 1212 may comprise a layered LDPC decoder with a full-parallel, row-parallel, or block-parallel architecture. LDPC decoder (s) generally operate by iteratively performing local calculations and passing those results by exchanging messages within the bipartite graph 700, along the edges, and updating these messages by performing computations at the nodes based on the incoming messages. These steps may typically be repeated several times and may be referred to as message passing steps. For example, each variable node 710 in the graph 700 may initially be provided with a “soft bit” (e.g., representing the received bit of the code word) that indicates an estimate of the associated bit’s value as determined by observations from the communications channel. The “soft bit” may be represented by a log-likelihood ratio (LLR) that in some aspects may be defined as the log ( (probability the bit is 0) / (probability the bit is 1) ) . Using these LLRs the LDPC decoders may update messages by iteratively reading them, or some portion thereof, from memory and writing an updated message, or some portion thereof, back to, memory. The update operations are typically based on the parity check constraints of the corresponding LDPC code. In implementations for lifted LDPC codes, messages on like edges are often processed in parallel. According to aspects, following these decoding techniques, the decoder 1212 may decode the bitstream 1210 based on the LLRs to determine the message 1102 containing data and/or encoded voice or other content transmitted from the base station (e.g., Node B 110) . The decoder may decode the bitsteam 1210 in accordance with aspects of the present disclosure presented below (e.g., by implementing operations 1300 illustrated in FIG. 13) .

Example Improved Iterative Decoder For LDPC Codes With Weights and Biases

As noted above, Low-density parity check (LDPC) codes are a particular type of error correcting codes which use an iterative coding system. LDPC codes can be represented by bipartite graphs (often referred to as “Tanner graphs” ) , wherein a set of variable nodes corresponds to bits of a code word (e.g., information bits or systematic bits) , and a set of check nodes correspond to a set of parity-check constraints that define the code. Edges in the graph connect variable nodes to check nodes. Thus, the nodes of the graph are separated into two distinctive sets, variable nodes and check nodes, with edges connecting the two different types of nodes.

LDPC decoder (s) generally operate by iteratively performing local calculations and passing those results by exchanging messages within the bipartite graph, along the edges, and updating these messages by performing computations at the nodes based on the incoming messages. These steps may typically be repeated several times and may be referred to as message passing steps. For example, each variable node in the bipartite graph may initially be provided with a “soft bit” (e.g., representing the received bit of the code word) that indicates an estimate of the associated bit’s value as determined by observations from the communications channel. Using these soft bits the LDPC decoders may update messages by iteratively reading them, or some portion thereof, from memory and writing an updated message, or some portion thereof, back to, memory. The update operations are typically based on the parity check constraints of the corresponding LDPC code. In implementations for lifted LDPC codes, messages on like edges are often processed in parallel.

According to aspects, a first type message passing algorithm, as described above, is known as a Sum-Product algorithm. The Sum-Product algorithm is summarized in

equations

1 and 2 for the ‘i ^th’ iteration, below. In each iteration of equations 1 and 2 (indexed by i) , every variable node, v, updates messages and sends them to one of its adjacent check nodes, c, by summing up the channel input message and the message from all its adjacent check nodes besides CN, c, as shown in equation 1. Then, every check node, c, updates the messages and sends them to its adjacent variable node, v, by combining the messages from all its adjacent variable nodes besides VN, v, as shown in equation 3. Additionally, equation 3 illustrates the output LLR for a hard decision after i-th iteration.

Msg from VN to CN: LLR _i, v2c=LLR _in, v+∑ _c′≠cLLR _i-1, c′2v (eq. 1)

Hard Decision: LLR _out, v=LLR _in, v+∑ _cLLR _i-1, c2v (eq. 3)

According to aspects, LLR _in, v in equation 1 are the received soft bits from the channel and LLR _i-1, c′2v may be initialized to zeros when i=1. According to aspects, one drawback with the Sum-Product message passing algorithm desribed above is that computing tanh/tanh ^-1 is not easy (e.g., in terms of decoding complexity and power usage) for a hardware decoder.

Another type of message passing algorithm is known as the Minimum-Sum (Min-Sum) algorithm. The Min-Sum algorithm is summarized in

equations

4 and 5 for the ‘i ^th’ iteration, below. Additionally, equation 6 illustrates the output LLR for a hard decision.

Msg from VN to CN: LLR _i, v2c=LLR _in, v+∑ _c′≠cLLR _i-1, c′2v (eq. 4)

Msg from CN to VN: LLR _i, c2v=sign (∏ _v′≠vLLR _i. v′2c) ·min _v′≠v (|LLR _i, v′2c|) (eq. 5)

Hard Decision: LLR _out, v=LLR _in, v+∑ _cLLR _i-1, c2v (eq. 6)

Compared to Sum-Product algorithm, Min-Sum algorithm makes an approximation when updating messages from check node to variable node, which is easier to compute, as shown in equation 5.

As illustrated, the Min-Sum algorithm reduces the complexity of the decoding process as the decoder no longer has to evaluate the tanh/tanh ^-1 function line the Sum-Product algorithm. Instead, the Min-Sum algorithm approximates the Sum-Product algorithm using the ‘sign’ and ‘min’ functions.

However, the approximating the Sum-Product algorithm by using the Min-Sum algorithm suffers from performance deterioration. To address this performance deterioration, weights or offsets have, in some cases, been added to the CN-to-VN equation of the Min-Sum algorithm to better approximate the Sum-Product algorithm. For example, Equation 7, below, illustrates an example of a normalized Min-Sum algorithm (e.g., the CN-to-VN equation) that adds a weight, ‘w’ , to help better approximate the Sum-Product algorithm. Additionally, Equation 8, below, illustrates an example of an offset Min-Sum algorithm (e.g., the CN-to-VN equation) that adds a bias, ‘b’ , to help better approximate the Sum-Product algorithm.

Msg CN to VN: LLR _i, c2v=w·sign (∏ _v′≠vLLR _i. v′2c) ·min _v′≠v (|LLR _i, v′2c|) (eq. 7)

Msg CNtoVN: LLR _i, c2v=sign (∏ _v′≠vLLR _i. v′2c) ·max (0, min _v′≠v (LLR _i, v′2c) -b)

(eq. 8)

In some cases, ‘w’ and ‘b’ may take a fixed value, which may be optimized offline. Additionally, in some cases, the weight and bias may not be limited to just one value but a small set of values. In such a case, the decoder may pick one value from the set of values according to the node degree or the amplitude of the message. However, the existing algorithms, such as the normalized Min-Sum equation and the offset Min-Sum, are still limited in their Sum-Product approximation as either only weights or only biases (i.e., not both) are added to the CN-to-VN equation. Additionally, the existing algorithms typically only share one value or a set of values for every connection in the tanner graph and the same weights/biases are used for different iterations of the algorithm.

Thus, aspects of the present disclosure propose techniques to help better approximate the Sum-Product algorithm and help resolve the issues with existing Min-Sum algorithms. For example, in some cases, techniques may involve adding both weights and biases to every connection from CNs to VNs in a tanner graph and varying the weights/biases in different iterations of the decoding process.

FIG. 13 illustrates example operations 1300 for wireless communication in a wireless network. In some cases, operations 1300 may be used to perform decoding of LDPC code words, for example, by applying at least one of weights or biases to every connection in a tanner graph. In some cases, operations 1300 may be performed by a wireless communications device, such as a base station 110 or a user equipment 120.

Operations 1300 begin at 1302 by receiving a low-density parity-check (LDPC) -encoded codeword. At 1304, the wireless communications device decodes the codeword using a tanner base graph comprising a plurality of check nodes and a plurality of variable nodes, wherein decoding the codeword using the tanner graph comprises variably applying at least one of weights or biases to each check-node-to-variable-node connection and variable-node-to-check-node connection in the tanner graph.

As noted above, aspects of the present disclosure propose techniques for an improved iterative decoder for LDPC codes with weights and biases. For example, in some cases, aspects of the present disclosure propose a message passing algorithm that variably applies different weights and/or biases to every connection from check nodes (CNs) to variable nodes (VNs) in the tanner graph used to decode an LDPC codeword. It should be noted that similar techniques may also be performed with respect to every connection from VNs to CNs. Further, aspects of the present disclosure propose to variably applying different weights/biases to different iterations of the message passing algorithm. This message passing algorithm is illustrated below in Equations 9-11.

Msg from VN to CN: LLR _i, v2c=LLR _in, v+∑ _c′≠cLLR _i-1, c′2v (eq. 9)

Msg CNtoVN: LLR _i, c2v=

sign (∏ _v′≠vLLR _i. v′2c) ·max (0, w _i, c2v·min _v′≠v (LLR _i, v′2c) -b _i, c2v) (eq. 10)

Hard Decision: LLR _out, v=LLR _in, v+∑ _cLLR _i-1, c2v (eq. 11)

As illustrated in Equation 10, aspects of the present disclosure propose adding both a weight and bias to the CN-to-VN message passing equation. In some cases, an array of different weights and different biases may be stored in memory and selected by the wireless communications device when decoding an LDPC codeword. According to aspects the size of the array of weights and biases may be E*L, where E is the number of edges in the tanner graph and L is the iteration number of the decoding process/algorithm. According to certain aspects, each possible configuration of LDPC codes may correspond to a different weight/bias array.

In some cases, the wireless communications device may switch between different weight/bias modes when performing decoding of an LDPC codeword. For example, for different iterations of the decoding process, the wireless communications device may switch between a “weight + bias” mode (in which both a weight and bias are applied to every connection in the tanner graph, a “weight-only” mode (in which only a weight is applied to the connections in the tanner graph) , a “bias-only” mode (in which only a bias is applied to the connections in the tanner graph) , or a “no weight/bias” mode (in which neither weights or biases are applied to any of the connections in the tanner graph) .

For example, in some cases, the wireless communications device can perform decoding in the “weight-only” mode and apply only weights to each check-node-to-variable-node connection in the tanner graph for a first five iterations (e.g., a first plurality of iterations) of the decoding process. According to aspects, using the “weight-only” mode allows the decoding process to converge faster.

Thereafter, the wireless communications device may continue decoding using the “weight + bias” mode and applying both weights and biases to each check-node-to-variable-node connection in the tanner graph for iterations 6-20 (e.g., a second plurality of iterations) of the decoding process. According to aspects, the “weight + bias” mode provides a between tradeoff between convergence speed and performance.

Thereafter, the wireless communications device may continue decoding using the “bias-only” mode and applying only biases to each check-node-to-variable-node connection in the tanner graph for iterations 21-50 (e.g., a third plurality of iterations) of the decoding process. The “bias-only” mode provides better convergence performance and is less complex to compute.

Thereafter, the wireless communications device may use the “no weight/bias” mode and apply no weights and no biases to any check-node-to-variable-node connection in the tanner graph to iterations after the 50 ^th iteration (e.g., a fourth plurality of iterations) of the decoding process. According to aspects, the “no weight/bias” mode provides the least computation complexity.

According to aspects, the wireless communications device may make the selection of which mode to use based on a tradeoff between complexity and performance. Further, it should be noted that each of the modes described above may be considered as a special case of the proposed algorithm in Equations 9-11. For example, for the “weight-only” mode, the wireless communications device may set the bias, ‘b’ , to zero in Equation 10. For the “bias-only” mode, the wireless communications device may set the weight, ‘w’ , to one in Equation 10.

According to aspects, for multi-edge type (MET) -LDPC codes, the wireless communications device may select and share weights and/or biases among edges of a same-edge type. For example, referring back to FIG. 10, the wireless communications device may select a first weight (e.g., from the weight/bias array described above) and apply the weight to each check-node-to-variable-node of a first type (e.g., 1002) . The wireless communications device may also select a second bias (e.g., from the weight/bias array described above) and apply the weight to each check-node-to-variable-node of a second type (e.g., 1004) . According to aspects, since edges (i.e., connections) in the tanner graph can share weights and/or biases, the size of the array may be reduced to Eb*L, where Eb is the edge number in the base code tanner graph.

According to aspects, the weight/bias array pair may then be shared among all the code generated from the same base code. Thus, to decode a LDPC codeword for an eMBB case, only two pairs of weight/bias arrays are required, one for base graph one (BG1) and one for base graph two (BG2) .

Aspects of the present disclosure also propose techniques by which the wireless communications device may learn the best weight and/or bias to apply to each check-node-to-variable-node connection in the tanner graph. For example, in some cases, the wireless communications device may employ a machine learning algorithm to determine the best weights and/or biases to apply.

FIG. 14 illustrates an example machine learning/neural network diagram for learning which weights and/or biases to apply to which check-node-to-variable-node connection in the tanner graph during decoding, according to aspects of the present disclosure. Firstly, the convention belief propagation decoder (Sum-Product algorithm or Min-Sum algorithm) is transformed into neural network by attaching weights/biases to at least some edges of the variable-check node or check-variable node connection. Training samples (noised codewords) are generated by feeding corresponding LDPC encoder with random bits and corrupted by a certain level of noise. The samples are processed by the neural network, and the output is compared with the transmitted codewords, wherein the difference is evaluated by the loss function which is usually cross entropy. The parameters, weights/biases of the neural network are updated, targeting a minimization of the loss function output.

FIG. 15 illustrates a complexity comparison between message passing algorithms described in the present disclosure. For example, FIG. 15 illustrates the number of operations for every iteration of the decoding process, where E is the number of edges in the Tanner graph (i.e., the number of bit-1s in parity-check matrix) . According to aspects, the complexity of Min-Sum Neural Network (MSNN) (e.g., Equations 9-11) is similar to min-sum decoding algorithm (e.g., Equations 4-6) , and hardware friendly compared to sum-product decoding algorithm (e.g., Equations 1-3) .

According to aspects of the present disclosure, the techniques presented herein provide several advantages over the existing decoding algorithms. For example, techniques provided herein (e.g., Equations 9-11) result in performance that even better than sum-product under limited iteration number. More specifically, the techniques provided herein provide better approximation towards sum-production algorithm and mitigate the impact from the cycles of finite-length LDPC. Additionally, the techniques provided herein provide significantly better performance than Min-Sum decoding algorithm, even better than sum-product when high signal-to-noise ratio (SNR) .

Additionally, the decoding algorithm provided herein (e.g., Equations 9-11) decreases decoding complexity (e.g., no tanh/atanh computation, very similar to min-sum) and is hardware-friendly and, thus, conserves power resources at the wireless communications device. Further, parameters (e.g., weights and/or biases) can be optimized for base code of MET code and shared among all its expanded codes. Moreover, techniques presented herein are robust to a rate-matching algorithm. For example, the weight/bias array for a mother code still works well after rate-matching. Additionally, techniques provide a flexible mode transition strategy that allows the wireless communications device play the tradeoff between complexity and performance. Further, techniques presented herein can be easily translated into neural network structure, and trained by machine learning algorithm. Additionally, the neural network/machine learning algorithm may be used to optimize the parameter when it is traditionally difficult to analyze. (e.g., with existence of quantization noise) . For instance, nearly all practical systems apply fixed-point implementation of algorithm designed under float-point assumption. The errors introduced by rounding the numbers is known as quantization noise. Unfortunately, this kind of error is non-linear and dependent on the specific quantization scheme, and different algorithm, or different stages of the algorithm, has different sensitivity to quantization noise. Therefore, it is very hard to analyze even by an experienced expert.

FIG. 16 illustrates a communications device 1600 that may include various components (e.g., corresponding to means-plus-function components) configured to perform operations for the techniques disclosed herein, such as the operations illustrated in FIG. 13. The communications device 1600 includes a processing system 1602 coupled to a transceiver 1608. The transceiver 1608 is configured to transmit and receive signals for the communications device 1600 via an antenna 1610, such as the various signal described herein. The processing system 1602 may be configured to perform processing functions for the communications device 1600, including processing signals received and/or to be transmitted by the communications device 1600.

The processing system 1602 includes a processor 1604 coupled to a computer-readable medium/memory 1612 via a bus 1606. In certain aspects, the computer-readable medium/memory 1612 is configured to store instructions that when executed by processor 1604, cause the processor 1604 to perform the operations illustrated in FIG. 13, or other operations for performing the various techniques discussed herein.

In certain aspects, the processing system 1602 further includes a receiver component 1614 for performing the operations illustrated at 1302 of FIG. 13. Additionally, the processing system 1602 includes a decoder component 1616 for performing the operations illustrated at 1304 in FIG. 13. The receiver component 1614 and the decoder component 1616 may be coupled to the processor 1604 via bus 1606. In certain aspects, the receiver component 1614 and the decoder component 1616 may be hardware circuits. In certain aspects, the receiver component 1614 and the decoder component 1616 may be software components that are executed and run on processor 1604.

The methods disclosed herein comprise one or more steps or actions for achieving the methods. The method steps and/or actions may be interchanged with one another without departing from the scope of the claims. In other words, unless a specific order of steps or actions is specified, the order and/or use of specific steps and/or actions may be modified without departing from the scope of the claims.

As used herein, a phrase referring to “at least one of” a list of items refers to any combination of those items, including single members. As an example, “at least one of: a, b, or c” is intended to cover a, b, c, a-b, a-c, b-c, and a-b-c, as well as any combination with multiples of the same element (e.g., a-a, a-a-a, a-a-b, a-a-c, a-b-b, a-c-c, b-b, b-b-b, b-b-c, c-c, and c-c-c or any other ordering of a, b, and c) .

As used herein, the term “determining” encompasses a wide variety of actions. For example, “determining” may include calculating, computing, processing, deriving, investigating, looking up (e.g., looking up in a table, a database or another data structure) , ascertaining and the like. Also, “determining” may include receiving (e.g., receiving information) , accessing (e.g., accessing data in a memory) and the like. Also, “determining” may include resolving, selecting, choosing, establishing and the like.

The previous description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects. Thus, the claims are not intended to be limited to the aspects shown herein, but is to be accorded the full scope consistent with the language of the claims, wherein reference to an element in the singular is not intended to mean “one and only one” unless specifically so stated, but rather “one or more. ” Unless specifically stated otherwise, the term “some” refers to one or more. All structural and functional equivalents to the elements of the various aspects described throughout this disclosure that are known or later come to be known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be encompassed by the claims. Moreover, nothing disclosed herein is intended to be dedicated to the public regardless of whether such disclosure is explicitly recited in the claims. No claim element is to be construed under the provisions of 35 U.S.C. §112 (f) unless the element is expressly recited using the phrase “means for” or, in the case of a method claim, the element is recited using the phrase “step for. ”

The various operations of methods described above may be performed by any suitable means capable of performing the corresponding functions. The means may include various hardware and/or software component (s) and/or module (s) , including, but not limited to a circuit, an application specific integrated circuit (ASIC) , or processor. Generally, where there are operations illustrated in figures, those operations may have corresponding counterpart means-plus-function components with similar numbering.

The various illustrative logical blocks, modules and circuits described in connection with the present disclosure may be implemented or performed with a general purpose processor, a digital signal processor (DSP) , an application specific integrated circuit (ASIC) , a field programmable gate array (FPGA) or other programmable logic device (PLD) , discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but in the alternative, the processor may be any commercially available processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

If implemented in hardware, an example hardware configuration may comprise a processing system in a wireless node. The processing system may be implemented with a bus architecture. The bus may include any number of interconnecting buses and bridges depending on the specific application of the processing system and the overall design constraints. The bus may link together various circuits including a processor, machine-readable media, and a bus interface. The bus interface may be used to connect a network adapter, among other things, to the processing system via the bus. The network adapter may be used to implement the signal processing functions of the PHY layer. In the case of a user terminal 120 (see FIG. 1) , a user interface (e.g., keypad, display, mouse, joystick, etc. ) may also be connected to the bus. The bus may also link various other circuits such as timing sources, peripherals, voltage regulators, power management circuits, and the like, which are well known in the art, and therefore, will not be described any further. The processor may be implemented with one or more general-purpose and/or special-purpose processors. Examples include microprocessors, microcontrollers, DSP processors, and other circuitry that can execute software. Those skilled in the art will recognize how best to implement the described functionality for the processing system depending on the particular application and the overall design constraints imposed on the overall system.

If implemented in software, the functions may be stored or transmitted over as one or more instructions or code on a computer readable medium. Software shall be construed broadly to mean instructions, data, or any combination thereof, whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. Computer-readable media include both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. The processor may be responsible for managing the bus and general processing, including the execution of software modules stored on the machine-readable storage media. A computer-readable storage medium may be coupled to a processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. By way of example, the machine-readable media may include a transmission line, a carrier wave modulated by data, and/or a computer readable storage medium with instructions stored thereon separate from the wireless node, all of which may be accessed by the processor through the bus interface. Alternatively, or in addition, the machine-readable media, or any portion thereof, may be integrated into the processor, such as the case may be with cache and/or general register files. Examples of machine-readable storage media may include, by way of example, RAM (Random Access Memory) , flash memory, ROM (Read Only Memory) , PROM (Programmable Read-Only Memory) , EPROM (Erasable Programmable Read-Only Memory) , EEPROM (Electrically Erasable Programmable Read-Only Memory) , registers, magnetic disks, optical disks, hard drives, or any other suitable storage medium, or any combination thereof. The machine-readable media may be embodied in a computer-program product.

A software module may comprise a single instruction, or many instructions, and may be distributed over several different code segments, among different programs, and across multiple storage media. The computer-readable media may comprise a number of software modules. The software modules include instructions that, when executed by an apparatus such as a processor, cause the processing system to perform various functions. The software modules may include a transmission module and a receiving module. Each software module may reside in a single storage device or be distributed across multiple storage devices. By way of example, a software module may be loaded into RAM from a hard drive when a triggering event occurs. During execution of the software module, the processor may load some of the instructions into cache to increase access speed. One or more cache lines may then be loaded into a general register file for execution by the processor. When referring to the functionality of a software module below, it will be understood that such functionality is implemented by the processor when executing instructions from that software module.

Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) , or wireless technologies such as infrared (IR) , radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, include compact disc (CD) , laser disc, optical disc, digital versatile disc (DVD) , floppy disk, and

disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Thus, in some aspects computer-readable media may comprise non-transitory computer-readable media (e.g., tangible media) . In addition, for other aspects computer-readable media may comprise transitory computer-readable media (e.g., a signal) . Combinations of the above should also be included within the scope of computer-readable media.

Thus, certain aspects may comprise a computer program product for performing the operations presented herein. For example, such a computer program product may comprise a computer-readable medium having instructions stored (and/or encoded) thereon, the instructions being executable by one or more processors to perform the operations described herein. For example, instructions for performing the operations described herein and illustrated in FIG. 13.

Further, it should be appreciated that modules and/or other appropriate means for performing the methods and techniques described herein can be downloaded and/or otherwise obtained by a user terminal and/or base station as applicable. For example, such a device can be coupled to a server to facilitate the transfer of means for performing the methods described herein. Alternatively, various methods described herein can be provided via storage means (e.g., RAM, ROM, a physical storage medium such as a compact disc (CD) or floppy disk, etc. ) , such that a user terminal and/or base station can obtain the various methods upon coupling or providing the storage means to the device. Moreover, any other suitable technique for providing the methods and techniques described herein to a device can be utilized.

It is to be understood that the claims are not limited to the precise configuration and components illustrated above. Various modifications, changes and variations may be made in the arrangement, operation and details of the methods and apparatus described above without departing from the scope of the claims.

Claims

A method for wireless communication in a wireless network performed by a wireless communications device, comprising:

receiving a low-density parity-check (LDPC) -encoded codeword; and

decoding the codeword using a tanner base graph comprising a plurality of check nodes and a plurality of variable nodes, wherein decoding the codeword using the tanner graph comprises variably applying at least one of weights or biases to each check-node-to-variable-node connection and variable-node-to-check-node connection in the tanner graph.
The method of claim 1, further comprising:

varying values for the applied weights or biases for different iterations of the decoding.
The method of claim 1, further comprising:

varying between applying the at least one of weights or biases for different iterations of the decoding.
The method of claim 3, wherein varying between applying the at least one of weights or biases comprises one or more of:

applying only one or more weights to each check-node-to-variable-node connection in the tanner graph for a first plurality of iterations of the decoding;

applying one or more weights and one or more biases to each check-node-to-variable-node connection in the tanner graph for a second plurality of iterations of the decoding;

applying only one or more biases to each check-node-to-variable-node connection in the tanner graph for a third plurality of iterations of the decoding; or

applying no weights and no biases to each check-node-to-variable-node connection in the tanner graph for a fourth plurality of iterations of the decoding.
The method of claim 1, where applying at least one of weights or biases to each check-node-to-variable-node connection in the tanner graph, comprises:

applying a same weight or a same bias to check-node-to-variable-node connections of a same type.
The method of claim 1, further comprising:

training at least one of the applied weights or the applied bias using a machine learning algorithm.
The method of claim 1, wherein the training comprises using a fixed signal to noise ratio.
The method of claim 1, wherein the value of weights is larger than zero;
The method of claim 1, wherein when the sign of a message, passed from a check node to a variable node in the tanner graph, is inversed after applying a bias, the message is then set to zero.
The method of claim 1, wherein the weights and biases are stored in memory and be loaded by the wireless communications device when calculating a message along a corresponding connection from a check node to a variable node at a corresponding iteration.
An apparatus for wireless communication in a wireless network performed by a wireless communications device, comprising:

at least one processor configured to:

receive a low-density parity-check (LDPC) -encoded codeword; and

decode the codeword using a tanner base graph comprising a plurality of check nodes and a plurality of variable nodes, wherein decoding the codeword using the tanner graph comprises variably applying at least one of weights or biases to each check-node-to-variable-node connection and variable-node-to-check-node connection in the tanner graph; and

a memory coupled with the at least one processor.
An apparatus for wireless communication in a wireless network performed by a wireless communications device, comprising:

means for receiving a low-density parity-check (LDPC) -encoded codeword; and

means for decoding the codeword using a tanner base graph comprising a plurality of check nodes and a plurality of variable nodes, wherein decoding the codeword using the tanner graph comprises variably applying at least one of weights or biases to each check-node-to-variable-node connection and variable-node-to-check-node connection in the tanner graph.
A non-transitory computer-readable medium for wireless communication in a wireless network performed by a wireless communications device, comprising:

instructions that, when executed by at least one processor, configure the at least one processor to:

receive a low-density parity-check (LDPC) -encoded codeword; and

decode the codeword using a tanner base graph comprising a plurality of check nodes and a plurality of variable nodes, wherein decoding the codeword using the tanner graph comprises variably applying at least one of weights or biases to each check-node-to-variable-node connection and variable-node-to-check-node connection in the tanner graph.