WO2019211601A1

WO2019211601A1 - An analogue-digital hybrid computer

Info

Publication number: WO2019211601A1
Application number: PCT/GB2019/051201
Authority: WO
Inventors: David Summerland; Roger Light; Luke Knight
Original assignee: Search For The Next Ltd
Priority date: 2018-04-30
Filing date: 2019-04-30
Publication date: 2019-11-07
Also published as: EP3799646A1; GB201807069D0

Abstract

A hybrid analogue-digital computer comprising configurable analogue circuitry arranged to apply functions on analogue signals in the analogue domain received through an analogue input of the computer system and provide an analogue output that provides an analogue output of the computer system. The computer system includes an analogue accumulator arranged to accumulate output values from the configurable analogue circuitry, and a comparator that receives the output of the accumulator means, compares said output with a threshold value and outputs a one-bit flag signal based on said comparison. The flag signal is used by a digital controller of the computer system together with program flow information and configuration information to configure the configurable analogue circuitry. Through this arrangement the need to convert analogue values into the digital domain is avoided. This allows the digital circuitry to be significantly simplified. The invention is thought to be of particular use in embedded devices. One example is described in which the computer system is used to control a bipolar transistor in a high power circuit.

Description

An Analogue-Digital Hybrid Computer

The present invention relates to an analogue-digital hybrid computer.

Digital computers serially execute instructions on digital data in order to perform calculations. Analogue computers use analogue circuitry to perform calculations using analogue signals. Digital computers have the advantage of being extremely flexible and that carrying out calculations does not introduce noise into the signal. Analogue computers have the advantages that calculations can occur substantially instantaneously rather than needing a series of instructions to be executed, and have potentially much lower power consumption than an equivalent digital circuit. Significantly for systems where the input and output is of analogue nature, using an analogue computer means there is no need to convert the signal from analogue to digital and back again, saving both power, time and silicon space. A hybrid analogue- digital computer contains aspects of both digital and analogue computers.

A Programmable and Configurable Mixed-Mode FPAA SoC Suma George et al IEEE Transactions on (VLSI) Systems Vol. 24. No. 6 June 2016, p2253 describes a general purpose hybrid computer comprising an array of configurable analogue and digital sets; a microprocessor; a set of digital to analogue converters, which can be used to provide analogue values to the analogue sets from the micro processor; and an analogue to digital converter (ADC) that provides calculated values from the analogue sets to the microprocessor. The digital circuitry is arranged to configure the analogue circuitry depending on the analogue calculation to be made and the result of the calculation is fed back to digital circuitry via the ADC. The ADC needs to provide sufficient voltage resolution to adequately resolve the analogue signal. This adds to the complexity of the design. According to a first aspect of the invention there is provided a hybrid analogue-digital computer system comprising: analogue circuitry that includes: configurable analogue circuitry arranged to apply functions on an analogue input, an analogue accumulator means arranged to accumulate output values from the configurable analogue circuitry; and a comparator arranged to receive the output of the accumulator means, compare said output value with a threshold value and output a digital flag signal based on said comparison; digital circuitry that includes: a memory in which is stored program flow information and configuration information to configure the analogue circuitry, and a controller that uses the program flow information and configuration information in the memory and the digital flag signal from the comparator to control the program flow and/or to reconfigure the configurable analogue circuitry.

During operation, analogue input signals may pass continuously through the programmable analogue circuit (i.e. are not sampled and held) in order to provide a continuous analogue output signal at an output of the computer system. Functions applied in the analogue domain can be applied continuously to the analogue input signal meaning that changes in the value of the analogue input signal or the function applied will be reflected in the value of the analogue output more immediately compared with carrying out the functions digitally.

The configurable analogue circuitry may be arranged to receive and apply one or more functions to one or more analogue input signals from one or more analogue inputs of the computer system. Additionally or alternatively, the configurable analogue circuitry may be arranged to receive one or more analogue input signals that have been internally generated by the computer system.

The digital circuitry is adapted to be able to repeatedly reconfigure the configurable analogue circuitry in order to change the functions applied by the analogue circuitry on the analogue input signal.

Using the accumulator means to store analogue values of intermediate arithmetic steps from the configurable analogue circuitry means that manipulation of these values need not be carried out by the digital circuitry. This avoids the need to convert analogue values of the analogue calculations back into the digital domain and thus the need for a complex ADC that can adequately resolve the analogue values. It also means that the digital circuitry can be considerably simplified as all arithmetic functions can be carried out in the analogue domain. The reduced transistor count allowed by this enables a reduction in circuit density, cost and size of the hybrid computer system. The transmission of relatively simple flag signals from the analogue circuitry to the digital circuitry which, in contrast to the complex analogue output of the configurable analogue circuitry, can be single binary digit outputs, provides an input from the analogue circuitry to the digital circuitry which can be used to repeatedly reconfigure the analogue circuitry according to the program flow. As such the digital circuitry can be used to change the analogue processing being performed, and the analogue inputs used, from one program instruction to the next to, for example to, produce complicated analogue output waveforms. The digital flag signal may be used to change program flow or could be used to reconfigure analogue circuitry without changing program flow.

The configurable analogue circuitry may comprise a first set of configurable analogue circuits (first set) having a first analogue output and a second set of configurable analogue circuits (second set) having a second analogue output a first control associated with the first set and a second control associated with the second set; the first and second sets being independently configurable via their respective first and second controls. The each of the controls may be implemented by analogue switches having digital inputs to receive digital control signals from the controller.

Each of the first and second sets may have an analogue input to receive the same analogue signal or different analogue signals simultaneously. Favourably each of the first and second sets has more than one input in order that they can each receive more than one analogue signal simultaneously.

By having two independently configurable sets it is possible to run two parallel computational processes to provide two analogue outputs that do not need to have the same value. An analogue signal outputted from the configurable analogue circuitry can be used as, or to derive, an analogue output signal of the hybrid analogue-digital computer system.

In embodiments where there are at least two configurable sets of analogue circuitry, it may be preferred that the output of either may be used to provide the output of the hybrid analogue-digital computer system. Where this is so, the system may comprise a first selector, e.g. a multiplexer, to select which of the outputs from the two configurable sets of analogue circuitry to use. In certain embodiments it may be favourable to include a pulse width modulator (PWM) and a further selector, the output of the first selector forming an input to both the PWM and the further selector and the output from the PWM forming a second input to the further selector. The further selector being arranged to select either the PWM output or first selector output as an analogue output of the hybrid computer system.

The analogue circuitry may be arranged such that the output of either or both of the first and second sets can be selected so as to be looped back to provide an analogue input signal(s) to either set.

The hybrid analogue-digital computer system favourably further comprises an analogue memory arranged to receive and store an analogue value, e.g. from the output of the configurable analogue circuitry and/or from the accumulator means. The analogue memory may be arranged to receive and store an analogue value in response to receipt of a write control signal from the controller. An analogue value held in the analogue memory may be available as an analogue input to the configurable analogue circuitry.

The analogue memory allows the storage and retrieval of analogue values determined by the configurable analogue circuitry that can be used to influence the configuration or output of the configurable analogue circuitry without the need to convert the values into digital form.

The analogue memory favourably comprises an array of addressable analogue memory elements arranged to receive an address signal from the controller to select an analogue memory element from the array to be written or read to. In one arrangement the accumulator means may be arranged to receive an analogue output signal of the configurable analogue circuitry and accumulate output values taken at discrete times.

The analogue accumulator means may be arranged to receive a digital control signal from the controller and in response carry out an accumulation function. The analogue signal outputted by the second set of configurable analogue circuits may be arranged to be received by the accumulator means and can be used to manipulate the analogue input to the first set of configurable analogue circuits and/or reconfigure the first set of configurable analogue circuits. Where the configurable analogue circuitry comprises at least two sets of configurable analogue circuits, the analogue accumulator means may be comprised from a configuration of the second set of configurable analogue circuits with the analogue memory.

In said configuration an analogue output of the second set in a first accumulation cycle is held in the analogue memory and used to provide a new input to the second set during a second accumulation cycle. The output of the second set corresponds to an accumulation value. This accumulation value replaces the value held in the analogue memory from the first accumulation cycle and is used to provide a new input to the second set during a third accumulation cycle. The output of the second set is connected to the input to the comparator to provide the comparator with the output value which it compares with the threshold value.

The hybrid analogue-digital computer system may comprise a store of constant values. The store of constant values may be used to provide one or more internal user defined analogue signals that can to be used to influence the output of the first and/or second configurable analogue circuits.

Where the store of constant values are held in a digital memory, the hybrid analogue- digital computer system may comprise a digital to analogue converter (DAC) arranged to output an analogue signal indicative of a selected constant value from the store of constant values, the output analogue signal forming at least part of the analogue input to the configurable analogue circuitry.

The hybrid analogue-digital computer system may comprise a multiplexer having multiple analogue inputs and an analogue output that provides an input for the configurable analogue circuitry. The multiplexer may be arranged to receive a switch signal from the controller to select between the multiple analogue inputs to select an input for the configurable analogue circuitry. The multiplexer may be implemented by multiple discrete multiplexer devices.

The multiplexer may have two outputs in order to provide the same or different input signals simultaneously to the first and second configurable circuit sets. The multiplexer can be used to choose between one or more of: one or more external analogue inputs, an output of the accumulator means, the output of the first and/or second sets of configurable analogue circuitry, an output of the analogue memory or the internal user defined signal.

The (computer readable) memory that holds the program flow information and configuration information to configure the analogue circuitry may comprise an addressable memory array. The addressable memory array may be comprised from one or more of the analogue memory elements each capable of holding an analogue value and one or more digital memory elements each capable of holding a digital value. The memory may have an analogue output for outputting an analogue value held in one of the analogue memory elements. A row of the memory array may comprise at least one analogue memory element and at least one digital memory element accessed with the same address. The computer system further comprise a memory output comparator arranged to compare the analogue output from one of the analogue memory elements with a memory threshold value and in response provide a digital output.

The use of a hybrid analogue-digital memory provides advantages over using a digital memory alone. The digital nature of the memory means that it is readily compatible with the remainder of the digital circuitry, e.g. the controller. The inclusion of analogue memory element allows the memory to hold values greater than it could otherwise do with its bit width. This allows the bit width of the memory and thus bus width of the computer system to be kept relatively small simplifying the overall complexity of the computer system.

The controller is adapted to use a digital value held in the digital memory elements of a row to selectively use the analogue value held in the analogue memory element of the row as either a digital value or an analogue value and to provide an output: based on a multiple-bit digital value of the row formed from both the digital memory elements and the digital output derived from the analogue memory element; and/or comprising an instruction to use the analogue value of the analogue memory element.

By being able to treat an analogue memory element of a row as holding a digital value the effective digital bit width of the row is increased. For example, in a memory array in which each row comprises three digital memory elements and one analogue memory element, when the analogue memory element is treated as holding a digital value the row holds a four-bit wide digital value (word size).

Where the memory comprises at least two analogue elements in a row (memory location), the analogue outputs from each memory element of the row may be outputted to the analogue circuitry separately. Alternatively the outputs from multiple analogue element of a row may be combined (e.g. multiplied or summed) to provide a combined analogue signal output to the analogue circuitry. The values associated with analogue memory cells of different columns of the same row may different by at least one order of magnitude.

The control threshold value, which may be an analogue value, may correspond or be derived from a constant value held in a memory cell or from the output of one of the configurable analogue circuitry blocks or a fixed analogue reference value incorporated in the analogue circuitry. Where derived from a memory cell, the memory cell may be an analogue or digital memory cell. The memory cell may form part of the program memory of the digital circuitry and be activated when the control threshold value is required. Alternatively the memory cell may always active to continuously provide the control threshold value. In the latter case the memory cell may be physically separated from the program memory. The same applies mutatis mutandis to the memory threshold value.

The analogue memory elements of the non-volatile memory may be implemented using degraded bipolar junction transistors.

Each transistor may be programmed by a method comprising: applying a reverse voltage across the transistor for a period of time, the reverse voltage being sufficient to cause degradation of the transistors current gain value, then applying a forward voltage across the transistor to obtain an indication of the its current gain value; and iterating these steps until a desired current gain value of the transistor is reached.

Where the memory is implemented using degraded transistors, different current values may be applied to the bases of transistors of different columns of the memory in order to provide the variation in order of magnitude of the stored value between columns, for example a current of a first order of magnitude can be applied to the base of activated transistors in one of the columns, and a current of a second order of magnitude applied to the bases of activated transistors of the second column.

According to another aspect of the invention there is provided a transistor device comprising: a transistor having a first terminal and second terminal about which the transistor device is connectable into a circuit in order to control current flow through the circuit; and a third terminal through which a control signal can be applied in order to vary the current through the first and second terminals; the transistor device further comprising a hybrid analogue-digital computer according to any previous claim, the output of the hybrid analogue-digital computer providing the control signal to the third terminal; the hybrid analogue-digital computer having a first input to receive an analogue signal indicative of the voltage at the first terminal.

According to a further aspect of the invention there is provided a memory system comprising an analogue memory element capable of holding an analogue value; the memory system having a first output that provides an analogue output; the memory system further comprising a comparator arranged to compare the analogue output from the analogue memory element with a threshold signal and in response provide a digital output, the digital output from the comparator providing a digital output of the memory system. The invention will now be described by way of example with reference to the following Figures in which:

Figure l is a schematic diagram of a hybrid analogue-digital computer;

Figure 2 is a schematic diagram of a variant hybrid analogue-digital computer;

Figure 3 is a schematic diagram of further variant hybrid analogue-digital computer Figure 4 is a schematic illustrating the memory element array of the digital analogue memory of Fig 3; and

Figure 5 is a simplified schematic of a transistor device comprising the hybrid analogue-digital computer system of Fig 1. With reference to Fig 1 there is shown a hybrid analogue-digital computer having analogue circuitry 10 and digital circuitry 20.

The analogue circuitry 10 includes a first configurable electronic circuitry block (first block) 11 and a second configurable electronic circuitry block (second block) 12, each block 11, 12 having an analogue input 11A 12A and arranged to operate in parallel to apply functions (e.g. one or more of PID control, multiply, invert, and comparison) on an analogue signal received through its respective input. Favourably though not shown, each block 11, 12 will also include a second analogue input.

The first analogue block can be configured, when operating, to apply function(s) to analogue input signal(s), received through an analogue input of the computer system (three are shown in Figure 1) or generated internally e.g. from a constant value store, and outputs a continuous analogue output signal that is used to provide a continuous analogue output signal at an analogue output of the computer system. Depending on the analogue input signal(s) and/or the function of the analogue block, the continuous analogue output signal may have a value that varies continuously or may remain substantially constant.

The analogue inputs signals may be received by the computer system via its analogue inputs from connected external devices e.g., a sensor or an external control device.

First configuration control circuitry (not shown), comprising analogue switches having digital control inputs, provides means by which the first block 11 is configured by the digital circuitry 20 based on program instructions. Second configuration control circuitry (not shown), comprising analogue switches having digital control inputs, provides means by which the second block 12 is configured by the digital circuitry 20 based on the program instructions. An accumulator 13 is arranged to accumulate output signals from the second block 12 under control from an accumulator control signal from a control 21 of the digital circuitry 21. The accumulator 13 stores a value to be manipulated according to the instruction of the program being executed. The output of the accumulator 13 provides an input to an electronic comparator circuit 14 that outputs a digital flag signal - a one bit that switches between 0 and 1.

The analogue circuitry 10 further comprises a multiplexer 15 having a first and second output 15 A 15B that provides respective inputs for the first and second blocks 11,12, and inputs 15C from the outputs of the first and second analogue blocks, the accumulator, and three external inputs (though the number can vary).

The multiplexer 15 is arranged in response to a digital selector signal to select one or more of the inputs 15C to the multiplexer 15 to output from the multiplexer 15 so as to provide one or more inputs to the blocks 11,12.

The digital circuitry 20 comprises controller circuitry (controller) 21, non-volatile (persistent) memory circuitry 22(e.g. one time programmable) that holds program instructions and an oscillator 23 that provides a clock signal.

Example implementations of the persistent memory include programmable fuses or the use of floating gate MOS devices.

The controller 21 is arranged to execute the program instructions held in the non- volatile memory 22 to select, via the first and second configuration circuits, the configuration of the first and second analogue blocks 11, 12 to select through the selector signals, the inputs on the multiplexer 15 and via the accumulator control signal, instruct the accumulator 13 to operate.

The controller 21 is arranged to receive the digital flag signal from the comparator 14 and in response can modify the program flow, for example to alter the selection of input to the first and/or second blocks 11, 12 or configuration of the first and/or second blocks 11, 12 so as to alter the function(s) applied by the analogue block to the analogue signal passing through the analogue block. Because the data value manipulation is carried out in the analogue domain, the digital circuitry 20 can be relatively simple. For example, in one arrangement the digital instruction word size may be 4-bit, meaning up to 2⁴ unique instructions are possible to drive the analogue computation process. Each instruction is passed to the controller 21, which determines which series of analogue connections are made to control the way the analogue values are manipulated.

Figure 2 illustrates a variant embodiment of hybrid computer of Fig 1. In this variant, the non-volatile memory 22 holds, in addition to program instructions, an array of constant values which can be selected by the controller 21 and converted to an equivalent analogue signal through a digital-to-analogue converter 24, the output of which forms an input of the multiplexer 15 that can be selected in order to be an input one or both of the configurable analogue blocks 11, 12.

The analogue circuitry 10 further includes an analogue re-writable memory 16 (e.g. random access memory (RAM)) comprised from an array of addressable analogue memory elements. The controller 21 is adapted to select, via address signals, an analogue memory element from the array in order to perform a read or write function. The analogue re-writable memory 16 has an input 16A provided by an output 17A of a second multiplexer 17 arranged to receive a selector signal from the controller 21 in order to choose either an analogue signal from the output of the accumulator 13 or the output of the second analogue block 12. The output of a memory element selected to be read is provided as an input to the first multiplexer 15.

One of the input channels (CONTROL) to the multiplexer 15 can be used as a bi directional input/output channel of the hybrid computer system. This is achieved by connecting the output of the first block 11 to the CONTROL channel and using a switch (ENABLE) 18 operated by a digital control signal from the controller 21 to control feed of the first block’s analogue output to the CONTROL channel.

Each feature of Fig 2 that is described in addition to Fig 1 may be implemented independently from one another, namely each may be used without the others.

Figure 3 is a schematic of a further variant embodiment of hybrid analogue-digital computer having analogue circuitry 100 and digital circuitry 200. The digital circuitry 200 comprises controller circuitry (controller) 210, non-volatile memory circuitry 220 (e.g. one time programmable) that holds program instructions and constant values, and an oscillator 230 that provides a clock signal.

The analogue circuitry 100 includes a first configurable electronic circuitry block (first block) 110 and a second configurable electronic circuitry block 120 (second block), first and second output multiplexers 130A, 130B, block input multiplexers 150, and rewritable analogue memory 160. Additionally the analogue circuitry comprises one more analogue inputs and an analogue output that function as the analogue inputs and output of the computer system. Each block 110, 120 has first and second analogue inputs 110 A 110B, 120 A 120B (though optionally more) and are arranged to operate in parallel to apply functions (e.g. one or more of PID control, multiply, invert, and comparison) on analogue signals received through its respective inputs.

A first configuration control circuitry (not shown) implemented by analogue switches having digital control inputs, provides means by which the first block 110 is configured by the digital circuitry 200 based on program instructions. A second configuration control circuitry (not shown) again implemented by analogue switches having digital control inputs, provides means by which the second block 120 is configured by the digital circuitry 200 based on the program instructions. Through the first and second configuration control circuitry the first and second blocks 110, 120 can be configured independently of one another to perform different calculations.

The first and second blocks 110, 120 may have different circuitry. For example, each block need only comprise the circuits required for the calculations it is intended or expected to perform. This allows for a more simplified design. Alternatively each block 110 120 may comprise identical circuitry. This increases the overall complexity of the system but provides the computer system has greater general purpose utility.

Each of the first block 110 and the second block 120 have an analogue output 110C 120C. Both outputs 110C 120C of the first and second blocks 110 120 are connected to inputs of the first output multiplexer 130A. The first output multiplexer 130A, under control from a selector signal from controller 210, is used to select between the outputs of the first and second blocks 110, 120 in order to provide an analogue output signal of the computer system.

The output of the first output multiplexer 130A provides an input to both the second output multiplexer 130B and a pulse width modulator (PWM) 170. The pulse width modulator 170 modulates the analogue signal from the first output multiplexer 130A using optionally control signals from the controller 210 and/or a configuration bit value held in a constant value store 300 to provide a modulated output. The modulated output of the PWM 170 provides a second input to the second output multiplexer 130B. The second output multiplexer 130B, under control from another configuration bit value held in the constant value store 300, is used to select either the output from the first output multiplexer 130A or the output from the PWM 170 as an analogue output of the computer system.

The analogue circuitry 100 includes an analogue re-writable memory (ARWM) 160. In this example the analogue re-writable memory 160 comprises three memory elements, RAM0, RAM1 and RAM2 each able to hold a separate analogue value. It will be appreciated that the number of memory elements in the ARWM 160 may vary. The ARWM 160 may be implemented by conventional sample-hold type circuits e.g. comprising a capacitor and op-amp. Alternatively the memory may be implemented using a floating gate analogue memory in which the gate of a MOS transistor serves as a capacitor. Such a method is described, for example in An Analog Floating-gate Memory in a Standard Digital Technology Proceedings of Fifth International Conference on Microelectronics for Neural Networks; 12-14 Feb. 1996 ISBN 0-8186-7373-7

Through an arrangement of switches 400 controlled by digital control signals from the controller 210, the input of the ARWM 160 can be selectively connected to the analogue output of either the first block 110, second block 120 or an analogue constant held in the non-volatile memory 220 associated with the digital circuitry 200. Additionally the input to the ARWM 160 may also be connected to the output of any one element of the ARWM 160, thus allowing a value held in one element of the ARWM 160 to be moved to another element of the ARWM 160. To store a value in a memory element of the ARWM 160, the input to the ARWM 160 is connected through the arrangement of switches 400 to the analogue output of either the first block 110, second block 120, non-volatile memory 220 associated with the digital circuitry 200, or, where a value is to be copied between memory elements, the output of the memory element of the ARWM 160 that is to be copied; the memory element that is to store the analogue value is activated by a digital WRITE control signal from the digital controller 210.

The analogue output of memory element RAM0 is connected to an input of the block input multiplexer 150 so that it can be selectively used as an input to either the first or second blocks 110, 120. The output of RAM 1 is connected to one of the analogue inputs 110A of the first block 110. The output of RAM2 is connected to one of the analogue inputs 120A of the second block 120.

In one arrangement the analogue circuitry is configured by the controller 210 so that the second block 120 and ARWM 160 are configured to provide the equivalent function of the accumulator of the circuitry of Figs 1 and 2. In such an arrangement the first analogue block can be configured to continuously modify an analogue input signal(s), e.g. received directly or otherwise from an analogue input of the computer system or from an internally generated analogue input signal (e.g. from the ARWM 160), to provide a continuous analogue output signal that provides a continuous analogue output of the computer system. Depending on the analogue input signal(s) and/or the function of the analogue block, the continuous analogue output signal may have a value that varies continuously or may remain substantially constant.

For the purpose of providing the accumulator function only a single memory element is required. In the present example memory element RAM2 is assigned to this purpose.

The second block 120 and RAM2 are configured such that RAM2 stores an analogue output value from the second block 120 in a first accumulation cycle. The output of RAM2 forms an analogue input value via input 120 A to the second block 120 in a second accumulation cycle; the output value of the second block 120 in the second accumulation cycle is an accumulated value corresponding to the accumulated value held by the accumulator 13 of Fig 1 or Fig 2 after the first two outputs of the second block 12. In a third accumulation cycle the accumulated value output from the second block 120 replaces the existing value held in RAM2 and forms an analogue input value to the second block 120 in a third accumulation cycle. In response the second block outputs 120 a further accumulation value which corresponds to the accumulated value held by the accumulator 13 of Fig 1 or 2 of three outputs of the second block 12

The output of the second block 120 is connected to an electronic comparator circuit 140. The comparator circuit 140 compares the accumulated values outputted from the second block with control threshold value derived from a constant valve from the constant memory store 300 and outputs a digital one-bit flag signal to the controller 210

The use of constant values in the constant store 300 for providing inputs to the comparator circuitry 140, PWM 170 and second output multiplexer DOB reduces the number of control lines from the controller 210 that are needed.

In embodiment of Fig 3 the constant store 300 is separate from the ARWM 160 and non-volatile memory 220. The use of constants to provide the control threshold value, and provide inputs to the PWM l70m second output multiplexer DOB and the first and second analogue blocks 110, 120 as a further analogue input reduces the number of control lines from the controller 210 that are needed.

The block input multiplexer 150 has a first and second output 150A 150B connected to inputs 110B DOB for the first and second blocks 110, 120, and inputs from a constant value held in the non-volatile memory 220, the output of the ARWM 160 (RAM0) and three external analogue inputs (though the number can vary). Optionally it may also be arranged to have inputs directly from the outputs of the first and second analogue blocks 110, 120,

The block input multiplexer 150 is arranged in response to a digital selector signal from the controller 210 to select one or more of the inputs to the multiplexer 150 to pass to the blocks 110, 120. The controller 210 of the digital circuitry 220 is arranged to execute the program instructions held in the non-volatile memory 220 to select, via the first and second configuration control circuits, the configuration of the first and second analogue blocks, to select through the digital selector signals, the inputs on the block input multiplexer 150 and to configure the second block 120 and ARWM 160 to provide the accumulator function.

The controller 210 of the digital circuitry 220 is arranged to receive the one-bit digital flag signal from the comparator circuit 140 and in response can modify the program flow, for example to alter the selection of input to the first and/or second blocks 110, 120, and/or configuration of the first and/or second blocks 110, 120 via the configuration control circuitry.

As before, because the data value manipulation is carried out in the analogue domain, and the input from the analogue circuitry 100 to the controller 210 comprises a single-bit flag signal, the digital circuitry 200 can be relatively simple. In the example of Fig 3, the digital circuitry 200 is 5-bit, meaning that the digital bus and hence program counter of the controller 210 are 5 bits wide meaning up to 2⁵ unique instructions words are possible to drive the analogue computation process. Each instruction is passed to the controller 210, which determines which series of analogue connections are made to control the way the analogue values are manipulated by the analogue circuitry.

In the embodiment of Fig 3 the purely digital non-volatile memory of Figs 1 and 2 is replaced with a hybrid digital- analogue memory. As illustrated in Fig 4, the memory comprises a 2D addressable array.

Each addressable row (memory location) of the array is five bits wide comprised from three digital memory elements D and two analogue memory elements A. The digital and analogue elements are segregated into separate columns; the digital analogue elements occupy three columns of the array and the analogue memory elements two columns of the array. Each analogue column has two outputs 221, 222. A first output 221 provides an analogue output to be held either in ARWM 160 or fed as an input of the block input multiplexer 150 under control of the switching arrangement 400. The second output 222 forms a first input to a memory output comparator 240 which compares the analogue output value from the addressed row with a memory threshold value signal, e.g. derived from a constant bit value in the constant value store 300, and in response outputs a high or low signal to the controller 221.

Through this arrangement each analogue memory element A can be treated as holding either an analogue value or a digital l-bit value. As such any row of the array can either be treated as holding an addressable 5-bit digital value or be used to instruct that one or both of the analogue values held in the analogue memory elements of the row be made available to the analogue circuitry, through control of switch arrangement 400.

Whether the row is treated as holding a 5-bit-digital value (instruction word size) or an analogue value is determined by the 3 -bit digital value held by the three digital memory elements in the row. One of the eight (2³) possible values that could be held by the digital memory elements of each row is assigned to read one of the analogue memory elements of the row, and a second of the eight possible values is assigned to the other analogue memory element. For the other six remaining values the control logic is configured to treat the row as holding a 5-bit digital value.

Alternatively or additionally one of the eight (2³) possible values that could be held by the digital memory elements of each row is assigned to read both of the analogue memory elements of the row. Where this is so, the analogue values are combined by a combining function 500, e.g. implemented by an op amp, that combine (e.g. multiply or sum) the two analogue values of a row to provide a combined analogue output value.

This combining technique is thought to provide particular benefit when used with two analogue values that are of significantly different sizes as it allows for increased resolution of the resulting value. For example, the first column of analogue elements may be used to store values of a different order of magnitude to those of the second column.

It will be appreciated that the bit-width of the array (and thus of the bus) and the number and relative proportion of digital and analogue elements per row may vary. The digital-analogue memory 220 may be implemented from an array of digital memory elements such as, for example, programmable fuses. The analogue memory elements may be implemented by selecting sizes of resistor etc at manufacture.

Alternatively the analogue memory elements may be implemented using degraded bipolar junction transistors. It is known that the current gain of a bipolar junction transistor is permanently degraded by reverse biasing a transistor above its breakdown voltage; see, for example: Degradation Of Junction Parameters Of An Electrically Stressed NPN Bipolar Transistor Active and Passive Elec. Comp., 2001, Vol. 24, pp. 155-163. The level of degradation depends on the size of the reverse biased voltage and the length of time the reversed biased voltage is applied. The current gain value of the transistor can be treated as an analogue (or digital) value stored by the transistor which can be read by applying a forward voltage across it. To program the transistor with a value, a reverse bias voltage is purposely applied across a bipolar transistor to intentionally degrade its current gain value to a desired value.

This can be accomplished by applying (e.g. pulsing) a reverse voltage (above breakdown voltage) across the transistor to degrade it before applying a forward voltage across the transistor to measure its current gain. These steps are iterated until the current gain has fallen to the desired value. Once degraded by the process the transistor will retain its degraded current gain value each time it is forward biased under normal conditional thereby providing a non-volatile memory element. Referring back to Figs 3 and 4, where degraded transistors are used to implement the analogue part of the hybrid memory, the value output of a memory cell corresponds to the current through the transistor which is dependent on the current gain of the transistor and the current applied to the base of the transistor. The same current value is applied to transistors of the same column when they are activated meaning that the difference in the current through each transistor is dependent only on the current gain of the transistor. Different current values may be applied to the bases of transistors of different columns in order to provide the variation in order of magnitude of the stored value between columns, for example a current of a first order of magnitude can be applied to the base of activated transistors in one of the columns, and a current of a second order of magnitude applied to the bases of activated transistors of the second column.

The array of digital and analogue elements may be provided on the same or different circuit boards connected using a conventional word (row) and bit(column) lines and accessed during a conventional address decoder based on received instructions through an address bus from the control.

It will be appreciated that variations of the designs of the above embodiments are possible. For example, the analogue circuitry may comprise more than two configurable analogue blocks; where so there may be more than two comparators to provide multiple flag signals simultaneously to the controller. The PWM 170 and second output multiplexer 130B are optional, as is the first output multiplexer if it is wished only to use the output from one of the blocks.

The hybrid computer system variously described above is typically intended to be used as a control device with a dedicated function, e.g. as an embedded device. The configurable analogue circuits, non-volatile memory (e.g. hybrid digital analogue memory) and configuration bits values provide the flexibility for the computer system to be programmed according to the control device’s intended function. Although the accumulators described above are arranged to accumulate values at discrete separated times, it is possible in variant embodiments that the accumulator maybe accumulate the output values configurable analogue circuitry continuously.

Figure 5 is a schematic illustrating the hybrid computer of Fig 1 (though could be of Fig 2, 3 or other variation thereof) implemented as a controller in a transistor device. The transistor device comprises a bipolar junction transistor (BJT) for connection in a relatively high power circuit. A relative small analogue output signal from the hybrid computer, derived from or comprising the output of the first analogue block is provided to the base terminal of the BJT to control current through the BJT and thus through the relatively high power circuit. The hybrid computer has three inputs, a first connected to the collector of the BJT, a second to the emitter of the BJT and the third input arranged for receiving an analogue signal from a source external to the transistor device. The three inputs of the device forms selectable inputs of the first multiplexer 15.

Claims

1. A hybrid analogue-digital computer system comprising: analogue circuitry that includes:

configurable analogue circuitry arranged to apply functions on an analogue input,

an analogue accumulator means arranged to accumulate output values from the configurable analogue circuitry; and

a comparator arranged to receive the output of the accumulator means, compare said output value with a threshold value and output a digital flag signal based on said comparison; digital circuitry that includes:

a memory in which is stored program flow information and configuration information to configure the analogue circuitry, and

a controller that uses the program flow information and configuration information in the memory and the digital flag signal from the comparator to control the program flow and/or to reconfigure the configurable analogue circuitry.

2. A hybrid analogue-digital computer system according to claim 1 in which the accumulator means is arranged to receive a digital control signal from the controller circuitry and in response carry out an accumulation function.

3. A hybrid analogue-digital computer system according to claim 1 or 2 wherein the configurable analogue circuitry comprises a first set of configurable analogue circuits having a first analogue output that provides an output for the hybrid analogue-digital computer system; and a second set of configurable analogue circuits having an second analogue output. a first control associated with the first set of configurable circuits and a second control associated with the second set of configurable analogue circuits the first and second sets of configurable analogue circuitry being independently configurable via their respective first and second controls.

4. A hybrid analogue-digital computer system according to claim 3 wherein the second of the second set of configurable analogue circuits is arranged to be accumulated by the accumulator means.

5. A hybrid analogue-digital computer system according to claim 3 wherein the accumulator means comprises the second set of configurable analogue circuits and a memory element; in which the memory element is arranged to store an output of the second set of configurable analogue circuits in a first accumulation cycle and the output of the memory element provides an analogue input value to the second set of configurable analogue circuits in a second accumulation cycle.

6. A hybrid analogue-digital computer system according to any previous claim wherein the memory in which is stored program flow information and configuration information to configure the analogue circuitry, comprises an analogue memory arranged to receive and store a value from the output of the configurable analogue circuitry and/or the accumulator means in response to receipt of a write control signal from the controller; the value held in the analogue memory being available as an input to the configurable analogue circuitry.

7. A hybrid analogue-digital computer system according to claim 6 wherein the memory comprises an array of addressable analogue memory elements arranged to receive an address signal from the controller to select an analogue memory element from the array to be written or read to.

8. A hybrid analogue-digital computer system according to any previous claim comprising a multiplexer having multiple analogue inputs, and arranged to receive a switch signal from the controller to select between the multiple analogue inputs, to provide the analogue input to configurable analogue circuitry.

9. A hybrid analogue-digital computer system according to any previous claim wherein the memory in which is stored program flow information and configuration information to configure the analogue circuitry, comprises an addressable memory array; the addressable memory array comprised from analogue memory elements each capable of holding an analogue value and digital memory elements each capable of holding a digital value; the memory having an analogue output for outputting an analogue value held in one of the analogue memory elements; wherein a row of the memory array comprises at least one of the analogue memory elements and multiple of the digital memory elements accessed with the same address; the computer system further comprising a memory output comparator arranged to compare the analogue output from the analogue memory element with a threshold signal and in response provide a digital output, the digital output from the comparator providing a digital output of the memory.

10. A hybrid analogue-digital computer system according to claim 8 wherein the controller is adapted to use a digital value held in the digital memory elements of a row to selectively use the analogue value held in the analogue memory element of the row as either a digital value or an analogue value and to provide an output: based on a multiple-bit digital value of the row formed from both the digital memory elements and the digital output derived from the analogue memory element; and/or comprising an instruction to use the analogue value of the analogue memory element.

11. A hybrid analogue-digital computer system comprising: an analogue input for receiving an external analogue input and an analogue output for connection to an external device adapted to receive an analogue output signal of the hybrid analogue-digital computer system a first set reconfigurable analogue circuitry arranged to apply functions on the received analogue input signal in the analogue domain and having an analogue output used to provide an analogue output signal of the computer system; and a digital flag signal generator arranged to generate a flag digital flag signal in response to the analogue output from the reconfigurable analogue circuitry; and digital circuitry arranged to reconfigure the configurable analogue circuitry in order to modify the functions applied to the input signal in response to receipt of the flag signal.

12. A transistor device comprising:

a transistor having a first terminal, second terminal about which the transistor device is connectable into a circuit in order to control current flow through the circuit; and a third terminal through which a control signal can be applied in order to vary the current through the first and second terminals; the transistor device further comprising a hybrid analogue-digital computer according to any previous claim, the output of the hybrid analogue-digital computer providing the control signal to the third terminal; the hybrid analogue-digital computer having a first input to receive an analogue signal indicative of the voltage at the first terminal.

13. A memory system comprising an analogue memory element capable of holding an analogue value; the memory system having a first output that provides an analogue output; the memory system further comprising a comparator arranged to compare the analogue output from the analogue memory element with a threshold signal and in response provide a digital output, the digital output from the comparator providing a digital output of the memory system.

14. A memory system according to claim 13 including an addressable memory array; the addressable memory array comprised from one or more of the analogue memory elements and one or more digital memory elements that each hold a digital value; wherein a row of the memory array comprises at least one analogue memory element and at least one digital memory element accessed with the same address.

15. A memory system according to claim 14 wherein a first column of the array comprises digital memory elements and a second column of the array comprises the analogue memory elements.

16. A computer system comprising the memory system of claim 13, 14 or 15 and control logic adapted to use digital value held in the digital memory element of a row to selectively use the value held in the analogue memory element of the row as a digital or analogue value and to provide an output: based on an at least 2-bit digital value of the row formed from both the digital memory element and the digital output derived from the analogue memory element; and/or comprising an instruction to use the analogue value of the analogue memory element.