WO2019204967A1 - 一种用于存储设备的存储器控制电路 - Google Patents

一种用于存储设备的存储器控制电路 Download PDF

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Publication number
WO2019204967A1
WO2019204967A1 PCT/CN2018/084116 CN2018084116W WO2019204967A1 WO 2019204967 A1 WO2019204967 A1 WO 2019204967A1 CN 2018084116 W CN2018084116 W CN 2018084116W WO 2019204967 A1 WO2019204967 A1 WO 2019204967A1
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Prior art keywords
data
data blocks
control circuit
circuit
read
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PCT/CN2018/084116
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English (en)
French (fr)
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范茜
周威
单明星
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华为技术有限公司
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Priority to PCT/CN2018/084116 priority Critical patent/WO2019204967A1/zh
Priority to CN201880076748.6A priority patent/CN111406282B/zh
Publication of WO2019204967A1 publication Critical patent/WO2019204967A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store

Definitions

  • the present invention relates to the field of digital circuits, and more particularly to read and write control of memories.
  • Non-volatile memory devices primarily include non-volatile memory and control circuitry.
  • the non-volatile memory includes a plurality of memory cells, each of which can store n-bit data, that is, corresponding to 2 n memory states, and each memory state corresponds to one threshold voltage.
  • the control circuit reads the required data from the memory cells of the non-volatile memory by comparing the read voltage to the threshold voltage.
  • the reliability of the storage medium in the storage unit is affected by the number of times of writing (PE, Program and Erase count) and the data retention time.
  • the threshold voltage of each storage state increases, and when the data retention time increases, the threshold voltage of each storage state decreases, and the above changes may cause overlapping of the storage states, thereby causing each storage state.
  • the read voltage margin is reduced, eventually causing the memory control circuit to increase the probability of reading erroneous data.
  • Embodiments of the present invention provide a memory control circuit that can be used to solve the problem that the probability that the memory control circuit reads erroneous data from the non-volatile memory increases when the number of erasing times increases or the data retention time increases. .
  • a memory control circuit for writing data to and reading data from a non-volatile memory.
  • the memory control circuit includes an identical circuit and a read/write control circuit, wherein the same circuit is used to receive a plurality of data blocks and perform bitwise AND operations on the same, generate redundant data blocks, and obtain a plurality of data blocks and obtain The redundant data block is output to the read/write control circuit; the read/write control circuit is used to write multiple data blocks and redundant data blocks into the non-volatile memory, or read and output multiple data from the non-volatile memory.
  • the non-volatile memory includes a plurality of storage units, wherein data for performing the same bitwise AND operation in the plurality of data blocks and the redundant data blocks is stored in a storage unit, wherein the plurality of storage units are Each memory cell has a capacity of n bits and has 2 n storage states, wherein the number of the plurality of data blocks is n-1, and n is an integer greater than or equal to 2.
  • the same or circuit performs bitwise OR calculation of multiple data blocks and obtains redundant data blocks, only half of the storage states in the non-volatile memory are used to store multiple data blocks and redundant data blocks. Therefore, the difference between the threshold voltages corresponding to each storage state is about twice as large as the original, so that the degree of overlap of the storage states for storing the plurality of data blocks and the redundant data blocks is reduced, and the read error of the memory control circuit is reduced. The probability of the data.
  • the redundant data block is also used to generate an erroneous data block based on the associated data block, so that the erroneous data block cannot be read.
  • the memory control circuit further includes an error correction encoding circuit, wherein the error correction encoding circuit is configured to receive a plurality of original data blocks, generate verification data according to the plurality of original data blocks, and generate the plurality of data The block outputs to the same OR circuit, wherein the plurality of data blocks includes a plurality of original data blocks and parity data.
  • the verification information generated by the error correction coding circuit is used to verify whether the data is incorrect when the data is read from the non-volatile memory, and the accuracy of reading the data is improved.
  • the memory control circuit further includes an error correction decoding circuit, wherein the error correction decoding circuit is configured to receive a plurality of data blocks output by the read/write control circuit, and decode and correct the plurality of data blocks. And outputting a plurality of data blocks that have been decoded and corrected.
  • the error correction decoding circuit reduces the probability of errors in the data block by correcting the data block.
  • the read and write control circuit is further configured to read and output an associated data block from the non-volatile memory, wherein the associated data block includes a redundant data block, and a plurality of data blocks without the erroneous data block.
  • the erroneous data block is a data block in which the amount of erroneous data in the plurality of data blocks exceeds the error correction capability of the error correction decoding circuit.
  • the error correction decoding circuit is further configured to receive an associated data block output by the read/write control circuit, decode and correct the associated data block, and output the decoded data block after decoding and error correction. To the same or circuit.
  • the same circuit is further used to read the associated data block in the error correction decoding circuit, and perform the bitwise OR operation on the associated data block to generate and output the restored data block. Due to the relationship of the same OR operation, the memory control circuit can obtain the restored data block by associating the data block, thereby realizing the recovery of the erroneous data block and preventing the erroneous data block from being read.
  • the plurality of data blocks are a plurality of page data.
  • the speed of reading and writing is faster.
  • the plurality of data blocks are a plurality of codeword data.
  • the code size of the error correction coding unit and the error correction coding unit is codeword data, the calculation speed is faster.
  • the storage unit is a TLC storage unit.
  • the TLC storage unit In a storage segment with a storage capacity greater than 3 bits, the TLC storage unit has a higher lifetime.
  • the OR circuit is configured to receive a plurality of codeword data and perform a bitwise AND operation thereof to generate redundant codeword data, and output the plurality of codeword data and the redundant codeword data to Read and write control circuit.
  • the read/write control circuit is configured to respectively splicing a plurality of codeword data and redundant codeword data into a plurality of page data and redundant page data, and writing the plurality of page data and the redundant page data into the nonvolatile memory.
  • the read/write control circuit is further configured to read a plurality of page data, crop the plurality of page data into a plurality of codeword data, and output the plurality of codeword data.
  • the error correction encoding circuit is configured to receive a plurality of original codeword data, generate parity data, and output the original codeword data including the parity data as a plurality of codeword data to an AND circuit.
  • the error correction coding unit code granularity is codeword data, the calculation speed is faster.
  • the error correction decoding circuit is configured to receive a plurality of codeword data, decode and error correct the plurality of codeword data, and output a plurality of codeword data that are decoded and error corrected.
  • the error correction decoding unit decodes the granularity into codeword data, the calculation speed is faster.
  • the read/write control circuit is configured to read the associated page data, trim the associated page data into associated codeword data, and output the associated codeword data.
  • the same OR circuit is used to receive the associated codeword data and perform a bitwise AND operation on the same, generate recovered codeword data, and output recovered codeword data.
  • the error correction decoding circuit is configured to receive the associated codeword data, decode and correct the associated codeword data, and output the decoded codeword data after decoding and error correction.
  • a memory control method comprising: the same circuit receiving a plurality of data blocks and performing bitwise AND operations on the same, generating redundant data blocks, and multiple data blocks And the obtained redundant data block is output to the read/write control circuit; the read/write control circuit writes the plurality of data blocks and the redundant data block into the non-volatile memory, or reads and outputs the plurality of non-volatile memories from the non-volatile memory a data block, the non-volatile memory includes a plurality of storage units, wherein data for performing the same bitwise AND operation in the plurality of data blocks and the redundant data blocks is stored in a storage unit, the plurality of storage units Each of the storage units has a capacity of n bits and has 2 n storage states, wherein the number of the plurality of data blocks is n-1, and n is an integer greater than or equal to 2.
  • the same circuit performs bitwise AND operations on multiple data blocks and obtains redundant data blocks, only half of the storage states in the non-volatile memory are used to store multiple data blocks and redundant data blocks. Therefore, the difference between the threshold voltages corresponding to each storage state is about twice the original value, and the degree of overlap of the storage states for storing the plurality of data blocks and the redundant data blocks is decreased, and the memory control circuit is prevented from reading the erroneous data. The chance.
  • the redundant data block is also used to generate an erroneous data block based on the associated data block, so that the erroneous data block cannot be read.
  • the memory control circuit further includes an error correction coding circuit
  • the memory control method further includes: the error correction coding circuit receives the plurality of original data blocks, generates the verification data according to the plurality of original data blocks, and generates the plurality of data The block outputs to the same OR circuit, wherein the plurality of data blocks includes a plurality of original data blocks and parity data.
  • the verification information generated by the error correction coding circuit is used to verify whether the data is incorrect when the data is read from the non-volatile memory, and the accuracy of reading the data is improved.
  • the memory control circuit further includes an error correction decoding circuit
  • the memory control method further includes: the error correction decoding circuit receives the plurality of data blocks output by the read/write control circuit, and translates the plurality of data blocks. Code and error correction, and output multiple blocks of data that are decoded and error corrected. Within the scope of error correction capability, the error correction decoding circuit reduces the probability of errors in the data block by correcting the data block.
  • the read and write control circuit reads and outputs an associated data block from a non-volatile memory, wherein the associated data block includes redundant data blocks, and a plurality of data blocks without erroneous data blocks,
  • the erroneous data block is a data block in which the amount of erroneous data in the plurality of data blocks exceeds the error correction capability of the error correction decoding circuit.
  • the error correction decoding circuit receives the associated data block output by the read/write control circuit, decodes and corrects the associated data block, and outputs the decoded and error corrected associated data block to the same or Circuit.
  • the same circuit reads the associated data block in the error correction decoding circuit, performs a bitwise OR operation on the associated data block, and generates and outputs a restored data block. Due to the relationship of the same OR operation, the memory control circuit can obtain the restored data block by associating the data block, thereby realizing the recovery of the erroneous data block and preventing the erroneous data block from being read.
  • the plurality of data blocks are a plurality of page data.
  • the speed of reading and writing is faster.
  • the plurality of data blocks are a plurality of codeword data.
  • the code size of the error correction coding unit and the error correction coding unit is codeword data, the calculation speed is faster.
  • the same OR circuit receives a plurality of codeword data and performs a bitwise OR operation to generate redundant codeword data, and outputs a plurality of codeword data and redundant codeword data to the read and write.
  • Control circuit The read/write control circuit splicing a plurality of codeword data and redundant codeword data into a plurality of page data and redundant page data, respectively, and writing a plurality of page data and redundant page data into the nonvolatile memory.
  • the read/write control circuit reads a plurality of page data, cuts a plurality of page data into a plurality of codeword data, and outputs a plurality of codeword data.
  • the error correction encoding circuit receives the plurality of original codeword data, generates the parity data, and outputs the original codeword data including the parity data as a plurality of codeword data to the same circuit.
  • the error correction coding unit code granularity is codeword data, the calculation speed is faster.
  • the error correction decoding circuit receives a plurality of codeword data, decodes and corrects the plurality of codeword data, and outputs a plurality of codeword data that are decoded and error corrected.
  • the error correction decoding unit decodes the granularity into codeword data, the calculation speed is faster.
  • the read/write control circuit reads the associated page data, clips the associated page data to associated codeword data, and outputs the associated codeword data.
  • the same circuit receives the associated codeword data and performs a bitwise AND operation on the same, generates recovered codeword data, and outputs recovered codeword data.
  • the error correction decoding circuit receives the associated codeword data, decodes and corrects the associated codeword data, and outputs the decoded codeword data after decoding and error correction.
  • a data storage device comprising a memory control circuit and a non-volatile memory, wherein the memory control circuit writes data to the non-volatile memory and The data is read in a non-volatile memory, the memory control circuit being a memory control circuit in the first aspect and its possible implementations.
  • the same circuit performs bitwise AND operations on multiple data blocks and obtains redundant data blocks, only half of the storage states in the non-volatile memory are used to store multiple data blocks and redundant data blocks. Therefore, the difference between the threshold voltages corresponding to each storage state is about twice the original value, and the degree of overlap of the storage states for storing the plurality of data blocks and the redundant data blocks is decreased, and the memory control circuit is prevented from reading the erroneous data. The chance.
  • the redundant data block is also used to generate an erroneous data block based on the associated data block, so that the erroneous data block cannot be read.
  • a communication device in an embodiment of the present invention, the communication device comprising a memory control circuit and a non-volatile memory, wherein the memory control circuit writes data into the non-volatile memory, and The data is read in a memory that is a memory control circuit in the first aspect and its possible implementations.
  • the same circuit performs bitwise AND operations on multiple data blocks and obtains redundant data blocks, only half of the storage states in the non-volatile memory are used to store multiple data blocks and redundant data blocks. Therefore, the difference between the threshold voltages corresponding to each storage state is about twice the original value, and the degree of overlap of the storage states for storing the plurality of data blocks and the redundant data blocks is decreased, and the memory control circuit is prevented from reading the erroneous data. The chance.
  • the redundant data block is also used to generate an erroneous data block based on the associated data block, so that the erroneous data block cannot be read.
  • FIG. 1 is a schematic diagram of a storage device for data storage according to an embodiment of the present invention.
  • FIG. 2 is a schematic diagram of a memory array in an embodiment of the present invention.
  • FIG. 3 is a table showing a storage state truth value of a storage unit according to an embodiment of the present invention.
  • FIG. 4 is a schematic diagram of a memory control circuit in accordance with an embodiment of the present invention.
  • FIG. 5 is a table showing a storage state truth value of another storage unit according to an embodiment of the present invention.
  • FIG. 6 is a schematic diagram of a more specific memory control circuit in accordance with an embodiment of the present invention.
  • FIG. 7 is a flowchart showing the operation of a memory control circuit according to an embodiment of the present invention.
  • FIG. 8 is a schematic diagram of a communication device according to an embodiment of the present invention.
  • An embodiment of the present invention takes a storage device 100 for data storage shown in FIG. 1 as an example.
  • the storage device 100 may be an SSD (Solid State Driver) or other device including a non-volatile memory.
  • the storage device 100 includes an interface logic circuit 120, a control circuit 140, a plurality of non-volatile memories 160, and an external buffer circuit 180.
  • the interface logic circuit 120 performs data transmission with the host through an interface protocol, wherein the interface protocol may be SATA (Serial Advanced Technology Attachment), PCI-E (Peripheral Component Interconnect-Express), or Other interface protocols that provide data transmission.
  • the control circuit 140 is used to control the read and write process of data.
  • the control circuit 140 includes a processing circuit 142, a buffer management circuit 144, and a memory control circuit 146.
  • the processing circuit 142 is configured to load firmware and perform a data IO (Input and Output) function and a data management function of the storage device 100, the functions including parsing the request input to the storage device 100, and the memory control circuit 146
  • the plurality of non-volatile memories 160 send read and write commands;
  • the cache management circuit 144 is configured to manage the external cache circuit 180 to improve the utilization of the external cache circuit 180 and reduce the complexity of managing the storage device 100;
  • the memory control circuit 146 is used for Data read and write tasks of a plurality of non-volatile memories 160 are performed.
  • the non-volatile memory 160 is used to store data and still retain data after power-off, wherein the plurality of non-volatile memories 160 can be integrated or packaged in one IC to obtain smaller power consumption and larger The amount of data stored.
  • the non-volatile memory 160 can be a NAND Flash (NAND NAND flash), or other type of flash memory.
  • the nonvolatile memory 160 in the embodiment of the present invention is a NAND Flash.
  • the external buffer circuit 180 is used to buffer the data in the processing circuit 142, and to cache data of the plurality of non-volatile memories 160 and the host for data transmission.
  • the storage device 100 can be disposed on a Printed Circuit Board (PCB) or an Integrated Circuit (IC).
  • PCB Printed Circuit Board
  • IC Integrated Circuit
  • the interface logic circuit 120, the control circuit 140, and the plurality of non-volatile memories 160 are disposed on the PCB as three discrete devices, wherein each of the above circuits can be implemented as a separate IC and passed through The connection lines on the PCB are for data transfer; in another implementation, the interface logic 120, the control circuit 140, and the plurality of non-volatile memories 160 are integrated or packaged on one IC. It can be understood that the above three parts can be integrated or separated as needed.
  • the interface logic circuit 120 and the control circuit 140 can be integrated or packaged on an Application-Specific Integrated Circuit (ASIC), and then multiple nonvolatiles.
  • ASIC Application-Specific Integrated Circuit
  • the memory 160 is disposed together on the PCB.
  • the plurality of non-volatile memories 160 can also be arranged as a separate circuit, such as packaged or integrated on an IC.
  • the non-volatile memory 160 includes a plurality of memory cells that make up a number of two-dimensional memory arrays.
  • a memory array 200 in the non-volatile memory 160 includes k word lines (Word Lines, WLs), that is, word lines 0, word lines 1 ... word lines k-1, and m Bit line (BL), that is, bit line 0, bit line 1 ... bit line m-1.
  • WLs Word Lines
  • BL bit line
  • Each word line and bit line can define a memory cell 210, and the number of word lines and bit lines can determine the capacity of the non-volatile memory 160.
  • the k word lines and m bit lines of the memory array 200 can determine m*k memory cells.
  • the number of word lines and bit lines of the memory array 200 is related to the specific circuit structure and storage capacity of the nonvolatile memory 160.
  • the amount of data that each storage unit 210 can store is n bits, wherein the n-bit data amount corresponds to 2 n kinds of storage states, and the value of n and the MOS (Metal-Oxide-Semiconductor) tube used by the storage unit related.
  • TLC Multiple-Level Cell
  • MOS Metal-Oxide-Semiconductor
  • all the storage units in the embodiment of the present invention are TLC (Triple-Level Cell) storage units, but it should be noted that the storage in all embodiments according to the present invention.
  • the unit may also use a QLC (Quadra-Level Cell) storage unit or other storage unit capable of storing more data.
  • each memory cell 210 can store n-bit data
  • a plurality of memory cells on each word line can store one or more page data, wherein each page data is stored in the same bit of all memory cells on the same word line. In the bit.
  • Each page data includes a plurality of codeword data. For example, when one page of data includes j codeword data, the data amount of one codeword data is m/j bits, and the data amount of one page data is m bits.
  • the original truth table 300 shown in FIG. 3 is a possible truth table of eight storage states corresponding to the TLC storage unit.
  • the eight storage states corresponding to each TLC storage unit include: an erase state, a state 1 ..., and a state 7, and the above eight storage states correspond to the first, second, and third bits of the stored 3-bit data. If possible, for example, when the memory cell is in state 1, the data stored in the first bit, the second bit, and the third bit are 1, 1, 0, respectively, and when the memory cell is in state 2, the first bit, the second The data stored in the bit and the third bit are 1, 0, and 0, respectively.
  • the above eight storage states and their corresponding 3-bit data are encoded according to the Gray code, that is, any two adjacent 3-bit data has only one bit binary number.
  • the memory control circuit 146 when the memory control circuit 146 writes data to the memory cells of the non-volatile memory 160, the memory cells must first be placed in an erased state. When the data in the storage unit is erased, new data can be written to the storage unit.
  • the above erased state can also be regarded as writing 3-bit data to the memory cell, wherein the data stored by the first bit, the second bit, and the third bit are 1, 1, 1, respectively, that is, erase data and write data 1 The operations of 1, 1 share the same state.
  • Each of the eight storage states has a corresponding threshold voltage, and the threshold voltages are sequentially arranged according to their corresponding storage states. For example, the threshold voltage of the erase state is the smallest, and the threshold voltage of the state 7 is the largest.
  • the memory control circuit 146 reads data from the TLC memory cells in the non-volatile memory 160
  • the read voltage generated by the memory control circuit 146 is compared with the threshold voltage, and the first and second bits in the TLC memory cell are read out. Bit and third bit data.
  • the threshold voltage corresponding to the above eight kinds of storage states increases correspondingly, and the voltage value increases accordingly.
  • the increase in the smaller threshold voltage is greater than the increase in the threshold voltage at which the voltage value is larger, for example, the increase in the threshold voltage of the erased state may be greater than the increase in the threshold voltage of the state 7. Therefore, when the threshold voltages corresponding to the above eight kinds of storage states are increased to a certain extent, these storage states may overlap, and the degree of overlap may become larger, causing the memory control circuit 146 to read erroneous data. Conversely, in another possible case, when the time in which the memory cells in the memory control circuit 146 hold data increases, the threshold voltages corresponding to the above eight memory states are correspondingly reduced, and the threshold voltages having smaller voltage values are correspondingly reduced.
  • the magnitude of the decrease is less than the magnitude of the decrease in the threshold voltage at which the voltage value is larger. Therefore, when the threshold voltages corresponding to the above eight kinds of storage states are reduced to a certain extent, these storage states also overlap and the degree of overlap becomes larger, causing the memory control circuit 146 to read erroneous data. Therefore, as the number of times the nonvolatile memory 160 erases data increases, or the time to hold the data increases, the probability that the memory control circuit 146 reads out the erroneous data increases.
  • Memory control circuit 400 is a specific implementation of memory control circuit 146 in accordance with an embodiment of the present invention.
  • the memory control circuit 400 is for writing data to the nonvolatile memory 160 and reading data from the nonvolatile memory 160.
  • the memory control circuit 400 includes an AND circuit 420, a read/write control circuit 440, an error correction coding circuit 460, and an error correction decoding circuit 480.
  • the error correction coding circuit 460 is configured to receive a plurality of original data blocks, and generate verification data according to the original data blocks, and output the plurality of original data blocks and the verification data as a plurality of data blocks to the same circuit 420.
  • the error correction coding circuit 460 can correct the original data block by using an LDPC code (Low Density Parity Check Code), a BCH code (Bose-Chaudhuri-Hocquenghem Code), or other coding method with error correction function. coding.
  • the OR circuit 420 is configured to receive a plurality of data blocks output by the error correction coding circuit 460, perform bitwise OR operations on the plurality of data blocks, generate redundant data blocks, and output the plurality of data blocks and the redundant data blocks to Read and write control circuit 440. For example, when a plurality of data blocks are three page data, the first page data and the second page data are bitwise ORed, and the obtained result is bitwise ORed with the third page data. The redundant page data is obtained, and the redundant page data and the above three page data are output to the read/write control circuit 440.
  • LDPC code Low Density Parity Check Code
  • BCH code Bit-Chaudhuri-Hocquenghem Code
  • the read and write control circuit 440 performs read and write of data to the nonvolatile memory 160 by transmitting a read command and a write command to the nonvolatile memory 160. Specifically, the read/write control circuit 440 writes a plurality of data blocks and redundant data blocks generated by the same OR circuit 420 to the nonvolatile memory 160, or reads and outputs a plurality of data from the nonvolatile memory 160. Piece.
  • the non-volatile memory 160 includes a plurality of storage units, and the data held by each of the storage units includes data of a plurality of data blocks and redundant data blocks for performing the same bitwise AND operation.
  • the data for performing the same bitwise AND operation refers to: the data of the same bit of each data block in the plurality of data blocks in the bitwise AND operation, and the same bit in the redundant data block The data.
  • a plurality of data blocks include data blocks B 0 : 0 , 1, 1, 1 and data blocks B 1 : 1 , 0, 1, 1 having a length of 4 bits, and redundant data blocks R are B 0 and B 1
  • the result of the bitwise OR operation that is, the redundant data block R: 0 , 0 , 1 , 1, and the data for performing the same bitwise AND operation at this time means the same bit in B 0 , B 1 and R
  • the data, such as the highest bit data in B 0 , B 1 and R, is 0 , 1 , 0.
  • These data for the same bitwise AND operation will be stored together in the same memory location.
  • the second highest bit (1, 0, 0) of each data block will also be stored together to another memory. Unit, and so on.
  • Nonvolatile memory storage unit 160 in each memory cell can be saved, and n-bit data having 2 n storage state, where 2 n-1 2 n th state of one or more memory cells in the memory
  • the storage state is used to store a plurality of data blocks and redundant data blocks, that is, the number of the plurality of data blocks is n-1, and the redundant data block is one data block, wherein the value range of n is greater than or equal to 2 The integer.
  • the T corresponding to the TLC storage unit is 3, and each TLC storage unit can store a total of 3 bits of data, that is, has 8 storage states.
  • the error correction decoding circuit 480 is configured to receive a plurality of data blocks output by the read/write control circuit 440, decode the check data by using the same coding method as the error correction coding circuit 460, and perform error correction on the plurality of data blocks, and A plurality of data blocks that are decoded and error corrected are output.
  • the read and write processes of the above data may also be independently performed by the write data circuit and the read data circuit.
  • the read and write control circuit 440 includes a write data circuit and a read data circuit, wherein the write data circuit will be generated by the same circuit 420.
  • the data block and the redundant data block are written to the nonvolatile memory 160, and the read data circuit reads and outputs a plurality of data blocks from the nonvolatile memory 160.
  • the data blocks in all embodiments of the invention may be page data, codeword data or other lengths of data, such as 1-bit data. That is, the data block that the memory control circuit 400 calculates or processes the data may be page data, codeword data, or other length data, and the data block in which the memory control circuit 400 and the non-volatile memory 160 perform data reading and writing may also be used. Is page data, codeword data or other length data.
  • the error correction encoding circuit 460 receives a plurality of original codeword data and generates parity data, which is output as a plurality of codeword data to the same OR circuit 420; the same OR circuit 420 receives a plurality of The code word data is subjected to a bitwise AND operation, and outputs a plurality of code word data and redundant code word data; the read/write control circuit 440 respectively splices the plurality of code word data and the redundant code word data into the data. Multiple page data and redundant page data, and multiple page data is cut into multiple codeword data when reading data.
  • the error correction decoding circuit 480 receives a plurality of codeword data, decodes and corrects the parity data, and outputs a plurality of codeword data subjected to error correction.
  • each of the nonvolatile memories 160 is caused.
  • the n-1 bit capacity in the storage unit is used to hold n-1 bit data in a plurality of data blocks, and the remaining 1 bit capacity is used to hold 1-bit data in the redundant data block, and thus the nonvolatile memory
  • the storage unit in 160 is used to store a plurality of data blocks and the storage state of the redundant data block becomes half of the original, that is, the storage state becomes 2 n-1 .
  • the truth table 500 shown in FIG. 5 is four storage states for storing a plurality of data blocks in the eight storage states corresponding to the TLC storage unit, that is, an erase state, a state 2, a state 4, and a state 6.
  • the first bit and the second bit in each TLC storage unit are respectively used to store 1-bit data, that is, a plurality of data blocks; and the third bit is used to save the first bit data and the second bit data to be bitwise or The result of the operation, ie the redundant data block.
  • State 1, State 3, State 5, and State 7 are not used to store data as compared to the original truth table 200.
  • each of the erase state, state 2, state 4, and state 6 is separated by a storage state that is not used to store data, the threshold voltages corresponding to the erase state, state 2, state 4, and state 6 The distribution is more uniform, causing the degree of overlap of the erased state, state 2, state 4, and state 6 to be reduced, facilitating the memory control circuit 146 to read the correct data.
  • FIG. 400 A more specific embodiment of a memory control circuit 400 in accordance with an embodiment of the present invention is shown in FIG.
  • the memory control circuit 400 can recover the erroneous data block based on the associated data block.
  • the read and write control circuit 440 in the memory control circuit 400 is further configured to read and output associated data blocks from the non-volatile memory 160, wherein the associated data blocks include redundant data blocks and no error data blocks. Multiple data blocks.
  • the error correction decoding circuit 480 is further configured to receive the associated data block output by the read/write control circuit 440, decode the parity data in the associated data block by using the same encoding method as the error correction encoding circuit 460, and perform the associated data block on the associated data block. Error correction, and output associated data blocks that are decoded and corrected.
  • the same circuit 420 is further configured to read the associated data block in the error correction decoding circuit 480, perform a bitwise OR operation on the associated data block, generate a restored data block, and output the restored data block, and the restored data at this time.
  • the block is an error-corrected error block.
  • the redundant data block is the third page data.
  • the read/write control circuit 440 When the second page data stored in the nonvolatile memory 160 is read by the read/write control circuit 440, and the amount of error data exceeds the error correction capability of the error correction decoding circuit 480, the read/write control circuit 440 The first page data and the third page data are read again in the volatile memory 160, and the decoding of the first page data and the third page data is completed by the error correction decoding circuit 480; the same OR circuit 420 reads and decodes The first page data and the third page data, and performing a bitwise AND operation on the first page data and the third page data, generating and outputting a restored data block, wherein the restored data block is decoded The second page of data.
  • the data block that the memory control circuit 400 calculates or processes for the data may be page data, codeword data, or other lengths of data.
  • the read/write control circuit 440 reads the associated page data from the nonvolatile memory 160 and crops the associated page data into associated codeword data; the error correction decoding circuit 480 receives the associated code. Word data, parsing the test data, correcting the associated codeword data, and outputting the error-corrected associated codeword data; the same OR circuit 420 performs a bitwise OR operation on the error-corrected associated codeword data, and The error-corrected associated codeword data is output.
  • FIG. 7 is a workflow diagram 700 of a memory control circuit 400 in accordance with an embodiment of the present invention.
  • the error correction encoding circuit 460 in the memory control circuit 400 reads the original data block (step 710) and encodes the original data block to generate a plurality of data blocks (step 711).
  • the OR circuit 420 performs a bitwise AND operation on the plurality of data blocks (step 712) to generate redundant data blocks.
  • the read and write control circuit 440 writes a plurality of data blocks and redundant data blocks into the nonvolatile memory 160.
  • the read and write control circuit 440 reads a plurality of data blocks from the nonvolatile memory 160 when reading data from the nonvolatile memory 160.
  • the error correction decoding circuit 480 decodes the plurality of data blocks (steps) 721), and outputting the decoded plurality of data blocks (step 722); when the error data amount of the plurality of data blocks exceeds the error correction capability of the error correction decoding circuit 480 (step 720),
  • the read and write control circuit 440 reads the associated data block from the non-volatile memory 160 (step 730), and the error correction decoding circuit 480 decodes the associated data block (step 731), and the OR circuit 420 pairs the associated data block.
  • a bitwise AND operation is performed (step 732), a recovered data block is generated, and a restored data block is output (step 733).
  • the memory control circuit 400 begins the next write and read operation of the non-volatile memory 160.
  • a schematic diagram of a communication device 800 includes a bus 810, a processor 820, a storage device 830, a display device 840, an input device 850, a radio frequency circuit 860, and a communication module 870.
  • the storage device 830 is a storage device 100 for data storage provided by an embodiment of the present invention, and includes a memory control circuit 400 and one or more non-volatile memories 160 according to an embodiment of the present invention.
  • the communication device 800 can be a mobile phone, a laptop or a server, or the like.
  • the processor 820, the storage device 830, the display device 840, the input device 850, the radio frequency circuit 860, and the communication module 870 are communicatively coupled to each other, and there is a data transmission connection, and the data transmission connection can be connected to the processor 820 and the storage device through communication, respectively.
  • the display device 840, the input device 850, the radio frequency circuit 860, and the bus 810 of the communication module 870 are implemented.
  • the bus 810 can be an AXI (Advanced eXtensible Interface) bus protocol, or other bus protocol.
  • the processor 820 may be a Central Processing Unit (CPU) for running software programs and/or instructions stored in the storage device 830 to perform various functions of the communication device 800, which may be based on an X86 architecture.
  • the display device 840 is configured to output visual text, graphics, video, and any combination thereof.
  • the display device 840 may be an LCD (Liquid Crystal Display) or an LPD (Lighting Power Density).
  • the user can enter commands and information into the communication device 800 through the input device 850, such as image data that needs to be stored, where the input device 850 can be a mouse, keyboard, scanner, or camera.
  • the radio frequency circuit 860 is configured to receive and transmit electromagnetic waves, convert the electrical signals into electromagnetic waves, or convert the electromagnetic waves into electrical signals, and communicate with the communication network or other communication device through the electromagnetic waves.
  • the communication module 870 is for processing communication data, such as communication data represented by an electromagnetic signal received by the RF circuit 860 and converted into an electrical signal.
  • the disclosed apparatus and method may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the circuit is only a logical function division.
  • there may be another division manner for example, multiple circuits or components may be combined or Can be integrated into another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or circuit, and may be in an electrical, mechanical or other form.

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Abstract

一种存储器控制电路（400），涉及数字电路领域，用于读写非易失性存储器（160）中的数据，包括同或电路（420）和读写控制电路（440）。同或电路（420）用于对多个数据块做按位同或运算并产生冗余数据块，读写控制电路（440）用于将多个数据块和冗余数据块写入非易失性存储器（160），以及从非易失性存储器（160）中读取多个数据块，其中多个数据块和冗余数据块存储于一个存储单元中。其中，非易失性存储器（160）包括多个存储单元，每个存储单元的容量为n比特且具有2 n个存储状态，多个数据块的个数为n-1个，n为大于等于2的整数。由于每个存储单元中只有2 n-1个存储状态用于保存数据，因此存储状态对应的阈值电压的差值变为原来的两倍左右，使得存储状态的重叠程度下降，减小存储器控制电路（400）读出错误数据的几率。

Description

一种用于存储设备的存储器控制电路 技术领域
本发明涉及数字电路领域，尤其涉及存储器的读写控制。
背景技术
非易失性存储设备主要包括非易失性存储器和控制电路。非易失性存储器包括多个存储单元，每个存储单元可以存储n比特数据，即对应了2 n个存储状态，且每个存储状态对应一个阈值电压。通过将读电压与阈值电压相比较，控制电路从非易失性存储器的存储单元中读取所需要的数据。存储单元中的存储介质的可靠性受到擦写次数(PE，Program and Erase count)和数据保持时间的影响。其中，当擦写次数增大时各存储状态的阈值电压增大，当数据保持时间增大时各存储状态的阈值电压减小，上述变化均会导致各存储状态发生重叠，从而使得各存储状态的读电压裕量减少，最终导致存储器控制电路读出错误数据的概率增加。
发明内容
本发明的实施例提供了一种存储器控制电路，可以用于解决当擦写次数增大或数据保持时间增大时，存储器控制电路从非易失性存储器中读取错误数据的概率增加的问题。
第一方面，在本发明的实施例中提供一种存储器控制电路，用于向非易失性存储器中写入数据，并从非易失性存储器中读取数据。存储器控制电路包括同或电路和读写控制电路，其中，同或电路用于接收多个数据块并对其做按位同或运算，产生冗余数据块，并将多个数据块和得到的冗余数据块输出至读写控制电路；读写控制电路用于将多个数据块和冗余数据块写入非易失性存储器，或从非易失性存储器中读取并输出多个数据块，上述非易失性存储器包括多个存储单元，其中多个数据块和冗余数据块中用于进行同一位按位同或运算的数据存储于一个存储单元中，上述多个存储单元中的每个存储单元的容量为n比特且具有2 n个存储状态，其中多个数据块的个数为n-1个，n为大于等于2的整数。
由于同或电路对多个数据块做按位同或算并得到冗余数据块，非易失性存储器中的存储单元中只有一半的存储状态用于保存多个数据块和冗余数据块，因此每个存储状态对应的阈值电压的差值变为原来的两倍左右，使得用于保存多个数据块和冗余数据块的存储状态的重叠程度下降，减小了存储器控制电路读出错误数据的几率。在恢复错误数据块时，冗余数据块还用于根据关联数据块产生错误数据块，避免错误数据块无法读出。
在一种实施方式中，存储器控制电路还包括纠错编码电路，其中，纠错编码电路用于接收多个原始数据块，根据所述多个原始数据块产生校验数据，并将多个数据块 输出至同或电路，其中多个数据块包括多个原始数据块和校验数据。纠错编码电路产生的校验信息用于检验从非易失性存储器中读取数据时数据是否有误，提高了读取数据的准确率。
在一种实施方式中，存储器控制电路还包括纠错译码电路，其中，纠错译码电路用于接收读写控制电路输出的多个数据块，对多个数据块进行译码和纠错，并输出经过译码和纠错的多个数据块。在纠错能力范围内，纠错译码电路通过对数据块进行纠错，减少数据块发生错误的几率。
在一种实施方式中，读写控制电路还用于从非易失性存储器中读取并输出关联数据块，其中关联数据块包括冗余数据块，以及不含错误数据块的多个数据块，所述错误数据块为多个数据块中错误数据量超过纠错译码电路的纠错能力的数据块。
在一种实施方式中，纠错译码电路还用于接收读写控制电路输出的关联数据块，对关联数据块进行译码和纠错，并将经过译码和纠错的关联数据块输出至同或电路。
在一种实施方式中，同或电路还用于读取纠错译码电路中的关联数据块，将关联数据块做按位同或运算，产生并输出恢复数据块。由于同或运算的关系，存储器控制电路可以通过关联数据块得到恢复数据块，从而实现对错误数据块的恢复，避免错误数据块无法读出。
在一种实施方式中，多个数据块为多个页数据。非易失性存储器读写的粒度为页数据时，其读写的速度较快。
在一种实施方式中，多个数据块为多个码字数据。纠错编码单元和纠错译码单元的编译码粒度为码字数据时，其计算的速度较快。
在一种实施方式中，存储单元为TLC存储单元。在存储容量大于3bit的存储段元中，TLC存储单元具有较高的使用寿命。
在一种实施方式中，同或电路用于接收多个码字数据并对其做按位同或运算，产生冗余码字数据，并将多个码字数据和冗余码字数据输出至读写控制电路。读写控制电路用于分别将多个码字数据和冗余码字数据拼接成多个页数据和冗余页数据，并将多个页数据和冗余页数据写入非易失性存储器。读写控制电路还用于读取多个页数据，将多个页数据裁剪为多个码字数据，并输出多个码字数据。非易失性存储器读写的粒度为页数据且纠错编码单元和纠错译码单元的编译码粒度为码字数据时，存储器控制电路的计算的速度较快。
在一种实施方式中，纠错编码电路用于接收多个原始码字数据，产生校验数据，并将包含校验数据的原始码字数据作为多个码字数据输出至同或电路。纠错编码单元编码粒度为码字数据时，其计算的速度较快。
在一种实施方式中，纠错译码电路用于接收多个码字数据，并对多个码字数据进行译码和纠错，输出经过译码和纠错的多个码字数据。纠错译码单元译码粒度为码字数据时，其计算的速度较快。
在一种实施方式中，读写控制电路用于读取关联页数据，将关联页数据剪裁为关联码字数据，并输出关联码字数据。同或电路用于接收关联码字数据并对其做按位同或运算，产生恢复码字数据，并输出恢复码字数据。纠错译码电路用于接收关联码字数据，并对关联码字数据进行译码和纠错，输出经过译码和纠错的关联码字数据。非 易失性存储器读写的粒度为页数据且纠错编码单元和纠错译码单元的编译码粒度为码字数据时，存储器控制电路的计算的速度较快。
第二方面，在本发明的实施例中提供一种存储器控制方法，包括：同或电路接收多个数据块并对其做按位同或运算，产生冗余数据块，并将多个数据块和得到的冗余数据块输出至读写控制电路；读写控制电路将多个数据块和冗余数据块写入非易失性存储器，或从非易失性存储器中读取并输出多个数据块，上述非易失性存储器包括多个存储单元，其中多个数据块和冗余数据块中用于进行同一位按位同或运算的数据存储于一个存储单元中，上述多个存储单元中的每个存储单元的容量为n比特且具有2 n个存储状态，其中多个数据块的个数为n-1个，n为大于等于2的整数。
由于同或电路对多个数据块做按位同或运算并得到冗余数据块，非易失性存储器中的存储单元中只有一半的存储状态用于保存多个数据块和冗余数据块，因此每个存储状态对应的阈值电压的差值变为原来的两倍左右，使用于保存多个数据块和冗余数据块的存储状态的重叠程度下降，减小了存储器控制电路读出错误数据的几率。在恢复错误数据块时，冗余数据块还用于根据关联数据块产生错误数据块，避免错误数据块无法读出。
在一种实施方式中，存储器控制电路还包括纠错编码电路，存储器控制方法还包括：纠错编码电路接收多个原始数据块，根据多个原始数据块产生校验数据，并将多个数据块输出至同或电路，其中多个数据块包括多个原始数据块和校验数据。纠错编码电路产生的校验信息用于检验从非易失性存储器中读取数据时数据是否有误，提高了读取数据的准确率。
在一种实施方式中，所述存储器控制电路还包括纠错译码电路，存储器控制方法还包括：纠错译码电路接收读写控制电路输出的多个数据块，对多个数据块进行译码和纠错，并输出经过译码和纠错的多个数据块。在纠错能力范围内，纠错译码电路通过对数据块进行纠错，减少数据块发生错误的几率。
在一种实施方式中，读写控制电路从非易失性存储器中读取并输出关联数据块，其中关联数据块包括冗余数据块，以及不含错误数据块的多个数据块，所述错误数据块为所述多个数据块中错误数据量超过所述纠错译码电路的纠错能力的数据块。
在一种实施方式中，纠错译码电路接收读写控制电路输出的关联数据块，对关联数据块进行译码和纠错，并将经过译码和纠错的关联数据块输出至同或电路。
在一种实施方式中，同或电路读取纠错译码电路中的关联数据块，将关联数据块做按位同或运算，产生并输出恢复数据块。由于同或运算的关系，存储器控制电路可以通过关联数据块得到恢复数据块，从而实现对错误数据块的恢复，避免错误数据块无法读出。
在一种实施方式中，所述多个数据块为多个页数据。非易失性存储器读写的粒度为页数据时，其读写的速度较快。
在一种实施方式中，所述多个数据块为多个码字数据。纠错编码单元和纠错译码单元的编译码粒度为码字数据时，其计算的速度较快。
在一种实施方式中，同或电路接收多个码字数据并对其做按位同或运算，产生冗余码字数据，并将多个码字数据和冗余码字数据输出至读写控制电路。读写控制电路 分别将多个码字数据和冗余码字数据拼接成多个页数据和冗余页数据，并将多个页数据和冗余页数据写入非易失性存储器。读写控制电路读取多个页数据，将多个页数据裁剪为多个码字数据，并输出多个码字数据。非易失性存储器读写的粒度为页数据且纠错编码单元和纠错译码单元的编译码粒度为码字数据时，存储器控制电路的计算的速度较快。
在一种实施方式中，纠错编码电路接收多个原始码字数据，产生校验数据，并将包含校验数据的原始码字数据作为多个码字数据输出至同或电路。纠错编码单元编码粒度为码字数据时，其计算的速度较快。
在一种实施方式中，纠错译码电路接收多个码字数据，并对多个码字数据进行译码和纠错，输出经过译码和纠错的多个码字数据。纠错译码单元译码粒度为码字数据时，其计算的速度较快。
在一种实施方式中，读写控制电路读取关联页数据，将关联页数据剪裁为关联码字数据，并输出关联码字数据。同或电路接收关联码字数据并对其做按位同或运算，产生恢复码字数据，并输出恢复码字数据。纠错译码电路接收关联码字数据，并对关联码字数据进行译码和纠错，输出经过译码和纠错的关联码字数据。非易失性存储器读写的粒度为页数据且纠错编码单元和纠错译码单元的编译码粒度为码字数据时，存储器控制电路的计算的速度较快。
第三方面，在本发明的实施例中提供一种数据存储设备，该数据存储设备包括存储器控制电路和非易失性存储器，其中存储器控制电路向非易失性存储器中写入数据，并从非易失性存储器中读取数据，上述存储器控制电路为第一方面中及其可能的实施方式中的存储器控制电路。
由于同或电路对多个数据块做按位同或运算并得到冗余数据块，非易失性存储器中的存储单元中只有一半的存储状态用于保存多个数据块和冗余数据块，因此每个存储状态对应的阈值电压的差值变为原来的两倍左右，使用于保存多个数据块和冗余数据块的存储状态的重叠程度下降，减小了存储器控制电路读出错误数据的几率。在恢复错误数据块时，冗余数据块还用于根据关联数据块产生错误数据块，避免错误数据块无法读出。
第四方面，在本发明的实施例中提供一种通信设备，该通信设备包括存储器控制电路和非易失性存储器，其中存储器控制电路向非易失性存储器中写入数据，并从非易失性存储器中读取数据，上述存储器控制电路为第一方面中及其可能的实施方式中的存储器控制电路。
由于同或电路对多个数据块做按位同或运算并得到冗余数据块，非易失性存储器中的存储单元中只有一半的存储状态用于保存多个数据块和冗余数据块，因此每个存储状态对应的阈值电压的差值变为原来的两倍左右，使用于保存多个数据块和冗余数据块的存储状态的重叠程度下降，减小了存储器控制电路读出错误数据的几率。在恢复错误数据块时，冗余数据块还用于根据关联数据块产生错误数据块，避免错误数据块无法读出。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍。
图1为本发明实施例中一种用于数据存储的存储设备的示意图。
图2为本发明实施例中一种存储阵列的示意图。
图3为本发明实施例中一种存储单元的存储状态真值表。
图4为本发明实施例中一种存储器控制电路的示意图。
图5为本发明实施例中另一种存储单元的存储状态真值表。
图6为本发明实施例中一种更为具体的存储器控制电路的示意图。
图7为本发明实施例中一种存储器控制电路的工作流程图。
图8为本发明实施例中一种通信设备的示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明实施例以图1所示的一种用于数据存储的存储设备100为例。存储设备100可以是SSD(Solid State drivers，固态硬盘)，或者其他包括非易失性存储器的设备。存储设备100包括接口逻辑电路120、控制电路140、多个非易失性存储器160和外部缓存电路180。接口逻辑电路120通过接口协议与主机进行数据传输，其中接口协议可以为SATA(Serial Advanced Technology Attachment，串行高级技术附件)、PCI-E(Peripheral Component Interconnect-Express，快速外设组件互连)或者其他能提供数据传输的接口协议。控制电路140用于控制数据的读写过程，具体来说，控制电路140包括处理电路142、缓存管理电路144和存储器控制电路146。其中，处理电路142用于加载固件并执行存储设备100的数据IO(Input and Output，输入输出)功能和数据管理功能，上述功能包括解析输入到存储设备100的请求，以及通过存储器控制电路146向多个非易失性存储器160发送读写命令；缓存管理电路144用于管理外部缓存电路180，以提高外部缓存电路180的利用率，降低管理存储设备100的复杂度；存储器控制电路146用于执行多个非易失性存储器160的数据读写任务。非易失性存储器160用于存储数据并在断电后仍能保存数据，其中多个非易失性存储器160可以被集成或封装于一个IC之中，以获得较小的功耗和较大的数据存储量。非易失性存储器160可以为NAND Flash(与非门型闪存)，或其他类型的闪存存储器。为了方便描述，本发明实施例中的非易失性存储器160均为NAND Flash。外部缓存电路180用于缓存处理电路142中的数据，以及缓存多个非易失性存储器160与主机进行数据传输的数据。
存储设备100可以被设置于一个印制电路板(Printed Circuit Board，PCB)或集成电路(Integrated Circuit，IC)。在一种实现方式中，接口逻辑电路120、控制电路140和多个非易失性存储器160作为三个分立器件被设置于PCB板上，其中上 述每个电路可以以独立的IC实现，并通过PCB板上的连接线进行数据传输；在另一种实现方式中，接口逻辑电路120、控制电路140和多个非易失性存储器160被集成或封装于一个IC上。可以理解上述三部分可以根据需要进行集成或分立，例如可以将接口逻辑电路120、控制电路140集成或封装于一个专用集成电路(Application-Specific Integrated Circuit，ASIC)上，再与多个非易失性存储器160一起设置于PCB上。
多个非易失性存储器160还可以被设置成一个独立的电路，例如被封装或集成于一个IC上。非易失性存储器160包括多个存储单元，所述多个存储单元组成若干个二维的存储阵列。如图2所示的是非易失性存储器160中的一种存储阵列200，包括k个字线(Word Line，WL)，即字线0、字线1…字线k-1，以及m个位线(Bit Line，BL)，即位线0、位线1…位线m-1。每个字线和位线可以确定一个存储单元210，字线和位线的数量可以决定非易失性存储器160的容量。例如，存储阵列200的k个字线和m个位线可以确定m*k个存储单元。存储阵列200的字线和位线的个数与非易失性存储器160的具体电路结构和存储容量有关。
每个存储单元210可以存储的数据量为n比特，其中n比特数据量对应2 n种存储状态，n的取值与存储单元所使用的MOS(Metal-Oxide-Semiconductor，金属氧化物半导体)管有关。为了方便描述，本发明实施例中所有的存储单元均为TLC(Triple-Level Cell，每个存储单元存储3比特数据)存储单元，但需要注意的是，根据本发明的所有实施例中的存储单元也可以采用QLC(Quadra-Level Cell，每个存储单元存储4比特数据)存储单元或其他能够存储更多数据量的存储单元。
由于每个存储单元210可以存储n比特数据，每个字线上的多个存储单元可以存储一个或多个页数据，其中每个页数据存储于同一个字线上的所有存储单元的相同比特位中。例如，在存储阵列200中，字线0上具有m个TLC存储单元，由于每个TLC存储单元可以存储3比特数据，因此上述m个TLC存储单元可以存储3个页数据，这3个页数据分别存储于m个TLC存储单元的第一位、第二位和第三位。每一个页数据包括多个码字数据，例如当一个页数据包括j个码字数据，则一个码字数据的数据量为m/j比特，一个页数据的数据量为m比特。
如图3所示的原始真值表300为TLC存储单元对应的8种存储状态的一种可能的真值表。每个TLC存储单元对应的8种存储状态包括：擦除状态、状态1……和状态7，上述8种存储状态对应所存储的3比特数据中第一位、第二位和第三位所有可能的情况，例如，当存储单元处于状态1时，第一位、第二位和第三位存储的数据分别为1、1、0，当存储单元处于状态2时，第一位、第二位和第三位存储的数据分别为1、0、0。上述8种存储状态与其对应的3比特数据按照格雷码进行编码，即任意两个相邻的3比特数据只有一位二进制数不同。需要注意的是，当存储器控制电路146向非易失性存储器160的存储单元写数据时，必须先使该存储单元处于擦除状态。当存储单元中的数据被擦除后，才能向存储单元写入新的数据。上述擦除状态同样可以视为向存储单元写入3比特数据，其中第一位、第二位和第三位存储的数据分别为1、1、1，即，擦除数据和写入数据1、1、1的操作共享同一个状态。
上述8种存储状态的每个存储状态均有对应的阈值电压，且阈值电压根据其对应的存储状态顺序排列，例如擦除状态的阈值电压最小，状态7的阈值电压最大。当存储器控制电路146从非易失性存储器160中的TLC存储单元中读取数据时，存储器控制电路146产生的读电压与阈值电压进行比较，并读出TLC存储单元中第一位、第二位和第三位数据。在一种可能的情况下，当存储器控制电路146对非易失性存储器160的存储单元擦写数据的次数增大时，上述8种存储状态对应的阈值电压会相应地增大，且电压值较小的阈值电压的增大幅度大于电压值较大的阈值电压的增大幅度，例如擦除状态的阈值电压的增大幅度会大于状态7的阈值电压的增大幅度。因此，当上述8种存储状态对应的阈值电压增大到一定程度时，这些存储状态会发生重叠，且重叠程度会不断变大，导致存储器控制电路146可能读出错误的数据。相反的，在另一种可能的情况下，当存储器控制电路146中的存储单元保持数据的时间增加，上述8种存储状态对应的阈值电压会相应地减小，且电压值较小的阈值电压的减小幅度小于电压值较大的阈值电压的减小幅度。因此，当上述8种存储状态对应的阈值电压减小到一定程度时，这些存储状态同样会发生重叠且重叠程度会不断变大，导致存储器控制电路146可能读出错误的数据。因此，当非易失性存储器160擦写数据的次数增大，或保持数据的时间增加，存储器控制电路146读出错误数据的几率都会增大。
如图4所示的存储器控制电路400是根据本发明实施例的存储器控制电路146的一种具体的实现方式。存储器控制电路400用于向非易失性存储器160中写入数据，并从非易失性存储器160中读取数据。存储器控制电路400包括同或电路420、读写控制电路440、纠错编码电路460和纠错译码电路480。其中，纠错编码电路460用于接收多个原始数据块，并根据原始数据块产生校验数据，将多个原始数据块和校验数据作为多个数据块输出至同或电路420。纠错编码电路460可以通过LDPC码(Low Density Parity Check Code，低密度奇偶校验码)、BCH码(Bose-Chaudhuri-Hocquenghem Code)或其他具有纠错功能的编码方法对原始数据块进行纠错编码。同或电路420用于接收纠错编码电路460输出的多个数据块，将多个数据块做按位同或运算，产生冗余数据块，并将多个数据块和冗余数据块输出至读写控制电路440中。例如，当多个数据块为三个页数据，则将第一个页数据与第二个页数据做按位同或运算，将得到的结果与第三个页数据做按位同或运算，得到冗余页数据，再将上述冗余页数据和上述三个页数据输出至读写控制电路440中。
读写控制电路440通过向非易失性存储器160发送读命令和写命令，以实现对非易失性存储器160的数据读写。具体来说，读写控制电路440将同或电路420产生的多个数据块和冗余数据块写入非易失性存储器160，或者从非易失性存储器160中读取并输出多个数据块。其中，非易失性存储器160包括多个存储单元，每一个存储单元保存的数据包括多个数据块和冗余数据块中用于进行同一位按位同或运算的数据。用于进行同一位按位同或运算的数据是指：在按位同或运算中，多个数据块中的每个数据块的相同比特位的数据，以及冗余数据块中的相同比特位的数据。例如，多个数据块包括长度为4比特的数据块B 0：0、1、1、1以及数据块B 1：1、0、1、1，冗余数据块R为B 0和B 1做按位同或运算的结果，即冗余数据块R：0、0、1、1，此时用于进行同一位按位同或运算的数据是指B 0、B 1和R中相同比特位的数据，例如B 0、B 1和R 中的最高位数据，即0、1、0。这些用于进行同一位按位同或运算的数据会一起被存在到同一个存储单元中，类似的，各个数据块的第二高位(1、0、0)也会被一起存储到另一个存储单元，依次类推。
非易失性存储器160中的存储单元中的每个存储单元都可以保存n比特数据并具有2 n个存储状态，其中一个或多个存储单元的2 n个存储状态中的2 n-1个存储状态用于存储多个数据块和冗余数据块，即，多个数据块的个数为n-1个，冗余数据块为1个数据块，其中n的取值范围是大于等于2的整数。例如TLC存储单元对应的n为3，每个TLC存储单元一共可以存储3比特数据，即具有8种存储状态，由于冗余数据块是多个数据块按位做同或运算的结果，因此实际上总共只有4种存储状态用于存储多个数据块和冗余数据块，而其余4种存储状态不用于保存数据。纠错译码电路480用于接收读写控制电路440输出的多个数据块，采用与纠错编码电路460相同的编码方法对校验数据进行译码，对多个数据块进行纠错，并输出经过译码和纠错的多个数据块。上述数据的读写过程也可以分别由写数据电路和读数据电路独立完成，例如，读写控制电路440包括写数据电路和读数据电路，其中，写数据电路将同或电路420产生的多个数据块和冗余数据块写入非易失性存储器160，读数据电路从非易失性存储器160中读取并输出多个数据块。
本发明的所有实施例中的数据块可以是页数据、码字数据或其他长度的数据，例如1比特数据。即，存储器控制电路400对数据进行计算或处理的数据块可以是页数据、码字数据或其他长度的数据，并且存储器控制电路400与非易失性存储器160进行数据读写的数据块也可以是页数据、码字数据或其他长度的数据。例如，在上述数据读写过程中，纠错编码电路460接收多个原始码字数据并产生校验数据，将其作为多个码字数据输出至同或电路420；同或电路420接收多个码字数据并对其做按位同或运算，输出多个码字数据和冗余码字数据；读写控制电路440在写数据时分别将多个码字数据和冗余码字数据拼接成多个页数据和冗余页数据，并在读数据时将多个页数据裁剪为多个码字数据。纠错译码电路480接收多个码字数据，对校验数据进行译码和纠错，输出经过纠错的多个码字数据。
由于同或电路420将多个数据块进行按位同或运算，并将产生的冗余数据块和多个数据块同时写入非易失性存储器160，使得非易失性存储器160中的每个存储单元中的n-1比特容量用于保存多个数据块中的n-1比特数据，而剩余的1比特容量用于保存冗余数据块中的1比特数据，因此非易失性存储器160中的存储单元用于保存多个数据块和冗余数据块的存储状态变为原来的一半，即存储状态变为2 n-1。当存储器控制电路146向非易失性存储器160的存储单元写数据的次数增大时，或者当存储器控制电路146中的存储单元保持数据的时间增加时，由于用于存储多个数据块的存储状态变为原来的一半，上述存储状态的对应的阈值电压的差值变为原来的两倍左右，因此上述存储状态的重叠程度下降，减小了存储器控制电路146读出错误数据的几率，提高了存储设备100存储数据和读取数据的可靠性。
如图5所示的真值表500为TLC存储单元对应的8种存储状态中用于保存多个数据块的4种存储状态，即擦除状态、状态2、状态4和状态6。其中，每个TLC存储单元中的第一位和第二位分别用于保存1比特数据，即多个数据块；第三位用于保存第 一位数据和第二位数据做按位同或运算的结果，即冗余数据块。与原始真值表200相比，状态1、状态3、状态5和状态7不用于存储数据。由于擦除状态、状态2、状态4和状态6中的每个存储状态之间都间隔了一个不用于存储数据的存储状态，因此擦除状态、状态2、状态4和状态6对应的阈值电压分布更加均匀，使得擦除状态、状态2、状态4和状态6的重叠程度降低，有利于存储器控制电路146读出正确的数据。
如图6所示的是根据本发明实施例的一种存储器控制电路400的一种更为具体的实施方式。当某个数据块中的错误数据量超过了纠错译码电路480的纠错能力时，存储器控制电路400可以根据关联数据块对错误数据块进行恢复。具体来说，存储器控制电路400中的读写控制电路440还用于从非易失性存储器160中读取并输出关联数据块，其中关联数据块包括冗余数据块，以及不含错误数据块的多个数据块。纠错译码电路480还用于接收读写控制电路440输出的关联数据块，采用与纠错编码电路460相同的编码方法对关联数据块中的校验数据进行译码，对关联数据块进行纠错，并输出经过译码和纠错的关联数据块。同或电路420还用于读取纠错译码电路480中的关联数据块，将关联数据块做按位同或运算，产生恢复数据块，并输出所述恢复数据块，此时的恢复数据块为经过纠错后的错误数据块。由于同或运算中存在的等价关系，即由a⊙b＝c可以得到a⊙c＝b，因此存储器控制电路400通过对冗余数据块以及不含错误数据块的多个数据块做同或运算，得到恢复数据块，使得存储器控制电路400可以对超过纠错能力的错误数据块进行恢复，避免错误数据块无法读出导致数据丢失。
例如，当多个数据块包括2个页数据，即第一页数据和第二页数据，冗余数据块为第三页数据。当存储于非易失性存储器160中的第二页数据被读写控制电路440读出，并且其错误数据量超过纠错译码电路480的纠错能力时，则读写控制电路440从非易失性存储器160中再次读取第一页数据和第三页数据，并由纠错译码电路480完成对第一页数据和第三页数据的译码；同或电路420读取译码后的第一页数据和第三页数据，并对上述第一页数据和第三页数据做按位同或运算，产生并输出恢复数据块，其中所述恢复数据块为经过译码后的第二页数据。
存储器控制电路400对数据进行计算或处理的数据块可以是页数据、码字数据或其他长度的数据。例如，在上述数据读写过程中，读写控制电路440从非易失性存储器160中读取关联页数据，并将关联页数据裁剪为关联码字数据；纠错译码电路480接收关联码字数据，对检验数据进行解析，对关联码字数据进行纠错，并输出经过纠错的关联码字数据；同或电路420对经过纠错的关联码字数据做按位同或运算，并输出经过纠错的关联码字数据。
如图7所示的是根据本发明实施例的一种存储器控制电路400的工作流程图700。在向非易失性存储器160写数据时，存储器控制电路400中的纠错编码电路460读取原始数据块(步骤710)并对原始数据块进行编码，产生多个数据块(步骤711)。同或电路420对多个数据块进行按位同或运算(步骤712)，产生冗余数据块。读写控制电路440将多个数据块和冗余数据块写入非易失性存储器160中。在从非易失性存储器160读数据时，读写控制电路440从非易失性存储器160中读取多个数据块。当多个数据块中的若干个数据块的错误数据量没有超出纠错译码电路480的纠错能力时(步骤720)，则纠错译码电路480对多个数据块进行译码(步骤721)，并输出经过 译码的多个数据块(步骤722)；当多个数据块中的若干个数据块的错误数据量超过了纠错译码电路480的纠错能力(步骤720)，则读写控制电路440从非易失性存储器160中读取关联数据块(步骤730)，纠错译码电路480对关联数据块进行译码(步骤731)，同或电路420对关联数据块进行按位同或运算(步骤732)，产生恢复数据块，并输出恢复数据块(步骤733)。完成上述步骤后，存储器控制电路400开始对非易失性存储器160进行下一次数据块的写和读操作。
如图8所示的为一种通信设备800的示意图，包括总线810、处理器820、存储设备830、显示设备840、输入设备850、射频电路860和通信模块870。其中，存储设备830为本发明实施例提供的一种用于数据存储的存储设备100，包括根据本发明实施例提供的存储器控制电路400和一个或多个非易失性存储器160。通信设备800可以为移动电话、便携式电脑或服务器等。处理器820、存储设备830、显示设备840、输入设备850、射频电路860和通信模块870之间互相通信耦合，并存在数据传输连接，该数据传输连接可以通过分别通信连接处理器820、存储设备830、显示设备840、输入设备850、射频电路860和通信模块870的总线810来实现。总线810可以为AXI(Advanced eXtensible Interface)总线协议，或其他总线协议。处理器820可以是中央处理器(Central Processing Unit，CPU)，用于运行存储在存储设备830中的软件程序和/或指令，以执行通信设备800的各种功能，上述CPU可以是基于X86架构、基于ARM架构和基于cortex-A架构的CPU。显示设备840用于输出可视的文本、图形、视频及其任意的组合，显示设备840可以是LCD(Liquid Crystal Display，液晶显示器)或LPD(Lighting Power Density，发光聚合物显示器)。用户可以通过输入设备850输入命令和信息至通信设备800中，例如需要存储的图像数据，其中输入设备850可以是鼠标、键盘、扫描仪或摄像头等。射频电路860用于接收和发送电磁波，将电信号变换成电磁波，或是将电磁波变换成电信号，并且通过电磁波与通信网络或其他通信设备进行通信。通信模块870用于处理通信数据，例如射频电路860接收的电磁波并变换成的电信号所表示的通信数据。
在本申请所提供的几个实施例中，应该理解到，所揭露的装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述电路的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个电路或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或电路的间接耦合或通信连接，可以是电性，机械或其它的形式。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (16)

  1. 一种存储器控制电路，用于向非易失性存储器中写入数据，并从所述非易失性存储器中读取数据，所述存储器控制电路包括同或电路和读写控制电路，其中：
    所述同或电路用于接收多个数据块，将所述多个数据块做按位同或运算，产生冗余数据块，并将所述多个数据块和所述冗余数据块输出至所述读写控制电路；
    所述读写控制电路用于将所述多个数据块和所述冗余数据块写入所述非易失性存储器中，所述非易失性存储器包括多个存储单元，所述多个数据块和所述冗余数据块中用于进行同一位按位同或运算的数据存储于一个所述存储单元中，所述多个存储单元中的每个存储单元的容量为n比特且具有2 n个存储状态，所述多个数据块的个数为n-1个，其中n为大于等于2的整数；
    所述读写控制电路还用于从所述非易失性存储器中读取并输出所述多个数据块。
  2. 如权利要求1所述的存储器控制电路，其特征在于，所述存储器控制电路还包括纠错编码电路，其中：
    所述纠错编码电路用于接收多个原始数据块，根据所述多个原始数据块产生校验数据，并将所述多个数据块输出至所述同或电路，其中所述多个数据块包括所述多个原始数据块和所述校验数据。
  3. 如权利要求1或2所述的存储器控制电路，其特征在于，所述存储器控制电路还包括纠错译码电路，其中：
    所述纠错译码电路用于接收所述读写控制电路输出的所述多个数据块，对所述多个数据块进行译码和纠错，并输出所述多个数据块。
  4. 如权利要求3所述的存储器控制电路，其特征在于：
    所述读写控制电路还用于从所述非易失性存储器中读取并输出关联数据块，所述关联数据块包括所述冗余数据块以及不含错误数据块的所述多个数据块，所述错误数据块为所述多个数据块中错误数据量超过所述纠错译码电路的纠错能力的数据块；
    所述纠错译码电路还用于接收所述读写控制电路输出的所述关联数据块，对所述关联数据块进行译码和纠错，并将所述关联数据块输出至所述同或电路，其中所述关联数据块的错误数据量不超过所述纠错译码电路的纠错能力；
    所述同或电路还用于读取所述纠错译码电路输出中的所述关联数据块，将所述关联数据块做按位同或运算，产生恢复数据块，并输出所述恢复数据块。
  5. 一种存储器控制方法，其特征在于，所述存储器控制方法包括：
    同或电路接收多个数据块，将所述多个数据块做按位同或运算，产生冗余数据块，并将所述多个数据块和所述冗余数据块输出至读写控制电路；
    所述读写控制电路将所述多个数据块和所述冗余数据块写入非易失性存储器，所述非易失性存储器包括多个存储单元，所述多个数据块和所述冗余数据块中用于进行同一位按位同或运算的数据存储于一个所述存储单元中，所述多个存储单元中的每个存储单元的容量为n比特且具有2 n个存储状态，所述多个数据块的个数为n-1个，其中n为大于等于2的整数；
    所述读写控制电路从所述非易失性存储器中读取并输出所述多个数据块。
  6. 如权利要求5所述的存储器控制方法，其特征在于，所述存储器控制方法还包括：
    所述纠错编码电路接收多个原始数据块，根据所述多个原始数据块产生校验数据，并将所述多个数据块输出至所述同或电路，其中所述多个数据块包括所述多个原始数据块和所述校验数据。
  7. 如权利要求5或6所述的存储器控制方法，其特征在于，所述存储器控制方法还包括：
    所述纠错译码电路接收所述读写控制电路输出的所述多个数据块，对所述多个数据块进行译码和纠错，并输出所述多个数据块。
  8. 如权利要求7所述的存储器控制方法，其特征在于，所述存储器控制方法还包括：
    所述读写控制电路从所述非易失性存储器中读取并输出关联数据块，所述关联数据块包括所述冗余数据块以及不含错误数据块的所述多个数据块，所述错误数据块为所述多个数据块中错误数据量超过所述纠错译码电路的纠错能力的数据块；
    所述纠错译码电路接收所述读写控制电路输出的所述关联数据块，对所述关联数据块进行译码和纠错，并将所述关联数据块输出至所述同或电路；
    所述同或电路读取所述纠错译码电路中的所述关联数据块，将所述关联数据块做按位同或运算，产生恢复数据块，并输出所述恢复数据块。
  9. 一种数据存储设备，其特征在于，所述数据存储设备包括存储器控制电路和非易失性存储器，所述存储器控制电路向所述非易失性存储器中写入数据，并从所述非易失性存储器中读取数据，所述存储器控制电路包括同或电路和读写控制电路，其中：
    所述同或电路用于接收多个数据块，将所述多个数据块做按位同或运算，产生冗余数据块，并将所述多个数据块和所述冗余数据块输出至所述读写控制电路；
    所述读写控制电路用于将所述多个数据块和所述冗余数据块写入所述非易失性存储器，所述非易失性存储器包括多个存储单元，所述多个数据块和所述冗余数据块中用于进行同一位按位同或运算的数据存储于一个所述存储单元中，所述多个存储单元中的每个存储单元的容量为n比特且具有2 n个存储状态，所述多个数据块的个数为n-1个，其中n为大于等于2的整数；
    所述读写控制电路还用于从所述非易失性存储器中读取并输出所述多个数据块。
  10. 如权利要求9所述的数据存储设备，其特征在于，所述存储器控制电路还包括纠错编码电路，其中：
    所述纠错编码电路用于接收多个原始数据块，根据所述多个原始数据块产生校验数据，并将所述多个数据块输出至所述同或电路，其中所述多个数据块包括所述多个原始数据块和所述校验数据。
  11. 如权利要求9或10所述的数据存储设备，其特征在于，所述存储器控制电路还包括纠错译码电路，其中：
    所述纠错译码电路用于接收所述读写控制电路输出的所述多个数据块，对所述多个数据块进行译码和纠错，并输出所述多个数据块。
  12. 如权利要求11所述的数据存储设备，其特征在于：
    所述读写控制电路还用于从所述非易失性存储器中读取并输出关联数据块，所述关联数据块包括所述冗余数据块以及不含错误数据块的所述多个数据块，所述错误数据块为所述多个数据块中错误数据量超过所述纠错译码电路的纠错能力的数据块；
    所述纠错译码电路还用于接收所述读写控制电路输出的所述关联数据块，对所述关联数据块进行译码和纠错，并将所述关联数据块输出至所述同或电路；
    所述同或电路还用于读取所述纠错译码电路中的所述关联数据块，将所述关联数据块做按位同或运算，产生恢复数据块，并输出所述恢复数据块。
  13. 一种通信设备，其特征在于，所述通信设备包括存储器控制电路和非易失性存储器，所述存储器控制电路向所述非易失性存储器中写入数据，并从所述非易失性存储器中读取数据，所述存储器控制电路包括同或电路和读写控制电路，其中：
    所述同或电路用于接收多个数据块，将所述多个数据块做按位同或运算，产生冗余数据块，并将所述多个数据块和所述冗余数据块输出至所述读写控制电路；
    所述读写控制电路用于将所述多个数据块和所述冗余数据块写入所述非易失性存储器，所述非易失性存储器包括多个存储单元，所述多个数据块和所述冗余数据块中用于进行同一位按位同或运算的数据存储于一个所述存储单元中，所述多个存储单元中的每个存储单元的容量为n比特且具有2 n个存储状态，所述多个数据块的个数为n-1个，其中n为大于等于2的整数；
    所述读写控制电路还用于从所述非易失性存储器中读取并输出所述多个数据块。
  14. 如权利要求13所述的通信设备，其特征在于，所述存储器控制电路还包括纠错编码电路，其中：
    所述纠错编码电路用于接收多个原始数据块，根据所述多个原始数据块产生校验数据，并将所述多个数据块输出至所述同或电路，其中所述多个数据块包括所述多个原始数据块和所述校验数据。
  15. 如权利要求13或14所述的通信设备，其特征在于，所述存储器控制电路还包括纠错译码电路，其中：
    所述纠错译码电路用于接收所述读写控制电路输出的所述多个数据块，对所述多个数据块进行译码和纠错，并输出所述多个数据块。
  16. 如权利要求15所述的通信设备，其特征在于：
    所述读写控制电路还用于从所述非易失性存储器中读取并输出关联数据块，所述关联数据块包括所述冗余数据块以及不含错误数据块的所述多个数据块，所述错误数据块为所述多个数据块中错误数据量超过所述纠错译码电路的纠错能力的数据块；
    所述纠错译码电路还用于接收所述读写控制电路输出的所述关联数据块，对所述关联数据块进行译码和纠错，并将所述关联数据块输出至所述同或电路；
    所述同或电路还用于读取所述纠错译码电路中的所述关联数据块，将所述关联数据块做按位同或运算，产生恢复数据块，并输出所述恢复数据块。
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100070679A1 (en) * 2008-09-15 2010-03-18 Seagate Technology Llc System and method of managing memory
CN101751334A (zh) * 2009-12-30 2010-06-23 中国人民解放军国防科学技术大学 一种基于还原程序的硬件故障检测方法
US20110107013A1 (en) * 2009-11-03 2011-05-05 Francis Ho High Throughput Flash Memory System
CN102855934A (zh) * 2012-08-23 2013-01-02 上海宏力半导体制造有限公司 非易失性存储器系统及其擦除方法
CN104756193A (zh) * 2013-01-14 2015-07-01 惠普发展公司，有限责任合伙企业 非易失性存储器阵列逻辑

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8769188B2 (en) * 2009-11-18 2014-07-01 Mediatek Inc. Nonvolatile memory controller and method for writing data to nonvolatile memory
KR101984900B1 (ko) * 2012-07-24 2019-05-31 삼성전자 주식회사 메모리 장치 및 상기 메모리 장치의 독출 전압 결정 방법
US9281049B1 (en) * 2014-10-28 2016-03-08 Xilinx, Inc. Read clock forwarding for multiple source-synchronous memory interfaces
KR102245129B1 (ko) * 2014-11-24 2021-04-28 삼성전자 주식회사 멀티레벨 셀을 포함하는 크로스 포인트 메모리 장치 및 크로스 포인트 메모리 장치의 동작방법
CN104679448B (zh) * 2015-02-05 2017-10-03 深圳市硅格半导体有限公司 数据比特流转换的方法和装置
CN107027326B (zh) * 2015-11-25 2018-12-07 华为技术有限公司 存储系统中数据备份的方法及装置
KR20180000199A (ko) * 2016-06-22 2018-01-02 에스케이하이닉스 주식회사 크로스 토크를 보상할 수 있는 인터페이스 회로, 이를 포함하는 반도체 장치 및 시스템

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100070679A1 (en) * 2008-09-15 2010-03-18 Seagate Technology Llc System and method of managing memory
US20110107013A1 (en) * 2009-11-03 2011-05-05 Francis Ho High Throughput Flash Memory System
CN101751334A (zh) * 2009-12-30 2010-06-23 中国人民解放军国防科学技术大学 一种基于还原程序的硬件故障检测方法
CN102855934A (zh) * 2012-08-23 2013-01-02 上海宏力半导体制造有限公司 非易失性存储器系统及其擦除方法
CN104756193A (zh) * 2013-01-14 2015-07-01 惠普发展公司，有限责任合伙企业 非易失性存储器阵列逻辑

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