WO2019198235A1

WO2019198235A1 - Simulation device and simulation program

Info

Publication number: WO2019198235A1
Application number: PCT/JP2018/015580
Authority: WO
Inventors: 鈴木　弘一; 正勝外山; 石川　博章
Original assignee: 三菱電機株式会社
Priority date: 2018-04-13
Filing date: 2018-04-13
Publication date: 2019-10-17

Abstract

According to the present invention, a division and conversion unit (111) divides a guest code of a unit of conversion into one or more guest code blocks, and converts each guest code block into a host code block. A reconversion unit (116) re-divides the guest code of the unit of conversion into one or more guest code blocks of a unit equal to or smaller than a unit of re-division, and converts each guest code block after the re-division into host code blocks, on the basis of an occurrence time of an event processing of a peripheral device and an offset time. A code execution unit (115) executes any one among the host code blocks obtained by the division and conversion unit and the host code blocks obtained by the re-conversion unit.

Description

Simulation apparatus and simulation program

The present invention relates to a technique for simulating the operation of a microcomputer and peripheral devices.

In recent years, software simulators are used in software development for embedded devices in order to start software debugging early. The software simulator is a simulator that simulates the operation of a system in which software operates. The simulated system is composed of a microcomputer and peripheral devices. By using this simulator, software debugging can be performed before the hardware test environment in which the software operates is completed.

A conventional simulator is disclosed in Patent Document 1, for example.
A conventional simulator includes an ISS (instruction set simulator), a peripheral device simulation unit, a host code storage unit, a management table, and a guest code storage unit. The ISS reads guest code, which is a program that runs on a CPU (Central Processing Unit), and divides the guest code into blocks. The ISS then inserts periodic processing into the block, converts the block into a host code block, and executes the host code block. Periodic processing includes simulation time update, interrupt processing, and program counter update. A host code block is stored in the host code storage unit.

In the conventional simulator, the following processing is performed.
First, it is checked whether the next host code address exists based on the program counter.
If the host code does not exist, the guest code is divided, cyclic processing is inserted, and conversion into a host code block is performed.
Next, the ISS reads the host code block from the host code storage unit and executes the read host code block. At this time, the program counter is updated by periodic processing.
Thereafter, when the simulation is not finished, the process for the next host code block is performed.
The conversion unit is a unit that does not span at least an unconditional branch instruction. The block is divided so as not to straddle at least the conditional branch instruction. At least before the branch destination (label), the data is divided into blocks or conversion units.

Japanese Patent No. 5021584

Patent Document 1 discloses a technique for switching a guest code division unit to a smaller division unit according to the presence of a breakpoint and an instruction execution event. However, since event processing of the peripheral device occurs at the associated time, switching cannot be performed in the event processing of the peripheral device.

An object of the present invention is to make it possible to execute a host code block obtained by re-division by dividing a guest code based on an event processing occurrence time of a peripheral device.

The simulation apparatus of the present invention
A division conversion unit that divides the guest code of the conversion unit into one or more guest code blocks, and converts each guest code block into a host code block;
Based on the event processing occurrence time of the peripheral device and the offset time, the guest code of the conversion unit is subdivided into one or more guest code blocks below the subdivision unit, and each guest code block after the subdivision is A re-converter that converts to host code blocks;
A code execution unit that executes either the host code block obtained by the division conversion unit or the host code block obtained by the re-conversion unit;

According to the present invention, it is possible to execute a host code block obtained by re-division by dividing a guest code based on the event processing occurrence time of a peripheral device.

1 is a configuration diagram of a simulation apparatus 100 according to Embodiment 1. FIG. FIG. 3 is a configuration diagram of a simulation unit 110 in the first embodiment. FIG. 3 shows a storage unit 160 in Embodiment 1; 3 is a flowchart of a simulation method according to the first embodiment. FIG. 3 is a diagram illustrating an example of block division according to the first embodiment. FIG. 5 is a diagram illustrating an example of block conversion according to the first embodiment. 5 is a flowchart of subdivision control (S110) in the first embodiment. FIG. 3 shows an example of block re-division in Embodiment 1. 6 is a flowchart of event registration processing in the first embodiment. 6 is a flowchart of event deletion processing according to the first embodiment. The figure which shows the shift | offset | difference of the timing of the event process of a peripheral device and the process of ISS. 2 is a hardware configuration diagram of a simulation apparatus 100 according to Embodiment 1. FIG.

In the embodiment and the drawings, the same reference numerals are given to the same elements and corresponding elements. Description of elements having the same reference numerals will be omitted or simplified as appropriate. The arrows in the figure mainly indicate the flow of data or the flow of processing.

Embodiment 1 FIG.
The simulation apparatus 100 will be described with reference to FIGS.
The simulation apparatus 100 is also called a simulator.

*** Explanation of configuration ***
Based on FIG. 1, the structure of the simulation apparatus 100 is demonstrated.
The simulation apparatus 100 is a computer including hardware such as a processor 101, a memory 102, an auxiliary storage device 103, an input device 104, and a display 105. These hardwares are connected to each other via signal lines.

The processor 101 is an IC (Integrated Circuit) that performs arithmetic processing, and controls other hardware. For example, the processor 101 is a CPU (Central Processing Unit), a DSP (Digital Signal Processor), or a GPU (Graphics Processing Unit).
The memory 102 is a volatile storage device. The memory 102 is also called main memory or main memory. For example, the memory 102 is a RAM (Random Access Memory). Data stored in the memory 102 is stored in the auxiliary storage device 103 as necessary.
The auxiliary storage device 103 is a nonvolatile storage device. For example, the auxiliary storage device 103 is a ROM (Read Only Memory), a HDD (Hard Disk Drive), or a flash memory. Data stored in the auxiliary storage device 103 is loaded into the memory 102 as necessary.
The input device is a keyboard, a mouse, and a pointing device. An example of a pointing device is a touch panel.
The display 105 is a display device.

The simulation apparatus 100 includes elements such as a simulation unit 110, a device simulation unit 120, and an event management unit 130. These elements are realized by software.

The auxiliary storage device 103 stores a simulation program for causing a computer to function as the simulation unit 110, the device simulation unit 120, and the event management unit 130. The simulation program is loaded into the memory 102 and executed by the processor 101.
Furthermore, the auxiliary storage device 103 stores an OS (Operating System). At least a part of the OS is loaded into the memory 102 and executed by the processor 101.
That is, the processor 101 executes the simulation program while executing the OS.
Data obtained by executing the simulation program is stored in a storage device such as the memory 102, the auxiliary storage device 103, a register in the processor 101, or a cache memory in the processor 101.

The memory 102 functions as a guest code storage unit 140, a host code storage unit 150, and a storage unit 160. However, other storage devices may function as the guest code storage unit 140, the host code storage unit 150, and the storage unit 160 instead of the memory 102 or together with the memory 102.

The simulation apparatus 100 may include a plurality of processors that replace the processor 101. The plurality of processors share the role of the processor 101.

The simulation program can be recorded (stored) in a computer-readable manner on a nonvolatile recording medium such as an optical disk or a flash memory.

Next, the guest code storage unit 140 and the host code storage unit 150 will be described.
The guest code storage unit 140 stores a guest code 141.
The host code storage unit 150 stores one or more host code blocks 152 generated based on the guest code 141.

Based on FIG. 2, the simulation part 110 is demonstrated.
The simulation unit 110 is also called an ISS (instruction set simulator).
The simulation unit 110 simulates the CPU of the system to be simulated. A system to be simulated is called a target system.

The simulation unit 110 includes a division conversion unit 111, a program counter 112, an interrupt reception unit 113, a time management unit 114, a code execution unit 115, a reconversion unit 116, and a control unit 117.
The division conversion unit 111 divides the guest code for the conversion unit into one or more guest code blocks before subdivision, inserts periodic processing into each guest code block, and converts each guest code block into a host code. Thus, one or more host code blocks before subdivision are generated. An event execution routine for executing event processing of peripheral devices is not added to the periodic processing inserted by the division conversion unit 111.
The program counter 112 stores an address of an instruction to be executed next, and updates the address as the program progresses in the target system.
The interrupt reception unit 113 simulates an interrupt to the CPU in the target system.
The time management unit 114 calculates the simulation time based on the CPU consumption cycle in the target system, and manages the simulation time. The simulation time is the time in the target system.
The re-conversion unit 116 re-divides the guest code for the conversion unit into one or more guest code blocks equal to or less than the re-division unit based on the event processing occurrence time of the peripheral device and an offset time 162 to be described later. One or more host code blocks after re-division are generated by inserting processing into each guest code block after re-division and converting each guest code block into host code. An event execution routine for executing event processing of peripheral devices is added to the periodic processing inserted by the re-dividing unit 116.
The code execution unit 115 executes either the host code block obtained by the division conversion unit 111 or the host code block obtained by the re-division unit 116.
The control unit 117 performs various controls.

Next, the device simulation unit 120 and the event management unit 130 will be described.
The device simulation unit 120 simulates the operation of peripheral devices in the target system.
The event management unit 130 manages event processing of peripheral devices in the target system.

The storage unit 160 will be described with reference to FIG.
The storage unit 160 stores data such as a management table 161, an offset time 162, a subdivision unit 163, a conversion unit 164, a first status 165, a second status 166, and a change content 167.

The management table 161 associates a guest address with a host address for each guest code block 142 obtained by dividing a part of the guest code 141.
The guest address is the head address of the guest code block 142.
The host address is the head address of the host code block 152 corresponding to the guest code block 142.

The offset time 162 is a time length used for calculating a pre-timer time to be described later. The offset time 162 is also referred to as prefetch timing information. The offset time 162 is input to the simulation apparatus 100 from the outside.

The re-division unit 163 is the maximum size of re-division by the re-conversion unit 116, and is smaller than the maximum size of division by the division-conversion unit 111. For example, the subdivision unit 163 is specified in units of one instruction. The re-division unit 163 is input to the simulation apparatus 100 from the outside.

The conversion unit 164 is a unit for reading the guest code 141. The guest code 141 is read for each conversion unit.
The conversion unit 164 is a unit that does not span at least an unconditional branch instruction. The guest code 141 for the conversion unit is divided so as not to cross at least the conditional branch instruction. Further, the guest code 141 for the conversion unit is divided at least before the branch destination (label).

The first status 165 is a status indicating the presence / absence of a subdivision code.
The re-division code means the host code block 152 after re-division.

The second status 166 is a status indicating before and after subdivision.
Specifically, the second status 166 indicates whether the host address obtained from the management table 161 is the host address of the host code block before re-division or the host address of the host code block after re-division.

The change content 167 is the change content of the management table 161.

*** Explanation of operation ***
The operation of the simulation apparatus corresponds to a simulation method. The procedure of the simulation method corresponds to the procedure of the simulation program.

A simulation method will be described with reference to FIG.
In step S 101, the control unit 117 determines whether there is a host code block 152 corresponding to the program counter 112.
Specifically, the control unit 117 determines whether the host address corresponding to the program counter 112 is set in the management table 161. When the host address corresponding to the program counter 112 is set in the management table 161, there is a host code block 152 corresponding to the program counter 112.
If there is a host code block 152 corresponding to the program counter 112, the process proceeds to step S105.
If there is no host code block 152 corresponding to the program counter 112, the process proceeds to step S102.

In step S102, the division conversion unit 111 divides the guest code 141 for the conversion unit into one or more guest code blocks 142.
Specifically, the division conversion unit 111 reads the guest code 141 corresponding to the conversion unit with the address corresponding to the program counter 112 as the head. Then, the division conversion unit 111 divides the guest code 141 for the conversion unit into one or more guest code blocks 142.

FIG. 5 shows an example of block division.
In FIG. 5, the guest code 141 corresponding to the conversion unit is divided into two guest code blocks 142 including a first guest code block and a second guest code block.

Returning to FIG. 4, the description will be continued from step S103.
In step S 103, the division conversion unit 111 inserts periodic processing into each guest code block 142 and converts each guest code block 142 into a host code block 152.
The periodic processing includes at least simulation time update, interrupt processing, and program counter 112 update.
Then, the division conversion unit 111 stores each host code block 152 in the host code storage unit 150.

FIG. 6 shows an example of block conversion.
In FIG. 6, periodic processing is inserted into each of the first guest code block and the second guest code block. The first host code block is a block obtained by inserting periodic processing into the first guest code block and converting the format of the first guest code block from the format for guest code to the format for host code. The second host code block is a block obtained by inserting periodic processing into the second guest code block and converting the format of the second guest code block from the format for guest code to the format for host code.

Returning to FIG. 4, the description will be continued from step S104.
In step S104, the division conversion unit 111 updates the management table 161.
Specifically, the division conversion unit 111 associates the guest address and the host address with each other for each guest code block 142 and adds them to the management table 161.

In step S105, the control unit 117 acquires the host address corresponding to the program counter 112 from the management table 161.

In step S110, the reconversion unit 116 performs reconversion control.
The reconversion control (S110) will be described later.

In step S120, the code execution unit 115 executes the host code block 152 corresponding to the program counter 112.

Specifically, the code execution unit 115 operates as follows.
First, the code execution unit 115 acquires a host address corresponding to the program counter 112 from the management table 161.
Next, the code execution unit 115 reads the host code block 152 corresponding to the acquired host address from the host code storage unit 150.
Then, the code execution unit 115 executes the read host code block 152.

When the second status 166 is “before subdivision”, the host code block 152 before subdivision is executed.
When the second status 166 is “after re-division”, the post-division host code block 152 is executed.

When executing a periodic process to which an event execution routine is added, the code execution unit 115 operates as follows.
First, the code execution unit 115 acquires the current time (simulation time) from the time management unit 114.
Next, information on each event whose event occurrence time is earlier than the current time among the events registered in the event queue is acquired from the event management unit 130.
Then, the code execution unit 115 executes each event whose event occurrence time is earlier than the current time based on the acquired information. That is, the code execution unit 115 executes each event whose event occurrence time has passed but has not been executed.
Information about each event to be executed is deleted from the event queue by the event management unit 130. Furthermore, the pre-timer time described later is updated by the event management unit 130. The operation of the event management unit 130 will be described later.

In step S131, the control unit 117 determines whether the simulation is finished.
Specifically, the control unit 117 determines whether the program counter 112 indicates the final address of the guest code 141. When the program counter 112 indicates the final address of the guest code 141, the simulation ends.
However, the control unit 117 may determine whether the simulation is completed by another method. For example, the control unit 117 may determine that the simulation has ended when the simulation time is after a predetermined end time.
When the simulation is finished, the process of the simulation method is finished.
If the simulation has not ended, the process proceeds to step S101.

Based on FIG. 7, the reconversion control (S110) will be described.
In step S111, the reconversion unit 116 compares the current time (simulation time) with the pretimer time.
Specifically, the reconversion unit 116 acquires the current time from the time management unit 114, acquires the pretimer time from the event management unit 130, and compares the current time with the pretimer time.
The pre-timer time is a time that is earlier by the offset time 162 than the earliest event occurrence time among one or more event occurrence times registered in the event queue. That is, the pre-timer time is a time that is earlier than the earliest occurrence time among the occurrence times of unexecuted events by the offset time 162.
If the current time is a time after the pretimer time, the process proceeds to step S112.
If the current time is a time before the pre-timer time, the process proceeds to step S116.
However, if the event is not registered in the event queue, the process proceeds to step S116 regardless of the current time.

In step S112, the reconversion unit 116 refers to the first status 165 and determines the presence / absence of a subdivision code.
If there is no re-division code, the process proceeds to step S1131.
If there is a subdivision code, the process proceeds to step S114.

In step S1131, the re-conversion unit 116 re-divides the guest code 141 for the conversion unit into one or more guest code blocks 142.
The guest code 141 for the conversion unit is the same as that divided in step S102 (see FIG. 4).
Specifically, the reconversion unit 116 divides the guest code 141 for the conversion unit into one or more guest code blocks 142 with the repartition unit 163 as the maximum size of each guest code block. The conversion unit 164 is a unit in which neither a conditional branch instruction nor a branch destination (label) is present.

In step S1132, the re-conversion unit 116 inserts the periodic process to which the event execution routine is added into each guest code block 142 after the re-division, and converts each guest code block 142 into the host code block 152.
Thereby, one or more host code blocks 152 corresponding to the one or more guest code blocks 142 after the re-division are obtained.
The event execution routine is a routine for executing each event having an occurrence time before the current time (simulation time) among events registered in the event queue. That is, the event execution routine is a routine for executing each event whose occurrence time is before the current time but is not executed.

In step S 1133, the reconversion unit 116 updates the management table 161.
Specifically, the re-conversion unit 116 updates the address set set in the management table 161 to the address set after re-division. Each address set is a set of a guest address and a host address.

In step S 1134, the reconversion unit 116 stores the change content 167 of the management table 161. Further, the re-conversion unit 116 sets “division code present” to the first status 165 and sets “after division” to the second status 166.
After step S1134, the re-division control (S110) ends.

FIG. 8 shows an example of block subdivision.
In FIG. 8, the guest code 141 for the conversion unit is subdivided into a first guest code block and a second guest code block. Periodic processing is inserted into each of the first guest code block and the second guest code block. An event execution routine is added to each periodic process of the first guest code block and the second guest code block. The first host code block is a block obtained by inserting a periodic process with an event execution routine added to the first guest code block. The second host code block is a block obtained by inserting a periodic process with an event execution routine added to the second guest code block.

Returning to FIG. 7, the description will be continued.
Next, a case where the current time is a time after the pre-timer time and the first status 165 is “with re-division code” will be described.
In step S 114, the reconversion unit 116 determines the second status 166.
If the second status 166 is “before subdivision”, the process proceeds to step S115.
When the second status 166 is “after subdivision”, the subdivision control (S110) ends.

In step S 115, the reconversion unit 116 changes the management table 161 based on the change content 167. Further, the re-conversion unit 116 changes the second status 166 from “before re-division” to “after re-division”.
After step S115, the subdivision control (S110) ends.

Next, a case where the current time is a time before the pre-timer time will be described.
In step S 116, the reconversion unit 116 determines the second status 166.
When the second status 166 is “after subdivision”, the restoration condition is satisfied, and the process proceeds to step S117.
When the second status 166 is “before re-division”, the re-division control (S110) ends.

In step S117, the re-conversion unit 116 returns the management table 161 to the state before the re-division based on the change content 167. Furthermore, the re-conversion unit 116 changes the second status 166 from “after re-division” to “before re-division”.
After step S117, the re-division control (S110) ends.

The event registration process will be described based on FIG.
In step S 201, the device simulation unit 120 passes the event occurrence time and the reference to the callback function to the event management unit 130.
The event management unit 130 receives the event occurrence time and the reference to the callback function from the device simulation unit 120.

In step S202, the event management unit 130 registers the event occurrence time and the reference to the callback function in the event queue.
Specifically, the event management unit 130 inserts a set of the event occurrence time and the reference to the callback function into the event queue so that the event occurrence times are arranged in the order from the earliest time in the event queue.

In step S203, the event management unit 130 updates the pretimer time.
Specifically, the event management unit 130 selects the earliest event occurrence time from the event queue, and calculates a time that is an offset time 162 before the selected event occurrence time. Then, the event management unit 130 updates the pretimer time with the calculated time.

Based on FIG. 10, the event deletion process will be described.
In step S211, the event management unit 130 deletes the executed event from the event queue.
Specifically, the event management unit 130 deletes a set of the event occurrence time and the reference to the callback function from the event queue for the executed event.

In step S212, the event management unit 130 updates the pretimer time.
The update method is the same as the method in step S203 (see FIG. 9).

*** Effects of Embodiment 1 ***
First, a simulator to be compared with the simulation apparatus 100 will be described as a target simulator, and then the effects of the simulation apparatus 100 will be described.
In the target simulator, it may be necessary to simulate the operation of peripheral devices of the CPU. There are roughly two types of peripheral device operations. The first operation is an operation that accepts read access or write access from the CPU and responds to the accepted access. The second operation is an operation that performs processing spontaneously when a specific time has elapsed from a certain timing. For example, as a voluntary process, a process that generates an interrupt from a timer at regular intervals, a process that detects reception from the outside after a certain period of time has elapsed from a transmission process in a communication device, or after analog-digital conversion is started For example, a process of terminating the analog-digital conversion when a predetermined time has elapsed. Such spontaneous processing that occurs at the time is called event processing of peripheral devices.
When such an operation of the peripheral device is simulated by the target simulator, it is considered that the first operation can be included in the ISS instruction execution. However, the second operation is considered to execute event processing that matches the simulation time at that time in the periodic processing.

In the target simulator, if the block division size is large, the timing difference between the event processing of the peripheral device and the ISS processing becomes large.
Based on FIG. 11, a timing shift between the event processing of the peripheral device and the ISS processing will be described.
In FIG. 11, the processing of the target simulator is described in time order from top to bottom, and ISS processing (1), periodic processing (1), ISS processing (2), and periodic processing (2) are executed in order.
In the periodic process (1), the event process (1) of the peripheral device is executed. The event process (1) occurrence time is the event (1) occurrence time shown in FIG. 11 on the same time axis as the ISS process (1). However, in a general high-speed simulator for software development, the ISS process and the periodic process are not executed in parallel, and the ISS process and the periodic process are executed in order as shown in FIG. This is because parallel operation greatly reduces the overall simulation speed. As a result, there arises a deviation that the event (1) processing that should be processed at the time of occurrence of the event (1) is processed by the periodic processing (1). This shift is due to the fact that the ISS process (that is, instruction execution) in the shaded area shown in FIG. 11 should be executed after the event (1) process, but is executed before the event (1) process. It means a difference in context. This shift is called a timing shift between the event processing of the peripheral device and the ISS processing. In FIG. 11, this deviation is referred to as a timing deviation (1) between the event process and the ISS process.
The difference in timing between the event processing of the peripheral device and the ISS processing increases as the block size increases.

Also, in the target simulator, there is no means to divide the block into smaller parts near the timing when the event processing of the peripheral device is executed. For this reason, unless all the blocks are divided into small pieces, the timing shift between the event processing of the peripheral device and the ISS processing cannot be reduced. However, dividing all blocks into smaller blocks increases the number of blocks and the number of periodic processes to be executed. Therefore, the entire simulation speed is reduced.

In the simulation apparatus 100, the guest code is subdivided based on the offset time and the event occurrence time. Therefore, the code before and after the occurrence of the event can be subdivided finely, and the timing deviation between the event processing of the peripheral device and the ISS processing can be reduced. Furthermore, since re-division is performed only on the code before and after the occurrence of the event, a reduction in processing speed due to re-division can be reduced.
Further, in the simulation apparatus 100, since the state before the re-division is restored based on the offset time and the event occurrence time, the re-division is performed if the next event does not occur for a while even after the re-division is performed once. The previous state is restored (see step S117 in FIG. 7). For this reason, a decrease in processing speed due to re-division becomes temporary, and the decrease in processing speed can be reduced.
Moreover, in the simulation apparatus 100, by making the subdivision unit changeable, it is possible to prevent the division from becoming finer than necessary depending on the simulation situation. As a result, a decrease in processing speed is reduced.
In the simulation apparatus 100, the presence / absence of the event execution routine can be switched together with the re-division. Therefore, the event execution routine can be omitted in a state where no event execution is necessary, and the execution speed can be increased.

*** Other configurations ***
In Embodiment 1, time and time may be expressed using the number of cycles.

*** Supplement to the embodiment ***
Based on FIG. 12, the hardware configuration of the simulation apparatus 100 will be described.
The simulation apparatus 100 includes a processing circuit 109.
The processing circuit 109 is hardware that implements the simulation unit 110, the device simulation unit 120, and the event management unit 130.
The processing circuit 109 may be dedicated hardware or the processor 101 that executes a program stored in the memory 102.

When the processing circuit 109 is dedicated hardware, the processing circuit 109 is, for example, a single circuit, a composite circuit, a programmed processor, a parallel programmed processor, an ASIC, an FPGA, or a combination thereof.
ASIC is an abbreviation for Application Specific Integrated Circuit, and FPGA is an abbreviation for Field Programmable Gate Array.
The simulation apparatus 100 may include a plurality of processing circuits that replace the processing circuit 109. The plurality of processing circuits share the role of the processing circuit 109.

In the processing circuit 109, some functions may be realized by dedicated hardware, and the remaining functions may be realized by software or firmware.

Thus, the processing circuit 109 can be realized by hardware, software, firmware, or a combination thereof.

The embodiment is an example of a preferred embodiment and is not intended to limit the technical scope of the present invention. The embodiment may be implemented partially or in combination with other embodiments. The procedure described using the flowchart and the like may be changed as appropriate.

100 simulation device, 101 processor, 102 memory, 103 auxiliary storage device, 104 input device, 105 display, 109 processing circuit, 110 simulation unit, 111 division conversion unit, 112 program counter, 113 interrupt reception unit, 114 time management unit, 115 Code execution unit, 116 re-conversion unit, 117 control unit, 120 device simulation unit, 130 event management unit, 140 guest code storage unit, 141 guest code, 142 guest code block, 150 host code storage unit, 152 host code block, 160 Storage unit, 161 management table, 162 offset time, 163 subdivision unit, 164 conversion unit, 165 first status, 166 second status, 167 change The contents, 168 Puretaima time.

Claims

A division conversion unit that divides the guest code of the conversion unit into one or more guest code blocks, and converts each guest code block into a host code block;
Based on the event processing occurrence time of the peripheral device and the offset time, the guest code of the conversion unit is subdivided into one or more guest code blocks below the subdivision unit, and each guest code block after the subdivision is A re-converter that converts to host code blocks;
A simulation apparatus comprising: a code execution unit that executes either a host code block obtained by the division conversion unit or a host code block obtained by the reconversion unit.
The code execution unit is a host code block obtained by the reconversion unit when the simulation time is a time after the pre-timer time that is earlier than the earliest occurrence time of occurrence times of unexecuted events by the offset time. The simulation apparatus according to claim 1, wherein:
The simulation apparatus according to claim 1, wherein the re-conversion unit re-divides the guest code of the conversion unit with the re-division unit as a maximum size.
The division conversion unit inserts a periodic process to which an event execution routine for executing the event process is not added into a guest code block, and the guest code block into which the periodic process to which the event execution routine is not added is inserted as a host code Convert to block,
The reconversion unit inserts a periodic process to which the event execution routine is added into a guest code block, and converts the guest code block into which the periodic process to which the event execution routine is added is converted into a host code block. The simulation apparatus according to any one of claims 1 to 3.
A division conversion process for dividing a guest code of a conversion unit into one or more guest code blocks, and converting each guest code block into a host code block;
Based on the event processing occurrence time of the peripheral device and the offset time, the guest code of the conversion unit is subdivided into one or more guest code blocks below the subdivision unit, and each guest code block after the subdivision is Re-conversion process to convert to host code block;
A simulation program for causing a computer to execute a code execution process for executing any one of a host code block obtained by the division conversion process and a host code block obtained by the reconversion process.