WO2019196927A1 - Device and processor for implementing resource index replacement - Google Patents

Device and processor for implementing resource index replacement Download PDF

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Publication number
WO2019196927A1
WO2019196927A1 PCT/CN2019/082422 CN2019082422W WO2019196927A1 WO 2019196927 A1 WO2019196927 A1 WO 2019196927A1 CN 2019082422 W CN2019082422 W CN 2019082422W WO 2019196927 A1 WO2019196927 A1 WO 2019196927A1
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WIPO (PCT)
Prior art keywords
instruction
resource index
index
type resource
unit
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Ceased
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PCT/CN2019/082422
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English (en)
French (fr)
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WO2019196927A9 (en
Inventor
Chang Liu
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Hangzhou C Sky Microsystems Co Ltd
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Hangzhou C Sky Microsystems Co Ltd
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Publication date
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Priority to EP19786104.0A priority Critical patent/EP3769213A4/en
Priority to US16/488,435 priority patent/US11340905B2/en
Priority to JP2020554898A priority patent/JP7325437B2/ja
Publication of WO2019196927A1 publication Critical patent/WO2019196927A1/en
Publication of WO2019196927A9 publication Critical patent/WO2019196927A9/en
Anticipated expiration legal-status Critical
Priority to US17/660,565 priority patent/US11734014B2/en
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5011—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
    • G06F9/5016—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals the resource being the memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G06F9/384—Register renaming
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
    • G06F9/5038—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals considering the execution order of a plurality of tasks, e.g. taking priority or time dependency constraints into consideration

Definitions

  • register renaming The amount of resources used for storing execution results and execution scheduling has become a critical factor that impacts the cost of processors.
  • a processor needs to rename a general-purpose register of instructions as a physical register index or other resource indexes having similar functions while the processor is performing scheduling, transmission, execution, and writeback, so as to eliminate spurious correlation among the instructions. This renaming process is referred to as register renaming.
  • the present disclosure provides adevice for implementing resource index replacement, comprising an instruction scheduling unit configured to receive a first type resource index from a resource allocating unit and then issue an instruction to an instruction executing unit for execution, to receive a second type resource index from the resource allocating unit, to execute the instruction from the instruction scheduling unit, and to issue a result of the instruction execution and the second type resource index to a result storing unit.
  • the result storing unit comprises a plurality of resource for storing instruction execution results and execution results.
  • the result storing unit is configured to allocate the first type resource index to an instruction entering the instruction scheduling unit and to allocate the second type resource index to an instruction entering the instruction execution unit.
  • the present disclosure also provides aprocessor comprising the above device for implementing resource index replacement.
  • the present disclosure provides a method for implementing resource index replacement.
  • FIG. 1 is a schematic diagram of an exemplarydevice for implementing resource index replacement, according to someembodiments of the present disclosure.
  • FIG. 2 is a schematic diagram of an exemplaryinstruction composition and resource index, according to someembodiments of the present disclosure.
  • FIG. 3 is a schematic diagram of an exemplary device for implementing resource index replacement after receiving a first instruction, according to someembodiments of the present disclosure.
  • FIG. 4 is a schematic diagram of an exemplary device for implementing resource index replacement after receiving a second instruction, according to someembodiments of the present disclosure.
  • FIG. 5 is a schematic diagram of an exemplary device for implementing resource index replacement after executing a first instruction, according to someembodiments of the present disclosure.
  • FIG. 6 is a schematic diagram of an exemplary device for implementing resource index replacement after executing a second instruction, according to someembodiments of the present disclosure.
  • Register renaming is a technique that eliminates these false data dependencies and that achieves better processor performance by allowing superscalar, speculative, or out-of-order execution of instructions.
  • the amount of resources available for renaming determines the number of processors capable of speculative execution. More resources dedicated to renaming lead to speculative execution of more instructions by the processors, which in turn leads to higher processor performance.
  • a large quantity of resources dedicated to renaming increases the area and timing cost of the processors, thereby causing the overall processor cost to rise.
  • FIG. 1 is a schematic diagram of an exemplary device for implementing resource index replacement, according to some embodiments of the present disclosure.
  • device 10 comprises an instruction scheduling unit 20, an instruction executing unit 30, a result storing unit 40, and a resource allocating unit 50.
  • Instruction scheduling unit 20 includes circuitryconfigured to receive a first type resource index from resource allocating unit 50 and to store the index and a corresponding instruction for later transmission to an instruction executing unit 30.
  • Instruction executing unit 30 includes circuitryconfigured to receive a second type resource index from resource allocating unit 50, to receive the instruction from the instruction scheduling unit 20, to execute the instruction, and to issuean execution result of the instruction execution and the second type resource index to result storing unit 40.
  • Result storing unit 40 comprises a plurality of resources 41 for storing instruction execution results.
  • Result storing unit 40 includes circuitryconfigured toreceive execution results from instruction executing unit 30 and store the execution results in resources 41.
  • Resources 41 are configured to be designated by the second type resource index.
  • Resource allocating unit50 includes circuitryconfigured to allocate the first type resource index to an instruction and issue the instruction to instruction scheduling unit 20 and to allocate the second type resource index to an instruction and issue the instruction toinstruction executing unit 30.
  • resource allocating unit50 allocates the first type resource index when an instruction enters instruction scheduling unit 20, and replaces the first type resource index with the second type resource index when the instruction is issuedby instruction scheduling unit 20 to instruction executing unit 30.
  • the resource allocated by resource allocating unit 50 to an instruction when the instruction enters instruction scheduling unit 20 does not correspond to resources 41 of result storing unit 40.
  • the second type resource index used to replace thefirst type resource index by resource allocating unit 50 when the instruction is issuedby instruction scheduling unit 20 to instruction executing unit 30 corresponds to resources 41 of result storing unit 40.
  • the instruction comprises at least one of a source operand index ora targetoperand index.
  • Resource allocating unit 50 implements the allocation of the first type resource index by replacing the targetoperand index with the first type resource index.
  • the sourceoperand index of the instruction corresponds to a target operand index of a secondinstruction
  • resource allocating unit 50 replaces the source operand index of the instruction with the first type resource index of the second instruction.
  • the first type resource index of the secondinstruction is replaced by the second type resource index
  • the first type resource index ofthe instruction is simultaneously replaced by the second type resource index.
  • the instruction can be issuedby instruction scheduling unit 20 to instruction executing unit 30 only when instruction executing unit 30 generates an execution result of the second instruction.
  • resource allocating unit 50 allocates a first type resource index to an instruction when the instruction enters instruction scheduling unit 20 and replaces the first type resource index with a second type resource index when the instruction is issuedby instruction scheduling unit 20 to instruction executing unit 30, and result storing unit 40 stores execution results according to the second type resource index from the instruction executing unit 30.
  • the present disclosure can prevent overly early allocation of the second type resource index when the instruction enters instruction scheduling unit 20, thereby reducing the demand for resource quantities in result storing unit 40 and improving the resource utilization efficiency.
  • Embodiments of the present disclosure further provide aprocessor for implementing resource index replacement. It is appreciated that the processor can comprise the device for implementing resource index replacement described above (e.g., device 10) .
  • an instruction executed by the processor comprises any number of targetoperands and source operands.
  • FIG. 2 is a schematic diagram of an exemplary instruction composition and resource index, according to some embodiments of the present disclosure.
  • instruction 92 comprises one targetoperand index 61 and one source operand index 62, both of which are a general-purpose register index.
  • the source operand is a targetoperand of another instruction 91. Therefore, instruction 91 corresponds to instruction 92 or is referred to as a producer instruction of instruction 92.
  • resource allocating unit 50 of the processor renames the targetoperand as a physical register tag71.
  • the tag is the first type resource index and does not correspond to a physical register of result storing unit 40 (e.g., resources 41 of result storing unit 40 shown in FIG. 1) .
  • resource allocating unit 50 also renames the source operand as a physical register tagof the targetoperand of the producer instructionor a physical register index.
  • the latter is the second type resource index and corresponds to a physical register of result storing unit 40.
  • instruction 92 when instruction executing unit 30 generates an execution result of instruction 91, instruction 92 can be issued from instruction scheduling unit 20 to instruction executing unit 30.
  • instruction 92 When instruction 92 is issuedfrom instruction scheduling unit 20 to instruction executing unit 30, instruction 92’s physical register tag71 is replaced by physical register index 82.
  • instruction scheduling unit 20 obtains the execution result from instruction 91 according to physical register tag72 of the source operand or physical register index 82, and issues the execution result from instruction 91 asthe source operand of instruction 92 to instruction executing unit 30.
  • Instruction executing unit 30 executes instruction 92 and then issuesan execution result of instruction 92 and physical register index 81 to result storing unit 40.
  • Result storing unit 40 stores the execution result of instruction 92 in a physical register indicated by physical register index 81.
  • FIG. 3 is a schematic diagram of an exemplary device for implementing resource index replacement after receiving a first instruction, according to some embodiments of the present disclosure.
  • the target register index is the general-purpose register r1
  • the source operand index is the general-purpose register r2.
  • Resource allocating unit 50 allocates a physical register tagT3 to replace r1.
  • FIG. 4 is a schematic diagram of an exemplary device for implementing resource index replacement after receiving a second instruction, according to some embodiments of the present disclosure.
  • instruction92enters instruction scheduling unit 20 the target register index is general-purpose register r3, and the source operand index is general-purpose register r1.
  • the source operand is the same as the target operand of instruction91, and therefore, instruction91is a producer instruction of instruction92.
  • resource allocating unit 50 allocates a new physical register tagT7 to replace r3 while source operand index r1 of instruction92is replaced by physical register tagT3, which also represents the target operand of instruction91.
  • FIG. 5 is a schematic diagram of an exemplary device for implementing resource index replacement afterexecuting a first instruction, according to some embodiments of the present disclosure.
  • resource allocating unit 50 replaces physical register tagT3 with a physical register index P6.
  • Physical register index P6 corresponds to a specificphysical register in result storing unit 40, namely physical register No. 6.
  • source operand index T3 of instruction92 is also replaced by physical register index P6.
  • FIG. 6 is a schematic diagram of an exemplary device for implementing resource index replacement after executing a second instruction, according to some embodiments of the present disclosure.
  • instruction executing unit30 issuesan execution result and physical register index P6 to result storing unit 40.
  • Result storing unit 40 stores the execution result to the physical register No. 6.
  • instruction92 can be issued from instruction scheduling unit 20 to instruction executing unit 30.
  • instruction scheduling unit can obtain the execution result ofinstruction91via physical register index P6 and issuesthe execution result as a source operand of instruction 92 to instruction executing unit 30. While instruction 92 is issued to instruction executing unit 30, resource allocating unit 50 replaces the physical register tagT7 with a physical register index P0. Physical register index P0 corresponds to a specific physical register in result storing unit 40, namely physical register No. 0. Afterinstruction executing unit30 generates an execution result for instruction 92, result storing unit 40 can store the execution result to the physical register No. 0.
  • Embodiments of the present disclosure further provide amethodfor implementing resource index replacement. It is appreciated that the method can be implemented by the device (e.g., device 10) and the processor described above.

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Devices For Executing Special Programs (AREA)
PCT/CN2019/082422 2018-04-13 2019-04-12 Device and processor for implementing resource index replacement Ceased WO2019196927A1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP19786104.0A EP3769213A4 (en) 2018-04-13 2019-04-12 DEVICE AND PROCESSOR FOR IMPLEMENTING A RESOURCE INDEX REPLACEMENT
US16/488,435 US11340905B2 (en) 2018-04-13 2019-04-12 Device and processor for implementing resource index replacement
JP2020554898A JP7325437B2 (ja) 2018-04-13 2019-04-12 リソースインデックス置換を実施するデバイス及びプロセッサ
US17/660,565 US11734014B2 (en) 2018-04-13 2022-04-25 Device and processor for implementing resource index replacement

Applications Claiming Priority (2)

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CN201810331737.X 2018-04-13
CN201810331737.XA CN108614736B (zh) 2018-04-13 2018-04-13 实现资源索引替换的装置及处理器

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US16/488,435 A-371-Of-International US11340905B2 (en) 2018-04-13 2019-04-12 Device and processor for implementing resource index replacement
US17/660,565 Continuation US11734014B2 (en) 2018-04-13 2022-04-25 Device and processor for implementing resource index replacement

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WO2019196927A1 true WO2019196927A1 (en) 2019-10-17
WO2019196927A9 WO2019196927A9 (en) 2020-08-20

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11340905B2 (en) 2018-04-13 2022-05-24 C-Sky Microsystems Co., Ltd. Device and processor for implementing resource index replacement
JP2023549058A (ja) * 2020-11-10 2023-11-22 インターナショナル・ビジネス・マシーンズ・コーポレーション 発行時間におけるマイクロプロセッサ・レジスタ・タグの割り当て

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114428638B (zh) * 2020-10-29 2026-03-20 杭州中天微系统有限公司 指令发射单元、指令执行单元、相关装置和方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050138334A1 (en) 2003-12-23 2005-06-23 Intel Corporation Late allocation of registers
CN1650258A (zh) * 2002-04-25 2005-08-03 皇家飞利浦电子股份有限公司 可扩展处理器中的自动任务分配
CN102422262A (zh) * 2009-05-08 2012-04-18 松下电器产业株式会社 处理器
CN105786498A (zh) * 2016-02-25 2016-07-20 广州阿里巴巴文学信息技术有限公司 用于修改应用程序的方法、设备和电子设备
CN108614736A (zh) * 2018-04-13 2018-10-02 杭州中天微系统有限公司 实现资源索引替换的装置及处理器

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI230357B (en) * 2003-12-19 2005-04-01 Sunplus Technology Co Ltd Device and method for writing data in a processor to memory at unaligned location
CN102495724A (zh) * 2011-11-04 2012-06-13 杭州中天微系统有限公司 一种加快存储指令执行效率的数据处理器
US9996348B2 (en) * 2012-06-14 2018-06-12 Apple Inc. Zero cycle load
US9652246B1 (en) * 2012-12-20 2017-05-16 Marvell International Ltd. Banked physical register data flow architecture in out-of-order processors
CN104216681B (zh) * 2013-05-31 2018-02-13 华为技术有限公司 一种cpu指令处理方法和处理器
CN105242905B (zh) * 2015-10-29 2018-03-09 华为技术有限公司 数据假相关的处理方法和装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1650258A (zh) * 2002-04-25 2005-08-03 皇家飞利浦电子股份有限公司 可扩展处理器中的自动任务分配
US20050138334A1 (en) 2003-12-23 2005-06-23 Intel Corporation Late allocation of registers
CN102422262A (zh) * 2009-05-08 2012-04-18 松下电器产业株式会社 处理器
CN105786498A (zh) * 2016-02-25 2016-07-20 广州阿里巴巴文学信息技术有限公司 用于修改应用程序的方法、设备和电子设备
CN108614736A (zh) * 2018-04-13 2018-10-02 杭州中天微系统有限公司 实现资源索引替换的装置及处理器

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11340905B2 (en) 2018-04-13 2022-05-24 C-Sky Microsystems Co., Ltd. Device and processor for implementing resource index replacement
US11734014B2 (en) 2018-04-13 2023-08-22 C-Sky Microsystems Co., Ltd. Device and processor for implementing resource index replacement
JP2023549058A (ja) * 2020-11-10 2023-11-22 インターナショナル・ビジネス・マシーンズ・コーポレーション 発行時間におけるマイクロプロセッサ・レジスタ・タグの割り当て
JP7740847B2 (ja) 2020-11-10 2025-09-17 インターナショナル・ビジネス・マシーンズ・コーポレーション 発行時間におけるマイクロプロセッサ・レジスタ・タグの割り当て

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US20210334131A1 (en) 2021-10-28
CN108614736B (zh) 2021-03-02
WO2019196927A9 (en) 2020-08-20
JP7325437B2 (ja) 2023-08-14
EP3769213A1 (en) 2021-01-27
EP3769213A4 (en) 2021-05-19
US20220244963A1 (en) 2022-08-04
CN108614736A (zh) 2018-10-02
US11340905B2 (en) 2022-05-24
JP2021520553A (ja) 2021-08-19
US11734014B2 (en) 2023-08-22

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