WO2019196634A1

WO2019196634A1 - Data processing method and apparatus

Info

Publication number: WO2019196634A1
Application number: PCT/CN2019/079438
Authority: WO
Inventors: 汪明; 陈平
Original assignee: 华为技术有限公司
Priority date: 2018-04-13
Filing date: 2019-03-25
Publication date: 2019-10-17
Also published as: CN110377534B; CN110377534A

Abstract

Embodiments of the present invention relate to the technical field of data processing. Disclosed are a data processing method and apparatus. The data processing apparatus comprises: a graphics processing unit, a service processing device, and a first memory management unit. The graphics processing unit is used for requesting first data corresponding to a first virtual address; the service processing device is used for converting the first virtual address into a second virtual address and outputting the second virtual address to the first memory management unit; the first memory management unit is used for searching for a first physical address corresponding to the second virtual address according to a first mapping table; the service processing device is also used for obtaining second data stored at the first physical address in an external memory; the service processing device is further used for processing the second data to obtain the first data, and outputting the first data to the graphics processing unit without a bus and the external memory.

Description

Data processing method and device

The present application claims priority to Chinese Patent Application No. 201 810 301 312 5.9, filed on Apr. 13, 2018, the entire disclosure of which is incorporated herein by reference. .

Technical field

The present invention relates to the field of data processing technologies, and in particular, to a data processing method, apparatus, and computer readable medium.

Background technique

In the consumer electronics fields such as mobile phones and televisions, mobile phones and 4K TVs that support 4K video playback are gradually becoming popular, and 8K TVs are gradually entering people's lives. As the resolution of video increases, the demand for system bandwidth is also increasing. Chip designers generally use image data compression technology to reduce the bandwidth of the system.

However, in the same chip, if two functional modules that need to directly transmit data use different compression technologies, there will be compatibility problems between the two. A typical scene, such as panoramic video playback, needs to send the decoded video data to a graphics processing unit (GPU) for rendering, and then output to the display for display. If the GPU and the decoder used in a video playback device respectively use different compression technologies, for example, the GPU adopts a first compression technology, and the decoder uses a second compression technology, a first compression technique, and a second. If the compression technique is different, the data decoded by the decoder cannot be directly sent to the GPU for processing. That is to say, when the compression technology used by the GPU and the decoder is different, the GPU cannot recognize or directly use the data output by the decoder. This problem is more common when the decoder and GPU are provided by different vendors. It can be seen that when the GPU and a certain functional module are incompatible, the GPU cannot recognize the data output by the function module, and the data that is not recognized or used by the GPU needs to be converted into data that the GPU can recognize or use and output to the GPU.

A problem for converting data that is not identifiable or used by the GPU to data that the GPU can recognize or use and output to the GPU. Currently, a technical solution adopted is to convert data that is not identifiable or used by the GPU into data recognizable or used by the GPU through a separate service processing device and store the data in the memory, and the GPU reads the identifiable or used data from the memory. And process it. Please refer to FIG. 1. FIG. 1 is a schematic flowchart of converting data that is not recognized or used by a GPU into data that can be recognized or used by a GPU and output to a GPU. As shown in FIG. 1, 101 denotes data that the GPU does not recognize or use, 102 denotes a service processing device, 103 denotes data that the GPU can recognize or use, and 104 denotes a GPU. The service processing device converts data that is unrecognizable or used by the GPU into data that the GPU can recognize or use, and stores the data in the memory, and the GPU reads the identifiable or used data from the memory through the bus. In this scenario, the business processing device needs to write the data that the output GPU can recognize or use to the memory, and the GPU needs to read the identifiable or used data from the memory. It can be seen that, in the above technical solution, converting data that is not recognized or used by the GPU into data that can be recognized or used by the GPU and outputting to the GPU requires a lot of system bandwidth.

Summary of the invention

The present application provides a data processing method and apparatus for conserving system bandwidth in converting data that is unrecognizable or used by a GPU into data that the GPU can recognize or use and output to the GPU.

The first aspect of the present invention provides a data processing apparatus, including: a graphics processor, a service processing device, and a first memory management unit (MMU); the graphics processor and the first memory management The unit is respectively coupled to the service processing device; the graphics processor is configured to request first data corresponding to the first virtual address, the first data is data processed by the service processing device and can be used by the graphics processor The service processing device is configured to convert the first virtual address into a second virtual address and output the second virtual address to the first memory management unit, where the second virtual address corresponds to And the first memory management unit is configured to search for a first physical address corresponding to the second virtual address according to the first mapping table; and the service processing device is further used by the service processing device. Acquiring the second data stored in the first physical address in the memory, the second data cannot be used or recognized by the graphics processor The data processing device is coupled to the memory via a bus; the service processing device is further configured to process the second data to obtain the first data, in the absence of the bus or one of the memories or The first data is output to the graphics processor in the case of full participation. The second data and the first data are data of different types or formats.

Optionally, the service processing apparatus is configured to convert the second data into the first data to enable the graphics processor to use the first data. Optionally, the service processing apparatus includes at least one of: a decompression unit, a compression unit, a decryption unit, or an encryption unit. The business processing apparatus may perform at least one of a decompression operation, a compression operation, a decryption operation, or an encryption operation. For example, a typical example of the service processing device is a decompression unit. In the present application, the service processing device can implement various data processing operations and can be applied to multiple scenarios.

Optionally, the first memory management unit may map the second virtual address to the first physical address according to the first mapping table. The first mapping table includes a correspondence between at least one virtual address and at least one physical address. The service processing apparatus may implement an address translation function to convert the first virtual address into the second virtual address. The first mapping table may be configured for driver software running by the graphics processor or other processor.

In the present application, in a case where the data processing device does not store the first data requested by the graphics processor, the service processing device acquires the second data, processes the second data to obtain the first data, and outputs the first data to the graphics processor. Data that is unrecognizable or used by the GPU can be converted to and recognized by the GPU and output to the graphics processor, saving system bandwidth.

Optionally, the channel for transmitting the second data between the service processing device and the graphics processor is an interface other than the bus. Optionally, the device is an integrated circuit.

In an optional implementation, a virtual address translation method is provided, where the service processing device is further configured to obtain service information, where the service information includes converting the first virtual address to the Information required by the second virtual address; the service processing device is specifically configured to convert the first virtual address into the second virtual address according to the service information.

Optionally, the first virtual address corresponds to the first data, and the second virtual address corresponds to the second data. The service processing device processes the second data to obtain the first data. Converting, by the service processing device, the first virtual address to the second virtual address may be understood by the service processing device determining, according to a virtual address corresponding to the first data that is required to be output to the graphics processor, Obtaining a virtual address corresponding to the second data required by the first data. The first data is data to be outputted by the service processing device, that is, data to be output to the graphics processor.

In this application, the service processing device may convert the virtual address corresponding to the data to be output into a virtual address corresponding to the data required to obtain the data to be output, so that the service processing device obtains the data to be output, which is simple to implement.

In an optional implementation, the data processing apparatus further includes a second memory management unit coupled between the graphics processor and the service processing device; the graphics processor is specifically configured to The second memory management unit sends a first data acquisition request, where the first data acquisition request includes a third virtual address, the third virtual address is used to indicate the first virtual address, and the second memory management unit is used by And searching for the first virtual address corresponding to the third virtual address according to the second mapping table, and further requesting, by the service processing device, the first data corresponding to the first virtual address.

Optionally, the second memory management unit is coupled to the graphics processor and the service processing device, respectively. The second mapping table may be configured for driver software running by the graphics processor or other processor. The second mapping table includes a mapping relationship of at least one virtual address to a virtual address. The second mapping table may further include a correspondence between at least one virtual address and at least one physical address. The first virtual address and the third virtual address are the same.

In the present application, the graphics processor requests data from the service processing device through the second memory management unit, so as to obtain data output by the service processing device, which is simple in implementation and strong in compatibility.

In an optional implementation, the graphics processor performs at least one of: generating the service information, configuring the first mapping table, or configuring the second mapping table by running driver software.

Optionally, the graphics processor performs operations such as generating the service information, configuring the first mapping table, or configuring the second mapping table by running driver software, so that the graphics processor obtains the required data. The service information generated by the driver software corresponds to data requested by the graphics processor.

In the present application, the graphics processor generates service information, configures the first mapping table, or configures the second mapping table by running the driver software, so as to satisfy various data acquisition requests sent by the graphics processor, and has high flexibility and can meet different applications. The needs of the scene.

In an optional implementation, the service processing device is specifically configured to receive the first physical address input by the first memory management unit, output the first physical address to a bus controller, and receive The second data output by the bus controller, the bus controller being coupled to the memory via the bus.

In an optional implementation, the data processing apparatus further includes an address filter coupled between the second memory management unit and the service processing device, and the second memory management unit is specifically configured to The address filter sends the first virtual address; the address filter is configured to receive the first virtual address, and if the first virtual address is in a target address interval, the first virtual The address is output to the service processing device.

Optionally, the address filter outputs an address in the target address interval to the service processing device, and an address not in the target address interval is not output to the service processing device.

In the present application, the address filter outputs the address in the target address range to the service processing device, which can reduce the processing load of the service processing device.

In an optional implementation, the graphics processor is further configured to send a second data acquisition request to the second memory management unit, where the second data acquisition request includes a fourth virtual address; a memory management unit, configured to: search a second physical address corresponding to the fourth virtual address according to the second mapping table, and send the second physical address to the address filter; the address filter, further And receiving the second physical address, where the second physical address is not in the target address interval, acquiring third data stored in the second physical address by using a bus controller, and outputting the first Three data to the graphics processor.

In the present application, the address filter acquires data stored at an address that is not in the target address range through the bus controller, and outputs the data to the graphics processor; the data requested by the graphics processor can be quickly output to the graphics processor.

In a second aspect, the present application provides a data processing method for a data processing apparatus, the data processing apparatus comprising a graphics processor, a service processing apparatus, and a first memory management unit coupled in sequence, the method comprising: the graphics The processor requests first data corresponding to the first virtual address, the first data is data processed by the service processing device and can be used or recognized by the graphics processor; the service processing device will be the first Converting the virtual address to the second virtual address and outputting the second virtual address to the first memory management unit, where the second virtual address corresponds to the second data before the processing by the service processing device; the first memory The management unit searches for a first physical address corresponding to the second virtual address according to the first mapping table; the service processing device acquires the second data stored in the first physical address in the memory, the second Data cannot be used or identified by the graphics processor, the data processing device being coupled to the memory via a bus; Second means for processing said first data to obtain the data, in a case where there is no bus or the memory or all of the participating the output of the first data to the graphics processor. The second data and the first data are data of different types or formats.

In the present application, in a case where the data processing device does not store the first data requested by the graphics processor, the service processing device acquires the second data, processes the second data to obtain the first data, and outputs the first data to the graphics processor. Ability to convert data that is unrecognizable or used by the GPU to data that the GPU can recognize or use, and save system bandwidth.

In an optional implementation manner, the converting, by the service processing device, the first virtual address to the second virtual address includes: the service processing device acquiring service information; the service information including the first virtual address Converting information required for the second virtual address; the service processing device converting the first virtual address to the second virtual address according to the service information.

In an optional implementation, the data processing apparatus further includes a second memory management unit coupled to the graphics processor; the first data corresponding to the first virtual address by the graphics processor includes: The graphics processor sends a first data acquisition request to the second memory management unit, the first data acquisition request includes a third virtual address, and the third virtual address is used to indicate the first virtual address; The second memory management unit searches for the first virtual address corresponding to the third virtual address according to the second mapping table, and further requests the first data corresponding to the first virtual address to the service processing device.

In an optional implementation manner, the method further includes performing at least one of: generating the service information, configuring the first mapping table, or configuring the second mapping table. In the present application, the graphics processor generates service information by running the driver software, configures the first mapping table, or configures the second mapping table, etc., so as to satisfy various data acquisition requests sent by the graphics processor, and the flexibility is high.

In an optional implementation manner, the acquiring, by the service processing device, the second data stored in the first physical address in the memory comprises: receiving, by the service processing device, the input by the first memory management unit Decoding a first physical address; outputting the first physical address to a bus controller and receiving the second data output by the bus controller, the bus controller being coupled to the memory via the bus.

In an optional implementation, the data processing apparatus further includes an address filter coupled to the second memory management unit and the service processing device, respectively; the service processing device converts the second virtual address Before the third virtual address, the method further includes: the second memory management unit sends the first virtual address to the address filter; and the address filter receives the input by the second memory management unit Describe a first virtual address; if the first virtual address is in a target address interval, output the first virtual address to the service processing device.

In an optional implementation manner, the method further includes: the graphics processor sending a second data acquisition request to the second memory management unit, where the second data acquisition request includes a fourth virtual address; The second memory management unit searches for the second physical address corresponding to the fourth virtual address according to the second mapping table and sends the second physical address to the address filter; the address filter receives the first a second physical address, where the second physical address is not in the target address interval, acquiring third data stored in the second physical address by using a bus controller, and outputting the third data to the graphic processor.

In the present application, data stored at an address that is not in the target address range is acquired by the bus controller and output to the graphics processor; the data requested by the graphics processor can be quickly output to the graphics processor.

In an optional implementation manner, the service processing apparatus includes at least one of: a decompression unit, a compression unit, a decryption unit, or an encryption unit.

In the present application, the service processing device can implement various data processing operations and can be applied to multiple scenarios.

In a third aspect, the present application provides a computer readable storage medium storing a computer program, the computer program comprising program instructions, the program instructions being executed by a graphics processor The operations of generating the service information, configuring the first mapping table, or configuring the second mapping table in the first aspect and the second aspect described above are performed.

DRAWINGS

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings to be used in the embodiments of the present invention or the background art will be described below.

FIG. 1 is a schematic flow chart of converting data that is not identifiable or used by a GPU into data that can be recognized or used by a GPU and outputting to a GPU;

2 is a schematic structural diagram of a terminal provided by the present application;

FIG. 3 is a schematic flowchart of converting data that is unrecognizable or used by a GPU into data that can be recognized or used by a GPU and outputting the same to the GPU;

4 is a schematic structural diagram of a data processing apparatus provided by the present application;

FIG. 5 is a schematic structural diagram of original data and compressed data provided by the present application; FIG.

FIG. 6 is a schematic structural diagram of another data processing apparatus provided by the present application.

detailed description

With the technical solution introduced by the background technology, a large amount of system bandwidth is required in converting data that is unrecognizable or used by the GPU into data that the GPU can recognize or use and output to the GPU. Therefore, the present application provides a data processing method and apparatus for saving system bandwidth. The data processing apparatus and method provided by the present application can be applied to a GPU-containing device such as a desktop computer, a notebook computer, a television, a mobile phone, a tablet computer, a personal digital assistant, a wearable device, a game machine, or a video camera. Alternatively, the system bandwidth can include one or all of bus bandwidth or read and write bandwidth of the memory.

FIG. 2 is a schematic structural diagram of a terminal according to an embodiment of the present application. As shown in FIG. 2, the terminal 200 can include a system chip 210, a memory 215 (one or more computer readable storage media), a radio frequency (RF) module 216, and a peripheral system 217. These components can communicate over one or more communication buses 214.

The peripheral system 217 is mainly used to implement the interaction function between the terminal 200 and the user/external environment, and mainly includes the input and output devices of the terminal 200. In a specific implementation, the peripheral system 217 can include: a touch screen controller 218, a camera controller 219, an audio controller 220, and a sensor management module 221. Each controller may be coupled to a respective peripheral device such as touch screen 223, camera 224, audio circuit 225, and sensor 226. It should be noted that the peripheral system 217 may also include other I/O peripherals.

The system chip 210 may include a central processing unit 211, a graphics processor 227, a clock module 222, and a power management module 213. The central processing unit 211 and the graphics processing unit 227 can be integrated into one integrated circuit or separate devices. The graphics processor 227 can be configured with one or more memory management units and further integrated with the business processing device, which can perform operations such as reading, writing, decompressing, decrypting, compressing, and encrypting so that the acquired external The data is converted to data that the graphics processor 227 can recognize or use. The clock module 222 integrated in the system chip 210 is mainly used to generate a clock required for data transmission and timing control for the central processing unit 211. The power management module 213 integrated in the system chip 210 is mainly used to provide a stable, high-accuracy voltage for the central processing unit 211, the radio frequency module 216, and the peripheral system. The system chip 210 can further include a bus controller (not shown in FIG. 2) for managing the communication bus 214. The bus 214 involved in this embodiment may include various types of buses, such as a serial bus, a parallel bus, an Inter-Integrated Circuit (I2C) bus, or a peripheral component interconnect express (PCIe) bus. Etc., used to couple different components or modules in the system. The system chip 210 in this embodiment is merely an example, and various internal components or functions may be replaced by a plurality of chips or other separate components.

A radio frequency (RF) module 216 is used to receive and transmit radio frequency signals, primarily integrating the receiver and transmitter of terminal 200. A radio frequency (RF) module 216 communicates with the communication network and other communication devices via radio frequency signals. In a specific implementation, the radio frequency (RF) module 216 can include, but is not limited to: an antenna system, an RF transceiver, one or more amplifiers, a tuner, one or more oscillators, a digital signal processor, a CODEC chip, a SIM card, and Storage media, etc. In some embodiments, a radio frequency (RF) module 216 can be implemented on a separate chip.

Memory 215 is coupled to central processor 211 for storing various software programs and/or sets of instructions. In particular implementations, memory 215 can include high speed random access memory, and can also include non-volatile memory, such as one or more magnetic disk storage devices, flash memory devices, or other non-volatile solid state storage devices. The memory 215 can store an operating system (hereinafter referred to as a system) such as an embedded operating system such as ANDROID, IOS, WINDOWS, or LINUX. The memory 215 can also store a network communication program that can be used to communicate with one or more additional devices, one or more terminal devices, one or more network devices. The memory 215 can also store a user interface program, which can realistically display the content of the application through a graphical operation interface, and receive user control operations on the application through input controls such as menus, dialog boxes, and keys. .

The memory 215 can also store one or more applications. As shown in FIG. 2, these applications may include: social applications (such as Facebook), image management applications (such as photo albums), map applications (such as Google Maps), browsers (such as Safari, Google Chrome), etc. .

In the present application, central processor 211 can be used to read and execute computer readable instructions. Specifically, the central processing unit 211 can be used to call a program stored in the memory 215 and execute the instructions contained in the program. The graphics processor 227 can be used to perform various operations required to draw computer graphics, including vertex settings, lighting, pixel operations, and the like.

It should be understood that the terminal 200 is only an example provided by an embodiment of the present invention, and that the terminal 200 may have more or less components than the illustrated components, may combine two or more components, or may have components. Different configurations are implemented.

Please refer to FIG. 3. FIG. 3 is a schematic flowchart of converting data that is unrecognizable or used by a GPU into data that can be recognized or used by a GPU, that is, converting data of one type or format into another type or format. Does not change the data content. As shown in FIG. 3, 301 represents data that the GPU does not recognize or use, 302 represents a GPU integrated with the service processing device, and 303 represents data output by the GPU. The business processing device can convert data that is unrecognizable or used by the GPU into data that the GPU can recognize or use without changing the data content and output to the GPU. Since the service processing device is integrated with the GPU, the service processing device does not need to go through the bus to transmit data to the GPU, and the operation of reading and writing the memory can be omitted compared with the prior art, thereby achieving the goal of saving system bandwidth. Since the service processing device can directly transmit the obtained data to the graphics processor, the data need not be stored in an external memory and then read by the graphics processor from the memory, which can reduce the system. Memory consumption and bandwidth consumed by memory reads and writes.

In this embodiment, the graphics processor, also known as the display core, the visual processor, and the display chip, is an image computing operation specially performed on a personal computer, a workstation, a game machine, and some mobile devices (such as a tablet computer or a smart phone). The processor or microprocessor that is working. The data processing apparatus according to this embodiment may include one or more of a hardware accelerator, a logic circuit, or dedicated hardware for implementing data conversion.

FIG. 4 is a schematic structural diagram of a data processing apparatus provided in the present application. The apparatus may be located in the system chip 210, for example, a part of an integrated circuit inside the system chip 210. Alternatively, the device may also be the system chip 210 itself or the terminal 200 in FIG. The specific embodiment of the data processing device is not specifically limited in this embodiment. The data processing apparatus of FIG. 4 may include a graphics processor 410, a service processing apparatus 420, a first memory management unit 430, and a bus controller 440. The business processing device 420 is coupled to the graphics processor 410, the first memory management unit 430, and the bus controller 440, respectively. The graphics processor 410 and the service processing device 420 are integrated. As shown in FIG. 4, the data processing apparatus in the present application can implement the following operations: 401. The graphics processor 410 or other driver software running by the processor configures the first mapping table for the first memory management unit 430. The first mapping table includes a correspondence between at least one virtual address and at least one physical address. The other processor may be a central processing unit (CPU) or other type of processor device that can execute the driver software. 402. The graphics processor 410 requests the service processing device 420 for the first data corresponding to the first virtual address. The first data is data processed by the business processing device 420 and can be used or recognized by the graphics processor 420. VA in Fig. 4 represents the first virtual address. 403. The service processing device 420 converts the first virtual address into a second virtual address and outputs the second virtual address to the first memory management unit 430. The second virtual address corresponds to the second data before the processing by the service processing device 420. The second data may be stored in a memory external to the data processing device, may be the memory 215 as shown in FIG. 2, or may be a buffer or an on-chip memory in the system chip 210. The data processing device is coupled to the memory via a bus. VA' in Fig. 4 denotes a second virtual address. 404. The first memory management unit 430 searches for a first physical address corresponding to the second virtual address according to the first mapping table, and outputs the first physical address to the service processing device 420. The PA in Fig. 4 represents the first physical address. 405. The service processing device 420 outputs the first physical address to the bus controller 440. 406, the service processing device 420 receives second data from the bus controller 440, the second data and The first data is of a different type or format, so the second data cannot be directly used or recognized by the graphics processor 420. 407. The service processing device 420 processes the second data to obtain first data, and outputs the first data to the graphics processing without one or all of the bus or the memory participating. 410, to enable the graphics processor 410 to identify and use the first data. For example, the first data provided by the business processing device 420 to the graphics processor 410 does not pass through the bus and the memory. In this case, the bus and the memory are not involved in the transmission of the first data, so that the bus bandwidth is saved, and the storage space of the memory and the bandwidth of the read-write memory are also saved. Saves on total system bandwidth. Optionally, the channel through which the service processing device 420 transmits the first data to the graphics processor 410 is an interface other than a bus, such as a dedicated circuit interface.

In the implementation of the present invention, the address in the memory has a virtual address and a physical address, and the processor or other device accesses the data in the memory through the address. For example, information is stored in bytes in memory. To properly store or retrieve information, each byte unit is given a unique memory address, called a physical address. Illustratively, the physical addresses are numbered starting from 0, sequentially incremented by one each time, so the physical address space of the memory grows linearly. The physical address is the address signal used to address the memory locations in the memory and is the end result of the address translation. The external bus of the processor can be coupled to the memory through the pins of the system chip 210. The virtual address is generated by the compiler and is the logical address of the program. The above processors may be CPUs, GPUs, and other processors.

In the embodiment of the present invention, the virtual memory management mechanism requires the support of the memory management unit. The memory management unit can usually be considered as part of a CPU or GPU, or it can be selectively located outside of the CPU or GPU, ie as a standalone device. If the CPU or GPU does not have a memory management unit, or has a memory management unit but is not enabled, the memory address issued by the CPU or GPU execution unit will be directly transferred to the chip pins, such as the pins of the system chip 210, and the actual physical memory. For example, it is received by the memory 215 or the buffer in the system chip 210 or the on-chip memory, which is called a physical address (PA). If the processor has the memory management unit enabled, the memory address issued by the CPU or GPU execution unit will be intercepted by the memory management unit. The address from the CPU or GPU to the memory management unit is called the virtual address (VA), and the memory management unit. Translate this address into another address and send it to the external address pin of the chip where the CPU or GPU is located, that is, map the virtual address to a physical address. It can be seen that the memory management unit is responsible for the mapping of virtual addresses to physical addresses. It can be understood that the memory management unit can map the virtual address corresponding to each process to the physical address space corresponding to the process, so that each process, such as a CPU process or a GPU process, has its own independent physical address space. For example, the physical address actually generated by the memory management unit is typically a discrete discrete address, and the virtual address is a logical address for the CPU or GPU that uses the address, making the logical address appear to be more contiguous. Therefore, in virtual memory management, a memory management unit is used to implement conversion between an external memory address to an internal device, such as a usable and identifiable address of a CPU or GPU. In addition, the memory management unit can also provide memory access check of the hardware mechanism. The memory access permission check can protect the memory in the memory used by each process from being destroyed by other processes. In the embodiment of the present invention, the memory management unit can provide a memory access permission check on the hardware mechanism of the GPU, and the memory in the memory used by the process protecting the GPU is not destroyed by other processes.

In the present embodiment, business processing device 420 is integrated with graphics processor 410 and coupled to an external bus via bus controller 440 for further coupling to a memory external to the data processing device. Within the device, the channel between the service processing device 420 and the graphics processor 410 for transmitting data is an interface other than the bus. Therefore, the data transfer between the service processing device 420 and the graphics processor 410 does not have to go through the bus or external memory, for example, neither the bus nor the external memory participate in the data transmission, saving system bandwidth including bus bandwidth and memory bandwidth. .

In an optional implementation, a virtual address translation method is provided, as follows: the service processing device 420 is further configured to acquire service information; and the service information includes converting the first virtual address into a Information required for the second virtual address; the service processing device 420 is specifically configured to convert the first virtual address into the second virtual address according to the service information. The service information includes at least one of: an image start virtual address, a resolution, an image format, a step size, or compression header information.

The service processing device 420 may be at least one of a decompression unit, a compression unit, an encryption unit, or a decryption unit. The service processing device 420 may perform at least one of various operations such as a decompression operation, a compression operation, a decryption operation, or an encryption operation. Illustratively, the service processing device 420 is a decompression unit for decompressing data in one compressed format, such as second data, into data in another compressed format, such as the first data. The conversion between these two formats does not change the specific content of the data.

The service information in this embodiment may be generated by the driver software running by the graphics processor. The graphics processor 410 or other processor-driven driver software can generate a variety of service information. The service processing device 420 can obtain corresponding service information according to the data requested by the graphics processor 410. For example, the graphics processor 410 requests the encrypted data, the graphics processor 410 or other driver software running by the processor generates the first service information, and the service processing device 420 acquires the first service information, where the first service information includes The virtual address corresponding to the encrypted data is converted into information required for the virtual address corresponding to the unencrypted data. For another example, the graphics processor 410 requests to decompress data, the graphics processor 410 or other driver software running by the processor generates second service information, and the service processing device 420 acquires the second service information, where the second service information includes The virtual address corresponding to the uncompressed data is converted into information required for the virtual address corresponding to the compressed data. It will be appreciated that the service information corresponds to data requested by the graphics processor 410 and operations that the service processing device 420 needs to perform.

The service processing device 420 can perform different operations, but the principles of address translation are similar. A specific example of the address conversion method employed when the service processing device 420 performs the decompression operation as the decompression unit will be described below. The second data is data before decompression, such as Hisilicon Frame Buffer Compression (HFBC) format data. The first data is decompressed data, which can be used and recognized by the graphics processor, for example, ARM (Advanced RISC Machine, Advanced Framed Instruction Set Machine) frame compression (AFBC) format data. It should be noted that the following is only a typical example, and other examples can be obtained by those skilled in the art according to the following methods.

Step 1: The service processing device 420 acquires target service information. The target service information may include an image start virtual address, a resolution, an image format, a step size, and compressed header information. For example, the service information corresponding to the video image data with a resolution of 1280×720 includes: an image start virtual address 0x8000000000, a width 1280, a height 720, a step size 1280, and compression header information.

Step 2: The service processing device 420 determines target coordinates of the first data corresponding to the first virtual address in the image. For example, the first virtual address is 0x8000004000, the image starting virtual address is 0x8000000000, and the difference between the first virtual address and the starting virtual address of the image is calculated (0x8000004000-0x8000000000=0x4000), and the first data is located in the image. The coordinates (y=0x4000/1280=12, x=0x4000-1280×12=1024, so the coordinates are (1024, 12)).

Step 3: Determine the target data block corresponding to the target coordinate in the original data. The raw data includes the first data. The original data is data processed by the service processing device 420, that is, uncompressed data. FIG. 5 is a schematic structural diagram of original data and compressed data provided by the present application. In FIG. 5, 501 represents original data, 502 represents compressed data, 501 includes each rectangle representing a 16×16 data block, and 502 is divided into two parts, the upper part is an index address, the lower part is compressed data, and the lower part is compressed data, and 503 indicates The data block of the Mth column of one row, 504 represents the index address corresponding to the compressed data of the first row and the Mth column, and 505 represents the compressed data of the first row and the Mth column. The original data in FIG. 5 corresponds to the compressed data, and the business processing device 420 decompresses the compressed data to obtain the original data. The original data and the compressed data correspond to the same starting address, that is, the virtual address corresponding to the data block of the first row and the first column in 501 is the same as the virtual address corresponding to the index address of the first row and the first column of 502. As can be seen from FIG. 5, each data block included in the original data corresponds to one index address, and each index address corresponds to one compressed data. For example, 503 in FIG. 5 corresponds to 504, and 504 corresponds to 505. The following describes an example of determining the corresponding data block of the target coordinate in the original data: the target coordinate is (1024, 12), the size of each data block in the original data is 16×16, and the data block corresponding to the target coordinate point is the block PQ. , P=12/16=0, Q=1024/16=64, the target coordinate point corresponds to the data block of the first row and the 64th column in FIG.

Step 4: Determine a second virtual address corresponding to the target data block. The following is a specific example of determining the virtual address of the compressed data corresponding to the data block of the first row and the 64th column in the original data:

VA’_header=VA’_start+byte(header)×64;(1)

VA’_body=VA’_start+data(pa_header);(2)

Where VA'_start represents the starting virtual address of the compressed data, that is, the virtual address corresponding to the index address of the first row and the first column in FIG. 5; byte (header) represents the number of bytes occupied by one index address; VA'_header represents The data address corresponds to an index address; data (pa_header) represents the address stored by the VA'_header; VA'_body represents the virtual address of the compressed data corresponding to the data block, that is, the second virtual address. For example, the target data block is the data block of the first row and the 64th column in the original data, that is, 503 in FIG. 5, and the service processing device calculates the index address corresponding to the target data block by using the formula (1), and obtains the index address in FIG. The virtual address corresponding to the virtual address is obtained by using the virtual address stored in the virtual address, and the virtual address corresponding to the compressed data corresponding to the data block is calculated by using the formula (2) and the reference virtual address to obtain a virtual address corresponding to the 505. The business processing device 420 can include a coordinate locator, an address translator, and a decompression module. The coordinate locator is configured to determine target coordinates of the first data corresponding to the first virtual address in the image. The address converter is configured to implement conversion of the first virtual address to the second virtual address, that is, steps 2 to 4. The decompression module is configured to decompress the acquired compressed data.

The above describes a virtual address translation method. In an actual application, the operations performed by the service processing device 420 are different, and different address translation modes may be adopted. For example, the virtual address corresponding to the unencrypted third data is converted into the virtual address corresponding to the encrypted fourth data, and the service processing device 420 decrypts the fourth data to obtain the third data.

In the present application, the service processing device 420 can convert the virtual address corresponding to the data to be output into a virtual address corresponding to the data required to obtain the data to be output, so that the service processing device 420 obtains the data to be output, which is simple to implement.

FIG. 6 is a schematic structural diagram of another data processing apparatus provided by the present application, which is based on the apparatus shown in FIG. 4 and further refined. As shown in FIG. 6, the data processing device can be an integrated circuit located in the system chip 210. The data processing apparatus includes a graphics processor 620, a second memory management unit 630, an address filter 640, a service processing device 650, a first memory management unit 660, and a bus controller 670. The graphics processor 620, the second memory management unit 630, the address filter 640, the service processing device 650, and the first memory management unit 660 are sequentially coupled, and the service processing device 650 and The bus controller 670 is coupled. The data processing apparatus may perform the following operations: 601, the graphics processor 620 or other driver software running the driver software to configure the first mapping table or the second mapping table. The first mapping table is applied to the first memory management unit 660; the second mapping table is applied to the second memory management unit 630. The first mapping table is used to implement mapping of virtual addresses to physical addresses. The second mapping table is used to implement mapping of the virtual address system target address. If the target address needs to be further converted to a physical address by another memory management unit or mapping table, the target address is a virtual address. Alternatively, the target address can be a physical address without further conversion by other memory management units or mapping tables. Therefore, the second mapping table may include a mapping relationship of at least one virtual address to a virtual address, and may further include a correspondence between at least one virtual address and at least one physical address. Optionally, the first mapping table or the second mapping table may be dynamically configured by the driver software according to an occupation of a memory.

602. The graphics processor sends a first data acquisition request to the second memory management unit 630. The first data acquisition request includes a third virtual address. 603. The second memory management unit 630 searches for a target address corresponding to the third virtual address according to the second mapping table, and further sends the target address to the address filter 640. The address filter 640 is used for filtering or filtering to identify a particular address.

604. If the target address is in the target address range, the address filter 640 outputs the target address to the service processing device 650, and the address not in the target address interval is not sent to the service. Processing device 650 outputs. . At this time, the target address is the first virtual address mentioned in the previous embodiment. 605. The service processing device 650 further converts the target address into a second virtual address and outputs the second virtual address to the first memory management unit 660. The second virtual address corresponds to the second data before the processing by the service processing device 650. The target address corresponds to the first data processed by the service processing device 650. VA in Fig. 6 denotes the third virtual address, VA' denotes the target address, and VA" denotes the second virtual address. Alternatively, the target address interval may be preset for the address filter An address range of the image processor may be an address range of the driver software configuration run by the graphics processor or other processor. The address in the target address interval may be a virtual address, and the address not in the target address interval may be The physical address can be implemented by the address filter to distinguish the physical address from the virtual address.

606. The first memory management unit 660 searches for a first physical address corresponding to the second virtual address according to the first mapping table, and outputs the first physical address to the service processing device 650. The PA in Fig. 6 represents the first physical address. 607. The service processing device 650 outputs the first physical address to the bus controller 670. The service processing device 650 receives the second data from the bus controller 670. 609. The service processing device 650 processes the second data to obtain the first data, and outputs the first data to the graphics processor 620.

Optionally, 610. If the target address is not in the target address interval, the address filter 640 outputs the target address to the bus controller 670, where the target address is the second physical address. The data stored by the second physical address is data requested by the graphics processor 620. 611. The graphics processor 620 receives data that the bus controller 670 acquires and transmits in response to the second physical address. Since the address received by the address filter 640 may be an address that the service processing device 650 does not need, such as a physical address, once the address filter 640 outputs the address to the service processing device 650, the The business processing device 650 has unnecessary operations and even adverse effects. Therefore, the address filter 640 outputs only the address in the target address range to the service processing device 650, avoiding waste of resources.

Therefore, the address filter 640 is configured to filter the address generated by the second memory management unit 630, and provide an address within the target address range to the service processing device 650 for the address to be converted by the service processing device 650. The address filter 640 provides an address that is not within the target address range to the bus controller 670 such that the associated address is used directly as a physical address. Therefore, for the second memory management unit 630, the generated address within the target address range is another virtual address or another logical address, and the second memory management unit 630 implements the virtual address to the virtual address. Mapping, virtual addresses before and after mapping can be essentially the same. Alternatively, another virtual address generated after the mapping may be different from the virtual address before the mapping, for example, some information is added, including but not limited to an identifier corresponding to different software processes or an identifier indicating service information corresponding to the address. So that the virtual address generated after mapping is different from the virtual address before mapping. If the second memory management unit 630 generates an address that is not in the target address range, as in another address interval, it is used to implement mapping of the virtual address to the physical address, and the address output by the second memory management unit 630 at this time. It will be transmitted directly to the bus controller 670 to obtain data corresponding to the physical address. Therefore, the device is compatible with two different data acquisition technologies. The first technology is a data acquisition technology that needs to be processed by the service processing device 650. At this time, the virtual address requested by the graphics processor 620 passes through the preset target address interval. The business processing device 650 processes the external data, which is converted to data that the graphics processor 620 can recognize or use but the data content does not change. Another technique is that without the participation of the service processing device 650, the virtual address requested by the graphics processor 620 is directly translated into a physical address and external data is obtained according to the physical address, at which time the external data is recognized or used by the graphics processor 620. The data does not need to be converted by data format or type.

Therefore, the address filter of this embodiment may filter the input address, and output the address located in the first address interval to the service processing device 650, and will not be located in the first address interval, for example, in the second address interval. The address is directly output to the bus controller 670, and the first address interval and the second address interval do not overlap. Whether the data stored externally can be directly identified or used by the graphics processor 620, the graphics processor 620 will eventually obtain its required data. Optionally, the data processing apparatus may not include the address filter 640, that is, the address filter 640 is not necessary, and the second memory management unit 630 and the service processing apparatus 650 may be directly coupled.

The above solution can save the system bandwidth occupied by the graphics processor 620 when acquiring data. Other devices than the driver software in FIG. 6 may include a large number of circuits, such as at least one of a transistor, a logic gate circuit, or an analog circuit. The driver software may be stored in a computer readable storage medium and read and executed by the graphics processor 620 to generate the service information in the previous embodiment, configure the first mapping table, or configure the first The operation of the second mapping table. The computer readable storage medium can be the memory 215 of FIG. The available medium for the memory may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape), an optical medium (eg, a digital versatile disc (DVD)), or a semiconductor medium (eg, a solid state disk) , SSD)) and so on.

Alternatively, the bus controller referred to in the previous embodiment is the core of the bus system for connecting the device and other devices, such as other components within the system chip 210 or components other than the system chip. The bus system includes a bus and a bus controller. For example, the task of the bus controller is generally to manage the use of various types of buses, including the management of devices on the bus and the process management of the devices using the bus. In the bus controller implementation technology, there is not necessarily a separate controller, and its functions may be distributed to various components or devices coupled to each bus. The bus controller is coupled to the bus in this embodiment and can control the bus to access an external memory for reading data from a memory external to the device based on a physical address control bus transmitted from a service processing device, address filter or other device. And feedback to the graphics processor. Therefore, the graphics processor can acquire and utilize data stored outside the data processing device via the bus controller by using virtual memory management technology.

In the above implementation, since the device is attached to the bus through an internal bus controller and further connected to the memory on the bus, there is no need to transfer data between the different components inside the device via the bus. The memory may be an external memory of the system chip or an on-chip memory or a temporary storage device such as a buffer. When the business processing device provides the data requested by the graphics processor to the graphics processor, the data transmission does not pass through the bus outside the device, nor does it need to be stored in other memories coupled to the bus, which can save system bandwidth and further save The storage space of the system. Optionally, the channel between the service processing device and the graphics processor for transmitting the data is an interface other than the bus, such as a dedicated circuit interface. Therefore, the embodiment of the present application is equivalent to embedding a service processing device module in the device including the graphics processor, so that data transmission between the service processing device and the graphics processor does not pass through the bus and the external memory, and can be flexibly implemented differently. The conversion of data types or formats is easy for the graphics processor to recognize and use, and can effectively save bandwidth.

It should be noted that the term "coupled" as used in this application is used to mean the intercommunication or interaction between different components, and may include direct connection or indirect connection through other components. At least one of the embodiments is used to represent one or more in a broad sense, that is, to express one or any of a plurality of corresponding options.

The above is only the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any equivalent person can be easily conceived within the technical scope of the present invention by any person skilled in the art. Modifications or substitutions are intended to be included within the scope of the invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

A data processing device, comprising: a graphics processor, a service processing device, and a first memory management unit; wherein the graphics processor and the first memory management unit are respectively coupled to a service processing device;

The graphics processor is configured to request first data corresponding to the first virtual address, where the first data is data processed by the service processing device and can be used or recognized by the graphics processor;

The service processing device is configured to convert the first virtual address into a second virtual address and output the second virtual address to the first memory management unit, where the second virtual address corresponds to the service processing Second data before processing by the device;

The first memory management unit is configured to search for a first physical address corresponding to the second virtual address according to the first mapping table;

The service processing device is further configured to acquire the second data stored in the first physical address in a memory, the second data cannot be used or recognized by the graphics processor, and the data processing device Coupled to the memory by a bus;

The service processing device is further configured to process the second data to obtain the first data, and output the first data to the device without one or all of the bus or the memory participating The graphics processor.
A data processing apparatus according to claim 1, wherein

The service processing device is further configured to acquire service information; the service information includes information required to convert the first virtual address into the second virtual address;

The service processing device is specifically configured to convert the first virtual address into the second virtual address according to the service information.
The data processing device according to claim 1 or 2, wherein the data processing device further comprises a second memory management unit;

The graphics processor is configured to send a first data acquisition request to the second memory management unit, where the first data acquisition request includes a third virtual address, and the third virtual address is used to indicate the first Virtual address

The second memory management unit is configured to search the first virtual address corresponding to the third virtual address according to the second mapping table, and further request the service processing device to correspond to the first virtual address First data.
The data processing apparatus according to claim 3, wherein said graphics processor performs at least one of: generating said service information, configuring said first mapping table, or configuring said second mapping by running driver software table.
A data processing apparatus according to any one of claims 1 to 4, characterized in that

The service processing device is specifically configured to receive the first physical address input by the first memory management unit, output the first physical address to a bus controller, and receive the output by the bus controller Second data, the bus controller is coupled to the memory via the bus.
The data processing apparatus according to any one of claims 3 to 5, wherein the data processing apparatus further comprises an address filter;

The second memory management unit is specifically configured to send the first virtual address to the address filter;

The address filter is configured to receive the first virtual address, and output the first virtual address to the service processing device if the first virtual address is in a target address interval.
A data processing apparatus according to claim 6, wherein

The graphics processor is further configured to send a second data acquisition request to the second memory management unit, where the second data acquisition request includes a fourth virtual address;

The second memory management unit is further configured to search for a second physical address corresponding to the fourth virtual address according to the second mapping table, and send the second physical address to the address filter;

The address filter is further configured to receive the second physical address, where the second physical address is not in the target address interval, acquire the third storage of the second physical address by using a bus controller Data and outputting the third data to the graphics processor.
The data processing apparatus according to any one of claims 1 to 7, wherein the service processing apparatus comprises at least one of: a decompression unit, a compression unit, a decryption unit, or an encryption unit.
A data processing method is applied to a data processing device, wherein the data processing device comprises a graphics processor, a service processing device, and a first memory management unit, the method comprising:

The graphics processor requests first data corresponding to the first virtual address, the first data is data processed by the service processing device and can be used or recognized by the graphics processor;

The service processing device converts the first virtual address into a second virtual address and outputs the second virtual address to the first memory management unit, where the second virtual address corresponds to the processing by the service processing device Second data;

The first memory management unit searches for a first physical address corresponding to the second virtual address according to the first mapping table;

The service processing device acquires the second data stored in the first physical address in a memory, the second data is not usable or recognized by the graphics processor, and the data processing device is coupled to the bus through a bus The memory;

The service processing device processes the second data to obtain the first data, and outputs the first data to the graphics processor without one or all of the bus or the memory participating .
The data processing method according to claim 9, wherein the converting the first virtual address to the second virtual address by the service processing device comprises:

The service processing device acquires service information; the service information includes information required to convert the first virtual address to the second virtual address;

The service processing device converts the first virtual address into the second virtual address according to the service information.
The data processing method according to claim 9 or 10, wherein said data processing device further comprises a second memory management unit coupled to said graphics processor; said graphics processor requesting a first virtual address corresponding The first data includes:

The graphics processor sends a first data acquisition request to the second memory management unit, where the first data acquisition request includes a third virtual address, and the third virtual address is used to indicate the first virtual address;

Searching, by the second memory management unit, the first virtual address corresponding to the third virtual address according to the second mapping table, and further requesting, by the service processing device, the first data corresponding to the first virtual address .
The data processing method according to claim 11, wherein the method further comprises performing at least one of the following operations:

Generating the service information, configuring the first mapping table, or configuring the second mapping table.
The data processing method according to any one of claims 9 to 11, wherein the acquiring, by the service processing device, the second data stored in the first physical address in the memory comprises:

Receiving, by the service processing device, the first physical address input by the first memory management unit; outputting the first physical address to a bus controller, and receiving the second data output by the bus controller, The bus controller is coupled to the memory via the bus.
The data processing method according to any one of claims 11 to 13, wherein said data processing device further comprises an address filter coupled to said second memory management unit and said service processing device, respectively; Before the service processing device converts the second virtual address to the third virtual address, the method further includes:

Sending, by the second memory management unit, the first virtual address to the address filter;

The address filter receives the first virtual address input by the second memory management unit; and when the first virtual address is in a target address interval, outputting the first virtual address to the service processing Device.
The data processing method according to claim 14, wherein the method further comprises:

The graphics processor sends a second data acquisition request to the second memory management unit, where the second data acquisition request includes a fourth virtual address;

The second memory management unit searches for a second physical address corresponding to the fourth virtual address according to the second mapping table, and sends the second physical address to the address filter;

The address filter receives the second physical address, and if the second physical address is not in the target address interval, acquires third data stored by the second physical address by using a bus controller, and outputs The third data is to the graphics processor.
The data processing method according to any one of claims 9 to 15, wherein the service processing device comprises at least one of: a decompression unit, a compression unit, a decryption unit, or an encryption unit.