WO2019172168A1 - Amplifier circuit - Google Patents

Amplifier circuit Download PDF

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Publication number
WO2019172168A1
WO2019172168A1 PCT/JP2019/008325 JP2019008325W WO2019172168A1 WO 2019172168 A1 WO2019172168 A1 WO 2019172168A1 JP 2019008325 W JP2019008325 W JP 2019008325W WO 2019172168 A1 WO2019172168 A1 WO 2019172168A1
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Prior art keywords
power supply
channel
circuit
amplifier
amplification stage
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PCT/JP2019/008325
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French (fr)
Japanese (ja)
Inventor
宏明 桂井
裕之 福山
秀之 野坂
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日本電信電話株式会社
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Publication of WO2019172168A1 publication Critical patent/WO2019172168A1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/68—Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics

Definitions

  • the present invention relates to an amplifier circuit, and more particularly to an amplifier circuit in which a plurality of channel amplifiers are connected in multiple stages and a power supply voltage is divided and supplied.
  • the transistor performance is improved, while the drive voltage and breakdown voltage tend to decrease.
  • the power supply voltage to be supplied is often determined by the standard of the device to be used, and cannot be easily changed in actual use. Therefore, when using a transistor having a withstand voltage smaller than the power supply voltage, means such as 1) using a voltage drop due to resistance, 2) using a series regulator circuit, and 3) connecting the transistors in multiple stages are required.
  • Non-Patent Document 1 For example, in the buffer circuit of Non-Patent Document 1, there is shown an output stage in which transistors are connected in multiple stages in order to realize a circuit by a 1.8 V CMOS process with respect to a supply power voltage of 3.3 V.
  • the purpose of the circuit of Non-Patent Document 1 was to obtain a wide output amplitude with respect to the supply power supply voltage. However, even if the output amplitude is reduced with the same circuit configuration, the power consumption does not change.
  • the amplifier provided in the previous stage that handles a relatively small amplitude is driven with a power supply voltage that is lower than the power supply voltage of the amplifier in the output stage.
  • a circuit configuration for reducing power is shown.
  • a driver circuit is mounted on such an optical module, a power supply circuit corresponding to the number of power supply voltages required for each amplifier is required in order to operate the amplifiers constituting the driver circuit.
  • the power supply circuit necessary for each amplifier is realized by a switching regulator circuit, it is difficult to mount the power supply circuit on the same integrated circuit as the driver circuit because the power supply circuit size is large. Therefore, it is necessary to prepare a power supply circuit including a switching regulator circuit as a separate device from the optical module. For this reason, member cost and mounting cost will become large.
  • An object of the present invention is to provide an amplifier circuit capable of reducing power consumption by connecting a plurality of channel amplifier power supplies in cascade with respect to a single power supply voltage.
  • an embodiment is an amplifier circuit for amplifying a signal of a plurality of N (N is an integer of 2 or more) channels.
  • the above amplification stage is provided, and at least one amplification stage of the amplifier of each channel has a positive power supply terminal of the first channel amplification stage connected to the positive power supply line, and a negative power supply terminal connected to the positive power supply of the second channel amplification stage.
  • the positive power supply terminal of the nth (n is an integer greater than or equal to 2 and less than N) channel amplification stage is connected to the negative power supply terminal of the (n ⁇ 1) th amplification stage, and the negative power supply terminal is the n + 1st channel amplification.
  • a positive power supply terminal of the N-th amplification stage is connected to a negative power supply terminal of the (N ⁇ 1) -th amplification stage, a negative power supply terminal is connected to a negative power supply line, and the n ⁇ The amplification stage of the first channel and the n-th
  • An intermediate voltage stabilizing circuit for comparing an intermediate voltage between the amplification stage of the first channel and a reference voltage and controlling a current source of the amplification stage of the (n-1) th channel; The power supply voltage between the power supply lines is divided into N equal parts and applied to the amplifier of each channel.
  • a constant current circuit for generating a reference current between an intermediate voltage between the N-th channel amplification stage and the (N ⁇ 1) -th channel amplification stage and the negative power supply terminal voltage; and And a current mirror circuit that outputs a control current for controlling the current source of the amplification stage of the N-th channel.
  • the feedback control by the reference current generated from the current source circuit causes the amplifier of each channel to operate by the drive voltage obtained by dividing the single supply power supply voltage by the number of channels. It is possible to operate under the same conditions and reduce power consumption.
  • FIG. 1 is a block diagram of a two-channel amplifier circuit according to Embodiment 1 of the present invention.
  • FIG. FIG. 3 is a diagram illustrating a configuration when a voltage insensitive current source circuit is used in the amplifier circuit according to the first embodiment.
  • 1 is a diagram illustrating a circuit configuration of a voltage-insensitive current source circuit according to Example 1.
  • FIG. FIG. 3 is a diagram illustrating a circuit configuration of a differential amplification stage of the first channel amplifier according to the first embodiment;
  • FIG. 3 is a diagram illustrating a circuit configuration of a differential amplification stage of the second channel amplifier according to the first embodiment. It is a figure which shows the block configuration of the amplifier circuit of 2 channels concerning Example 2 of this invention.
  • FIG. 9 is a diagram illustrating a block configuration of a two-channel amplifier circuit according to a fourth embodiment of the invention.
  • FIG. 10 is a diagram illustrating a block configuration of a three-channel amplifier circuit according to Embodiment 5 of the present invention.
  • the amplifier circuit mainly amplifies a two-channel differential signal
  • the amplifier of each channel is a three-stage amplifier including a first differential amplifier stage, a second differential amplifier stage, and an output buffer stage.
  • N the supply power supply voltage
  • two or more multi-channels are possible (Example) 5).
  • the amplifier of each channel may have a single-stage configuration or a multi-stage configuration.
  • FIG. 1 shows a block configuration of a two-channel amplifier circuit according to Embodiment 1 of the present invention.
  • the amplifier circuit 10 includes a first channel amplifier including a first differential amplifier stage 11, a second differential amplifier stage 12, and an output buffer stage 13, a first differential amplifier stage 21, a second differential amplifier stage 22, and an output.
  • a second channel amplifier including a buffer stage 23 and an intermediate voltage stabilization circuit 31 are included.
  • the power supply voltage is supplied between the positive power supply line (VDD) and the negative power supply line (VSS), and each amplification stage of the first channel amplifier and each amplification stage of the second channel amplifier are cascaded between VDD and VSS. It is connected to the.
  • VDD positive power supply line
  • VSS negative power supply line
  • VDD Positive power supply voltage
  • Vmid Vmid-Negative power supply voltage
  • FIG. 2 shows a configuration when a voltage-insensitive current source circuit is used in the amplifier circuit according to the first embodiment. Only the first stage consisting of the first differential amplification stages 11 and 21 of the first and second channel amplifiers is extracted. A first voltage insensitive current source circuit 41 is inserted between VDD and Vmid, and a second voltage insensitive current source circuit 42 is inserted between Vmid and VSS. The output Ictrl of the second voltage insensitive current source circuit 42 is connected to the first differential amplification stage 21 of the second channel amplifier. In order to use the fact that the currents flowing through the first channel amplifier and the second channel amplifier are equal, the first voltage insensitive current source circuit 41 is inserted as a dummy, but the first differential amplification stage of the first channel amplifier 11 is not connected.
  • FIG. 3 shows a circuit configuration of the voltage-insensitive current source circuit according to the first embodiment.
  • the second voltage insensitive current source circuit 42 includes a constant current circuit 42a and a current mirror circuit 42b.
  • the constant current circuit 42a has a positive power supply terminal (V +) connected to Vmid and a negative power supply terminal (V ⁇ ) connected to VSS.
  • V + positive power supply terminal
  • V ⁇ negative power supply terminal
  • the current control output Ictrl1 is connected to the first differential amplification stage 21 of the second channel amplifier, so that the current source circuit provided in the normal differential amplification stage can be replaced with the first one.
  • the two-voltage insensitive current source circuit 42 controls the current source circuit of the first differential amplification stage 21 (see FIG. 5 below).
  • the current flowing through the first differential amplification stage 21 is determined by the reference current independent of the intermediate voltage, and the current I1 flowing through the first differential amplification stages 11 and 21 of the first and second channel amplifiers is It is uniquely determined without being affected by the intermediate voltage (Vmid).
  • the current control output Ictrl2 to the second differential amplification stage 22 of the second channel amplifier, the current I2 flowing through the second differential amplification stages 12 and 22 and the current control output Ictrl3 are second.
  • the output buffer stage 23 of the channel amplifier By connecting to the output buffer stage 23 of the channel amplifier, the current IO flowing through the output buffer stages 13 and 23 can be uniquely determined without being influenced by the intermediate voltage (Vmid).
  • the current I1 flowing through the first differential amplification stages 11 and 21 is determined by the second voltage insensitive current source circuit 42, and the intermediate voltage stabilization circuit 31
  • the two-channel amplifier can be driven under the same operating conditions.
  • the drive voltage applied to each channel amplifier can be reduced to an integer, and the power consumption of each channel amplifier can be reduced.
  • FIG. 4 illustrates a circuit configuration of the differential amplification stage of the first channel amplifier according to the first embodiment.
  • the first differential amplification stage 11 and the second differential amplification stage 12 of the first channel amplifier have the same circuit configuration.
  • the first differential amplification stage 11 is connected to the differential amplification stage connected to the differential inputs In1 (I C ) and In1 (I T ) and the differential outputs Out1 (O C ) and Out1 (O T ).
  • An output stage and a cascode-connected current source is an output stage and a cascode-connected current source.
  • the power supply voltage is supplied by connecting the positive power supply terminal (V +) to VDD and connecting the negative power supply terminal (V ⁇ ) to V + (VDD side) of the second channel amplifier.
  • the current sources cascode-connected in two stages are controlled by Vg1 and Vg2 generated from the voltage control output Vctrl of the intermediate voltage stabilization circuit 31, respectively.
  • the current source is described as an example of two-stage cascode connection, but is not limited thereto.
  • FIG. 5 illustrates a circuit configuration of a differential amplification stage of the second channel amplifier according to the first embodiment.
  • the first differential amplification stage 21 and the second differential amplification stage 22 of the second channel amplifier have the same circuit configuration.
  • the first differential amplification stage 21 is connected to the differential amplification stage connected to the differential inputs In1 (I C ) and In1 (I T ) and to the differential outputs Out1 (O C ) and Out1 (O T ).
  • An output stage and a cascode-connected current source is an output stage and a cascode-connected current source.
  • the power supply voltage is supplied by connecting the positive power supply terminal (V +) to V- (VSS side) of the first channel amplifier and connecting the negative power supply terminal (V-) to VSS.
  • the current source cascode-connected in two stages is controlled by the current control output Ictrl1 of the second voltage insensitive current source circuit 42.
  • the gate voltages Vga and Vgb applied to the current source transistor are determined based on Ictrl1.
  • the intermediate potential generation circuit 31 compares the intermediate voltage (Vmid) with the reference voltage (Vref), decreases Vctrl (Vg1, Vg2 in FIG. 4) when Vmid> Vref, and increases Vctrl when Vmid ⁇ Vref.
  • the intermediate potential generating circuit 31 operates so as to satisfy the above expression by repeating until Vmid and Vref become equal.
  • the potential difference between Vg1 and Vg2 only needs to be equal to the potential difference of the resistor R2 of the current source of the first differential amplification stage 21 of the second channel amplifier. That is, it is only necessary to perform control so that the potential difference between Vga and Vgb uniquely determined by the current control output Ictrl1 of the second voltage insensitive current source circuit 42 and the resistor R2 is equal.
  • FIG. 6 shows a block configuration of a two-channel amplifier circuit according to Embodiment 2 of the present invention.
  • the amplifier circuit 110 includes a first channel amplifier including a first differential amplifier stage 111, a second differential amplifier stage 112, and an output buffer stage 113, a first differential amplifier stage 121, a second differential amplifier stage 122, and an output.
  • a second channel amplifier including a buffer stage 123 and an intermediate voltage stabilizing circuit 131 are included.
  • the power supply voltage of the first and second differential amplification stages is supplied between VDD and VSS, and each amplification stage of the first channel amplifier and each amplification stage of the second channel amplifier are cascaded between VDD and VSS. It is connected to the.
  • the supply power supply voltages of the output buffer stages are different from those of the first embodiment in that each is connected between VDD and VSS.
  • Non-Patent Document 2 only the amplifier (differential amplification stage) provided in the previous stage that handles a relatively small amplitude can be driven with a small power supply voltage, and power consumption can be reduced accordingly.
  • the output buffer stage can handle a relatively large amplitude, it is possible to achieve both a reduction in power consumption and a large output amplitude.
  • FIG. 7 shows a block configuration of a two-channel amplifier circuit according to Embodiment 3 of the present invention.
  • a large current flows in the output buffer stage, which can be a noise source. Therefore, a method of separating the power supply of the differential amplifier stage and the power supply of the output buffer stage is taken.
  • the amplifier circuit 210 includes a first channel amplifier including a first differential amplifier stage 211, a second differential amplifier stage 212, and an output buffer stage 213, a first differential amplifier stage 221, a second differential amplifier stage 222, and an output.
  • a second channel amplifier including a buffer stage 223 and intermediate voltage stabilizing circuits 231 and 232 are included.
  • the power supply voltage of the first and second differential amplification stages is supplied between VDD and VSS, and each amplification stage of the first channel amplifier and each amplification stage of the second channel amplifier are cascaded between VDD and VSS. It is connected to the.
  • the power supply voltage of the output buffer stage is supplied between VDDO and VSSO different from the power supply of the differential amplifier stage, and the output buffer stages 213 and 223 are connected in cascade between VDDO and VSSO.
  • An intermediate voltage stabilization circuit 232 is also connected to the output buffer stage, enabling control independent of the differential amplification stage.
  • a voltage insensitive current source circuit may be provided in the same manner as the configuration shown in FIG.
  • FIG. 8 shows a block configuration of a two-channel amplifier circuit according to Embodiment 4 of the present invention. Only the first stage composed of the first differential amplification stages 311 and 321 of the first and second channel amplifiers of the amplifier circuit 310 is extracted. The configuration and operation of the intermediate voltage stabilization circuit 331 are the same as those in the first embodiment.
  • a differential amplifier may have functions such as direct external gain control (Manual Gain Control) and automatic gain control (Auto Gain Control) for making output amplitude constant.
  • the AGC circuit functions as a kind of feedback loop. Therefore, if it is included in the feedback loop composed of the intermediate voltage stabilization circuit 331, the loop may become unstable.
  • the current flowing through the AGC circuit is determined by the voltage insensitive current source circuits 341 and 42, and the intermediate voltage stabilizing circuit is passed from the AGC circuits 351 and 352 to the control terminals of the first differential amplification stages 311 and 321. Do not connect.
  • the configuration of the present embodiment can be applied not only to the AGC circuit but also to other feedback circuits.
  • FIG. 9 shows a block configuration of a three-channel amplifier circuit according to Embodiment 5 of the present invention.
  • a voltage insensitive current source circuit 441 is inserted between Vmid2 and VSS, and the output Ictrl is connected to the first differential amplification stage 451 of the third channel amplifier. Dummy voltage-insensitive current source circuits are inserted between VDD and Vmid1, and between Vmid1 and Vmid2, but are omitted here.
  • the voltage insensitive current source circuit 441 can uniquely determine the current I1 flowing through the first differential amplification stage without being influenced by the intermediate voltage (Vmid2).
  • the first differential amplifier stage 411 of the first channel amplifier is controlled (Vctrl1).
  • the multi-channel amplifier can be operated under the same operating conditions.
  • the stage is The positive power supply terminal of the first channel amplification stage is connected to the positive power supply line, the negative power supply terminal is connected to the positive power supply terminal of the second channel amplification stage, -The positive power supply terminal of the amplification stage of the n (n is an integer of 2 or more and less than N) channel is connected to the negative power supply terminal of the (n-1) th amplification stage, and the negative power supply terminal is the positive power supply of the amplification stage of the (n + 1) th channel Connected to the terminal, The positive power supply terminal of the Nth channel amplification stage is connected to the negative power supply terminal of the (N ⁇ 1) th channel amplification stage, and the negative power supply terminal is connected to the
  • the intermediate voltage stabilization circuit controls the current source of the n ⁇ 1 channel amplification stage by comparing the reference voltage with the intermediate voltage between the n ⁇ 1 channel amplification stage and the n ⁇ channel amplification stage. To do.
  • a voltage-insensitive current source circuit includes a constant current circuit that generates a reference current between an intermediate voltage between an N-th channel amplification stage and an N ⁇ 1-th channel amplification stage and the negative power supply terminal voltage; A current mirror circuit that outputs a control current for controlling the current source of the amplification stage of the N-th channel based on the current.

Abstract

Power consumption is reduced in the present invention by connecting the power supplies of amplifiers for a plurality of channels in cascade to a single power supply voltage. This amplifier circuit 10 comprises a first channel amplifier including one or more amplification stages 11-13, a second channel amplifier including one or more amplification stages 21, 23, and an intermediate voltage stabilization circuit 31. A shared power supply voltage is supplied between a positive power supply line (VDD) and a negative power supply line (VSS) and the power supplies of each of the amplification stages of the first channel amplifier and the power supplies of each of the amplification stages of the second channel amplifier are connected in cascade between VDD and VSS.

Description

増幅回路Amplifier circuit
　本発明は、増幅回路に関し、より詳細には、複数チャンネルの増幅器を多段に接続し、電源電圧を分割して供給する増幅回路に関する。 The present invention relates to an amplifier circuit, and more particularly to an amplifier circuit in which a plurality of channel amplifiers are connected in multiple stages and a power supply voltage is divided and supplied.
　ＣＭＯＳプロセスの微細化により、トランジスタの性能が向上する一方、その駆動電圧、耐圧は低下する傾向にある。しかしながら、一般的に、供給される電源電圧は、使用する装置の規格によって定められていることが多く、実使用上は容易に変更することができない。従って供給電源電圧より小さな耐圧のトランジスタを用いる場合、１）抵抗による電圧降下を用いる、２）シリーズレギュレータ回路を用いる、３）トランジスタを多段に接続する、といった手段が必要となる。 With the miniaturization of the CMOS process, the transistor performance is improved, while the drive voltage and breakdown voltage tend to decrease. However, in general, the power supply voltage to be supplied is often determined by the standard of the device to be used, and cannot be easily changed in actual use. Therefore, when using a transistor having a withstand voltage smaller than the power supply voltage, means such as 1) using a voltage drop due to resistance, 2) using a series regulator circuit, and 3) connecting the transistors in multiple stages are required.
　例えば、非特許文献１のバッファ回路においては、３．３Ｖの供給電源電圧に対し、１．８ＶＣＭＯＳプロセスにより回路を実現するために、トランジスタを多段に接続した出力段が示されている。非特許文献１の回路の目的は、供給電源電圧に対して広い出力振幅を得ようとすることであった。しかしながら、同じ回路構成で出力振幅を小さくしても、その消費電力は変わらない。 For example, in the buffer circuit of Non-Patent Document 1, there is shown an output stage in which transistors are connected in multiple stages in order to realize a circuit by a 1.8 V CMOS process with respect to a supply power voltage of 3.3 V. The purpose of the circuit of Non-Patent Document 1 was to obtain a wide output amplitude with respect to the supply power supply voltage. However, even if the output amplitude is reduced with the same circuit configuration, the power consumption does not change.
　一方、非特許文献２の光送信器のドライバ回路においては、比較的小さい振幅を扱う前段に備わる増幅器において、出力段の増幅器の電源電圧よりも小さい電源電圧で駆動することにより、ドライバ回路の消費電力を下げる回路構成が示されている。しかしながら、このような光モジュールでは、実装上の利便性を向上させるために、１つの電源電圧しか供給されないことがある。このような光モジュールにドライバ回路を実装する場合には、ドライバ回路を構成する増幅器を動作させるために、それぞれの増幅器に必要な電源電圧の数に応じた電源回路が必要となる。例えば、それぞれの増幅器に必要な電源回路をスイッチングレギュレータ回路で実現する場合、電源回路サイズが大きいために、ドライバ回路と同一の集積回路上に搭載することが難しい。そこで、スイッチングレギュレータ回路からなる電源回路を、光モジュールとは別デバイスとして用意する必要がある。このため、部材コスト、実装コストが大きくなってしまう。 On the other hand, in the driver circuit of the optical transmitter of Non-Patent Document 2, the amplifier provided in the previous stage that handles a relatively small amplitude is driven with a power supply voltage that is lower than the power supply voltage of the amplifier in the output stage. A circuit configuration for reducing power is shown. However, in such an optical module, only one power supply voltage may be supplied in order to improve mounting convenience. When a driver circuit is mounted on such an optical module, a power supply circuit corresponding to the number of power supply voltages required for each amplifier is required in order to operate the amplifiers constituting the driver circuit. For example, when the power supply circuit necessary for each amplifier is realized by a switching regulator circuit, it is difficult to mount the power supply circuit on the same integrated circuit as the driver circuit because the power supply circuit size is large. Therefore, it is necessary to prepare a power supply circuit including a switching regulator circuit as a separate device from the optical module. For this reason, member cost and mounting cost will become large.
　一方、それぞれの増幅器に必要な電源回路をシリーズレギュレータ回路で実現する場合、ドライバ回路と同一の集積回路に搭載することは可能であるが、消費電力削減の効果は失われてしまう。このように、従来の回路では、単一の電源電圧で動作させる場合、出力振幅が小さい増幅器であっても、部材コストおよび実装コストの抑制と、低消費電力動作との両立が困難であるという問題があった。 On the other hand, when the power supply circuit required for each amplifier is realized by a series regulator circuit, it can be mounted on the same integrated circuit as the driver circuit, but the effect of reducing power consumption is lost. In this way, in the conventional circuit, when operating with a single power supply voltage, it is difficult to achieve both low cost and low power consumption operation while suppressing the component cost and mounting cost even with an amplifier having a small output amplitude. There was a problem.
　本発明の目的は、単一の電源電圧に対し、複数チャンネルの増幅器の電源を縦続に接続することにより、消費電力を削減することができる増幅回路を提供することにある。 An object of the present invention is to provide an amplifier circuit capable of reducing power consumption by connecting a plurality of channel amplifier power supplies in cascade with respect to a single power supply voltage.
　本発明は、このような目的を達成するために、一実施態様は、複数のＮ（Ｎは２以上の整数）チャンネルの信号を増幅する増幅回路であって、各々のチャンネルの増幅器は、１以上の増幅段を備え、各チャンネルの増幅器の少なくとも１つの増幅段は、１チャンネル目の増幅段の正電源端子が正電源線に接続され、負電源端子が２チャンネル目の増幅段の正電源端子に接続され、ｎ（ｎは２以上Ｎ未満の整数）チャンネル目の増幅段の正電源端子がｎ－１番目の増幅段の負電源端子に接続され、負電源端子がｎ＋１チャンネル目の増幅段の正電源端子に接続され、Ｎチャンネル目の増幅段の正電源端子がＮ－１チャンネル目の増幅段の負電源端子に接続され、負電源端子が負電源線に接続され、前記ｎ－１チャンネル目の増幅段と前記ｎチャンネル目の増幅段との間の中間電圧と基準電圧とを比較して、前記ｎ－１チャンネル目の増幅段の電流源を制御する中間電圧安定化回路を備え、前記正電源線と前記負電源線との間の供給電源電圧がＮ等分されて、各チャンネルの増幅器に印加されることを特徴とする。 In order to achieve the above object, according to an embodiment of the present invention, an embodiment is an amplifier circuit for amplifying a signal of a plurality of N (N is an integer of 2 or more) channels. The above amplification stage is provided, and at least one amplification stage of the amplifier of each channel has a positive power supply terminal of the first channel amplification stage connected to the positive power supply line, and a negative power supply terminal connected to the positive power supply of the second channel amplification stage. Connected to the terminal, the positive power supply terminal of the nth (n is an integer greater than or equal to 2 and less than N) channel amplification stage is connected to the negative power supply terminal of the (n−1) th amplification stage, and the negative power supply terminal is the n + 1st channel amplification. A positive power supply terminal of the N-th amplification stage is connected to a negative power supply terminal of the (N−1) -th amplification stage, a negative power supply terminal is connected to a negative power supply line, and the n− The amplification stage of the first channel and the n-th An intermediate voltage stabilizing circuit for comparing an intermediate voltage between the amplification stage of the first channel and a reference voltage and controlling a current source of the amplification stage of the (n-1) th channel; The power supply voltage between the power supply lines is divided into N equal parts and applied to the amplifier of each channel.
　さらに、前記Ｎチャンネル目の増幅段と前記Ｎ－１チャンネル目の増幅段との間の中間電圧と前記負電源端子電圧との間で基準電流を生成する定電流回路と、前記基準電流に基づいて前記Ｎチャンネル目の増幅段の電流源を制御する制御電流を出力するカレントミラー回路とを含む電流源回路をさらに備えることもできる。 A constant current circuit for generating a reference current between an intermediate voltage between the N-th channel amplification stage and the (N−1) -th channel amplification stage and the negative power supply terminal voltage; and And a current mirror circuit that outputs a control current for controlling the current source of the amplification stage of the N-th channel.
　本発明によれば、電流源回路より生成された基準電流によるフィードバック制御により、単一の供給電源電圧をチャンネル数だけ分割した駆動電圧により各チャンネルの増幅器を動作させることで、各チャンネルの増幅器を同一条件で動作させるとともに、消費電力を低減することが可能となる。 According to the present invention, the feedback control by the reference current generated from the current source circuit causes the amplifier of each channel to operate by the drive voltage obtained by dividing the single supply power supply voltage by the number of channels. It is possible to operate under the same conditions and reduce power consumption.
本発明の実施例１にかかる２チャンネルの増幅回路のブロック構成を示す図である。1 is a block diagram of a two-channel amplifier circuit according to Embodiment 1 of the present invention. FIG. 実施例１にかかる増幅回路において電圧不感型電流源回路を用いた場合の構成を示す図である。FIG. 3 is a diagram illustrating a configuration when a voltage insensitive current source circuit is used in the amplifier circuit according to the first embodiment. 実施例１にかかる電圧不感型電流源回路の回路構成を示す図である。1 is a diagram illustrating a circuit configuration of a voltage-insensitive current source circuit according to Example 1. FIG. 実施例１にかかる第１チャンネル増幅器の差動増幅段の回路構成を示す図である。FIG. 3 is a diagram illustrating a circuit configuration of a differential amplification stage of the first channel amplifier according to the first embodiment; 実施例１にかかる第２チャンネル増幅器の差動増幅段の回路構成を示す図である。FIG. 3 is a diagram illustrating a circuit configuration of a differential amplification stage of the second channel amplifier according to the first embodiment. 本発明の実施例２にかかる２チャンネルの増幅回路のブロック構成を示す図である。It is a figure which shows the block configuration of the amplifier circuit of 2 channels concerning Example 2 of this invention. 本発明の実施例３にかかる２チャンネルの増幅回路のブロック構成を示す図である。It is a figure which shows the block configuration of the amplifier circuit of 2 channels concerning Example 3 of this invention. 本発明の実施例４にかかる２チャンネルの増幅回路のブロック構成を示す図である。FIG. 9 is a diagram illustrating a block configuration of a two-channel amplifier circuit according to a fourth embodiment of the invention. 本発明の実施例５にかかる３チャンネルの増幅回路のブロック構成を示す図である。FIG. 10 is a diagram illustrating a block configuration of a three-channel amplifier circuit according to Embodiment 5 of the present invention.
　以下、図面を参照しながら本発明の実施形態について詳細に説明する。本実施形態では、主として、２チャンネル差動信号を増幅する増幅回路であって、各チャンネルの増幅器は、第１差動増幅段、第２差動増幅段および出力バッファ段の３段構成の増幅器を例に説明する（実施例１～４）。本実施形態では、２チャンネル（Ｎ＝２）で供給電源電圧を２分割するが、供給電源電圧と各増幅器の動作電圧とを考慮して、２以上の多チャンネル化が可能である（実施例５）。また、各チャンネルの増幅器は、１段構成であっても多段構成であっても構わない。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the present embodiment, the amplifier circuit mainly amplifies a two-channel differential signal, and the amplifier of each channel is a three-stage amplifier including a first differential amplifier stage, a second differential amplifier stage, and an output buffer stage. (Examples 1 to 4). In this embodiment, the supply power supply voltage is divided into two by two channels (N = 2). However, considering the supply power supply voltage and the operating voltage of each amplifier, two or more multi-channels are possible (Example) 5). Further, the amplifier of each channel may have a single-stage configuration or a multi-stage configuration.
　図１に、本発明の実施例１にかかる２チャンネルの増幅回路のブロック構成を示す。増幅回路１０は、第１差動増幅段１１、第２差動増幅段１２および出力バッファ段１３を含む第１チャンネル増幅器と、第１差動増幅段２１、第２差動増幅段２２および出力バッファ段２３を含む第２チャンネル増幅器と、中間電圧安定化回路３１とから構成される。供給電源電圧は、正電源線（ＶＤＤ）～負電源線（ＶＳＳ）間に供給され、第１チャンネル増幅器の各増幅段と、第２チャンネル増幅器の各増幅段とが、ＶＤＤ～ＶＳＳ間に縦続に接続されている。 FIG. 1 shows a block configuration of a two-channel amplifier circuit according to Embodiment 1 of the present invention. The amplifier circuit 10 includes a first channel amplifier including a first differential amplifier stage 11, a second differential amplifier stage 12, and an output buffer stage 13, a first differential amplifier stage 21, a second differential amplifier stage 22, and an output. A second channel amplifier including a buffer stage 23 and an intermediate voltage stabilization circuit 31 are included. The power supply voltage is supplied between the positive power supply line (VDD) and the negative power supply line (VSS), and each amplification stage of the first channel amplifier and each amplification stage of the second channel amplifier are cascaded between VDD and VSS. It is connected to the.
　電流パスが他にないため、第１チャンネル増幅器を流れる電流の和と、第２チャンネル増幅器を流れる電流の和はと等しい。第１および第２チャンネル増幅器の構成が同じであれば、理想的には、　
　　正電源電圧（ＶＤＤ）－中間電圧（Ｖｍｉｄ）＝Ｖｍｉｄ－負電源電圧（ＶＳＳ）
すなわち、Ｖｍｉｄ－ＶＳＳ＝（１／２）（ＶＤＤ－ＶＳＳ）となる動作点が存在する。しかしながら、実際の増幅回路動作では、素子バラつきや、電圧変動、温度編号等の様々な要因から、その動作点が安定的に得られるとは限らない。そこで、中間電圧安定化回路３１は、中間電圧（Ｖｍｉｄ）と参照電圧（Ｖｒｅｆ）とを比較し、その結果（Ｖｃｔｒｌ）を第１チャンネル増幅器にフィードバックすることにより、Ｖｍｉｄ－ＶＳＳ＝（１／２）（ＶＤＤ－ＶＳＳ）となるように制御を行う。Ｖｒｅｆそのものは回路内部で、抵抗分圧などの手段により簡単に作れるため、シリーズレギュレータ回路のように消費電力を増大させることはない。 Since there is no other current path, the sum of the currents flowing through the first channel amplifier is equal to the sum of the currents flowing through the second channel amplifier. Ideally, if the first and second channel amplifier configurations are the same,
Positive power supply voltage (VDD)-Intermediate voltage (Vmid) = Vmid-Negative power supply voltage (VSS)
That is, there is an operating point where Vmid−VSS = (½) (VDD−VSS). However, in actual amplifier circuit operation, the operating point is not always stably obtained due to various factors such as element variation, voltage fluctuation, and temperature edition. Therefore, the intermediate voltage stabilization circuit 31 compares the intermediate voltage (Vmid) with the reference voltage (Vref), and feeds back the result (Vctrl) to the first channel amplifier, so that Vmid−VSS = (1/2 ) (VDD-VSS). Since Vref itself can be easily made in the circuit by means such as resistance voltage division, power consumption is not increased unlike a series regulator circuit.
　図２に、実施例１にかかる増幅回路において電圧不感型電流源回路を用いた場合の構成を示す。第１および第２チャンネル増幅器の第１差動増幅段１１，２１からなる初段のみを抽出してある。ＶＤＤ～Ｖｍｉｄ間に第１電圧不感型電流源回路４１、Ｖｍｉｄ～ＶＳＳ間に第２電圧不感型電流源回路４２が挿入されている。第２電圧不感型電流源回路４２の出力Ｉｃｔｒｌは、第２チャンネル増幅器の第１差動増幅段２１に接続されている。第１チャンネル増幅器と第２チャンネル増幅器とを流れる電流が等しいことを利用するため、第１電圧不感型電流源回路４１がダミーとして挿入されているが、第１チャンネル増幅器の第１差動増幅段１１とは接続されない。 FIG. 2 shows a configuration when a voltage-insensitive current source circuit is used in the amplifier circuit according to the first embodiment. Only the first stage consisting of the first differential amplification stages 11 and 21 of the first and second channel amplifiers is extracted. A first voltage insensitive current source circuit 41 is inserted between VDD and Vmid, and a second voltage insensitive current source circuit 42 is inserted between Vmid and VSS. The output Ictrl of the second voltage insensitive current source circuit 42 is connected to the first differential amplification stage 21 of the second channel amplifier. In order to use the fact that the currents flowing through the first channel amplifier and the second channel amplifier are equal, the first voltage insensitive current source circuit 41 is inserted as a dummy, but the first differential amplification stage of the first channel amplifier 11 is not connected.
　図３に、実施例１にかかる電圧不感型電流源回路の回路構成を示す。第２電圧不感型電流源回路４２は、定電流回路４２ａとカレントミラー回路４２ｂとから構成される。定電流回路４２ａは、正電源端子（Ｖ＋）がＶｍｉｄに接続され、負電源端子（Ｖ－）がＶＳＳに接続される。定電流回路４２ａは、Ｖ＋～Ｖ－間の電圧が変動しても、抵抗Ｒ１に流れる電流が一定となり、これを基準電流として、カレントミラー回路４２ｂで所望の係数で増幅し、電流制御出力Ｉｃｔｒｌ１～Ｉｃｔｒ３とする。 FIG. 3 shows a circuit configuration of the voltage-insensitive current source circuit according to the first embodiment. The second voltage insensitive current source circuit 42 includes a constant current circuit 42a and a current mirror circuit 42b. The constant current circuit 42a has a positive power supply terminal (V +) connected to Vmid and a negative power supply terminal (V−) connected to VSS. In the constant current circuit 42a, even if the voltage between V + and V− fluctuates, the current flowing through the resistor R1 becomes constant, and this is used as a reference current and amplified by a desired coefficient in the current mirror circuit 42b, and the current control output Ictrl1 ~ Ictr3.
　図２に示したように、電流制御出力Ｉｃｔｒｌ１を、第２チャンネル増幅器の第１差動増幅段２１に接続することにより、通常の差動増幅段が備えている電流源回路に代わって、第２電圧不感型電流源回路４２が第１差動増幅段２１の電流源回路を制御する（以下の図５を参照）。これにより、第１差動増幅段２１に流れる電流が、中間電圧に依存しない基準電流により決定されて、第１および第２チャンネル増幅器の第１差動増幅段１１，２１に流れる電流Ｉ１が、中間電圧（Ｖｍｉｄ）には影響されず、一意に決定される。 As shown in FIG. 2, the current control output Ictrl1 is connected to the first differential amplification stage 21 of the second channel amplifier, so that the current source circuit provided in the normal differential amplification stage can be replaced with the first one. The two-voltage insensitive current source circuit 42 controls the current source circuit of the first differential amplification stage 21 (see FIG. 5 below). Thereby, the current flowing through the first differential amplification stage 21 is determined by the reference current independent of the intermediate voltage, and the current I1 flowing through the first differential amplification stages 11 and 21 of the first and second channel amplifiers is It is uniquely determined without being affected by the intermediate voltage (Vmid).
　同様に、電流制御出力Ｉｃｔｒｌ２を第２チャンネル増幅器の第２差動増幅段２２に接続することにより、第２差動増幅段１２，２２に流れる電流Ｉ２を、および、電流制御出力Ｉｃｔｒｌ３を第２チャンネル増幅器の出力バッファ段２３に接続することにより、出力バッファ段１３，２３に流れる電流ＩＯを、中間電圧（Ｖｍｉｄ）には影響されず、それぞれ一意に決定することができる。 Similarly, by connecting the current control output Ictrl2 to the second differential amplification stage 22 of the second channel amplifier, the current I2 flowing through the second differential amplification stages 12 and 22 and the current control output Ictrl3 are second. By connecting to the output buffer stage 23 of the channel amplifier, the current IO flowing through the output buffer stages 13 and 23 can be uniquely determined without being influenced by the intermediate voltage (Vmid).
　以下、図４，５を参照して説明するように、第２電圧不感型電流源回路４２により第１差動増幅段１１，２１に流れる電流Ｉ１を決定し、中間電圧安定化回路３１により、第１差動増幅段１１，２１に加わる供給電源電圧（ＶＤＤ－ＶＳＳ）を２等分することによって、２チャンネル増幅器を同じ動作条件で駆動させることができる。同様に、３チャンネル以上の多チャンネル増幅器とした場合においても、各チャンネル増幅器に印加される駆動電圧を整数分の１にすることができ、各チャンネル増幅器の低消費電力化を図ることが可能となる。 Hereinafter, as will be described with reference to FIGS. 4 and 5, the current I1 flowing through the first differential amplification stages 11 and 21 is determined by the second voltage insensitive current source circuit 42, and the intermediate voltage stabilization circuit 31 By dividing the supply power voltage (VDD-VSS) applied to the first differential amplification stages 11 and 21 into two equal parts, the two-channel amplifier can be driven under the same operating conditions. Similarly, even when a multi-channel amplifier having three or more channels is used, the drive voltage applied to each channel amplifier can be reduced to an integer, and the power consumption of each channel amplifier can be reduced. Become.
　図４に、実施例１にかかる第１チャンネル増幅器の差動増幅段の回路構成を示す。第１チャンネル増幅器の第１差動増幅段１１と第２差動増幅段１２とは同じ回路構成である。第１差動増幅段１１は、差動入力Ｉｎ１（ＩC），Ｉｎ１（ＩT）に接続される差動増幅段と差動出力Ｏｕｔ１（ＯC），Ｏｕｔ１（ＯT）に接続される出力段、カスコード接続された電流源とを含む。 FIG. 4 illustrates a circuit configuration of the differential amplification stage of the first channel amplifier according to the first embodiment. The first differential amplification stage 11 and the second differential amplification stage 12 of the first channel amplifier have the same circuit configuration. The first differential amplification stage 11 is connected to the differential amplification stage connected to the differential inputs In1 (I C ) and In1 (I T ) and the differential outputs Out1 (O C ) and Out1 (O T ). An output stage and a cascode-connected current source.
　供給電源電圧は、正電源端子（Ｖ＋）をＶＤＤに接続し、負電源端子（Ｖ－）を第２チャンネル増幅器のＶ＋（ＶＤＤ側）に接続することにより供給される。２段にカスコード接続された電流源は、中間電圧安定化回路３１の電圧制御出力Ｖｃｔｒｌから生成されたＶｇ１，Ｖｇ２によって、それぞれ制御される。なお、電流源は、２段カスコード接続を例に記載したが、これに限らない。 The power supply voltage is supplied by connecting the positive power supply terminal (V +) to VDD and connecting the negative power supply terminal (V−) to V + (VDD side) of the second channel amplifier. The current sources cascode-connected in two stages are controlled by Vg1 and Vg2 generated from the voltage control output Vctrl of the intermediate voltage stabilization circuit 31, respectively. The current source is described as an example of two-stage cascode connection, but is not limited thereto.
　図５に、実施例１にかかる第２チャンネル増幅器の差動増幅段の回路構成を示す。第２チャンネル増幅器の第１差動増幅段２１と第２差動増幅段２２とは同じ回路構成である。第１差動増幅段２１は、差動入力Ｉｎ１（ＩC），Ｉｎ１（ＩT）に接続される差動増幅段と差動出力Ｏｕｔ１（ＯC），Ｏｕｔ１（ＯT）に接続される出力段、カスコード接続された電流源とを含む。 FIG. 5 illustrates a circuit configuration of a differential amplification stage of the second channel amplifier according to the first embodiment. The first differential amplification stage 21 and the second differential amplification stage 22 of the second channel amplifier have the same circuit configuration. The first differential amplification stage 21 is connected to the differential amplification stage connected to the differential inputs In1 (I C ) and In1 (I T ) and to the differential outputs Out1 (O C ) and Out1 (O T ). An output stage and a cascode-connected current source.
　供給電源電圧は、正電源端子（Ｖ＋）を第１チャンネル増幅器のＶ－（ＶＳＳ側）に接続し、負電源端子（Ｖ－）をＶＳＳに接続することにより供給される。２段にカスコード接続された電流源は、第２電圧不感型電流源回路４２の電流制御出力Ｉｃｔｒｌ１によって制御される。Ｉｃｔｒｌ１を基準として、電流源のトランジスタにかかるゲート電圧Ｖｇａ、Ｖｇｂを決定している。 The power supply voltage is supplied by connecting the positive power supply terminal (V +) to V- (VSS side) of the first channel amplifier and connecting the negative power supply terminal (V-) to VSS. The current source cascode-connected in two stages is controlled by the current control output Ictrl1 of the second voltage insensitive current source circuit 42. The gate voltages Vga and Vgb applied to the current source transistor are determined based on Ictrl1.
　第１チャンネル増幅器の第１差動増幅段１１に流れる電流がＩｃｔｒｌ１で決定されるＩ１と等しくなり、第１および第２チャンネル増幅器が増幅器として等しい特性を持つためには、電流源のトランジスタにかかるゲート電圧に関して、
　　Ｖｇａ－Ｖｓｓ＝　Ｖｇ１－Ｖｍｉｄ
　　Ｖｇｂ－Ｖｓｓ＝　Ｖｇ２－Ｖｍｉｄ
となる必要がある。 In order for the current flowing through the first differential amplifier stage 11 of the first channel amplifier to be equal to I1 determined by Ictrl1 and the first and second channel amplifiers have the same characteristics as the amplifier, it is applied to the current source transistor. Regarding gate voltage,
Vga-Vss = Vg1-Vmid
Vgb-Vss = Vg2-Vmid
It is necessary to become.
　中間電位発生回路３１は、中間電圧（Ｖｍｉｄ）と参照電圧（Ｖｒｅｆ）とを比較し、Ｖｍｉｄ＞Ｖｒｅｆの時にＶｃｔｒｌ（図４におけるＶｇ１、Ｖｇ２）を下げ、Ｖｍｉｄ＜Ｖｒｅｆの時にＶｃｔｒｌを上げる。中間電位発生回路３１は、ＶｍｉｄとＶｒｅｆとが等しくなるまで繰り返すことにより、上式を満たすように動作する。このとき、上式より、Ｖｇ１とＶｇ２との電位差が、第２チャンネル増幅器の第１差動増幅段２１の電流源の抵抗Ｒ２の電位差と等しくなればよい。すなわち、第２電圧不感型電流源回路４２の電流制御出力Ｉｃｔｒｌ１と抵抗Ｒ２とで一意に決定されるＶｇａとＶｇｂとの電位差に等しくなるように制御すればよい。 The intermediate potential generation circuit 31 compares the intermediate voltage (Vmid) with the reference voltage (Vref), decreases Vctrl (Vg1, Vg2 in FIG. 4) when Vmid> Vref, and increases Vctrl when Vmid <Vref. The intermediate potential generating circuit 31 operates so as to satisfy the above expression by repeating until Vmid and Vref become equal. At this time, from the above equation, the potential difference between Vg1 and Vg2 only needs to be equal to the potential difference of the resistor R2 of the current source of the first differential amplification stage 21 of the second channel amplifier. That is, it is only necessary to perform control so that the potential difference between Vga and Vgb uniquely determined by the current control output Ictrl1 of the second voltage insensitive current source circuit 42 and the resistor R2 is equal.
　図６に、本発明の実施例２にかかる２チャンネルの増幅回路のブロック構成を示す。増幅回路１１０は、第１差動増幅段１１１、第２差動増幅段１１２および出力バッファ段１１３を含む第１チャンネル増幅器と、第１差動増幅段１２１、第２差動増幅段１２２および出力バッファ段１２３を含む第２チャンネル増幅器と、中間電圧安定化回路１３１とから構成される。第１および第２差動増幅段の供給電源電圧は、ＶＤＤ～ＶＳＳ間に供給され、第１チャンネル増幅器の各増幅段と、第２チャンネル増幅器の各増幅段とが、ＶＤＤ～ＶＳＳ間に縦続に接続されている。出力バッファ段の供給電源電圧は、それぞれがＶＤＤ～ＶＳＳ間に接続されている点で、実施例１と異なる。 FIG. 6 shows a block configuration of a two-channel amplifier circuit according to Embodiment 2 of the present invention. The amplifier circuit 110 includes a first channel amplifier including a first differential amplifier stage 111, a second differential amplifier stage 112, and an output buffer stage 113, a first differential amplifier stage 121, a second differential amplifier stage 122, and an output. A second channel amplifier including a buffer stage 123 and an intermediate voltage stabilizing circuit 131 are included. The power supply voltage of the first and second differential amplification stages is supplied between VDD and VSS, and each amplification stage of the first channel amplifier and each amplification stage of the second channel amplifier are cascaded between VDD and VSS. It is connected to the. The supply power supply voltages of the output buffer stages are different from those of the first embodiment in that each is connected between VDD and VSS.
　非特許文献２と同様に、比較的小さい振幅を扱う前段に備わる増幅器（差動増幅段）のみ、小さな電源電圧で駆動し、その分の消費電力を削減することができる。一方、出力バッファ段では比較的大きな振幅を扱うことができるので、消費電力の削減と、大きな出力振幅とを両立することができる。 As in Non-Patent Document 2, only the amplifier (differential amplification stage) provided in the previous stage that handles a relatively small amplitude can be driven with a small power supply voltage, and power consumption can be reduced accordingly. On the other hand, since the output buffer stage can handle a relatively large amplitude, it is possible to achieve both a reduction in power consumption and a large output amplitude.
　図７に、本発明の実施例３にかかる２チャンネルの増幅回路のブロック構成を示す。各チャンネルの増幅器においては、出力バッファ段では大きな電流が流れるため、雑音源となり得る。そのため、差動増幅段の電源と出力バッファ段の電源を分離する手法が取られる。 FIG. 7 shows a block configuration of a two-channel amplifier circuit according to Embodiment 3 of the present invention. In the amplifier of each channel, a large current flows in the output buffer stage, which can be a noise source. Therefore, a method of separating the power supply of the differential amplifier stage and the power supply of the output buffer stage is taken.
　増幅回路２１０は、第１差動増幅段２１１、第２差動増幅段２１２および出力バッファ段２１３を含む第１チャンネル増幅器と、第１差動増幅段２２１、第２差動増幅段２２２および出力バッファ段２２３を含む第２チャンネル増幅器と、中間電圧安定化回路２３１，２３２とから構成される。第１および第２差動増幅段の供給電源電圧は、ＶＤＤ～ＶＳＳ間に供給され、第１チャンネル増幅器の各増幅段と、第２チャンネル増幅器の各増幅段とが、ＶＤＤ～ＶＳＳ間に縦続に接続されている。 The amplifier circuit 210 includes a first channel amplifier including a first differential amplifier stage 211, a second differential amplifier stage 212, and an output buffer stage 213, a first differential amplifier stage 221, a second differential amplifier stage 222, and an output. A second channel amplifier including a buffer stage 223 and intermediate voltage stabilizing circuits 231 and 232 are included. The power supply voltage of the first and second differential amplification stages is supplied between VDD and VSS, and each amplification stage of the first channel amplifier and each amplification stage of the second channel amplifier are cascaded between VDD and VSS. It is connected to the.
　出力バッファ段の供給電源電圧は、差動増幅段の電源とは異なるＶＤＤＯ～ＶＳＳＯ間に供給され、出力バッファ段２１３，２２３が、ＶＤＤＯ～ＶＳＳＯ間に縦続に接続されている。出力バッファ段にも中間電圧安定化回路２３２が接続され、差動増幅段から独立した制御を可能とする。本実施例においても、電圧不感型電流源回路を図２に示した構成と同様に備えていてもよい。 The power supply voltage of the output buffer stage is supplied between VDDO and VSSO different from the power supply of the differential amplifier stage, and the output buffer stages 213 and 223 are connected in cascade between VDDO and VSSO. An intermediate voltage stabilization circuit 232 is also connected to the output buffer stage, enabling control independent of the differential amplification stage. Also in this embodiment, a voltage insensitive current source circuit may be provided in the same manner as the configuration shown in FIG.
　図８に、本発明の実施例４にかかる２チャンネルの増幅回路のブロック構成を示す。増幅回路３１０の第１および第２チャンネル増幅器の第１差動増幅段３１１，３２１からなる初段のみを抽出してある。中間電圧安定化回路３３１の構成と動作は実施例１と同じである。 FIG. 8 shows a block configuration of a two-channel amplifier circuit according to Embodiment 4 of the present invention. Only the first stage composed of the first differential amplification stages 311 and 321 of the first and second channel amplifiers of the amplifier circuit 310 is extracted. The configuration and operation of the intermediate voltage stabilization circuit 331 are the same as those in the first embodiment.
　一般的に、差動増幅器においては、外部からの直接利得制御（Manual Gain Control）、出力振幅を一定とするための自動利得制御（Auto Gain Control）などの機能を有することがある。このうちＡＧＣ回路は、一種のフィードバックループとして機能する。従って、中間電圧安定化回路３３１で構成されるフィードバックループの中に含めてしまうと、ループが不安定化する恐れがある。 Generally, a differential amplifier may have functions such as direct external gain control (Manual Gain Control) and automatic gain control (Auto Gain Control) for making output amplitude constant. Among these, the AGC circuit functions as a kind of feedback loop. Therefore, if it is included in the feedback loop composed of the intermediate voltage stabilization circuit 331, the loop may become unstable.
　そこで、ＡＧＣ回路に流れる電流は、電圧不感型電流源回路３４１，４２で決定し、ＡＧＣ回路３５１，３５２から、第１差動増幅段３１１，３２１の制御端子に、中間電圧安定化回路を介さないで接続する。本実施例の構成は、ＡＧＣ回路に限らず、その他のフィードバック回路にも適用することができる。 Therefore, the current flowing through the AGC circuit is determined by the voltage insensitive current source circuits 341 and 42, and the intermediate voltage stabilizing circuit is passed from the AGC circuits 351 and 352 to the control terminals of the first differential amplification stages 311 and 321. Do not connect. The configuration of the present embodiment can be applied not only to the AGC circuit but also to other feedback circuits.
　図９に、本発明の実施例５にかかる３チャンネルの増幅回路のブロック構成を示す。増幅回路４１０は、第１差動増幅段、第２差動増幅段および出力バッファ段を含むチャンネル増幅器を、３チャンネル（Ｎ＝３）分ＶＤＤ～ＶＳＳ間に縦続に接続した増幅回路である。図９は、このうち第１差動増幅段からなる初段のみを抽出してある。 FIG. 9 shows a block configuration of a three-channel amplifier circuit according to Embodiment 5 of the present invention. The amplifier circuit 410 is an amplifier circuit in which channel amplifiers including a first differential amplifier stage, a second differential amplifier stage, and an output buffer stage are connected in cascade between VDD and VSS for three channels (N = 3). In FIG. 9, only the first stage consisting of the first differential amplification stage is extracted.
　Ｖｍｉｄ２～ＶＳＳ間に電圧不感型電流源回路４４１が挿入され、出力Ｉｃｔｒｌは、第３チャンネル増幅器の第１差動増幅段４５１に接続されている。ＶＤＤ～Ｖｍｉｄ１間、Ｖｍｉｄ１～Ｖｍｉｄ２間にはダミーの電圧不感型電流源回路が挿入されているが、ここでは省略してある。電圧不感型電流源回路４４１は、第１差動増幅段に流れる電流Ｉ１を、中間電圧（Ｖｍｉｄ２）には影響されず、一意に決定することができる。 A voltage insensitive current source circuit 441 is inserted between Vmid2 and VSS, and the output Ictrl is connected to the first differential amplification stage 451 of the third channel amplifier. Dummy voltage-insensitive current source circuits are inserted between VDD and Vmid1, and between Vmid1 and Vmid2, but are omitted here. The voltage insensitive current source circuit 441 can uniquely determine the current I1 flowing through the first differential amplification stage without being influenced by the intermediate voltage (Vmid2).
　各チャンネルの間に中間電圧安定化回路が挿入されており、中間電圧安定化回路４３１は、Ｖｒｅｆ１（＝（２／３）（ＶＤＤ－ＶＳＳ））と中間電圧（Ｖｍｉｄ１）とを比較して、第１チャンネル増幅器の第１差動増幅段４１１を制御する（Ｖｃｔｒｌ１）。中間電圧安定化回路４３２は、Ｖｒｅｆ２（＝（１／３）（ＶＤＤ－ＶＳＳ））と中間電圧（Ｖｍｉｄ２）とを比較して、第２チャンネル増幅器の第１差動増幅段４２１を制御する（Ｖｃｔｒｌ２）。 An intermediate voltage stabilization circuit is inserted between the channels, and the intermediate voltage stabilization circuit 431 compares Vref1 (= (2/3) (VDD−VSS)) with the intermediate voltage (Vmid1). The first differential amplifier stage 411 of the first channel amplifier is controlled (Vctrl1). The intermediate voltage stabilization circuit 432 compares Vref2 (= (1/3) (VDD−VSS)) with the intermediate voltage (Vmid2) to control the first differential amplification stage 421 of the second channel amplifier ( Vctrl2).
　電圧不感型電流源回路４４１は、第１差動増幅段４１１，４２１，４５１に流れる電流Ｉ１を決定し、中間電圧安定化回路４３１は、第１差動増幅段４１１に対して、ＶＤＤ－Ｖｍｉｄ１＝（１／３）（ＶＤＤ－ＶＳＳ）（＝ＶＤＤ－Ｖｒｅｆ１）となるように制御する。制御中間電圧安定化回路４３２は、第１差動増幅段４２１に対して、Ｖｍｉｄ１－Ｖｍｉｄ２＝（１／３）（ＶＤＤ－ＶＳＳ）（＝Ｖｒｅｆ１－Ｖｒｅｆ２）となるように制御する。 The voltage insensitive current source circuit 441 determines the current I1 flowing through the first differential amplification stages 411, 421, and 451, and the intermediate voltage stabilization circuit 431 provides VDD-Vmid1 to the first differential amplification stage 411. = (1/3) (VDD−VSS) (= VDD−Vref1). The control intermediate voltage stabilization circuit 432 controls the first differential amplification stage 421 so that Vmid1−Vmid2 = (1/3) (VDD−VSS) (= Vref1−Vref2).
　このようにして、第１差動増幅段４１１，４２１，４５１に加わる供給電源電圧（ＶＤＤ－ＶＳＳ）を３等分することによって、多チャンネル増幅器を同じ動作条件で動作させることができる。 In this way, by dividing the power supply voltage (VDD-VSS) applied to the first differential amplification stages 411, 421, 451 into three equal parts, the multi-channel amplifier can be operated under the same operating conditions.
　以下、４チャンネル以上の多チャンネル化も同様にして構成することができる。複数のＮ（Ｎは２以上の整数）チャンネルの信号を増幅する増幅回路であって、各々のチャンネルの増幅器が、１以上の増幅段を備えているとき、各チャンネルの増幅器の少なくとも１つの増幅段は、
　・１チャンネル目の増幅段の正電源端子が正電源線に接続され、負電源端子が２チャンネル目の増幅段の正電源端子に接続され、
　・ｎ（ｎは２以上Ｎ未満の整数）チャンネル目の増幅段の正電源端子がｎ－１番目の増幅段の負電源端子に接続され、負電源端子がｎ＋１チャンネル目の増幅段の正電源端子に接続され、
　・Ｎチャンネル目の増幅段の正電源端子がＮ－１チャンネル目の増幅段の負電源端子に接続され、負電源端子が負電源線に接続されることになる。 Hereinafter, a multi-channel configuration of four or more channels can be configured in the same manner. An amplifier circuit for amplifying a signal of a plurality of N (N is an integer of 2 or more) channels, and when each channel amplifier includes one or more amplification stages, at least one amplification of each channel amplifier The stage is
The positive power supply terminal of the first channel amplification stage is connected to the positive power supply line, the negative power supply terminal is connected to the positive power supply terminal of the second channel amplification stage,
-The positive power supply terminal of the amplification stage of the n (n is an integer of 2 or more and less than N) channel is connected to the negative power supply terminal of the (n-1) th amplification stage, and the negative power supply terminal is the positive power supply of the amplification stage of the (n + 1) th channel Connected to the terminal,
The positive power supply terminal of the Nth channel amplification stage is connected to the negative power supply terminal of the (N−1) th channel amplification stage, and the negative power supply terminal is connected to the negative power supply line.
　中間電圧安定化回路は、ｎ－１チャンネル目の増幅段とｎチャンネル目の増幅段との間の中間電圧と基準電圧とを比較して、ｎ－１チャンネル目の増幅段の電流源を制御する。 The intermediate voltage stabilization circuit controls the current source of the n−1 channel amplification stage by comparing the reference voltage with the intermediate voltage between the n−1 channel amplification stage and the n−channel amplification stage. To do.
　電圧不感型電流源回路は、Ｎチャンネル目の増幅段とＮ－１チャンネル目の増幅段との間の中間電圧と前記負電源端子電圧との間で基準電流を生成する定電流回路と、基準電流に基づいてＮチャンネル目の増幅段の電流源を制御する制御電流を出力するカレントミラー回路とを含む。 A voltage-insensitive current source circuit includes a constant current circuit that generates a reference current between an intermediate voltage between an N-th channel amplification stage and an N−1-th channel amplification stage and the negative power supply terminal voltage; A current mirror circuit that outputs a control current for controlling the current source of the amplification stage of the N-th channel based on the current.
　１０，１１０，２１０，３１０，４１０　増幅回路
　１１，１１１，２１１，３１１，２１，１２１，２２１，３２１，４１１，４２１，４３１　第１差動増幅段
　１２，１１２，２１２，２２，１２２，２２２　第２差動増幅段
　１３，１１３，２１３，２３，１２３，２２３　出力バッファ段
　３１，１３１，２３１，２３２，３３１，４３１，４３２　中間電圧安定化回路
　４１，３４１　第１電圧不感型電流源回路
　４２，３４２　第２電圧不感型電流源回路
　４４１　電圧不感型電流源回路
　４２ａ　定電流回路
　４２ｂ　カレントミラー回路
　３５１，３５２　ＡＧＣ回路 10, 110, 210, 310, 410 Amplifier circuit 11, 111, 211, 311, 21, 121, 221, 321, 411, 421, 431 First differential amplifier stage 12, 112, 212, 22, 122, 222 2 differential amplifier stages 13,113,213,23,123,223 output buffer stages 31,131,231,232,331,431,432 intermediate voltage stabilizing circuits 41,341 first voltage insensitive current source circuit 42, 342 Second voltage insensitive current source circuit 441 Voltage insensitive current source circuit 42a Constant current circuit 42b Current mirror circuit 351, 352 AGC circuit

Claims (3)

  1. 　複数のＮ（Ｎは２以上の整数）チャンネルの信号を増幅する増幅回路であって、
    　各々のチャンネルの増幅器は、１以上の増幅段を備え、各チャンネルの増幅器の少なくとも１つの増幅段は、
    　１チャンネル目の増幅段の正電源端子が正電源線に接続され、負電源端子が２チャンネル目の増幅段の正電源端子に接続され、
    　ｎ（ｎは２以上Ｎ未満の整数）チャンネル目の増幅段の正電源端子がｎ－１番目の増幅段の負電源端子に接続され、負電源端子がｎ＋１チャンネル目の増幅段の正電源端子に接続され、
    　Ｎチャンネル目の増幅段の正電源端子がＮ－１チャンネル目の増幅段の負電源端子に接続され、負電源端子が負電源線に接続され、
    　前記ｎ－１チャンネル目の増幅段と前記ｎチャンネル目の増幅段との間の中間電圧と基準電圧とを比較して、前記ｎ－１チャンネル目の増幅段の電流源を制御する中間電圧安定化回路を備え、
    　前記正電源線と前記負電源線との間の供給電源電圧がＮ等分されて、各チャンネルの増幅器に印加されることを特徴とする増幅回路。     An amplifying circuit for amplifying signals of a plurality of N (N is an integer of 2 or more) channels,
    Each channel amplifier comprises one or more amplification stages, and at least one amplification stage of each channel amplifier comprises:
    The positive power supply terminal of the amplification stage of the first channel is connected to the positive power supply line, the negative power supply terminal is connected to the positive power supply terminal of the amplification stage of the second channel,
    The positive power supply terminal of the amplification stage of the nth channel (n is an integer of 2 or more and less than N) is connected to the negative power supply terminal of the (n−1) th amplification stage, and the negative power supply terminal is the positive power supply terminal of the amplification stage of the (n + 1) th channel. Connected to
    The positive power supply terminal of the Nth channel amplification stage is connected to the negative power supply terminal of the (N−1) th channel amplification stage, the negative power supply terminal is connected to the negative power supply line,
    Comparing the intermediate voltage between the amplification stage of the (n-1) th channel and the amplification stage of the nth channel with a reference voltage, and controlling the current source of the amplification stage of the (n-1) th channel, the intermediate voltage stabilization Circuit
    An amplifier circuit characterized in that a supply power supply voltage between the positive power supply line and the negative power supply line is divided into N equal parts and applied to the amplifier of each channel.
  2. 　前記Ｎチャンネル目の増幅段と前記Ｎ－１チャンネル目の増幅段との間の中間電圧と前記負電源端子電圧との間で基準電流を生成する定電流回路と、前記基準電流に基づいて前記Ｎチャンネル目の増幅段の電流源を制御する制御電流を出力するカレントミラー回路とを含む電流源回路をさらに備えたことを特徴とする請求項１に記載の増幅回路。 A constant current circuit for generating a reference current between an intermediate voltage between the amplification stage of the N-th channel and the amplification stage of the (N−1) -th channel and the negative power supply terminal voltage; 2. The amplifier circuit according to claim 1, further comprising a current source circuit including a current mirror circuit that outputs a control current that controls a current source of an N-th amplifier stage.
  3. 　前記各チャンネルの増幅器の少なくとも１つの増幅段は、自動利得制御回路を備え、
    　前記電流源回路で生成された前記基準電流に基づいて、前記自動利得制御回路に流れる電流が決定されることを特徴とする請求項２に記載の増幅回路。     At least one amplification stage of the amplifier of each channel comprises an automatic gain control circuit;
    3. The amplifier circuit according to claim 2, wherein a current flowing through the automatic gain control circuit is determined based on the reference current generated by the current source circuit.
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JPH1031200A (en) * 1996-07-17 1998-02-03 Seiko Epson Corp Divided voltage generator for liquid crystal driving
JP2002314353A (en) * 2001-04-11 2002-10-25 Oki Electric Ind Co Ltd Semiconductor amplifier circuit
JP2004180268A (en) * 2002-09-30 2004-06-24 Toshiba Corp Amplifier circuit and liquid crystal display device using this
JP2012216896A (en) * 2011-03-31 2012-11-08 Fujitsu Ltd Power amplifier and communication device
JP2016225756A (en) * 2015-05-28 2016-12-28 三菱電機株式会社 Multistage amplifier
US20170047463A1 (en) * 2015-08-10 2017-02-16 California Institute Of Technology Systems and Methods for Controlling Supply Voltages of Stacked Power Amplifiers

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0247820U (en) * 1988-09-29 1990-04-03
JPH1031200A (en) * 1996-07-17 1998-02-03 Seiko Epson Corp Divided voltage generator for liquid crystal driving
JP2002314353A (en) * 2001-04-11 2002-10-25 Oki Electric Ind Co Ltd Semiconductor amplifier circuit
JP2004180268A (en) * 2002-09-30 2004-06-24 Toshiba Corp Amplifier circuit and liquid crystal display device using this
JP2012216896A (en) * 2011-03-31 2012-11-08 Fujitsu Ltd Power amplifier and communication device
JP2016225756A (en) * 2015-05-28 2016-12-28 三菱電機株式会社 Multistage amplifier
US20170047463A1 (en) * 2015-08-10 2017-02-16 California Institute Of Technology Systems and Methods for Controlling Supply Voltages of Stacked Power Amplifiers

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