WO2019170113A1 - Procédé et dispositif de détection à l'aveugle fondés sur un code de polarisation dans un système de communication - Google Patents

Procédé et dispositif de détection à l'aveugle fondés sur un code de polarisation dans un système de communication Download PDF

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Publication number
WO2019170113A1
WO2019170113A1 PCT/CN2019/077229 CN2019077229W WO2019170113A1 WO 2019170113 A1 WO2019170113 A1 WO 2019170113A1 CN 2019077229 W CN2019077229 W CN 2019077229W WO 2019170113 A1 WO2019170113 A1 WO 2019170113A1
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Prior art keywords
decoding
sequence
bit
difference
path
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PCT/CN2019/077229
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English (en)
Chinese (zh)
Inventor
刘荣科
孙贺
王桂杰
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华为技术有限公司
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
    • H04L1/0023—Systems modifying transmission characteristics according to link quality, e.g. power backoff characterised by the signalling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
    • H04L1/0036—Systems modifying transmission characteristics according to link quality, e.g. power backoff arrangements specific to the receiver
    • H04L1/0038—Blind format detection
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0078—Avoidance of errors by organising the transmitted data in a format specifically designed to deal with errors, e.g. location
    • H04L1/0079—Formats for control data

Definitions

  • the embodiments of the present invention relate to the field of communications technologies, and in particular, to a blind detection method and device based on a polarization code in a communication system.
  • the terminal device needs to know the downlink control information (DCI) configured by the base station to the terminal device before receiving or transmitting data, and the DCI passes the physical downlink control channel ( Physical Downlink Control channel (PDCCH) bearer.
  • DCI downlink control information
  • PDCCH Physical Downlink Control channel
  • the PDCCH has different formats, and each format corresponds to an aggregation level of a different Control Channel Element (CCE), where the aggregation level indicates the number of consecutive CCEs occupied by one PDCCH.
  • CCE Control Channel Element
  • the terminal device detects the DCI, the terminal device does not know which format of the DCI is carried by the PDCCH, and does not know which format of the PDCCH is used for the DCI to transmit. Therefore, the terminal device acquires the DCI by using a blind detection method.
  • one or more candidate PDCCHs constitute a search space.
  • the search space includes a Common Search Space (CSS) and a specific search space. After determining the search space, the terminal device attempts to decode a series of candidate PDCCHs in the search space, and performs a Cyclic Redundancy Check (CRC) on the decoding result to find its own DCI.
  • CCS Cyclic Redundancy Check
  • a Polar code is determined as a codec scheme of the control channel.
  • multiple blind detections are required for various possible DCI formats, and there are many problems of blind detection and low efficiency.
  • the embodiment of the present invention provides a blind detection method and device based on a polarization code in a communication system, so as to reduce the number of blind detections and improve the blind detection efficiency.
  • an embodiment of the present application provides a method for blind detection based on a polarization code in a communication system, including:
  • the receiving device obtains the blind detection information, where the blind detection information includes the length of the information bit sequence and the position of the frozen set in the sequence to be decoded corresponding to the DCIs of the different formats, where the DCI corresponding to the different format is to be decoded.
  • the length is the same.
  • the blind detection information includes at least a length of the first information bit sequence in the first to-be-decoded sequence corresponding to the downlink control information DCI of the first format, a location of the first frozen set, and a DCI of the second format. a length of the second information bit sequence in the corresponding second to-be-decoded sequence and a location of the second frozen set, wherein the first to-be-decoded sequence and the second to-be-decoded sequence are the same length;
  • the blind detection process may be used to perform blind detection of the first format DCI and the second format DCI for a continuous CCE by a blind detection process, thereby effectively reducing the number of detections and improving the blind detection efficiency.
  • the length of the first information bit sequence is greater than the length of the second information bit sequence
  • the first frozen set is a true subset of the second frozen set
  • the receiving device is configured according to the
  • the blind detection information is used to perform blind detection on the candidate physical downlink control channel PDCCH, including:
  • the receiving device acquires a first difference bit and a second difference bit according to the location of the first frozen set and the location of the second frozen set, where the first difference bit is the first to-be-decoded sequence and a position where the first bit attribute of the same location corresponding to the second to-be-decoded sequence is different, and the second difference bit is a same location of the first to-be-decoded sequence and the second to-be-decoded sequence Where the last bit attribute has a different position, the difference bit, that is, the bit corresponding to one sequence to be decoded is a frozen bit, and the bit information bit corresponding to another sequence to be decoded;
  • the receiving device performs blind detection on the candidate physical downlink control channel PDCCH according to the first difference bit, the second difference bit, and the length of the first information bit sequence and the length of the second information bit sequence. To obtain the DCI sent by the sending device.
  • the receiving device compares the candidate physics according to the first difference bit, the second difference bit, and the length of the first information bit sequence and the length of the second information bit sequence.
  • the downlink control channel PDCCH performs blind detection, including:
  • the receiving device acquires a candidate decoding path according to the soft information, the first difference bit, and the second difference bit carried on the candidate PDCCH, where the soft information is a coding device that uses a channel to encode the bit sequence. Transmitted to the receiving device, after the encoded bit sequence passes through the channel, the received signal sequence received by the receiving device;
  • the receiving device performs blind detection on the candidate physical downlink control channel PDCCH according to the candidate decoding path and the length of the first information bit sequence and the length of the second information bit sequence, to obtain the DCI sent by the sending device. .
  • the receiving device acquires a candidate decoding path according to the soft information, the first difference bit, and the second difference bit carried on the candidate PDCCH, including:
  • the receiving device acquires at least one first decoding path according to the soft information carried on the candidate PDCCH and the first difference bit, where the first decoding path is a decoding before the first difference bit a path, the first decoding sequence is the same as the first decoding path corresponding to the second to-be-decoded sequence, that is, only the first to-be-decoded sequence or the second to-be-decoded sequence needs to be decoded. ;
  • the receiving device acquires at least one second decoding path according to the soft information, the first difference bit, and the second difference bit carried on the candidate PDCCH, where the second decoding path is the a coding path between the difference bit and the second difference bit, the first coded sequence is different from the second code path corresponding to the second code to be decoded, that is, for the first to be decoded
  • the sequence and the second sequence to be decoded are separately decoded;
  • the receiving device acquires at least one third decoding path according to the soft information carried on the candidate PDCCH and the second difference bit, where the third decoding path is a decoding path after the second difference bit,
  • the first decoding sequence is the same as the third decoding path corresponding to the second to-be-decoded sequence; that is, only the first to-be-decoded sequence or the second to-be-decoded sequence needs to be decoded;
  • the receiving device obtains at least one candidate decoding path according to the at least one of the first decoding path, the at least one second decoding path, and the at least one third decoding path, and specifically, at least one third is obtained.
  • a candidate decoding path is obtained according to the third decoding path and the first decoding path and the second decoding path on the same path as the third decoding path.
  • the receiving device acquires at least one second decoding path according to the soft information, the first difference bit, and the second difference bit carried on the candidate PDCCH, including:
  • At least one first sub-decoding path corresponding to the first to-be-decoded sequence and the first part according to the soft information, the first difference bit, and the second difference bit carried on the candidate PDCCH At least one second sub-decoding path corresponding to the two to-be-decoded sequences, where the first sub-decoding path and the second sub-decoding path are between the first difference bit and the second difference bit Decoding path
  • the receiving device according to the length of the first information bit sequence and the length of the second information bit sequence, the first path metric value or each of the second sub-decodings of each of the first sub-decoding paths The second path metric of the path is compensated;
  • the receiving device according to the length of the first information bit sequence and the length of the second information bit sequence, the first path metric value of each of the first sub-decoding paths or Performing compensation processing on the second path metric value of each of the second sub-decoding paths, including:
  • Receiving, by the receiving device, compensation processing for each of the first path metric values according to a difference between a length of the first information bit sequence and a length of the second information bit sequence, or for each of the second path metric values Perform compensation and subtraction processing.
  • the receiving device performs compensation processing on each of the first path metric values according to a difference between a length of the first information bit sequence and a length of the second information bit sequence, or Each of the second path metric values is compensated and subtracted, including:
  • the receiving device performs a compensation addition process on each of the first path metric values according to the compensation difference value, or performs compensation and subtraction processing on each of the second path metric values.
  • the receiving device performs blind detection on the candidate physical downlink control channel PDCCH according to the candidate decoding path and the length of the first information bit sequence and the length of the second information bit sequence.
  • the DC sent by the sending device including:
  • the receiving device sequentially extracts the first information bit sequence in each of the candidate decoding paths according to the length of the first information bit sequence, until the DCI check of the first format in the extracted first information bit sequence
  • the DCI sent by the sending device is obtained, or the DCI of the first format in the first information bit sequence extracted in all candidate decoding paths fails to pass the check;
  • the receiving device sequentially extracts the first decoding channel in the candidate decoding path according to the length of the second information bit sequence. a second information bit sequence, until the DCI check of the second format in the extracted second information bit sequence passes, to obtain a DCI sent by the sending device, or a second information bit sequence extracted in all candidate decoding paths The DCI of the second format has not passed the verification.
  • the embodiment of the present application provides a receiving device, including:
  • An acquiring module configured to acquire blind detection information, where the blind detection information includes at least a length of a first information bit sequence in a first to-be-decoded sequence corresponding to the downlink control information DCI of the first format, and a location of the first frozen set and a length of the second information bit sequence and a second frozen set position in the second to-be-decoded sequence corresponding to the DCI of the second format, wherein the first to-be-decoded sequence and the second to-be-decoded sequence length the same;
  • the blind detection module is configured to perform blind detection on the candidate physical downlink control channel PDCCH according to the blind detection information, to obtain the DCI sent by the sending device.
  • the blind detection module is specifically configured to:
  • first difference bit is the first sequence to be decoded and the second a position at which a first bit attribute in the same position corresponding to the sequence to be decoded is different
  • second difference bit is a last bit in the same position corresponding to the first to-be-decoded sequence and the second to-be-decoded sequence a different location of the attribute, the bit attribute being an information bit or a frozen bit
  • the blind detection module is further specifically used for:
  • the candidate physical downlink control channel PDCCH is blindly detected according to the candidate decoding path and the length of the first information bit sequence and the length of the second information bit sequence to obtain a DCI sent by the transmitting device.
  • the blind detection module is further specifically used for:
  • the first decoding path is a decoding path before the first difference bit,
  • the first decoding sequence is the same as the first decoding path corresponding to the second to-be-decoded sequence;
  • the blind detection module is further specifically used for:
  • At least one second sub-decoding path corresponding to the sequence, the first sub-decoding path and the second sub-decoding path are decoding paths between the first difference bit and the second difference bit ;
  • Destroying the at least one first sub-decoding path and/or the at least one second sub-decoding path according to the first path metric value or the second path metric value after the compensation process, to obtain at least one The second decoding path is described.
  • the blind detection module is further specifically used for:
  • the blind detection module is further specifically used for:
  • the blind detection module is further specifically used for:
  • the second information bit sequence is sequentially extracted in each of the candidate decoding paths according to the length of the second information bit sequence. And obtaining, by the DCI check of the second format in the extracted second information bit sequence, the DCI sent by the sending device, or the second format in the second information bit sequence extracted in all candidate decoding paths. None of the DCIs passed the verification.
  • an embodiment of the present application provides a receiving device, including: a memory, a processor, and a computer program, where the computer program is stored in the memory, and the processor runs the computer program to perform the first aspect as above and The first aspect of the various possible methods of designing the method.
  • an embodiment of the present application provides a storage medium storing a computer program for implementing the method as described in the first aspect and various possible designs of the first aspect.
  • an embodiment of the present application provides a computer program product, where the computer program product includes computer program code, when the computer program code is run on a computer, causing the computer to perform the foregoing first aspect and the first aspect. Possible methods of designing the described.
  • an embodiment of the present application provides a chip, including a memory and a processor, where the memory is used to store a computer program, where the processor is configured to call and run the computer program from the memory, so that the chip
  • the memory is used to store a computer program
  • the processor is configured to call and run the computer program from the memory, so that the chip
  • the method and device for detecting a blind code based on a polarization code in the communication system provided by the embodiment, the method for acquiring blind detection information by the receiving device, where the blind detection information includes at least a first to-be-decoded sequence corresponding to the DCI of the first format.
  • the length of the code sequence and the second sequence to be decoded are the same, so that the receiving device can perform blind detection of at least the first format DCI and the second format DCI on the consecutive CCEs according to the blind detection information, that is, in one blind detection.
  • blind detection of DCI in at least two formats can be performed, which reduces the number of blind detections and improves the efficiency of blind detection.
  • FIG. 1 is a schematic structural diagram of a system for blind detection based on a polarization code in a communication system according to an embodiment of the present disclosure
  • FIG. 2 is a signaling flowchart of a method for detecting a blind code based on a polarization code in a communication system according to an embodiment of the present disclosure
  • FIG. 3A is a schematic diagram of extracting a difference bit according to an embodiment of the present application.
  • FIG. 3B is a schematic diagram of extracting a difference bit according to an embodiment of the present application.
  • FIG. 3C is a schematic diagram of extracting a difference bit according to an embodiment of the present application.
  • FIG. 4 is a flowchart of a method for blind detection based on a polarization code in a communication system according to an embodiment of the present disclosure
  • FIG. 5 is a schematic structural diagram of a decoding path according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic flowchart of a decoding algorithm according to an embodiment of the present disclosure.
  • FIG. 7 is a schematic diagram of comparison of decoding performance according to an embodiment of the present application.
  • FIG. 8 is a schematic diagram of comparison of decoding performance according to an embodiment of the present application.
  • FIG. 9 is a schematic diagram of comparison of decoding performance according to an embodiment of the present application.
  • FIG. 10 is a schematic diagram of comparison of decoding performance according to an embodiment of the present application.
  • FIG. 11 is a schematic diagram of comparison of decoding performance according to an embodiment of the present application.
  • FIG. 12 is a schematic diagram of comparison of decoding performance according to an embodiment of the present application.
  • FIG. 13 is a performance comparison diagram of an improved decoding and an exhaustive detection scheme according to an embodiment of the present application.
  • FIG. 14 is a schematic diagram of extracting a difference bit according to an embodiment of the present application.
  • FIG. 15 is a schematic diagram of extracting a difference bit according to an embodiment of the present application.
  • FIG. 16 is a schematic structural diagram of a receiving device according to an embodiment of the present disclosure.
  • FIG. 17 is a schematic structural diagram of hardware of a receiving device according to an embodiment of the present disclosure.
  • the embodiments of the present application can be applied to a wireless communication system.
  • the wireless communication system mentioned in the embodiments of the present application includes but is not limited to: Narrow Band-Internet of Things (NB-IoT), global mobile Global System for Mobile Communications (GSM), Enhanced Data Rate for GSM Evolution (EDGE), Wideband Code Division Multiple Access (WCDMA), Code Division Multiple Access (CDMA) 2000 System (Code Division Multiple Access, CDMA2000), Time Division-Synchronization Code Division Multiple Access (TD-SCDMA), Long Term Evolution (LTE), and Next Generation 5G Mobile Communication System .
  • NB-IoT Narrow Band-Internet of Things
  • GSM Global System for Mobile Communications
  • EDGE Enhanced Data Rate for GSM Evolution
  • WCDMA Wideband Code Division Multiple Access
  • CDMA Code Division Multiple Access
  • CDMA2000 Code Division Multiple Access 2000 System
  • TD-SCDMA Time Division-Synchronization Code Division Multiple Access
  • LTE Long Term Evolution
  • Next Generation 5G Mobile Communication System Next Generation 5G Mobile Communication
  • FIG. 1 is a schematic structural diagram of a system for blind detection based on a polarization code according to an embodiment of the present application.
  • the network device encodes Downlink Control Information (DCI) and carries it on the Physical Downlink Control Channel (PDCCH).
  • DCI Downlink Control Information
  • PDCH Physical Downlink Control Channel
  • the terminal device acts as the decoding side and tries in the search space. A series of candidate PDCCHs are decoded, and the DCI of the own is found by performing Cyclic Redundancy Check (CRC) on the decoding result.
  • CRC Cyclic Redundancy Check
  • the terminal device includes, but is not limited to, a mobile station (Mobile Station, MS), a mobile terminal (Mobile Terminal), a mobile telephone (Mobile Telephone), a mobile phone (handset), and a portable device (portable equipment). And so on, the terminal device can communicate with one or more core networks via a Radio Access Network (RAN), for example, the terminal device can be a mobile phone (or "cellular" phone), with wireless communication Functional computers, etc., terminal devices can also be portable, pocket-sized, handheld, computer-integrated or in-vehicle mobile devices or devices.
  • RAN Radio Access Network
  • terminal devices can also be portable, pocket-sized, handheld, computer-integrated or in-vehicle mobile devices or devices.
  • the present application describes various embodiments in connection with a network device.
  • the network device may be a device for communicating with the terminal device, for example, may be a Global System for Mobile Communications (GSM) or a Base Transceiver Station (BTS) in CDMA, or may be a WCDMA system.
  • the base station (NodeB, NB) may also be an evolved base station (Evolved Node B, eNB or eNodeB) in the LTE system, or the network device may be a relay station, an access point, an in-vehicle device, a wearable device, and a future 5G network.
  • PLMN Public Land Mobile Network
  • the polarization code is determined as the coding and coding scheme of the control channel, and in the process for blind detection, the coding scheme of the network device for the DCI is a Polar code coding scheme.
  • the Polar code herein includes, but is not limited to, an Arikan Polar code, a PC-Polar code, a CA-Polar code, and a PC-CA-Polar code.
  • Arikan Polar refers to the original Polar code, which is not cascaded with other codes, only information bits and frozen bits.
  • PC-Polar is a Polar code of Cascade Check (PC)
  • CA-Polar is a Cyclic Redundancy Check Aided (CA) Polar code and other cascading Polar codes.
  • the PC-CA-Polar code is a Polar code that concatenates both the PC and the CRC. PC-Polar and CA-Polar improve the performance of Polar codes by cascading different codes.
  • the Kronecker product defined as log 2 N matrices F 2 ; the addition and multiplication operations referred to above are addition and multiplication operations on a binary Galois field.
  • a part of the bits in u N are used to carry information (for example, DCI in this embodiment), which is called information bits, and the set of indexes of these bits is denoted as A; another part of the bits is set as the transceiver end.
  • a predetermined fixed value called freeze bits (bits fixed), which complement the index set a by a represents C.
  • freeze bits bits fixed
  • the Polar code is decoded based on a Successive Cancellation (SC) decoding algorithm or a Serial List Elimination (SC List, SCL) decoding algorithm or the like.
  • SC decoding algorithm that is, sequentially decodes from the first bit.
  • the serial cancellation list decoding algorithm is an improvement of the SC decoding algorithm. Multiple candidate decoding paths are reserved in each bit, and after decoding all the bits, all candidate decoding paths in the list are selected according to certain criteria, The final decoding result.
  • the network device since the terminal device does not know what DCI is sent by the network device, the network device needs multiple SC or SCL decoding for various possible DCI formats, and there are many detection times and low efficiency. .
  • a blind detection method based on a polarization code in a communication system is proposed to reduce the number of detections and improve the detection efficiency.
  • FIG. 2 is a signaling flowchart of a method for blind detection based on a polarization code in a communication system according to an embodiment of the present disclosure. As shown in Figure 2, the method includes:
  • the sending device sends the DCI on the physical downlink control channel.
  • the receiving device acquires the blind detection information, where the blind detection information includes at least a length of the first information bit sequence in the first to-be-decoded sequence corresponding to the downlink control information DCI of the first format, and a location of the first frozen set and the first a length of the second information bit sequence and a second frozen set position in the second to-be-decoded sequence corresponding to the DCI of the second format, wherein the first to-be-decoded sequence and the second to-be-decoded sequence are the same length ;
  • the receiving device performs blind detection on the candidate physical downlink control channel PDCCH according to the blind detection information, to obtain a DCI sent by the sending device.
  • the sending device may be a network device, and the receiving device may be a terminal device.
  • time-frequency resources allocated to a physical downlink control channel are divided into a plurality of Control Channel Elements (CCEs).
  • the CCE is the smallest unit that constitutes the PDCCH.
  • the PDCCH can be aggregated by L CCEs.
  • the L is called the Aggregation Level (AL).
  • the network device selects a suitable aggregation level to transmit the PDCCH of the terminal device according to the condition of the channel and the length of the DCI to be sent, and the DCI is carried on the PDCCH.
  • the DCI when DCI is polar coded, the DCI is carried on multiple information bits, and in the process, frozen bits are filled between information bits. Among them, the set of filled frozen bits is called a frozen set.
  • the number and location of frozen bits in the freeze set can be constructed in various ways, such as a Polar Weight (PW) construction.
  • PW Polar Weight
  • a possible implementation of the PW construction can be found in 3GPP TSG RAN WG1 Meeting #87. R1-1611254 proposes that this embodiment does not particularly limit the specific construction manner.
  • the DCI of the at least two formats is pre-designed in this embodiment.
  • the pre-designed content includes: the DCI of at least two formats corresponds to the same mother code length and the rate matching method, that is, the lengths of the information bit sequences corresponding to the DCIs of different formats and the sum of the lengths of the frozen bit sequences are equal.
  • the length of the information bit sequence may be the sum of the length of the DCI and the length of the CRC check bit, and the information bit sequence is filled to the position of the information bit.
  • the rate matching method means that bits on the transmission channel are repeated or punctured to match the carrying capacity of the physical channel, and the bit rate required for the transmission format is reached during channel mapping.
  • the length of the mother code is 2 n , and n is an integer greater than 0.
  • the length of the mother code can be understood as the sum of the length of the information bits before the encoding and the length of the frozen bits, or can be understood as the length of the encoded bit sequence, or It is understood as the length of the sequence to be decoded.
  • the network device may obtain blind detection information according to the pre-designed content, where the blind detection information includes a pre-designed mother code length corresponding to the DCI of the format.
  • the mother code length is the same as the mother code length corresponding to the DCI of at least one other format.
  • the network device fills the DCI and the CRC check bit correspondingly to the position of the information bit (also referred to as an information bit), and fills the frozen bit correspondingly to the position of the frozen bit (also It is called a frozen bit), and then encoded by rate matching or the like to obtain a coded bit sequence.
  • the network device sends the encoded bit sequence to the terminal device through the channel. After the encoded bit sequence passes through the channel, the received signal sequence received by the terminal device is soft information, and the terminal device performs decoding according to the received signal sequence.
  • the sequence to be decoded refers to a sequence of information bits before encoding and frozen bits.
  • the information bit sequence is obtained on the premise that the mother code length (the length of the sequence to be decoded), the position of the freeze set, and the received signal sequence are known. Considering that the frozen bit is known to both the transmitting and receiving parties, the frozen bit can be decoded without error, that is, the value agreed by the transmitting and receiving parties. Therefore, what is really needed for decoding is DCI.
  • the decoding method commonly used by the decoding end is SC decoding or SCL decoding.
  • the terminal device does not know which format of DCI is carried on the PDCCH, and does not know which candidate PDCCH is used for transmission by the DCI. Therefore, the terminal device does not know the length of the sequence to be decoded and freezes. The location of the set. However, the terminal device knows which state it is in and the DCI information that it expects to receive in this state, that is, the terminal device can determine the format of the possible DCI according to the state information of the terminal device.
  • the terminal device in the idle state (IDLE) state, the terminal device expects to receive a paging message (Paging); after initiating random access, the terminal device expects to receive a random access response; and expects uplink when there is uplink data to be transmitted.
  • Paging paging message
  • UL Grant UL Grant
  • the terminal device can acquire the blind detection information according to the state information of the terminal device and the foregoing pre-designed content, that is, determine the format of the possible DCI carried on the candidate PDCCH.
  • the blind detection information includes a length of the information bit sequence and a position of the frozen set in the sequence to be coded corresponding to the DCIs of the plurality of different formats, wherein the lengths of the to-be-decoded sequences corresponding to the DCIs of different formats are the same.
  • the blind detection information includes at least two corresponding information corresponding to DCIs of different formats, and the blind detection information includes at least a length of the first information bit sequence in the first to-be-decoded sequence corresponding to the DCI of the first format. a length of the second information bit sequence and a second frozen set position in the second to-be-decoded sequence corresponding to the location of the first frozen set and the DCI of the second format, wherein the first sequence to be decoded and the second to-be-coded The decoding sequence is the same length.
  • the terminal device can complete verification of multiple possible DCI formats by using one blind detection process according to the blind detection information, thereby effectively reducing the number of detections and improving the detection efficiency.
  • the blind detection process is described in detail by using the terminal device to determine that the format of the DCI sent by the network device is the first format or the second format.
  • the number of CCEs occupied by the two is the same, so that the start and end points of the corresponding CCEs can be the same, which makes the terminal When performing blind detection, blind detection of DCI of the first format and DCI of the second format may be simultaneously performed for consecutive CCEs.
  • the terminal device After receiving the soft information, the terminal device performs decoding verification on the first to-be-decoded sequence corresponding to the DCI of the first format and the second to-be-decoded sequence corresponding to the DCI in the second format according to the soft information. Code verification.
  • the terminal device can obtain more information by using the SC decoding algorithm or the SCL decoding algorithm on the premise of knowing the length of the first information bit sequence and the position of the first frozen set and the soft information.
  • a candidate decoding path performing CRC check on each candidate decoding path. If there is a candidate decoding path for successful verification, the format of the DCI sent by the network device is the first format; if there is no successful verification
  • the candidate decoding path indicates that the format of the DCI transmitted by the network device is not the first format.
  • the implementation is similar, and details are not described herein again.
  • the blind detection information is obtained by the receiving device, and the blind detection information includes at least the first information bit in the first to-be-decoded sequence corresponding to the DCI of the first format.
  • the lengths of the two to-be-decoded sequences are the same, so that the receiving device can perform blind detection of at least the first format DCI and the second format DCI on the consecutive CCEs according to the blind detection information, that is, in a blind detection process, Blind detection of at least two formats of DCI reduces the number of blind detections and improves the efficiency of blind detection.
  • a detailed embodiment is used to detect the decoding algorithm in the blind detection scheme based on the polarization code by using the terminal device to blindly detect the DCI of the first format and the DCI of the second format in a blind detection process.
  • Decoding input the length of two possible DCIs, the soft information corresponding to the candidate PDCCH.
  • Decoding output CRC check result of decoding result of candidate PDCCH in different format DCI.
  • the pre-designed content further includes: the length of the first information bit sequence is greater than the length of the second information bit sequence, and the first frozen set is a true subset of the second frozen set, that is, the DCI length of the two formats. different.
  • the network device determines the location of the frozen set according to the pre-designed content, and generates DCI according to the location of the frozen set.
  • FIG. 4 is a flowchart of a method for blind detection based on a polarization code in a communication system according to an embodiment of the present disclosure. As shown in FIG. 4, the method includes:
  • the terminal device, L 2 acquires a second information bit sequence length corresponding to the length of K 2 according to the first DCI format 1 first information bit sequence corresponding to a length based on the length K 1 L DCI second format, And obtaining the location of the first frozen set and the location of the second frozen set.
  • K 1 L 1 +24
  • K 2 L 2 +24
  • 24 is the length of the CRC
  • the terminal device acquires a first difference bit u a and a second difference bit u b according to a location of the first freeze set F 1 and a location of the second freeze set F 2 ; wherein the first difference bit u a is the first to wait And the second difference bit u b is the last position in the same position corresponding to the first to-be-decoded sequence and the second to-be-decoded sequence, where the first bit attribute of the same position corresponding to the second to-be-decoded sequence is different.
  • a bit attribute has a different position, and the bit attribute is an information bit or a freeze bit.
  • the position referred to in this embodiment can be understood as the sequence number of the information bit or the frozen bit in the sequence to be decoded, and can also be referred to as the index of the information bit or the index of the frozen bit.
  • 0 represents a freeze bit
  • a or B represents an information bit.
  • the first frozen set is a true subset of the second frozen set, and may mean that the number of frozen bits in the first frozen set is smaller than the number of frozen bits in the second frozen set, and for the first to-be-decoded sequence and the second to-be-decoded sequence The same position is a frozen bit in the first sequence to be decoded, and is also a frozen bit in the second sequence to be decoded.
  • the first difference bit is the sixth bit
  • the second difference bit is the 14th bit.
  • the sixth bit of the first to-be-decoded sequence is an information bit
  • the sixth bit of the second to-be-decoded sequence is a frozen bit, that is, a position different for the first bit attribute of the same position, in the first difference bit Previously, the information bits of the two sequences to be decoded and the arrangement of the frozen bits were the same.
  • the 14th bit of the first sequence to be decoded is an information bit
  • the 14th bit of the second sequence to be decoded is a frozen bit, that is, a position different for the last bit attribute of the same position, after the second difference bit, two to The information bits of the decoding sequence are arranged in the same order as the frozen bits.
  • the first difference bit and the second difference bit may also be the same position.
  • the embodiment of the present application is also applicable to the case where the first difference bit and the second difference bit are the same position.
  • the first difference bit and the second difference bit shown in FIG. 3A are taken as an example for detailed description. The implementation manners of the same position are similar, and the details are not described herein again.
  • the terminal device may perform blind detection on the candidate PDCCH according to the first difference bit, the second difference bit, and the length of the first information bit sequence and the length of the second information bit sequence to obtain the DCI sent by the network device.
  • the terminal device acquires a candidate decoding path according to the soft information, the first difference bit, and the second difference bit carried on the candidate PDCCH.
  • the terminal device may divide the decoding process into at least three parts according to the first difference bit and the second difference bit, where the first part is the decoding before the first difference bit, and the second part is the first difference bit and The decoding between the second difference bits, the third part is the decoding after the second difference bit, which will be described in detail below with reference to FIG.
  • FIG. 5 is a schematic structural diagram of a decoding path according to an embodiment of the present application.
  • the Polar code with the length of the mother code N corresponds to a full binary tree with a depth of N.
  • Each layer edge corresponds to one information bit or frozen bit.
  • Each node except the leaf node is left.
  • the edges between the right two successor nodes are labeled 0 and 1, respectively.
  • the decoding path from the root node to any leaf node length N corresponds to one decoding sequence (including frozen bits).
  • the path formed from the root node to any one node corresponds to a path metrics (PM) value.
  • the path metric is defined as the probability of the decoding sequence corresponding to the path, and its logarithmic form is often used for implementation.
  • the path metric value corresponding to each node is determined according to parameters such as soft information of the node and path metric values corresponding to the parent node of the node. This embodiment does not limit the specific manner of the path metric. Any path metric used in the Polar decoding for the SCL decoding algorithm can be applied to the present application.
  • the initial path is set to an empty path, all candidate paths are expanded by bit 0 or 1, and the path metrics are updated respectively, and the candidate paths are sorted by path metrics, and the path metric with the largest path is retained.
  • L candidate paths are deleted, and the remaining candidate paths are deleted.
  • the information bit sequences corresponding to the candidate paths are output in descending order of the path metric values, and the information is sequentially selected in the output order.
  • the bit sequence is subjected to a CRC check to obtain a decoded result.
  • L is the search width, that is, the maximum number of saved paths, and L is greater than or equal to 1.
  • the conventional decoding process is improved in conjunction with the first difference bit and the second difference bit of the present application, wherein the first difference bit is not in the same position as the second difference bit, similar to that shown in FIG. 3A.
  • the decoding process of the present application will be described in detail below with reference to FIG. 5.
  • the terminal device acquires at least one first decoding path according to the soft information and the first difference bit carried on the candidate PDCCH, where the first decoding path is a decoding path before the first difference bit, and the first sequence to be decoded
  • the first decoding path corresponding to the second sequence to be decoded is the same.
  • the two to-be-decoded sequences correspond to the same first decoding path before the first difference bit, so only the first to-be-decoded sequence or the second to-be-decoded sequence needs to be subjected to conventional SCL decoding before the first difference bit. , get the first decoding path.
  • the conventional SCL decoding includes extension and deletion of a decoding path.
  • decoding is performed according to the conventional SCL decoding algorithm, that is, all candidate paths are extended by bit 0 or 1, to obtain a first decoding path, and the path metric values are respectively updated.
  • the decoding calculation amount is reduced, and the decoding efficiency is improved.
  • the terminal device acquires at least one second decoding path according to the soft information, the first difference bit and the second difference bit carried on the candidate PDCCH, where the second decoding path is between the first difference bit and the second difference bit
  • the decoding path is different, and the first decoding sequence is different from the second decoding path corresponding to the second to-be-decoded sequence.
  • the decoding is performed according to the frozen bit when decoding u a and u b , that is, only the path lengthening is performed without path expansion, and the first waiting is performed.
  • the decoding sequence performs path expansion when decoding u a and u b , but does not perform path competition and deletion.
  • decoding can be performed by conventional SCL decoding.
  • the decoding u b When the decoding u b is completed, after obtaining the sub-decoding paths corresponding to the two to-be-decoded sequences, the sub-decoding paths are combined, and then the path is deleted according to the merged path to obtain at least one second decoding. path.
  • the lengths of the DCI of the first format and the DCI of the second format are different, the lengths of the information bits corresponding to the two to-be-decoded sequences are different between the first difference bit and the second difference bit, so Without loss of decoding performance, the sub-decoding path needs to be compensated.
  • the specific implementation is as follows:
  • the terminal device acquires, according to the soft information carried on the candidate PDCCH, at least one first sub-decoding path corresponding to the first to-be-decoded sequence and at least one second sub-decoding path corresponding to the second to-be-decoded sequence, where A sub-decoding path and a second sub-decoding path are decoding paths between the first difference bit and the second difference bit.
  • the terminal device divides the two types of decoding between the first difference bit and the second difference bit, that is, the above-mentioned class A decoding and class B decoding.
  • FIG. 5 a schematic diagram of two types of decoding is also given. As shown in FIG. 5, the left side corresponds to the second sub-decoding path corresponding to the second to-be-decoded sequence, and the right side corresponds to the first to-be-decoded sequence. The first sub-decoding path.
  • a conventional SCL decoding method can be employed, that is, path expansion and deletion can be performed for each class.
  • the terminal device performs, according to the length of the first information bit sequence and the length of the second information bit sequence, the first path metric value of each first sub-decoding path or the second path metric value of each second sub-decoding path Compensation processing.
  • the first path metric value of the first sub-decoding path and the second path metric value of the second sub-decoding path are obtained.
  • the first path metric and the second path metric are both path metrics from the root node to the node corresponding to u b .
  • the first path metric value or the second path metric value is compensated according to the length of the first information bit sequence and the length of the second information bit sequence.
  • the first path metric value is compensated and increased according to the difference between the length of the first information bit sequence and the length of the second information bit sequence, or the second path metric value is compensated and subtracted.
  • the first path metric value When performing compensation compensation processing on the first path metric value, the first path metric value may be multiplied by a corresponding coefficient greater than 1, to increase the first path metric value, or the first path metric value may be further divided by For a coefficient less than 1, etc., the above coefficient may be determined according to the difference, and the coefficient may have a correspondence with the difference, and the coefficient may also be a function of the difference, and the first path metric can be combined with the difference.
  • the manner in which the increase processing is performed is within the protection scope of the present application.
  • the second path metric value when the second path metric value is compensated and subtracted, the second path metric value may be multiplied by a corresponding coefficient smaller than 1, to reduce the first path metric value, or the first path may be further
  • the metric is divided by a coefficient greater than 1, etc., and the above coefficient may be determined according to the difference, and the coefficient may have a correspondence with the difference, and the coefficient may also be a function of the difference, and the metric of the second path can be The manner in which the reduction process is performed is within the scope of protection of the present application.
  • the terminal device acquires the compensation difference according to the correspondence between the difference value and the compensation difference value; the terminal device performs compensation compensation processing on each first path metric value according to the compensation difference value, or each second path The metric value is compensated and subtracted.
  • the difference is positively correlated with the compensation difference, and the difference may have a corresponding relationship with the compensation difference, and the correspondence may be implemented by using a table, or may be implemented by a formula or a function, etc., the implementation
  • the specific implementation of the correspondence relationship is not particularly limited.
  • the terminal device performs at least one first sub-decoding path and/or at least one second sub-decoding path according to the first path metric value or the second path metric value after the compensation process, to obtain at least one Two decoding paths.
  • the first sub-decoding path and the second sub-decoding path are combined, and then according to the search width L and the first after the compensation process
  • the path metric and the second path metric perform a subtraction process on the at least one first sub-decoding path and/or the at least one second sub-decoding path to obtain at least one second decoding path.
  • the merged first sub-decoding path and the second sub-decoding path are uniformly sorted according to the path metric value from low to high. If the total number of sub-decoding paths exceeds the search width L, the lowest metric is obtained. The value path begins to delete the path, and deletes the sub-decoding path with the lowest metric value each time until the sub-decoding path corresponding to the L high-path metric values remains. If the total number of merged paths does not exceed the search width L, the path deletion operation is not performed.
  • the path is deleted at the node corresponding to u b , and the last reserved path is the node in the solid line box in FIG. 5, as shown in FIG. 5, left.
  • Three paths are reserved on the side, and five paths are reserved on the right side, that is, eight second decoding paths are finally obtained.
  • the first path metric value or the second path metric value is compensated, that is, the compensation difference of the path metric is introduced in the merging process to avoid potential decoding performance loss caused by the DCI length uncertainty.
  • the terminal device acquires at least one third decoding path according to the soft information and the second difference bit carried on the candidate PDCCH, where the third decoding path is a decoding path after the second difference bit, and the first sequence to be decoded
  • the third decoding path corresponding to the second sequence to be decoded is the same.
  • the information bits and the frozen bits of the first to-be-decoded sequence and the second to-be-decoded sequence are the same after the second difference bit, and the same soft information is input, when decoding by the SCL decoding method, two The sequence to be decoded corresponds to the same first decoding path before the first difference bit, so after the second difference bit, only the first to-be-decoded sequence or the second sequence to be decoded needs to be subjected to conventional SCL decoding to obtain the first A three decoding path that includes expansion and deletion of the decoding path.
  • the search width L can be set according to actual needs, for example, the search width in 1), the search width after merging the path in 2), and the search width in 3) can be set to the same value.
  • two different search widths can be set according to two types of decoding.
  • the manner in which the search width is set is not particularly limited herein.
  • the terminal device obtains at least one candidate decoding path according to the at least one first decoding path, the at least one second decoding path, and the at least one third decoding path.
  • the candidate decoding path is obtained according to the third decoding path and the first decoding path and the second decoding path on the same path as the third decoding path.
  • first decoding path, the second decoding path, and the third decoding path located on the same path refer to that the first decoding path continues to perform decoding, and the second decoding can be obtained.
  • the path is followed by decoding by the second decoding path to obtain a third decoding path, whereby the first decoding path, the second decoding path, and the third decoding path form a candidate decoding path.
  • FIG. 6 is a schematic flowchart of a decoding algorithm according to an embodiment of the present application.
  • the second sequence to be decoded is decoded according to the method shown in 1), that is, FIG. 3A to FIG.
  • the A-containing sequence in 3C performs conventional CRC-SCL decoding.
  • the second sequence to be decoded is decoded according to the method shown in 3), that is, the conventional CRC-SCL decoding is performed on the sequence containing A in FIGS. 3A to 3C.
  • F A [i] 0? It refers to whether the i-th bit in the second sequence to be decoded is a frozen bit.
  • Y represents Yes
  • N represents No.
  • decoding is performed according to the frozen bit, and the path is updated. , according to the information bits for decoding, path expansion and deletion.
  • the first sequence to be decoded (the sequence containing B in FIGS. 3A to 3C, referred to as class B) and the second sequence to be decoded are performed according to the method shown in 2) 3A to 3C, the sequence containing A, called class A) is classified and decoded.
  • F B [i] 0? It refers to whether the i-th bit in the first sequence to be decoded is a frozen bit. That is to say, before u b , the two types of decoding methods are conventionally decoded according to the frozen bit and the information bit. If the bit is frozen, the decoding is performed according to the frozen bit, and the path is updated.
  • the information bit is followed.
  • the terminal device performs blind detection on the candidate PDCCH according to the length of the candidate decoding path and the length of the first information bit sequence and the length of the second information bit sequence to obtain the DCI sent by the network device.
  • the terminal device sequentially extracts the first information bit sequence in each candidate decoding path according to the length of the first information bit sequence, until the DCI check of the first format in the extracted first information bit sequence passes,
  • the DCI sent by the network device that is, the DCI of the first format, or the DCI of the first format in the first information bit sequence extracted in all candidate decoding paths fails to pass the check; wherein the first information bit sequence includes The DCI of the first format and the CRC can be used to check the DCI of the first format by the CRC.
  • the terminal device sequentially extracts the second information bit sequence in each candidate decoding path according to the length of the second information bit sequence until the extraction is performed.
  • the DCI check of the second format in the second information bit sequence is passed, and the DCI sent by the network device, that is, the DCI of the second format, or the DCI in the second information bit sequence extracted in all candidate decoding paths is obtained. None of them passed the verification.
  • the second information bit sequence includes a DCI of the second format and a CRC, and the DCI of the second format can be verified by the CRC.
  • the current candidate PDCCH does not belong to the terminal device itself, and attempts to detect the next candidate PDCCH.
  • the polarization code decoding algorithm based on blind detection in this embodiment can complete the verification of two possible DCI formats by one decoding process without knowing the actual DCI information length, thereby reducing the number of busy detections and improving the number of busy detections. Blind detection efficiency.
  • the performance compensation mechanism is designed in the improved decoding algorithm for blind detection.
  • the path metric difference is introduced in the merging process to avoid the potential loss of decoding performance due to the uncertainty of DCI length.
  • the compensation method is simple and easy. easy to accomplish.
  • the improved decoding that is, the decoding method used in the present application, inputs two possible DCI lengths, decodes the received soft information when the actual DCI length is unknown, and performs CRC check according to the possible DCI length, and determines The final DCI length and DCI information.
  • the Block Error Ratio (BLER) performance of the decoding is simulated under different DCI length combinations and compared with the decoding performance of the CA-SCL algorithm with known DCI length.
  • CA-SCL is a conventional CA-SCL decoding in the prior art
  • Pd is an improved decoding of the present application.
  • the improved decoding refers to a decoding algorithm that obtains the decoding result of DCI in two formats.
  • the conventional CA-SCL decoding refers to decoding the DCI of two formats twice, that is, decoding one at a time. Formatted DCI.
  • Figure 7, Figure 8, and Figure 9 show the improved decoding and CA-SCL decoding when the DCI length combinations are ⁇ 25, 35 ⁇ , ⁇ 31, 51 ⁇ , ⁇ 10, 40 ⁇ , and the mother code length is 512 bits (bits).
  • (Conventional Decoding) Performance comparison in which the compensation difference in the compensation process is 7, 15, 20, respectively.
  • the error rate of the improved decoding algorithm is lower than that of the conventional decoding algorithm.
  • the bit error rate and the conventional decoding algorithm are improved under the same SNR.
  • the decoding algorithm is basically the same.
  • Figure 10, Figure 11, and Figure 12 show the performance of improved decoding and conventional CRC-SCL decoding when the DCI length combinations are ⁇ 25, 35 ⁇ , ⁇ 31, 51 ⁇ , ⁇ 10, 40 ⁇ , and the mother code length is 256 bits. Comparison. The compensation difference in the compensation process is 7, 15, and 20, respectively. As shown in FIG. 10, FIG. 11 and FIG. 12, under the same SNR, the error rate of the improved decoding algorithm is basically the same as that of the conventional decoding algorithm, and even slightly lower than the conventional decoding algorithm.
  • the improved decoding algorithm for blind detection is consistent with the performance curve of the conventional CA-SCL decoding algorithm under different DCI length combinations.
  • This application obtains two formats of DCI by one decoding algorithm. Decoding the DCI of one format separately from a single time improves the decoding efficiency and reduces the number of blind detections without causing loss of decoding performance.
  • FIG. 13 is a performance comparison diagram of an improved decoding and an exhaustive type detection scheme according to an embodiment of the present application.
  • the format of DCI is fomat1 and fomat1A
  • the PDCCH is transmitted in PDCCH 3 format (aggregation level 8) with low SNR (SNR ⁇ -5dB).
  • the PDCCH2 format is adopted in high SNR (SNR ⁇ -5dB).
  • the PDCCH (aggregation level is 4) is transmitted.
  • Table 2 gives the simulation parameters for each mother code length, where K 1 K 2 represents the length of the information bit sequence containing the 24-bit CRC, and L 1 L 2 represents the corresponding initial DCI length before the CRC encoding.
  • ⁇ K represents the difference in length of the information bit sequence
  • ⁇ PM represents the compensation difference used by the improved decoding algorithm in performing path merging.
  • curve fitting is performed according to the simulation results given in Table 2, and different fitting orders are used respectively.
  • the fitting function of the compensation difference and the length difference obtained by fitting according to the first-order function is:
  • the fitting function of the difference between the compensation difference and the length obtained by fitting according to the third-order function is:
  • the compensation difference may be obtained according to the above table 2 or the fitting function 1 and the fitting function 2 described above. It should be understood by those skilled in the art that the above-mentioned compensation difference is only exemplary, and the other manners for compensating the difference are not limited in this embodiment.
  • the format of the DCI is two, that is, there are two possible lengths of the DCI given, and the mother code length is the same, when the DCI format is greater than 2, that is, DCI
  • the present application is equally applicable when the possible length is greater than 2, and the length of the mother code is the same.
  • the difference from the embodiment of FIG. 4 described above may be the process of extracting and compensating the difference bits.
  • the implementation of the difference bit extraction and the compensation processing of the DCIs of the three lengths is given in the following with reference to FIG. 14 and FIG. 15.
  • the implementation of the DCI for the more length combinations is similar to this, and will not be repeated here.
  • FIG. 14 is a schematic diagram of extracting a difference bit according to an embodiment of the present application. As shown in FIG. 14, this embodiment extracts the first difference bit u a and the last difference bit u b between the three. That is, the present application is similar to the embodiment shown in FIG. 4, and only two difference bits are extracted.
  • a coding sequence between u a and u b respectively decoded sequence A, B and C sequence sequence, u b when the decoding is completed, when the sequence of the B and C sequences compensation process
  • the B sequence can be compensated according to the difference between the information bit sequence in the B sequence and the information bit sequence in the A sequence.
  • the information bit sequence in the C sequence and the information bit sequence in the A sequence can be compensated according to the difference between the information bit sequence in the B sequence and the information bit sequence in the A sequence.
  • the length difference is used to compensate the C sequence.
  • the A sequence may be compensated without compensation for the B sequence and the C sequence.
  • the A sequence may be compensated according to the average of the compensation differences between the two and the A sequence.
  • FIG. 15 is a schematic diagram of extracting a difference bit according to an embodiment of the present application.
  • the first difference bit u a between the three existences is extracted first, but the last difference position u b between the A sequence and the B sequence is extracted, and finally the last between the A sequence and the C sequence is extracted.
  • a difference bit u c is extracted after decoding to u a , the A sequence, the B sequence and the C sequence are respectively decoded, and when the u b decoding is completed, the sub decoding path corresponding to the B sequence is compensated, and then the sub corresponding to the A sequence The decoding path performs merge and delete processing, and then continues to decode the A sequence.
  • the sub-decoding path corresponding to the C sequence is compensated, and then the sub-decoding path corresponding to the A sequence is merged.
  • the deletion process continues to decode the A sequence after u c to obtain the final candidate decoding path. Therefore, in this embodiment, the last difference bit between each sequence and the A sequence is obtained.
  • the A sequence is not compensated, and the other sequences are compensated.
  • the process of the compensation process can be referred to above. The embodiments are not described herein again.
  • the present embodiment performs the detection of the DCI in the decoding process.
  • For each candidate PDCCH it can be determined by one decoding that the candidate PDCCH belongs to the user itself, and does not need to follow different information for each candidate PDCCH.
  • the length is decoded multiple times, thereby reducing the number of detections.
  • the improved decoding algorithm for blind detection proposed in this embodiment can complete at least two possibilities by one decoding process without knowing the actual DCI information length.
  • the verification of DCI format at the same time, the performance compensation mechanism is designed in the improved decoding algorithm for blind detection, and the compensation difference is introduced in the merge process to avoid the potential decoding performance loss due to the uncertainty of DCI length. .
  • FIG. 16 is a schematic structural diagram of a receiving device according to an embodiment of the present disclosure. As shown in FIG. 16, the receiving device 160 includes an obtaining module 1601 and a blind detecting module 1602. among them,
  • the obtaining module 1601 is configured to acquire the blind detection information, where the blind detection information includes at least the length of the first information bit sequence and the location of the first frozen set in the first to-be-decoded sequence corresponding to the downlink control information DCI of the first format. And a length of the second information bit sequence and a second frozen set position in the second to-be-decoded sequence corresponding to the DCI of the second format, wherein the first to-be-decoded sequence and the second to-be-decoded sequence The same length;
  • the blind detection module 1602 is configured to perform blind detection on the candidate physical downlink control channel PDCCH according to the blind detection information, to obtain the DCI sent by the sending device.
  • the blind detection module 1602 is configured to: acquire a first difference bit and a second difference bit according to a location of the first freeze set and a location of the second freeze set, where the first difference bit a position at which the first bit attribute of the same position corresponding to the first to-be-decoded sequence and the second to-be-decoded sequence is different, the second difference bit is the first to-be-decoded sequence and the a position where the last bit attribute in the same position corresponding to the second to-be-decoded sequence is different, and the bit attribute is an information bit or a freeze bit;
  • the blind detection module 1602 is further configured to: obtain a candidate decoding path according to the soft information, the first difference bit, and the second difference bit carried on the candidate PDCCH;
  • the candidate physical downlink control channel PDCCH is blindly detected according to the candidate decoding path and the length of the first information bit sequence and the length of the second information bit sequence to obtain a DCI sent by the transmitting device.
  • the blind detection module 1602 is further configured to: acquire at least one first decoding path according to the soft information carried on the candidate PDCCH and the first difference bit, where the first decoding path For the decoding path before the first difference bit, the first decoding path is the same as the first decoding path corresponding to the second to-be-decoded sequence;
  • the blind detection module 1602 is further specifically configured to:
  • At least one second sub-decoding path corresponding to the sequence, the first sub-decoding path and the second sub-decoding path are decoding paths between the first difference bit and the second difference bit ;
  • Destroying the at least one first sub-decoding path and/or the at least one second sub-decoding path according to the first path metric value or the second path metric value after the compensation process, to obtain at least one The second decoding path is described.
  • the blind detection module 1602 is further specifically configured to:
  • the blind detection module 1602 is further specifically configured to:
  • the blind detection module 1602 is further specifically configured to:
  • the second information bit sequence is sequentially extracted in each of the candidate decoding paths according to the length of the second information bit sequence. And obtaining, by the DCI check of the second format in the extracted second information bit sequence, the DCI sent by the sending device, or the second format in the second information bit sequence extracted in all candidate decoding paths. None of the DCIs passed the verification.
  • the receiving device provided by the embodiment of the present application can perform the method for detecting a blind code based on a polarization code in the above-mentioned communication system, and the implementation principle and the technical effect thereof are similar, and details are not described herein again.
  • the obtaining module and the blind detecting module of the embodiment may be implemented in a processor integrated or implemented as a processor.
  • FIG. 17 is a schematic structural diagram of hardware of a receiving device according to an embodiment of the present disclosure. As shown in FIG. 17, the receiving device 170 includes: a processor 1701 and a memory 1702;
  • a memory 1702 configured to store a computer program
  • the processor 1701 is configured to execute a computer program of the memory storage to implement the steps performed by the receiving device in the above embodiment. For details, refer to the related description in the foregoing method embodiments.
  • the memory 1702 can be either independent or integrated with the processor 1701.
  • the receiving device 170 may further include:
  • the bus 1703 is configured to connect the memory 1702 and the processor 1701.
  • the receiving device 170 shown in FIG. 17 may further include a receiver 1704 for receiving soft information and the like carried on the PDCCH.
  • the receiving device provided in this embodiment may be used to perform the method performed by the receiving device in the foregoing embodiments.
  • the implementation principle and technical effects are similar, and details are not described herein again.
  • the embodiment of the present application further provides a storage medium, where the storage medium stores a computer program, and the computer program is used to implement a polarization detection method based on a polarization code in the communication system shown in the foregoing embodiments.
  • the embodiment of the present application further provides a computer program product, comprising: computer program code, when the computer program code is run on a computer, causing the computer to perform polarization based on the communication system shown in the foregoing embodiments A blind detection method for codes.
  • the embodiment of the present application further provides a chip, including a memory and a processor, the memory is used to store a computer program, and the processor is configured to call and run the computer program from the memory, so that the chip performs the above A blind code detection method based on a polarization code in the communication system shown in the embodiment.
  • the disclosed apparatus and method may be implemented in other manners.
  • the device embodiments described above are only illustrative.
  • the division of the modules is only a logical function division.
  • multiple modules may be combined or integrated. Go to another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or module, and may be electrical, mechanical or otherwise.
  • modules described as separate components may or may not be physically separated, and the components displayed as modules may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • each functional module in each embodiment of the present invention may be integrated into one processing unit, or each module may exist physically separately, or two or more modules may be integrated into one unit.
  • the unit formed by the above module can be implemented in the form of hardware or in the form of hardware plus software functional units.
  • the above-described integrated modules implemented in the form of software function modules can be stored in a computer readable storage medium.
  • the software function module is stored in a storage medium, and includes a plurality of instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor (English: processor) to perform the embodiments of the present application. Part of the steps of the method.
  • processor may be a central processing unit (English: Central Processing Unit, CPU for short), or may be other general-purpose processors, digital signal processors (English: Digital Signal Processor, referred to as DSP), ASICs. (English: Application Specific Integrated Circuit, ASIC for short).
  • the general purpose processor may be a microprocessor or the processor or any conventional processor or the like. The steps of the method disclosed in connection with the invention may be directly embodied by the execution of the hardware processor or by a combination of hardware and software modules in the processor.
  • the memory may include high speed RAM memory, and may also include non-volatile memory NVM, such as at least one disk memory, and may also be a USB flash drive, a removable hard disk, a read only memory, a magnetic disk, or an optical disk.
  • NVM non-volatile memory
  • the bus may be an Industry Standard Architecture (ISA) bus, a Peripheral Component (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus.
  • ISA Industry Standard Architecture
  • PCI Peripheral Component
  • EISA Extended Industry Standard Architecture
  • the bus can be divided into an address bus, a data bus, a control bus, and the like.
  • address bus a data bus
  • control bus a control bus
  • the bus in the drawings of the present application is not limited to only one bus or one type of bus.
  • the above storage medium may be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read only memory (EEPROM), erasable In addition to Programmable Read Only Memory (EPROM), Programmable Read Only Memory (PROM), Read Only Memory (ROM), Magnetic Memory, Flash Memory, Disk or Optical Disk.
  • SRAM static random access memory
  • EEPROM electrically erasable programmable read only memory
  • EPROM Programmable Read Only Memory
  • PROM Programmable Read Only Memory
  • ROM Read Only Memory
  • Magnetic Memory Flash Memory
  • Disk Disk
  • Disk Optical Disk
  • An exemplary storage medium is coupled to the processor to enable the processor to read information from, and write information to, the storage medium.
  • the storage medium can also be an integral part of the processor.
  • the processor and the storage medium may be located in an Application Specific Integrated Circuits (ASIC).
  • ASIC Application Specific Integrated Circuits
  • the processor and the storage medium can also exist as discrete components in the electronic device or the master device.

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  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Quality & Reliability (AREA)
  • Mobile Radio Communication Systems (AREA)

Abstract

La présente invention concerne, selon un mode de réalisation, un procédé et un dispositif de détection à l'aveugle fondés sur un code de polarisation. Selon le procédé, un dispositif de réception acquiert des informations de détection à l'aveugle, les informations de détection à l'aveugle comprenant au moins une longueur d'une première séquence de bits d'informations dans une première séquence à décoder correspondant à des informations de commande de liaison descendante (DCI) dans un premier format, et un emplacement d'un premier ensemble gelé, ainsi qu'une longueur d'une seconde séquence de bits d'informations dans une seconde séquence à décoder correspondant à des DCI dans un second format et un emplacement du second ensemble gelé, la première séquence à décoder et la seconde séquence à décoder étant à la même longueur ; et le dispositif de réception effectue la détection à l'aveugle sur un canal physique de commande de liaison descendante physique (PDCCH) candidat en fonction des informations de détection à l'aveugle afin d'obtenir les DCI envoyées par le dispositif d'envoi. Le mode de réalisation de la présente invention permet de réduire le nombre de détections à l'aveugle et d'améliorer l'efficacité de détection à l'aveugle.
PCT/CN2019/077229 2018-03-09 2019-03-06 Procédé et dispositif de détection à l'aveugle fondés sur un code de polarisation dans un système de communication WO2019170113A1 (fr)

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CN112187409B (zh) * 2020-09-29 2023-01-13 哲库科技(北京)有限公司 译码方法和装置、终端、芯片及存储介质
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