WO2019167635A1 - Method for manufacturing three-dimensional semiconductor memory device - Google Patents

Method for manufacturing three-dimensional semiconductor memory device Download PDF

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Publication number
WO2019167635A1
WO2019167635A1 PCT/JP2019/005191 JP2019005191W WO2019167635A1 WO 2019167635 A1 WO2019167635 A1 WO 2019167635A1 JP 2019005191 W JP2019005191 W JP 2019005191W WO 2019167635 A1 WO2019167635 A1 WO 2019167635A1
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layer
semiconductor memory
memory device
manufacturing
dimensional semiconductor
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PCT/JP2019/005191
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French (fr)
Japanese (ja)
Inventor
和雄 吉備
大久保　和哉
俊武 津田
李　彰原
高橋　彰宏
坂本　渉
良典 西脇
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東京エレクトロン株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

Definitions

  • the following disclosure relates to a method for manufacturing a three-dimensional semiconductor memory device.
  • a semiconductor memory device in which memory cells are arranged three-dimensionally As a technique for increasing the degree of integration of semiconductor memory devices, many semiconductor memory devices in which memory cells are arranged three-dimensionally have been proposed.
  • a semiconductor memory device in which memory cells are arranged three-dimensionally is referred to as a three-dimensional semiconductor memory device.
  • a 3D NAND flash memory is known as a semiconductor memory device in which memory cells are arranged three-dimensionally.
  • One conventionally known three-dimensional semiconductor memory device (Patent Document 1 to Patent Document 4) has a plurality of memory strings in which a plurality of memory cells are connected in series.
  • the memory string has first to nth electrodes (n is a natural number of 2 or more).
  • the first to n-th electrodes are first to n-th conductor layers extending two-dimensionally, respectively.
  • the number of conductor layers is substantially equal to the number of memory cells included in the memory string. For this reason, as a method for increasing the degree of integration of the three-dimensional semiconductor memory device, it is conceivable to increase the number of conductor layers.
  • 3D NAND has been proposed in which the number of layers of a three-dimensional semiconductor memory device is 64 (Non-Patent Document 1).
  • Patent Documents 2 and 4 a method using selective epitaxial growth (SEG) has been proposed to form a contact for connecting a memory string of a three-dimensional semiconductor memory device and a substrate.
  • SEG selective epitaxial growth
  • the degree of integration of the three-dimensional semiconductor memory device it is conceivable to further increase the number of memory cells included in the memory string. That is, it is conceivable to further increase the number of conductor layers provided in the three-dimensional semiconductor memory device.
  • the aspect ratio of the channel hole extending from the uppermost layer of the conductor layer to the substrate is increased.
  • a method of manufacturing a three-dimensional semiconductor memory device is formed between a substrate and a stack formed on the substrate in which a plurality of oxide layers and nitride layers are alternately stacked. Removing the sacrificial layer through a slit that penetrates the stack. The manufacturing method also forms a contact layer electrically connected to the channel layer formed in the channel hole penetrating the stack by filling the void formed by removing the sacrificial layer through the slit. Process.
  • the channel region can be stably formed even when the number of layers of the three-dimensional semiconductor memory device is increased.
  • FIG. 1 is a diagram illustrating an example of a structure of a three-dimensional semiconductor memory device manufactured by a method of manufacturing a three-dimensional semiconductor memory device according to an embodiment of the present disclosure.
  • FIG. 2 is a flowchart illustrating an example of a flow of a method for manufacturing a three-dimensional semiconductor memory device according to an embodiment of the present disclosure.
  • FIG. 3 is a cross-sectional view illustrating a state in which a stack is formed in the method of manufacturing a three-dimensional semiconductor memory device according to an embodiment of the present disclosure.
  • FIG. 4 is a cross-sectional view illustrating a state in which channel holes are formed in the stack in the method for manufacturing a three-dimensional semiconductor memory device according to an embodiment of the present disclosure.
  • FIG. 1 is a diagram illustrating an example of a structure of a three-dimensional semiconductor memory device manufactured by a method of manufacturing a three-dimensional semiconductor memory device according to an embodiment of the present disclosure.
  • FIG. 2 is a flowchart illustrating an example of a
  • FIG. 5 is a cross-sectional view illustrating a state in which a channel structure is formed in a channel hole in the method for manufacturing a three-dimensional semiconductor memory device according to an embodiment of the present disclosure.
  • FIG. 6 is a cross-sectional view illustrating a state in which a slit is formed in the method for manufacturing a three-dimensional semiconductor memory device according to an embodiment of the present disclosure.
  • FIG. 7 is a cross-sectional view illustrating a state in which the sacrificial layer is removed in the method for manufacturing a three-dimensional semiconductor memory device according to an embodiment of the present disclosure.
  • FIG. 8 is a cross-sectional view illustrating a state in which a contact is opened in a channel hole in the method for manufacturing a three-dimensional semiconductor memory device according to an embodiment of the present disclosure.
  • FIG. 9 is a cross-sectional view illustrating a state in which the portion from which the sacrificial layer has been removed is backfilled in the method for manufacturing a three-dimensional semiconductor memory device according to an embodiment of the present disclosure.
  • FIG. 10 is a diagram for comparing the steps of the manufacturing method of the three-dimensional semiconductor memory device according to the embodiment of the present disclosure and the steps of the conventional manufacturing method.
  • a method for manufacturing a three-dimensional semiconductor memory device includes a substrate and a stack formed on the substrate, in which a plurality of oxide layers and nitride layers are alternately stacked. Removing a sacrificial layer to be formed through a slit penetrating the stack; Also, the manufacturing method of the three-dimensional semiconductor memory device is electrically connected to the channel layer formed in the channel hole penetrating the stack by filling the void formed by removing the sacrificial layer through the slit. Forming a contact layer.
  • the method of manufacturing a three-dimensional semiconductor memory device may include a step of forming a channel hole that reaches the bottom surface at a height where the sacrificial layer is formed through the stack.
  • the method for manufacturing a three-dimensional semiconductor memory device may further include a step of forming a first insulator layer, a channel layer, and a second insulator layer on the inner surface of the channel hole.
  • the method for manufacturing a three-dimensional semiconductor memory device may further include a step of removing the first insulator layer formed on the inner surface of the channel hole through a slit by etching. Good.
  • the step of removing the sacrificial layer may be performed by wet etching.
  • the step of removing the first insulator layer may be performed by dry etching.
  • the sacrificial layer may be formed of three layers of tungsten, silicon-doped tungsten, and titanium nitride.
  • the step of removing the sacrificial layer may use a mixed solution of phosphoric acid, acetic acid, and nitric acid.
  • an etching solution prepared by mixing phosphoric acid, acetic acid, and nitric acid at a mixing ratio of 2 to 30 mol / L, 0.2 to 10 mol / L, and 0.1 to 5 mol / L, respectively, may be used.
  • the etching solution may be used at a temperature of room temperature or higher and lower than 100 ° C.
  • FIG. 1 is a diagram illustrating an example of a structure of a three-dimensional semiconductor memory device 1 manufactured by a method for manufacturing a three-dimensional semiconductor memory device according to an embodiment of the present disclosure.
  • the X direction in FIG. 1 is also referred to as a horizontal direction
  • the Y direction is also referred to as a vertical direction.
  • the three-dimensional semiconductor memory device 1 includes a substrate 10, a conductive layer 20, a contact layer 30, a stack 40, and a slit 50.
  • the substrate 10 is, for example, a silicon substrate, a germanium substrate, a silicon-germanium substrate, or the like.
  • a peripheral circuit 11 is formed on the substrate 10.
  • the conductive layer 20 is disposed so as to be connected to the substrate 10.
  • the conductive layer 20 is made of, for example, polysilicon.
  • the substrate 10 and the conductive layer 20 are shown separately, but the substrate 10 and the conductive layer 20 may be the same and continuous in the horizontal direction of the drawing. Then, the peripheral circuit 11 and the stack 40 may be formed in different regions on the substrate 10, respectively.
  • a contact layer 30 is formed on the conductive layer 20.
  • the contact layer 30 is formed using a sacrificial layer 31 (see FIG. 3) described later.
  • Contact layer 30 is formed of, for example, polysilicon.
  • the contact layer 30 is disposed between the conductive layer 20 (substrate 10) and the stack 40, and is electrically connected to the substrate 10, the conductive layer 20, and the channel layer 62 (described later).
  • the stack 40 includes a plurality of insulator layers 41 and a plurality of conductor layers 42 extending in the lateral direction.
  • the insulator layers 41 and the conductor layers 42 are alternately arranged in the vertical direction.
  • a plurality of insulator layers are collectively denoted by reference numeral 41.
  • a plurality of conductor layers are collectively indicated by reference numeral 42.
  • Insulator layer 41 includes, for example, silicon oxide (SiO 2).
  • the conductor layer 42 includes, for example, polysilicon (Poly-Si), metal (for example, tungsten), metal nitride, or metal silicide.
  • the stack 40 can be formed by stacking an ONON (oxide / nitride) film or an OPOP (oxide / polysilicon) film on the conductive layer 20 (substrate 10).
  • the ONON film is a film formed by alternately stacking oxides and nitrides.
  • the OPOP film is a film formed by alternately stacking an oxide and polysilicon.
  • a slit 50 that is a hole reaching the contact layer 30 from the top of the stack 40 is formed.
  • a slit spacer 51 is formed on the inner peripheral surface of the slit 50.
  • the three-dimensional semiconductor memory device 1 further includes a channel structure 60.
  • the channel structure 60 includes a first insulator layer 61 formed in the channel hole CH, a channel layer 62, and a second insulator layer 63.
  • the channel structure 60 is, for example, a SONOS (Si—SiO 2 —SiN—SiO 2 —Poly-Si) structure.
  • the first insulator layer 61 is formed on the inner surface of the channel hole CH.
  • the first insulator layer 61 is, for example, an ONO layer that is a stacked film of a silicon oxide film 61a, a silicon nitride film 61b, and a silicon oxide film 61c.
  • the channel layer 62 is formed inside the first insulator layer 61.
  • the channel layer 62 is, for example, polysilicon.
  • the second insulator layer 63 is formed inside the channel layer 62.
  • the second insulator layer 63 is, for example, silicon oxide.
  • the first insulator layer 61, the channel layer 62, and the second insulator layer 63 each have a substantially cylindrical shape with a bottom having substantially the same center line as the channel hole CH. Further, the first insulator layer 61 is not formed at a position where the contact layer 30 is formed. For this reason, the contact layer 30 is connected to the channel layer 62 in the channel hole CH.
  • FIG. 2 is a flowchart illustrating an example of a flow of a method for manufacturing a three-dimensional semiconductor memory device according to an embodiment of the present disclosure.
  • the conductive layer 20 may be read as the substrate 10.
  • a sacrificial layer 31 (see FIG. 3) is formed on the prepared conductive layer 20 (step S11).
  • the insulator layer 41 and the sacrificial layer 42a (see FIG. 3) are alternately stacked on the sacrificial layer 31 to stack the stack 40a (see FIG. 3) (step S12).
  • a channel hole CH (see FIG. 4) reaching the conductive layer 20 through the stacked stack 40a and the sacrificial layer 31 is formed (step S13).
  • the channel hole CH is formed to such a depth that the channel layer 62 formed in the channel hole CH can be electrically connected to the contact layer 30 as described later.
  • the bottom surface of the channel hole CH does not necessarily reach the conductive layer 20.
  • a first insulator layer 61, a channel layer 62, and a second insulator layer 63 are sequentially formed so as to cover the inner surface of the channel hole CH to form a channel structure 60 (see FIG. 5) (see FIG. 5).
  • Step S14 a slit 50 (see FIG. 6) is formed in the stack 40a at a position where the channel hole CH is not formed (step S15). The slit 50 is formed to a depth that reaches the sacrificial layer 31 from the top of the stack 40a. Then, the sacrificial layer 31 (see FIG. 7) is removed through the slit 50 (step S16).
  • the first insulator layer 61 see FIG.
  • step S17 exposed by removing the sacrificial layer 31 is removed from the slit 50 (step S17).
  • the channel layer 62 is exposed from the channel hole CH.
  • the gap formed by removing the sacrificial layer 31 and the first insulator layer 61 is backfilled with a conductor (see FIG. 9).
  • the contact layer 30 that electrically connects the channel layer 62 and the conductive layer 20 (substrate 10) is formed (step S18).
  • the sacrificial layer 42a is removed from the slits 50 and the like and is backfilled, whereby the conductor layer 42 is formed at the position of the sacrificial layer 42a.
  • the three-dimensional semiconductor memory device 1 shown in FIG. 1 is formed.
  • steps S15 to S18 in FIG. 2 may be performed after the sacrifice layer 42a is removed and the conductor layer 42 is formed. That is, steps S11 to S18 in FIG. 2 may be executed for the stack 40a formed of the ONON film or may be executed for the stack 40 formed of the OPOP film.
  • the step of completing the three-dimensional semiconductor memory device 1 includes other steps for forming a structure not shown in FIG. 1, such as formation of a contact hole for extracting an electrode from the conductor layer 42 of the stack. The process is included, but the details are omitted here.
  • FIG. 3 is a cross-sectional view illustrating a state in which the sacrificial layer 31 and the stack 40a are formed in the method for manufacturing a three-dimensional semiconductor memory device according to the embodiment of the present disclosure.
  • the sacrificial layer 31 formed on the conductor layer 20 has, for example, a three-layer structure of tungsten (W), silicon-doped tungsten (Si-doped W), and titanium nitride (TiN). .
  • the sacrificial layer 31 may be formed of a plurality of polysilicon layers.
  • the method used for forming the sacrificial layer 31 is not particularly limited. For example, any method such as PE-CVD (Plasma-Enhanced Chemical Vapor Deposition), CVD (Chemical Vapor Deposition), ALD (Atomic Layer Deposition) can be used.
  • the thickness of the sacrificial layer 31 is preferably 40 nm (nanometers) or more and less than 80 nm.
  • the silicon concentration of the sacrificial layer 31 is preferably 3% or more and less than 7%.
  • the sacrificial layer 31 is formed to have a thickness of 60 nm and a silicon concentration of 5%.
  • the insulator layer 41 and the sacrificial layer 42a are alternately stacked so as to cover the upper surface of the sacrificial layer 31 to form the stack 40a.
  • FIG. 4 is a cross-sectional view illustrating a state in which the channel hole CH is formed in the stack 40a in the method for manufacturing a three-dimensional semiconductor memory device according to an embodiment of the present disclosure.
  • the formation of the channel hole CH is performed by etching or the like.
  • the depth of the channel hole CH only needs to reach the height at which the sacrificial layer 31 is formed. That is, the channel hole CH is formed so as to penetrate the stack 40a and reach the height at which the sacrificial layer 31 is formed.
  • FIG. 5 is a cross-sectional view illustrating a state in which the channel structure 60 is formed in the channel hole CH in the method for manufacturing a three-dimensional semiconductor memory device according to an embodiment of the present disclosure.
  • the channel structure 60 is formed by sequentially depositing each layer included in the channel structure 60 after cleaning the channel hole CH formed by etching.
  • the first insulator layer 61 is deposited.
  • the first insulator layer 61 is, for example, an ONO film that forms a portion of SiO2-SiN-SiO2 having a SONOS (Si-SiO2-SiN-SiO2-Poly-Si) structure.
  • the SiN layer becomes a charge storage layer, and the two SiO2 layers sandwich the SiN layer.
  • the first insulator layer 61 is formed by, for example, PE-CVD, CVD, ALD, or the like.
  • a channel layer 62 is further formed inside the first insulator layer 61 deposited so as to cover the inside of the channel hole CH.
  • the channel layer 62 is made of, for example, polysilicon.
  • the channel layer 62 is, for example, a Poly portion having a SONOS structure.
  • the second insulator layer 63 is made of, for example, silicon oxide.
  • the second insulator layer 63 is, for example, a Si portion having a SONOS structure.
  • FIG. 6 is a cross-sectional view illustrating a state in which the slit 50 is formed in the method for manufacturing a three-dimensional semiconductor memory device according to an embodiment of the present disclosure.
  • the slit 50 is formed by etching, for example.
  • the sacrificial layer 31 formed under the stack 40 becomes an etch stop layer that functions so as not to affect the etching of the lower layer.
  • the stack 40 is formed as an ONON layer in which an oxide and a nitride are sequentially deposited
  • the sacrificial layer 31 is made of tungsten (W), silicon-doped tungsten (Si-doped W), or titanium nitride (TiN). It is formed with a layer structure. If the sacrificial layer 31 has such a structure, etching can be stopped by the tungsten layer.
  • a slit spacer 51 is formed on the inner surface of the slit 50.
  • FIG. 7 is a cross-sectional view showing a state in which the sacrificial layer 31 is removed in the method for manufacturing a three-dimensional semiconductor memory device according to an embodiment of the present disclosure.
  • the sacrificial layer 31 is removed by, for example, wet etching or dry etching.
  • the sacrificial layer 31 is preferably removed by wet etching.
  • the method for bringing the etching solution into contact with the sacrificial layer 31 is not particularly limited.
  • the etchant may be dropped using single wafer spin processing or the like. Moreover, you may use a spray etc.
  • the sacrificial layer 31 may be immersed in the etching solution so as to be in contact with the etching solution.
  • the sacrificial layer 31 is removed by dipping in an etching solution.
  • the step for etching the sacrificial layer 31 includes a step of immersing the object in a heated etching solution.
  • the step includes, for example, a step of immersing the object in an etching solution and taking it out after a predetermined time and washing the etching solution adhering to the object.
  • the said process includes the process of drying the water etc. which have adhered to the target object after a washing
  • the type of etching solution for removing the sacrificial layer 31 is not particularly limited. Any etching solution may be used as long as it can dissolve W / Si doped W / TiN.
  • SPM sulfuric-acid and hydrogen-peroxide mixture
  • APM Ammonia-Hydrogen Peroxide Mixture
  • APM an aqueous ammonia solution or a hydrogen peroxide mixed solution
  • PAN Phosphoric-Acetic-Nitric-acids: a mixed solution of phosphoric acid, nitric acid, and acetic acid
  • the mixing ratio of SPM used in the present embodiment is not particularly limited, but the molar mixing ratio of sulfuric acid and hydrogen peroxide is preferably 4: 1 to 1: 5, more preferably 2: 1 to 2: 5. .
  • the use temperature of the etching solution is preferably 80 ° C. or higher and lower than 200 ° C., more preferably 100 ° C. or higher and lower than 140 ° C.
  • the reason why the temperature is 100 ° C. or higher is that if the temperature of the etching solution is 100 ° C. or higher, the etching rate will not be too low and the production efficiency will not be significantly reduced.
  • the reason why the temperature is lower than 140 ° C. is to suppress an error in the etching amount in the wafer and keep the etching conditions constant.
  • the temperature of the etchant is increased, the etching rate increases. However, in order to stabilize the quality, it is desirable to keep the change in the etching amount small.
  • the actual use temperature may be determined based on the balance between the etching rate and the quality within the above range.
  • the sacrificial layer 31 can be removed by etching at an etching rate of about 200 ( ⁇ / min) by SPM at a temperature of 100 ° C.
  • each layer of W / Si-doped W / TiN can be uniformly etched. For this reason, residual residue due to insufficient dissolution, corrosion due to excessive dissolution, and the like can be prevented.
  • the mixing ratio of various acids is not particularly limited in the treatment of the mixed aqueous solution of phosphoric acid, acetic acid and nitric acid, but 2 to 30 mol / L, 0.2 to 10 mol / L, respectively.
  • L preferably 0.1 to 5 mol / L. More preferably, it is 5 to 15 mol / L, 0.5 to 4 mol / L, and 0.1 to 2 mol / L for phosphoric acid, acetic acid, and nitric acid, respectively.
  • the operating temperature is preferably from room temperature to less than 100 ° C, more preferably from 50 ° C to less than 90 ° C. If the temperature of the etching solution is 50 ° C. or higher, the etching rate will not be too low, and the production efficiency will not be significantly reduced. On the other hand, if the temperature is lower than 90 ° C., an error in the etching amount in the wafer can be suppressed and the etching conditions can be kept constant. Although the etching rate is increased by increasing the temperature of the etching solution, the optimum processing temperature can be appropriately determined in consideration of suppressing the change in the etching amount.
  • the time required for etching the sacrificial layer 31 is not particularly limited, but is about 30 to 120 minutes.
  • FIG. 8 is a cross-sectional view illustrating a state in which an opening for exposing the channel layer 62 is formed in the channel hole CH in the method for manufacturing a three-dimensional semiconductor memory device according to the embodiment of the present disclosure.
  • Etching gas C 4 F 8 / CH 2 F 2 / Ar Gas flow rate: 10-30 / 40-80 / 200-1000sccm Pressure: 50-200mTorr Temperature: 10-40 ° C Power: 40MHz / 1000-2000W and 2MHz / 3000-50000W
  • the portion of the first insulator 61 that is removed is the portion that was in contact with the sacrificial layer 31. That is, a portion of the first insulator 61 sandwiched between the sacrificial layer 31 and the contact layer 62 is removed. As a result, the channel layer 62 formed inside the channel hole CH with respect to the first insulator 61 is exposed in the gap formed by removing the sacrificial layer 31.
  • FIG. 9 is a cross-sectional view illustrating a state in which the portion from which the sacrificial layer 31 has been removed is backfilled in the method for manufacturing a three-dimensional semiconductor memory device according to an embodiment of the present disclosure.
  • the contact layer 30 is formed by depositing a conductor, for example, polysilicon, in the gap formed by removing the sacrificial layer 31 and the portion of the first insulator 61 in contact with the sacrificial layer 31.
  • the contact layer 30 is in contact with the channel layer 62 exposed in the channel hole CH.
  • FIG. 10 is a diagram for comparing the process of the manufacturing method of the three-dimensional semiconductor memory device according to the embodiment of the present disclosure with the process of the conventional manufacturing method.
  • the conventional process is shown on the left side (A) of FIG.
  • the processing of this embodiment is shown on the right side (B) of FIG.
  • the manufacturing method of this embodiment may include the following steps. (0) Opening a channel hole (1) Cleaning the channel hole (2) Forming a first insulator layer 61 (ONO film) (3) Forming a channel layer 62 (polysilicon) (4) ) Forming the second insulator layer 62 (silicon oxide) (5) Removing the sacrificial layer 31 (6) Removing the first insulator layer 61 (ONO film) at a position in contact with the sacrificial layer 31 ( 7) Deposit polysilicon to be the contact layer 30
  • the process shown on the left side (A) of FIG. 10 is an example of a process flow conventionally used as a process for electrically connecting the conductive portion in the channel hole to the substrate.
  • This conventional example includes the following steps, for example. (0) Opening the channel hole (1) Cleaning the channel hole (2) By selective epitaxial growth (SEG), silicon is grown on the bottom of the channel hole (the silicon electrically connects the substrate and the conductive portion in the channel hole) Function to connect automatically) (3) An ONO film is formed inside the channel hole having silicon formed at the bottom. (4) Polysilicon serving as a spacer is deposited on the ONO film in a columnar shape to fill the channel hole. (5) In the channel hole.
  • SEG selective epitaxial growth
  • a columnar hole (contact hole) is formed by lithography in the formed columnar polysilicon (6)
  • the contact hole is etched to form an elongated hole reaching the silicon at the bottom of the channel hole (7)
  • the polysilicon is deposited to electrically connect the columnar polysilicon in the channel hole and the bottom silicon.
  • the upper portion of the channel hole is backfilled with oxide.
  • the manufacturing method according to the embodiment can stably form the channel region without the costly SEG process. Further, the manufacturing method of the embodiment can stably form the channel region without being affected by the decrease in the growth rate of the SEG even when the number of layers of the three-dimensional semiconductor memory device is increased. In addition, the manufacturing method of the embodiment does not require complicated film formation in the channel hole to form a contact with the substrate below the channel hole.
  • the manufacturing method of the embodiment does not require lithography for forming a channel contact in the channel hole. For this reason, the manufacturing method of the embodiment can manufacture a three-dimensional semiconductor memory device having a stable quality by a simple process compared to the conventional method.
  • the manufacturing method of the three-dimensional semiconductor memory device includes a substrate and a stack formed on the substrate, in which a plurality of oxide layers and nitride layers are alternately stacked. Removing a sacrificial layer to be formed through a slit penetrating the stack; In addition, the manufacturing method forms a contact layer electrically connected to the channel layer formed in the channel hole penetrating the stack by filling the gap formed by removing the sacrificial layer through the slit. The process of carrying out is included.
  • the manufacturing method of the three-dimensional semiconductor memory device does not include a step of forming a complicated contact structure in the channel hole and connecting the contact layer in the channel hole to the substrate.
  • the manufacturing method of the embodiment can easily form a contact at the bottom of the channel hole even when the number of stack layers is increased. For this reason, the manufacturing method of the embodiment can stably form the channel region.
  • the contact area between the contact layer and the channel layer can be adjusted by the thickness of the sacrificial layer. Therefore, according to the manufacturing method of the embodiment, a structure with a wide contact area can be easily formed.
  • the same slit can be used when the contact layer is formed and when the sacrificial layer in the stack is replaced with the conductor layer. For this reason, the manufacturing process of a three-dimensional semiconductor memory device can be simplified.
  • the method of manufacturing the three-dimensional semiconductor memory device may include a step of forming a channel hole that reaches the bottom surface at a height that the sacrificial layer is formed through the stack.
  • the manufacturing method of the embodiment may include a step of forming a first insulator layer, a channel layer, and a second insulator layer on the inner surface of the channel hole. As described above, in the manufacturing method according to the embodiment, the first insulator layer, the channel layer, and the second insulator layer are sequentially stacked to fill the inside of the channel hole. For this reason, the manufacturing method of the embodiment does not require complicated film formation inside the channel hole, and can stably form the channel region.
  • the method of manufacturing the three-dimensional semiconductor memory device according to the embodiment may further include a step of removing the first insulator layer formed on the inner surface of the channel hole through a slit by etching.
  • the manufacturing method of the embodiment removes the first insulator layer formed on the inner surface of the channel hole directly from the outside of the channel hole. For this reason, the manufacturing method of the embodiment can remove a desired portion of the first insulator layer without eroding other portions formed in the channel hole.
  • the step of removing the sacrificial layer may be performed by wet etching, and the step of removing the first insulator layer may be performed by dry etching. Therefore, the manufacturing method of the embodiment can manufacture a highly accurate three-dimensional semiconductor memory device by properly using the type of etching used depending on the degree of precision required.
  • the sacrificial layer may be formed of three layers of tungsten, silicon doped tungsten, and titanium nitride. For this reason, the manufacturing method of the embodiment can control the depth of the slit by using the sacrificial layer as an etching stopper layer when forming the slit. In addition, the manufacturing method of the embodiment can efficiently manufacture a three-dimensional semiconductor memory device by providing the sacrificial layer with a plurality of functions.

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Abstract

According to this method for manufacturing a three-dimensional semiconductor memory device, a sacrificial layer formed between a substrate and a stack that is formed on the substrate by layering a plurality of oxide layers and nitride layers in an alternating manner is removed through a slit penetrating the stack. Then, according to this method for manufacturing a semiconductor memory device, the void formed by removing the sacrificial layer through the slit is filled in. A contact layer that is electrically connected to a channel layer formed within a channel hole penetrating the stack is thus formed.

Description

３次元半導体記憶装置の製造方法Manufacturing method of three-dimensional semiconductor memory device
　以下の開示は、３次元半導体記憶装置の製造方法に関する。 The following disclosure relates to a method for manufacturing a three-dimensional semiconductor memory device.
　半導体記憶装置の集積度を高める手法として、メモリセルを３次元的に配置した半導体記憶装置が多数提案されている。以下、メモリセルを３次元的に配置した半導体記憶装置を、３次元半導体記憶装置と呼ぶ。 As a technique for increasing the degree of integration of semiconductor memory devices, many semiconductor memory devices in which memory cells are arranged three-dimensionally have been proposed. Hereinafter, a semiconductor memory device in which memory cells are arranged three-dimensionally is referred to as a three-dimensional semiconductor memory device.
　たとえば、メモリセルを３次元的に配置した半導体記憶装置として３Ｄ　ＮＡＮＤ型フラッシュメモリが知られている。従来知られている３次元半導体記憶装置の一つ（特許文献１乃至特許文献４）は、複数のメモリセルが直列に接続された複数のメモリストリングスを有する。メモリストリングスは、第１乃至第ｎの電極（ｎは２以上の自然数）を有する。第１乃至第ｎの電極はそれぞれ２次元的に広がる第１乃至第ｎの導電体層である。 For example, a 3D NAND flash memory is known as a semiconductor memory device in which memory cells are arranged three-dimensionally. One conventionally known three-dimensional semiconductor memory device (Patent Document 1 to Patent Document 4) has a plurality of memory strings in which a plurality of memory cells are connected in series. The memory string has first to nth electrodes (n is a natural number of 2 or more). The first to n-th electrodes are first to n-th conductor layers extending two-dimensionally, respectively.
　かかる３次元半導体記憶装置では、導電体層の数がメモリストリングスに含まれるメモリセルの数と略等しくなる。このため、３次元半導体記憶装置の集積度を上げる方法として、導電体層の数を増加させることが考えられる。たとえば、３次元半導体記憶装置の層数を６４層とした３Ｄ　ＮＡＮＤが提案されている（非特許文献１）。 In such a three-dimensional semiconductor memory device, the number of conductor layers is substantially equal to the number of memory cells included in the memory string. For this reason, as a method for increasing the degree of integration of the three-dimensional semiconductor memory device, it is conceivable to increase the number of conductor layers. For example, 3D NAND has been proposed in which the number of layers of a three-dimensional semiconductor memory device is 64 (Non-Patent Document 1).
　また、３次元半導体記憶装置のメモリストリングスと基板とを接続するコンタクトを形成するために選択的エピタキシャル成長（ＳＥＧ）を用いる手法が提案されている（特許文献２、４）。また、３次元半導体記憶装置のチャネル構造として、垂直部分と水平部分とからなるチャネル構造が提案されている（特許文献３）。 Also, a method using selective epitaxial growth (SEG) has been proposed to form a contact for connecting a memory string of a three-dimensional semiconductor memory device and a substrate (Patent Documents 2 and 4). As a channel structure of a three-dimensional semiconductor memory device, a channel structure composed of a vertical portion and a horizontal portion has been proposed (Patent Document 3).
特開平２００７－２６６１４３号公報Japanese Patent Laid-Open No. 2007-266143 米国特許出願公開第２０１７／０１８６７６７号明細書US Patent Application Publication No. 2017/0186767 米国特許第９６８５４５２号明細書US Pat. No. 6,865,452 米国特許出願公開第２０１２／００９８１３９号明細書US Patent Application Publication No. 2012/0098139
　３次元半導体記憶装置の集積度をさらに高めるためには、メモリストリングスに含まれるメモリセルの数をさらに増加させることが考えられる。すなわち、３次元半導体記憶装置が備える導電体層の数をさらに増加させることが考えられる。しかし、３次元半導体記憶装置の層数を増加させると、導電体層の最上層から基板まで延びるチャネルホールのアスペクト比が高くなる。 In order to further increase the degree of integration of the three-dimensional semiconductor memory device, it is conceivable to further increase the number of memory cells included in the memory string. That is, it is conceivable to further increase the number of conductor layers provided in the three-dimensional semiconductor memory device. However, when the number of layers of the three-dimensional semiconductor memory device is increased, the aspect ratio of the channel hole extending from the uppermost layer of the conductor layer to the substrate is increased.
　このため、３次元半導体記憶装置の層数が増加しても安定してチャネル領域を形成することができる３次元半導体記憶装置の製造方法が求められる。 Therefore, there is a need for a method for manufacturing a three-dimensional semiconductor memory device that can stably form a channel region even when the number of layers of the three-dimensional semiconductor memory device increases.
　開示する実施形態において、３次元半導体記憶装置の製造方法は、基板と、当該基板上に形成される、酸化物層と窒化物層とが交互に複数積層されるスタックと、の間に形成される犠牲層を、当該スタックを貫通するスリットを介して除去する工程を含む。当該製造方法はまた、スリットを介して犠牲層を除去することで形成される空隙を埋めることで、スタックを貫通するチャネルホール内に形成されるチャネル層に電気的に接続するコンタクト層を形成する工程を含む。 In the disclosed embodiment, a method of manufacturing a three-dimensional semiconductor memory device is formed between a substrate and a stack formed on the substrate in which a plurality of oxide layers and nitride layers are alternately stacked. Removing the sacrificial layer through a slit that penetrates the stack. The manufacturing method also forms a contact layer electrically connected to the channel layer formed in the channel hole penetrating the stack by filling the void formed by removing the sacrificial layer through the slit. Process.
　開示する実施態様によれば、３次元半導体記憶装置の層数が増加しても安定してチャネル領域を形成することができるという効果を奏する。 According to the disclosed embodiment, the channel region can be stably formed even when the number of layers of the three-dimensional semiconductor memory device is increased.
図１は、本開示の一実施形態に係る３次元半導体記憶装置の製造方法により製造される３次元半導体記憶装置の構造の一例を示す図である。FIG. 1 is a diagram illustrating an example of a structure of a three-dimensional semiconductor memory device manufactured by a method of manufacturing a three-dimensional semiconductor memory device according to an embodiment of the present disclosure. 図２は、本開示の一実施形態に係る３次元半導体記憶装置の製造方法の流れの一例を示すフローチャートである。FIG. 2 is a flowchart illustrating an example of a flow of a method for manufacturing a three-dimensional semiconductor memory device according to an embodiment of the present disclosure. 図３は、本開示の一実施形態に係る３次元半導体記憶装置の製造方法において、スタックが形成された状態を示す断面図である。FIG. 3 is a cross-sectional view illustrating a state in which a stack is formed in the method of manufacturing a three-dimensional semiconductor memory device according to an embodiment of the present disclosure. 図４は、本開示の一実施形態に係る３次元半導体記憶装置の製造方法において、スタックにチャネルホールが形成された状態を示す断面図である。FIG. 4 is a cross-sectional view illustrating a state in which channel holes are formed in the stack in the method for manufacturing a three-dimensional semiconductor memory device according to an embodiment of the present disclosure. 図５は、本開示の一実施形態に係る３次元半導体記憶装置の製造方法において、チャネルホール内にチャネル構造が形成された状態を示す断面図である。FIG. 5 is a cross-sectional view illustrating a state in which a channel structure is formed in a channel hole in the method for manufacturing a three-dimensional semiconductor memory device according to an embodiment of the present disclosure. 図６は、本開示の一実施形態に係る３次元半導体記憶装置の製造方法において、スリットが形成された状態を示す断面図である。FIG. 6 is a cross-sectional view illustrating a state in which a slit is formed in the method for manufacturing a three-dimensional semiconductor memory device according to an embodiment of the present disclosure. 図７は、本開示の一実施形態に係る３次元半導体記憶装置の製造方法において、犠牲層が除去された状態を示す断面図である。FIG. 7 is a cross-sectional view illustrating a state in which the sacrificial layer is removed in the method for manufacturing a three-dimensional semiconductor memory device according to an embodiment of the present disclosure. 図８は、本開示の一実施形態に係る３次元半導体記憶装置の製造方法において、チャネルホール内にコンタクトが開口された状態を示す断面図である。FIG. 8 is a cross-sectional view illustrating a state in which a contact is opened in a channel hole in the method for manufacturing a three-dimensional semiconductor memory device according to an embodiment of the present disclosure. 図９は、本開示の一実施形態に係る３次元半導体記憶装置の製造方法において、犠牲層が除去された部分を埋め戻した状態を示す断面図である。FIG. 9 is a cross-sectional view illustrating a state in which the portion from which the sacrificial layer has been removed is backfilled in the method for manufacturing a three-dimensional semiconductor memory device according to an embodiment of the present disclosure. 図１０は、本開示の一実施形態に係る３次元半導体記憶装置の製造方法の工程と、従来の製造方法の工程と、を比較するための図である。FIG. 10 is a diagram for comparing the steps of the manufacturing method of the three-dimensional semiconductor memory device according to the embodiment of the present disclosure and the steps of the conventional manufacturing method.
　開示する一つの実施形態において、３次元半導体記憶装置の製造方法は、基板と、当該基板上に形成される、酸化物層と窒化物層とが交互に複数積層されるスタックと、の間に形成される犠牲層を、当該スタックを貫通するスリットを介して除去する工程を含む。また、３次元半導体記憶装置の製造方法は、スリットを介して犠牲層を除去することで形成された空隙を埋めることで、スタックを貫通するチャネルホール内に形成されるチャネル層に電気的に接続するコンタクト層を形成する工程を含む。 In one disclosed embodiment, a method for manufacturing a three-dimensional semiconductor memory device includes a substrate and a stack formed on the substrate, in which a plurality of oxide layers and nitride layers are alternately stacked. Removing a sacrificial layer to be formed through a slit penetrating the stack; Also, the manufacturing method of the three-dimensional semiconductor memory device is electrically connected to the channel layer formed in the channel hole penetrating the stack by filling the void formed by removing the sacrificial layer through the slit. Forming a contact layer.
　また、開示する一つの実施形態において、３次元半導体記憶装置の製造方法は、スタックを貫通して犠牲層が形成される高さに底面が達するチャネルホールを形成する工程を含んでもよい。また、３次元半導体記憶装置の製造方法は、チャネルホールの内面上に、第１の絶縁体層と、チャネル層と、第２の絶縁体層と、を形成する工程をさらに含んでもよい。 Also, in one disclosed embodiment, the method of manufacturing a three-dimensional semiconductor memory device may include a step of forming a channel hole that reaches the bottom surface at a height where the sacrificial layer is formed through the stack. The method for manufacturing a three-dimensional semiconductor memory device may further include a step of forming a first insulator layer, a channel layer, and a second insulator layer on the inner surface of the channel hole.
　また、開示する一つの実施形態において、３次元半導体記憶装置の製造方法は、チャネルホールの内面上に形成される第１の絶縁体層を、エッチングによりスリットを介して除去する工程をさらに含んでもよい。 In one disclosed embodiment, the method for manufacturing a three-dimensional semiconductor memory device may further include a step of removing the first insulator layer formed on the inner surface of the channel hole through a slit by etching. Good.
　また、開示する一つの実施形態において、３次元半導体記憶装置の製造方法は、犠牲層を除去する工程はウェットエッチングにより実行してもよい。また、３次元半導体記憶装置の製造方法は、第１の絶縁体層を除去する工程はドライエッチングにより実行してもよい。 In one disclosed embodiment, in the method for manufacturing a three-dimensional semiconductor memory device, the step of removing the sacrificial layer may be performed by wet etching. In the method for manufacturing a three-dimensional semiconductor memory device, the step of removing the first insulator layer may be performed by dry etching.
　また、開示する一つの実施形態にかかる３次元半導体記憶装置の製造方法において、犠牲層は、タングステン、シリコンドープドタングステン、窒化チタンの３層で形成されてもよい。 In the method for manufacturing a three-dimensional semiconductor memory device according to one disclosed embodiment, the sacrificial layer may be formed of three layers of tungsten, silicon-doped tungsten, and titanium nitride.
　また、開示する一つの実施形態にかかる３次元半導体記憶装置の製造方法において、犠牲層を除去する工程は、硫酸と過酸化水素水との混合液を用いてもよい。また、硫酸と過酸化水素水とを各モル混合比＝４：１～１：５で混合して調整されるエッチング液を用いてもよい。また当該エッチング液を、８０℃以上２００℃未満の温度で用いることで犠牲層を除去してもよい。 In the method for manufacturing a three-dimensional semiconductor memory device according to one disclosed embodiment, the step of removing the sacrificial layer may use a mixed solution of sulfuric acid and hydrogen peroxide solution. Further, an etching solution that is prepared by mixing sulfuric acid and hydrogen peroxide water at a molar mixing ratio = 4: 1 to 1: 5 may be used. The sacrificial layer may be removed by using the etching solution at a temperature of 80 ° C. or higher and lower than 200 ° C.
　また、開示する一つの実施形態にかかる３次元半導体記憶装置の製造方法において、犠牲層を除去する工程は、燐酸、酢酸、硝酸の混合液を用いてもよい。また、燐酸、酢酸、硝酸をそれぞれ２～３０ｍｏｌ／Ｌ、０．２～１０ｍｏｌ／Ｌ、０．１～５ｍｏｌ／Ｌの混合比で混合して調整されるエッチング液を用いてもよい。また、当該エッチング液を、室温以上１００℃未満の温度で用いてもよい。 In the method for manufacturing a three-dimensional semiconductor memory device according to one disclosed embodiment, the step of removing the sacrificial layer may use a mixed solution of phosphoric acid, acetic acid, and nitric acid. Further, an etching solution prepared by mixing phosphoric acid, acetic acid, and nitric acid at a mixing ratio of 2 to 30 mol / L, 0.2 to 10 mol / L, and 0.1 to 5 mol / L, respectively, may be used. Further, the etching solution may be used at a temperature of room temperature or higher and lower than 100 ° C.
　以下に、開示する実施形態について、図面に基づいて詳細に説明する。各実施形態は、処理内容を矛盾させない範囲で適宜組み合わせることが可能である。 Hereinafter, disclosed embodiments will be described in detail based on the drawings. Each embodiment can be appropriately combined as long as the processing contents do not contradict each other.
（実施形態）
　図１は、本開示の一実施形態に係る３次元半導体記憶装置の製造方法により製造される３次元半導体記憶装置１の構造の一例を示す図である。以下、図１のＸ方向を横方向、Ｙ方向を縦方向とも呼ぶ。 (Embodiment)
FIG. 1 is a diagram illustrating an example of a structure of a three-dimensional semiconductor memory device 1 manufactured by a method for manufacturing a three-dimensional semiconductor memory device according to an embodiment of the present disclosure. Hereinafter, the X direction in FIG. 1 is also referred to as a horizontal direction, and the Y direction is also referred to as a vertical direction.
（３次元半導体記憶装置１の構造の一例）
　図１の例において、３次元半導体記憶装置１は、基板１０と、導電層２０と、コンタクト層３０と、スタック４０と、スリット５０と、を備える。 (Example of the structure of the three-dimensional semiconductor memory device 1)
In the example of FIG. 1, the three-dimensional semiconductor memory device 1 includes a substrate 10, a conductive layer 20, a contact layer 30, a stack 40, and a slit 50.
　基板１０はたとえば、シリコン基板、ゲルマニウム基板、シリコン－ゲルマニウム基板等である。基板１０上には周辺回路１１が形成される。 The substrate 10 is, for example, a silicon substrate, a germanium substrate, a silicon-germanium substrate, or the like. A peripheral circuit 11 is formed on the substrate 10.
　導電層２０は、基板１０と接続するように配置される。導電層２０はたとえばポリシリコンで形成する。また、図１の例では、基板１０と導電層２０とを別々に示すが、基板１０と導電層２０は同一であって図面の横方向に連続しているものとしてもよい。そして、基板１０上の異なる領域にそれぞれ周辺回路１１とスタック４０とが形成されるものとしてもよい。 The conductive layer 20 is disposed so as to be connected to the substrate 10. The conductive layer 20 is made of, for example, polysilicon. In the example of FIG. 1, the substrate 10 and the conductive layer 20 are shown separately, but the substrate 10 and the conductive layer 20 may be the same and continuous in the horizontal direction of the drawing. Then, the peripheral circuit 11 and the stack 40 may be formed in different regions on the substrate 10, respectively.
　導電層２０上にはコンタクト層３０が形成される。コンタクト層３０は後述する犠牲層３１（図３参照）を用いて形成される。コンタクト層３０はたとえばポリシリコンで形成される。コンタクト層３０は、導電層２０（基板１０）とスタック４０との間に配置され、基板１０、導電層２０およびチャネル層６２（後述）と電気的に接続する。 A contact layer 30 is formed on the conductive layer 20. The contact layer 30 is formed using a sacrificial layer 31 (see FIG. 3) described later. Contact layer 30 is formed of, for example, polysilicon. The contact layer 30 is disposed between the conductive layer 20 (substrate 10) and the stack 40, and is electrically connected to the substrate 10, the conductive layer 20, and the channel layer 62 (described later).
　スタック４０は、横方向に延在する複数の絶縁体層４１と複数の導電体層４２とを含む。絶縁体層４１と導電体層４２とは縦方向に交互に配置される。以下、複数の絶縁体層をまとめて符号４１で表示する。同様に、複数の導電体層をまとめて符号４２で表示する。絶縁体層４１はたとえば酸化シリコン（ＳｉＯ２）を含む。導電体層４２はたとえば、ポリシリコン（Ｐｏｌｙ－Ｓｉ）、金属（たとえばタングステン）、金属窒化物または金属珪化物を含む。 The stack 40 includes a plurality of insulator layers 41 and a plurality of conductor layers 42 extending in the lateral direction. The insulator layers 41 and the conductor layers 42 are alternately arranged in the vertical direction. Hereinafter, a plurality of insulator layers are collectively denoted by reference numeral 41. Similarly, a plurality of conductor layers are collectively indicated by reference numeral 42. Insulator layer 41 includes, for example, silicon oxide (SiO 2). The conductor layer 42 includes, for example, polysilicon (Poly-Si), metal (for example, tungsten), metal nitride, or metal silicide.
　スタック４０は、導電層２０（基板１０）上にＯＮＯＮ（ｏｘｉｄｅ／ｎｉｔｒｉｄｅ）膜またはＯＰＯＰ（ｏｘｉｄｅ／ｐｏｌｙｓｉｌｉｃｏｎ）膜を積層することによって形成することができる。ＯＮＯＮ膜とは、酸化物と窒化物とを交互に積層することにより形成される膜である。ＯＰＯＰ膜とは、酸化物とポリシリコンとを交互に積層することにより形成される膜である。導電層２０上にＯＮＯＮ膜を積層してスタック４０を形成する場合、所定数の酸化物層と窒化物層とが積層された後に、窒化物層をエッチング等により除去する。その後、窒化物層が除去されることで空いた空間をポリシリコン又はタングステンで埋め戻すことにより、窒化物層をポリシリコン層に置換する。これによってＯＰＯＰＯ膜又はＯＷＯＷ膜を形成する。 The stack 40 can be formed by stacking an ONON (oxide / nitride) film or an OPOP (oxide / polysilicon) film on the conductive layer 20 (substrate 10). The ONON film is a film formed by alternately stacking oxides and nitrides. The OPOP film is a film formed by alternately stacking an oxide and polysilicon. When the stack 40 is formed by stacking ONON films on the conductive layer 20, the nitride layer is removed by etching or the like after a predetermined number of oxide layers and nitride layers are stacked. Then, the nitride layer is replaced with a polysilicon layer by refilling the empty space by removing the nitride layer with polysilicon or tungsten. As a result, an OPOPO film or an OWOW film is formed.
　スタック４０には、スタック４０の上部からコンタクト層３０に達する穴部であるスリット５０が形成されている。また、スリット５０の内周面にはスリットスペーサ５１が形成されている。 In the stack 40, a slit 50 that is a hole reaching the contact layer 30 from the top of the stack 40 is formed. A slit spacer 51 is formed on the inner peripheral surface of the slit 50.
　３次元半導体記憶装置１はさらに、チャネル構造６０を備える。チャネル構造６０は、チャネルホールＣＨ内に形成された第１の絶縁体層６１と、チャネル層６２と、第２の絶縁体層６３と、を備える。チャネル構造６０はたとえば、ＳＯＮＯＳ（Ｓｉ－ＳｉＯ2－ＳｉＮ－ＳｉＯ2－Ｐｏｌｙ－Ｓｉ）構造である。 The three-dimensional semiconductor memory device 1 further includes a channel structure 60. The channel structure 60 includes a first insulator layer 61 formed in the channel hole CH, a channel layer 62, and a second insulator layer 63. The channel structure 60 is, for example, a SONOS (Si—SiO 2 —SiN—SiO 2 —Poly-Si) structure.
　第１の絶縁体層６１は、チャネルホールＣＨの内表面上に形成される。第１の絶縁体層６１はたとえば酸化シリコン膜６１ａ、窒化シリコン膜６１ｂおよび酸化シリコン膜６１ｃの積層膜であるＯＮＯ層である。 The first insulator layer 61 is formed on the inner surface of the channel hole CH. The first insulator layer 61 is, for example, an ONO layer that is a stacked film of a silicon oxide film 61a, a silicon nitride film 61b, and a silicon oxide film 61c.
　チャネル層６２は、第１の絶縁体層６１の内側に形成される。チャネル層６２はたとえばポリシリコンである。 The channel layer 62 is formed inside the first insulator layer 61. The channel layer 62 is, for example, polysilicon.
　第２の絶縁体層６３は、チャネル層６２の内側に形成される。第２の絶縁体層６３はたとえば酸化シリコンである。 The second insulator layer 63 is formed inside the channel layer 62. The second insulator layer 63 is, for example, silicon oxide.
　第１の絶縁体層６１、チャネル層６２および第２の絶縁体層６３はそれぞれチャネルホールＣＨと中心線が略同一の有底の略筒状である。また、第１の絶縁体層６１は、コンタクト層３０が形成される位置には形成されていない。このため、コンタクト層３０は、チャネルホールＣＨ内でチャネル層６２と接続する。 The first insulator layer 61, the channel layer 62, and the second insulator layer 63 each have a substantially cylindrical shape with a bottom having substantially the same center line as the channel hole CH. Further, the first insulator layer 61 is not formed at a position where the contact layer 30 is formed. For this reason, the contact layer 30 is connected to the channel layer 62 in the channel hole CH.
（３次元半導体記憶装置１の製造方法の流れの一例）
　図２は、本開示の一実施形態に係る３次元半導体記憶装置の製造方法の流れの一例を示すフローチャートである。なお、以下の説明中、導電層２０は基板１０と読み替えてもよい。 (Example of flow of manufacturing method of three-dimensional semiconductor memory device 1)
FIG. 2 is a flowchart illustrating an example of a flow of a method for manufacturing a three-dimensional semiconductor memory device according to an embodiment of the present disclosure. In the following description, the conductive layer 20 may be read as the substrate 10.
　まず、準備した導電層２０上に犠牲層３１（図３参照）を形成する（ステップＳ１１）。次に、犠牲層３１の上に、絶縁体層４１と犠牲層４２ａ（図３参照）とを交互に積層してスタック４０ａ（図３参照）を積層する（ステップＳ１２）。次に、積層したスタック４０ａおよび犠牲層３１を貫通して導電層２０に達するチャネルホールＣＨ（図４参照）を形成する（ステップＳ１３）。チャネルホールＣＨは、後述する通りチャネルホールＣＨ内に形成されるチャネル層６２がコンタクト層３０と電気的に接続することが可能な深さまで形成される。チャネルホールＣＨの底面は必ずしも導電層２０に到達していなくてもよい。次に、チャネルホールＣＨの内表面を覆うように、第１の絶縁体層６１、チャネル層６２および第２の絶縁体層６３を順次形成してチャネル構造６０（図５参照）を形成する（ステップＳ１４）。次にスタック４０ａのうち、チャネルホールＣＨが形成されていない位置にスリット５０（図６参照）を形成する（ステップＳ１５）。スリット５０は、スタック４０ａの最上部から犠牲層３１に到達する深さに形成する。そして、スリット５０を介して犠牲層３１（図７参照）を除去する（ステップＳ１６）。次に犠牲層３１が除去されることで露出した第１の絶縁体層６１（図８参照）をスリット５０から除去する（ステップＳ１７）。第１の絶縁体層６１が除去されることでチャネルホールＣＨ内からチャネル層６２が露出した状態となる。次に、犠牲層３１および第１の絶縁体層６１が除去されることで形成された空隙を導電体（図９参照）で埋め戻す。これによってチャネル層６２と導電層２０（基板１０）とを電気的に接続するコンタクト層３０が形成される（ステップＳ１８）。この後、スリット５０等から犠牲層４２ａを除去して埋め戻すことにより、犠牲層４２ａの位置に導電体層４２が形成される。これによって、図１に示す３次元半導体記憶装置１が形成される。 First, a sacrificial layer 31 (see FIG. 3) is formed on the prepared conductive layer 20 (step S11). Next, the insulator layer 41 and the sacrificial layer 42a (see FIG. 3) are alternately stacked on the sacrificial layer 31 to stack the stack 40a (see FIG. 3) (step S12). Next, a channel hole CH (see FIG. 4) reaching the conductive layer 20 through the stacked stack 40a and the sacrificial layer 31 is formed (step S13). The channel hole CH is formed to such a depth that the channel layer 62 formed in the channel hole CH can be electrically connected to the contact layer 30 as described later. The bottom surface of the channel hole CH does not necessarily reach the conductive layer 20. Next, a first insulator layer 61, a channel layer 62, and a second insulator layer 63 are sequentially formed so as to cover the inner surface of the channel hole CH to form a channel structure 60 (see FIG. 5) (see FIG. 5). Step S14). Next, a slit 50 (see FIG. 6) is formed in the stack 40a at a position where the channel hole CH is not formed (step S15). The slit 50 is formed to a depth that reaches the sacrificial layer 31 from the top of the stack 40a. Then, the sacrificial layer 31 (see FIG. 7) is removed through the slit 50 (step S16). Next, the first insulator layer 61 (see FIG. 8) exposed by removing the sacrificial layer 31 is removed from the slit 50 (step S17). By removing the first insulator layer 61, the channel layer 62 is exposed from the channel hole CH. Next, the gap formed by removing the sacrificial layer 31 and the first insulator layer 61 is backfilled with a conductor (see FIG. 9). As a result, the contact layer 30 that electrically connects the channel layer 62 and the conductive layer 20 (substrate 10) is formed (step S18). Thereafter, the sacrificial layer 42a is removed from the slits 50 and the like and is backfilled, whereby the conductor layer 42 is formed at the position of the sacrificial layer 42a. Thereby, the three-dimensional semiconductor memory device 1 shown in FIG. 1 is formed.
　なお、図２のステップＳ１５乃至Ｓ１８は、犠牲層４２ａを除去して導電体層４２を形成した後に実行してもよい。すなわち、図２のステップＳ１１乃至Ｓ１８は、ＯＮＯＮ膜により形成されるスタック４０ａに対して実行してもよく、ＯＰＯＰ膜により形成されるスタック４０に対して実行してもよい。 Note that steps S15 to S18 in FIG. 2 may be performed after the sacrifice layer 42a is removed and the conductor layer 42 is formed. That is, steps S11 to S18 in FIG. 2 may be executed for the stack 40a formed of the ONON film or may be executed for the stack 40 formed of the OPOP film.
　なお、３次元半導体記憶装置１を完成品とする工程は、スタックの導電体層４２から電極を取り出すためのコンタクトホールの形成等、図１に図示していない構造物を形成するための他の工程を含むが、ここではその詳細は省略する。 The step of completing the three-dimensional semiconductor memory device 1 includes other steps for forming a structure not shown in FIG. 1, such as formation of a contact hole for extracting an electrode from the conductor layer 42 of the stack. The process is included, but the details are omitted here.
（各工程の説明）
　次に図３乃至図９を参照しつつ、実施形態に係る３次元半導体記憶装置１の製造方法の各工程についてさらに詳細に説明する。 (Description of each process)
Next, each step of the method for manufacturing the three-dimensional semiconductor memory device 1 according to the embodiment will be described in more detail with reference to FIGS.
　図３は、本開示の一実施形態に係る３次元半導体記憶装置の製造方法において、犠牲層３１およびスタック４０ａが形成された状態を示す断面図である。図３の例では、導電体層２０の上に形成される犠牲層３１は、たとえば、タングステン（Ｗ）、シリコンドープドタングステン（Ｓｉ－ｄｏｐｅｄ　Ｗ）、窒化チタン（ＴｉＮ）の３層構造とする。また、ポリシリコンを複数層にして犠牲層３１としてもよい。犠牲層３１を形成するために用いる手法は特に限定されない。たとえば、ＰＥ－ＣＶＤ（Plasma-Enhanced　Chemical　Vapor　Deposition）、ＣＶＤ（Chemical　Vapor　Deposition）、ＡＬＤ（Atomic　Layer　Deposition）等任意の手法を用いることができる。 FIG. 3 is a cross-sectional view illustrating a state in which the sacrificial layer 31 and the stack 40a are formed in the method for manufacturing a three-dimensional semiconductor memory device according to the embodiment of the present disclosure. In the example of FIG. 3, the sacrificial layer 31 formed on the conductor layer 20 has, for example, a three-layer structure of tungsten (W), silicon-doped tungsten (Si-doped W), and titanium nitride (TiN). . Alternatively, the sacrificial layer 31 may be formed of a plurality of polysilicon layers. The method used for forming the sacrificial layer 31 is not particularly limited. For example, any method such as PE-CVD (Plasma-Enhanced Chemical Vapor Deposition), CVD (Chemical Vapor Deposition), ALD (Atomic Layer Deposition) can be used.
　犠牲層３１の厚みは４０ｎｍ（ナノメートル）以上８０ｎｍ未満とすることが好ましい。また、犠牲層３１のシリコン濃度は３％以上７％未満とすることが好ましい。たとえば、犠牲層３１は厚み６０ｎｍ、シリコン濃度５％となるよう形成する。 The thickness of the sacrificial layer 31 is preferably 40 nm (nanometers) or more and less than 80 nm. The silicon concentration of the sacrificial layer 31 is preferably 3% or more and less than 7%. For example, the sacrificial layer 31 is formed to have a thickness of 60 nm and a silicon concentration of 5%.
　犠牲層３１を形成した後、犠牲層３１の上表面を覆うように絶縁体層４１および犠牲層４２ａを交互に積層してスタック４０ａを形成する。 After the sacrificial layer 31 is formed, the insulator layer 41 and the sacrificial layer 42a are alternately stacked so as to cover the upper surface of the sacrificial layer 31 to form the stack 40a.
　図４は、本開示の一実施形態に係る３次元半導体記憶装置の製造方法において、スタック４０ａにチャネルホールＣＨが形成された状態を示す断面図である。チャネルホールＣＨの形成は、エッチング等により実行する。チャネルホールＣＨの深さは、犠牲層３１が形成される高さに底面が達していればよい。すなわち、チャネルホールＣＨは、スタック４０ａを貫通して、犠牲層３１が形成される高さに底面が達するように形成される。 FIG. 4 is a cross-sectional view illustrating a state in which the channel hole CH is formed in the stack 40a in the method for manufacturing a three-dimensional semiconductor memory device according to an embodiment of the present disclosure. The formation of the channel hole CH is performed by etching or the like. The depth of the channel hole CH only needs to reach the height at which the sacrificial layer 31 is formed. That is, the channel hole CH is formed so as to penetrate the stack 40a and reach the height at which the sacrificial layer 31 is formed.
　図５は、本開示の一実施形態に係る３次元半導体記憶装置の製造方法において、チャネルホールＣＨ内にチャネル構造６０が形成された状態を示す断面図である。チャネル構造６０は、エッチングにより形成されたチャネルホールＣＨを洗浄した後、チャネル構造６０に含まれる各層を順次堆積することにより形成する。まず、第１の絶縁体層６１を堆積する。第１の絶縁体層６１はたとえば、ＳＯＮＯＳ（Ｓｉ－ＳｉＯ2－ＳｉＮ－ＳｉＯ２－Ｐｏｌｙ－Ｓｉ）構造のＳｉＯ２－ＳｉＮ－ＳｉＯ２の部分を形成するＯＮＯ膜である。ＳｉＮ層が電荷蓄積層となり、２つのＳｉＯ２層がＳｉＮ層を挟む。第１の絶縁体層６１はたとえば、ＰＥ－ＣＶＤ、ＣＶＤ、ＡＬＤ等により形成する。 FIG. 5 is a cross-sectional view illustrating a state in which the channel structure 60 is formed in the channel hole CH in the method for manufacturing a three-dimensional semiconductor memory device according to an embodiment of the present disclosure. The channel structure 60 is formed by sequentially depositing each layer included in the channel structure 60 after cleaning the channel hole CH formed by etching. First, the first insulator layer 61 is deposited. The first insulator layer 61 is, for example, an ONO film that forms a portion of SiO2-SiN-SiO2 having a SONOS (Si-SiO2-SiN-SiO2-Poly-Si) structure. The SiN layer becomes a charge storage layer, and the two SiO2 layers sandwich the SiN layer. The first insulator layer 61 is formed by, for example, PE-CVD, CVD, ALD, or the like.
　チャネルホールＣＨの内側を覆うように堆積された第１の絶縁体層６１の内側にさらに、チャネル層６２が形成される。チャネル層６２はたとえばポリシリコンで形成する。チャネル層６２はたとえば、ＳＯＮＯＳ構造のＰｏｌｙの部分である。 A channel layer 62 is further formed inside the first insulator layer 61 deposited so as to cover the inside of the channel hole CH. The channel layer 62 is made of, for example, polysilicon. The channel layer 62 is, for example, a Poly portion having a SONOS structure.
　次に、チャネル層６２を形成した後にチャネルホールＣＨの中心部分に残る柱状の空隙に酸化物を堆積して第２の絶縁体層６３を形成する。第２の絶縁体層６３はたとえば酸化シリコンで構成する。第２の絶縁体層６３はたとえばＳＯＮＯＳ構造のＳｉの部分である。第２の絶縁体層６３が堆積されることで、図５に示す構造が完成する。なお、図５には４つのチャネルホールＣＨを示すが、チャネルホールの数や配置される位置は特に限定されない。 Next, after the channel layer 62 is formed, an oxide is deposited in the columnar voids remaining in the center portion of the channel hole CH to form the second insulator layer 63. The second insulator layer 63 is made of, for example, silicon oxide. The second insulator layer 63 is, for example, a Si portion having a SONOS structure. By depositing the second insulator layer 63, the structure shown in FIG. 5 is completed. In addition, although four channel holes CH are shown in FIG. 5, the number of channel holes and the positions where they are arranged are not particularly limited.
　図６は、本開示の一実施形態に係る３次元半導体記憶装置の製造方法において、スリット５０が形成された状態を示す断面図である。スリット５０は、たとえばエッチングにより形成する。スリット５０のエッチングの際に、スタック４０の下に形成された犠牲層３１は、下の層にエッチングの影響を与えないように機能するエッチストップ層となる。たとえば、スタック４０が酸化物と窒化物とを順次堆積したＯＮＯＮ層として形成される場合、犠牲層３１はタングステン（Ｗ）、シリコンドープドタングステン（Ｓｉ－ｄｏｐｅｄ　Ｗ）、窒化チタン（ＴｉＮ）の３層構造で形成する。犠牲層３１をこのような構造にすれば、タングステン層でエッチングを止めることができる。スリット５０の内面にはスリットスペーサ５１を成膜する。 FIG. 6 is a cross-sectional view illustrating a state in which the slit 50 is formed in the method for manufacturing a three-dimensional semiconductor memory device according to an embodiment of the present disclosure. The slit 50 is formed by etching, for example. When the slit 50 is etched, the sacrificial layer 31 formed under the stack 40 becomes an etch stop layer that functions so as not to affect the etching of the lower layer. For example, when the stack 40 is formed as an ONON layer in which an oxide and a nitride are sequentially deposited, the sacrificial layer 31 is made of tungsten (W), silicon-doped tungsten (Si-doped W), or titanium nitride (TiN). It is formed with a layer structure. If the sacrificial layer 31 has such a structure, etching can be stopped by the tungsten layer. A slit spacer 51 is formed on the inner surface of the slit 50.
　図７は、本開示の一実施形態に係る３次元半導体記憶装置の製造方法において、犠牲層３１が除去された状態を示す断面図である。犠牲層３１の除去はたとえば、ウェットエッチングまたはドライエッチングで行う。犠牲層３１の除去はウェットエッチングで行うことが好ましい。エッチング液を犠牲層３１に接触させる手法は特に限定されない。たとえば、枚葉スピン処理等を用いてエッチング液を滴下してもよい。また、スプレー等を用いてもよい。また、犠牲層３１がエッチング液に接触するようエッチング液に浸漬してもよい。好ましくは、エッチング液に浸漬することで犠牲層３１を除去する。たとえば、犠牲層３１をエッチングするための工程は、加温されたエッチング液中に対象物を浸漬する工程を含む。また、当該工程はたとえば、対象物をエッチング液中に浸漬した後所定時間経過後に取り出し、対象物に付着しているエッチング液を洗浄する工程を含む。また、当該工程はたとえば、洗浄工程後に、対象物に付着している水等を乾燥させる工程を含む。 FIG. 7 is a cross-sectional view showing a state in which the sacrificial layer 31 is removed in the method for manufacturing a three-dimensional semiconductor memory device according to an embodiment of the present disclosure. The sacrificial layer 31 is removed by, for example, wet etching or dry etching. The sacrificial layer 31 is preferably removed by wet etching. The method for bringing the etching solution into contact with the sacrificial layer 31 is not particularly limited. For example, the etchant may be dropped using single wafer spin processing or the like. Moreover, you may use a spray etc. Further, the sacrificial layer 31 may be immersed in the etching solution so as to be in contact with the etching solution. Preferably, the sacrificial layer 31 is removed by dipping in an etching solution. For example, the step for etching the sacrificial layer 31 includes a step of immersing the object in a heated etching solution. In addition, the step includes, for example, a step of immersing the object in an etching solution and taking it out after a predetermined time and washing the etching solution adhering to the object. Moreover, the said process includes the process of drying the water etc. which have adhered to the target object after a washing | cleaning process, for example.
　犠牲層３１をＷ／Ｓｉ－ｄｏｐｅｄ　Ｗ／ＴｉＮの３層で構成した場合、犠牲層３１を除去するためのエッチング液の種類は特に限定されない。エッチング液は、Ｗ／Ｓｉ　ｄｏｐｅｄ　Ｗ／ＴｉＮを溶解させることができるものであればよい。たとえば、ＳＰＭ（Sulfuric-acid　and　hydrogen-peroxide　mixture：硫酸過水）、ＡＰＭ（Ammonia-Hydrogen　Peroxide　Mixture：塩酸過水）等を用いることができる。ＡＰＭとしては、アンモニア水溶液、過酸化水素混合溶液を用いることができる。また、ＰＡＮ系と呼ばれるエッチング液（Phosphoric-Acetic-Nitric-acids：燐酸、硝酸、酢酸の混合液）を用いてもよい。 When the sacrificial layer 31 is composed of three layers of W / Si-doped W / TiN, the type of etching solution for removing the sacrificial layer 31 is not particularly limited. Any etching solution may be used as long as it can dissolve W / Si doped W / TiN. For example, SPM (Sulfuric-acid and hydrogen-peroxide mixture) can be used, and APM (Ammonia-Hydrogen Peroxide Mixture) can be used. As the APM, an aqueous ammonia solution or a hydrogen peroxide mixed solution can be used. Alternatively, an etching solution called PAN (Phosphoric-Acetic-Nitric-acids: a mixed solution of phosphoric acid, nitric acid, and acetic acid) may be used.
　本実施形態において用いるＳＰＭの混合比としては特に制限はないが、硫酸、過酸化水素の各モル混合比＝４：１～１：５が好ましく、さらに好ましくは２：１～２：５である。 The mixing ratio of SPM used in the present embodiment is not particularly limited, but the molar mixing ratio of sulfuric acid and hydrogen peroxide is preferably 4: 1 to 1: 5, more preferably 2: 1 to 2: 5. .
　また、ＳＰＭを用いる場合、エッチング液の使用温度は、８０℃以上２００℃未満が好ましく、１００℃以上１４０℃未満がさらに好ましい。１００℃以上とするのは、エッチング液の温度が１００℃以上であればエッチング速度が低くなり過ぎず、生産効率の著しい低下を招くことがないためである。また、１４０℃未満とするのは、ウェハ内のエッチング量の誤差を抑制し、エッチング条件を一定に保つためである。エッチング液の温度を高くした場合エッチング速度は上昇する。しかし、品質を安定させるためには、エッチング量の変化を小さく抑えることが望ましい。したがって、実際の使用温度は上記範囲内で、エッチング速度と品質とのバランスに基づき決定すればよい。たとえば、温度１００℃のＳＰＭにより、エッチングレート約２００（Å／ｍｉｎ）で犠牲層３１をエッチングにより除去することができる。このように調整した場合、Ｗ／Ｓｉ－ｄｏｐｅｄ　Ｗ／ＴｉＮの各層を均等にエッチングすることができる。このため、溶解不足による残差残りや、過剰な溶解による腐食等を防止することができる。 When using SPM, the use temperature of the etching solution is preferably 80 ° C. or higher and lower than 200 ° C., more preferably 100 ° C. or higher and lower than 140 ° C. The reason why the temperature is 100 ° C. or higher is that if the temperature of the etching solution is 100 ° C. or higher, the etching rate will not be too low and the production efficiency will not be significantly reduced. The reason why the temperature is lower than 140 ° C. is to suppress an error in the etching amount in the wafer and keep the etching conditions constant. When the temperature of the etchant is increased, the etching rate increases. However, in order to stabilize the quality, it is desirable to keep the change in the etching amount small. Therefore, the actual use temperature may be determined based on the balance between the etching rate and the quality within the above range. For example, the sacrificial layer 31 can be removed by etching at an etching rate of about 200 (Å / min) by SPM at a temperature of 100 ° C. When adjusted in this way, each layer of W / Si-doped W / TiN can be uniformly etched. For this reason, residual residue due to insufficient dissolution, corrosion due to excessive dissolution, and the like can be prevented.
　また、ＰＡＮ系のエッチング液を用いる場合、燐酸、酢酸、硝酸の混合水溶液の処理において、各種酸の混合比には特に制限はないが、それぞれ、２～３０ｍｏｌ／Ｌ、０．２～１０ｍｏｌ／Ｌ、０．１～５ｍｏｌ／Ｌが好ましい。さらに好ましくは、燐酸、酢酸、硝酸それぞれについて５～１５ｍｏｌ／Ｌ、０．５～４ｍｏｌ／Ｌ、０．１～２ｍｏｌ／Ｌが好ましい。 When a PAN-based etching solution is used, the mixing ratio of various acids is not particularly limited in the treatment of the mixed aqueous solution of phosphoric acid, acetic acid and nitric acid, but 2 to 30 mol / L, 0.2 to 10 mol / L, respectively. L, preferably 0.1 to 5 mol / L. More preferably, it is 5 to 15 mol / L, 0.5 to 4 mol / L, and 0.1 to 2 mol / L for phosphoric acid, acetic acid, and nitric acid, respectively.
　ＰＡＮ系のエッチング液を用いる場合、使用温度は室温以上１００℃未満が好ましく、さらに好ましくは５０℃以上９０℃未満が好ましい。エッチング液の温度が５０℃以上であればエッチング速度が低くなり過ぎず、生産効率が著しく低下することがない。一方、９０℃未満の温度であればウェハ内のエッチング量の誤差を抑制し、エッチング条件を一定に保つことができる。エッチング液の温度を高くすることでエッチング速度は上昇するが、エッチング量の変化を抑制することも考慮して適宜最適な処理温度を決定することができる。なお、犠牲層３１のエッチングに要する時間は特に限定されないが、３０分から１２０分程度である。 When a PAN-based etching solution is used, the operating temperature is preferably from room temperature to less than 100 ° C, more preferably from 50 ° C to less than 90 ° C. If the temperature of the etching solution is 50 ° C. or higher, the etching rate will not be too low, and the production efficiency will not be significantly reduced. On the other hand, if the temperature is lower than 90 ° C., an error in the etching amount in the wafer can be suppressed and the etching conditions can be kept constant. Although the etching rate is increased by increasing the temperature of the etching solution, the optimum processing temperature can be appropriately determined in consideration of suppressing the change in the etching amount. The time required for etching the sacrificial layer 31 is not particularly limited, but is about 30 to 120 minutes.
　図８は、本開示の一実施形態に係る３次元半導体記憶装置の製造方法において、チャネルホールＣＨ内にチャネル層６２を露出させる開口部が形成された状態を示す断面図である。犠牲層３１を除去した後、さらにエッチング液を変えてウェットエッチングまたはドライエッチングを行うことで、チャネルホールＣＨ内の第１の絶縁体６１の一部が除去される。第１の絶縁体６１の除去はドライエッチングで行うことが好ましい。エッチングの条件は、たとえば以下の通りである。
　エッチングガス：Ｃ４Ｆ８／ＣＨ２Ｆ２／Ａｒ
　ガス流量：１０～３０／４０～８０／２００～１０００ｓｃｃｍ
　圧力：５０～２００ｍＴｏｒｒ
　温度：１０～４０℃
　パワー：４０ＭＨｚ／１０００～２０００Ｗと２ＭＨｚ／３０００～５００００Ｗ FIG. 8 is a cross-sectional view illustrating a state in which an opening for exposing the channel layer 62 is formed in the channel hole CH in the method for manufacturing a three-dimensional semiconductor memory device according to the embodiment of the present disclosure. After removing the sacrificial layer 31, a part of the first insulator 61 in the channel hole CH is removed by further changing the etching solution and performing wet etching or dry etching. The removal of the first insulator 61 is preferably performed by dry etching. Etching conditions are as follows, for example.
Etching gas: C 4 F 8 / CH 2 F 2 / Ar
Gas flow rate: 10-30 / 40-80 / 200-1000sccm
Pressure: 50-200mTorr
Temperature: 10-40 ° C
Power: 40MHz / 1000-2000W and 2MHz / 3000-50000W
　第１の絶縁体６１のうち除去される部分は犠牲層３１に接していた部分である。すなわち、第１の絶縁体６１のうち、犠牲層３１とコンタクト層６２との間に挟まれる部分を除去する。これにより、第１の絶縁体６１よりもチャネルホールＣＨの内側に形成されたチャネル層６２が、犠牲層３１の除去によって形成された空隙内に露出される。 The portion of the first insulator 61 that is removed is the portion that was in contact with the sacrificial layer 31. That is, a portion of the first insulator 61 sandwiched between the sacrificial layer 31 and the contact layer 62 is removed. As a result, the channel layer 62 formed inside the channel hole CH with respect to the first insulator 61 is exposed in the gap formed by removing the sacrificial layer 31.
　図９は、本開示の一実施形態に係る３次元半導体記憶装置の製造方法において、犠牲層３１が除去された部分を埋め戻した状態を示す断面図である。犠牲層３１と第１の絶縁体６１のうち犠牲層３１に接する部分とが除去されて形成された空隙内に導電体たとえばポリシリコンを堆積してコンタクト層３０を形成する。コンタクト層３０はチャネルホールＣＨ内に露出されたチャネル層６２と接触する。 FIG. 9 is a cross-sectional view illustrating a state in which the portion from which the sacrificial layer 31 has been removed is backfilled in the method for manufacturing a three-dimensional semiconductor memory device according to an embodiment of the present disclosure. The contact layer 30 is formed by depositing a conductor, for example, polysilicon, in the gap formed by removing the sacrificial layer 31 and the portion of the first insulator 61 in contact with the sacrificial layer 31. The contact layer 30 is in contact with the channel layer 62 exposed in the channel hole CH.
　図１０は、本開示の一実施形態に係る３次元半導体記憶装置の製造方法の処理と、従来の製造方法の処理と、を比較するための図である。図１０の左側（Ａ）に従来の処理を示す。また、図１０の右側（Ｂ）に本実施形態の処理を示す。 FIG. 10 is a diagram for comparing the process of the manufacturing method of the three-dimensional semiconductor memory device according to the embodiment of the present disclosure with the process of the conventional manufacturing method. The conventional process is shown on the left side (A) of FIG. Also, the processing of this embodiment is shown on the right side (B) of FIG.
　図１０の右側（Ｂ）に示すように、本実施形態の製造方法は以下の工程を含んでよい。
（０）チャネルホールを開口する
（１）チャネルホールを洗浄する
（２）第１の絶縁体層６１（ＯＮＯ膜）を成膜する
（３）チャネル層６２（ポリシリコン）を成膜する
（４）第２の絶縁体層６２（酸化シリコン）を成膜する
（５）犠牲層３１を除去する
（６）犠牲層３１と接する位置の第１の絶縁体層６１（ＯＮＯ膜）を除去する
（７）コンタクト層３０となるポリシリコンを堆積する As shown on the right side (B) of FIG. 10, the manufacturing method of this embodiment may include the following steps.
(0) Opening a channel hole (1) Cleaning the channel hole (2) Forming a first insulator layer 61 (ONO film) (3) Forming a channel layer 62 (polysilicon) (4) ) Forming the second insulator layer 62 (silicon oxide) (5) Removing the sacrificial layer 31 (6) Removing the first insulator layer 61 (ONO film) at a position in contact with the sacrificial layer 31 ( 7) Deposit polysilicon to be the contact layer 30
　図１０の左側（Ａ）に示す工程は、チャネルホール内の導電部分を基板と電気的に接続するための処理として従来用いられている処理の流れの一例である。この従来例はたとえば以下の工程を含む。
（０）チャネルホールを開口する
（１）チャネルホールを洗浄する
（２）選択的エピタキシャル成長（ＳＥＧ）により、チャネルホールの底部にシリコンを成長させる（シリコンは基板とチャネルホール内の導電部分とを電気的に接続する機能を果たす）
（３）底部にシリコンが形成されたチャネルホール内部にＯＮＯ膜を成膜する
（４）ＯＮＯ膜上にスペーサとなるポリシリコンを柱状に堆積してチャネルホールを埋め戻す
（５）チャネルホール内に形成された柱状のポリシリコンの中にリソグラフィで柱状の穴（コンタクトホール）を開ける
（６）コンタクトホールをエッチングしてチャネルホール底部のシリコンまで到達する細長い穴を形成する
（７）穴の中にポリシリコンを堆積してチャネルホール内の柱状のポリシリコンと底部のシリコンとを電気的に接続する
（８）チャネルホールの上部分を酸化物で埋め戻す The process shown on the left side (A) of FIG. 10 is an example of a process flow conventionally used as a process for electrically connecting the conductive portion in the channel hole to the substrate. This conventional example includes the following steps, for example.
(0) Opening the channel hole (1) Cleaning the channel hole (2) By selective epitaxial growth (SEG), silicon is grown on the bottom of the channel hole (the silicon electrically connects the substrate and the conductive portion in the channel hole) Function to connect automatically)
(3) An ONO film is formed inside the channel hole having silicon formed at the bottom. (4) Polysilicon serving as a spacer is deposited on the ONO film in a columnar shape to fill the channel hole. (5) In the channel hole. A columnar hole (contact hole) is formed by lithography in the formed columnar polysilicon (6) The contact hole is etched to form an elongated hole reaching the silicon at the bottom of the channel hole (7) In the hole The polysilicon is deposited to electrically connect the columnar polysilicon in the channel hole and the bottom silicon. (8) The upper portion of the channel hole is backfilled with oxide.
　図１０の右側に示す工程（Ｂ）は、左側に示す従来の工程（Ａ）と比較すると、ＳＥＧによりシリコンを成長させる工程（左側の（２））と、チャネルホール内にコンタクトホールを開けるためのリソグラフィを実行する工程（左側の（５））と、がなくなっている。このため、実施形態の製造方法は、コストがかかるＳＥＧの工程をなくしてチャネル領域を安定して形成することができる。また、実施形態の製造方法は、３次元半導体記憶装置の層数が増加した場合でもＳＥＧの成長速度の低下の影響を受けることなくチャネル領域を安定して形成することができる。また、実施形態の製造方法は、チャネルホール内に複雑な成膜を行ってチャネルホール下部の基板とのコンタクトを形成する必要がない。このため、実施形態の製造方法は、チャネルホール内にチャネルコンタクトを形成するためのリソグラフィを行う必要がない。このため、実施形態の製造方法は、従来と比較して簡易な工程で安定した品質の３次元半導体記憶装置を製造することができる。 In the step (B) shown on the right side of FIG. 10, compared with the conventional step (A) shown on the left side, the step of growing silicon by SEG (left side (2)) and the step of opening a contact hole in the channel hole are performed. (5) on the left side is eliminated. For this reason, the manufacturing method according to the embodiment can stably form the channel region without the costly SEG process. Further, the manufacturing method of the embodiment can stably form the channel region without being affected by the decrease in the growth rate of the SEG even when the number of layers of the three-dimensional semiconductor memory device is increased. In addition, the manufacturing method of the embodiment does not require complicated film formation in the channel hole to form a contact with the substrate below the channel hole. For this reason, the manufacturing method of the embodiment does not require lithography for forming a channel contact in the channel hole. For this reason, the manufacturing method of the embodiment can manufacture a three-dimensional semiconductor memory device having a stable quality by a simple process compared to the conventional method.
（実施形態の効果）
　このように、実施形態にかかる３次元半導体記憶装置の製造方法は、基板と、当該基板上に形成される、酸化物層と窒化物層とが交互に複数積層されるスタックと、の間に形成される犠牲層を、当該スタックを貫通するスリットを介して除去する工程を含む。また、当該製造方法は、スリットを介して犠牲層を除去することで形成される空隙を埋めることで、スタックを貫通するチャネルホール内に形成されるチャネル層に電気的に接続するコンタクト層を形成する工程を含む。このため、実施形態にかかる３次元半導体記憶装置の製造方法は、チャネルホール内に複雑なコンタクト構造を形成してチャネルホール内のコンタクト層を基板に接続する工程を含まない。また、実施形態の製造方法は、スタックの層数が増加した場合でもチャネルホールの底部に容易にコンタクトを形成することができる。このため、実施形態の製造方法は安定してチャネル領域を形成することができる。また、実施形態の製造方法によれば、犠牲層の膜厚によってコンタクト層とチャネル層との接触面積を調整することができる。このため、実施形態の製造方法によれば、コンタクト面積の広い構造を容易に形成することができる。また、実施形態の製造方法によれば、コンタクト層形成時とスタック中の犠牲層の導電体層への置換時とに、同じスリットを利用できる。このため、３次元半導体記憶装置の製造工程を簡素化することができる。 (Effect of embodiment)
As described above, the manufacturing method of the three-dimensional semiconductor memory device according to the embodiment includes a substrate and a stack formed on the substrate, in which a plurality of oxide layers and nitride layers are alternately stacked. Removing a sacrificial layer to be formed through a slit penetrating the stack; In addition, the manufacturing method forms a contact layer electrically connected to the channel layer formed in the channel hole penetrating the stack by filling the gap formed by removing the sacrificial layer through the slit. The process of carrying out is included. For this reason, the manufacturing method of the three-dimensional semiconductor memory device according to the embodiment does not include a step of forming a complicated contact structure in the channel hole and connecting the contact layer in the channel hole to the substrate. In addition, the manufacturing method of the embodiment can easily form a contact at the bottom of the channel hole even when the number of stack layers is increased. For this reason, the manufacturing method of the embodiment can stably form the channel region. Further, according to the manufacturing method of the embodiment, the contact area between the contact layer and the channel layer can be adjusted by the thickness of the sacrificial layer. Therefore, according to the manufacturing method of the embodiment, a structure with a wide contact area can be easily formed. In addition, according to the manufacturing method of the embodiment, the same slit can be used when the contact layer is formed and when the sacrificial layer in the stack is replaced with the conductor layer. For this reason, the manufacturing process of a three-dimensional semiconductor memory device can be simplified.
　また、実施形態にかかる３次元半導体記憶装置の製造方法は、スタックを貫通して犠牲層が形成される高さに底面が達するチャネルホールを形成する工程を含んでもよい。また、実施形態の製造方法は、チャネルホールの内面上に、第１の絶縁体層と、チャネル層と、第２の絶縁体層と、を形成する工程を含んでもよい。このように、実施形態の製造方法は、チャネルホールの内部を第１の絶縁体層、チャネル層、第２の絶縁体層を順番に積層して埋め戻す。このため、実施形態の製造方法は、チャネルホール内部の複雑な成膜を必要とせず、安定してチャネル領域を形成することができる。 In addition, the method of manufacturing the three-dimensional semiconductor memory device according to the embodiment may include a step of forming a channel hole that reaches the bottom surface at a height that the sacrificial layer is formed through the stack. In addition, the manufacturing method of the embodiment may include a step of forming a first insulator layer, a channel layer, and a second insulator layer on the inner surface of the channel hole. As described above, in the manufacturing method according to the embodiment, the first insulator layer, the channel layer, and the second insulator layer are sequentially stacked to fill the inside of the channel hole. For this reason, the manufacturing method of the embodiment does not require complicated film formation inside the channel hole, and can stably form the channel region.
　また、実施形態にかかる３次元半導体記憶装置の製造方法は、チャネルホールの内面上に形成される第１の絶縁体層を、エッチングによりスリットを介して除去する工程をさらに含んでもよい。このように、実施形態の製造方法は、チャネルホールの内表面上に形成される第１の絶縁体層をチャネルホールの外側から直接除去する。このため、実施形態の製造方法は、チャネルホール内に成膜された他の部分を侵食することなく、第１の絶縁体層の所望の部分を除去することができる。 In addition, the method of manufacturing the three-dimensional semiconductor memory device according to the embodiment may further include a step of removing the first insulator layer formed on the inner surface of the channel hole through a slit by etching. As described above, the manufacturing method of the embodiment removes the first insulator layer formed on the inner surface of the channel hole directly from the outside of the channel hole. For this reason, the manufacturing method of the embodiment can remove a desired portion of the first insulator layer without eroding other portions formed in the channel hole.
　また、実施形態にかかる３次元半導体記憶装置の製造方法は、犠牲層を除去する工程はウェットエッチングにより実行し、第１の絶縁体層を除去する工程はドライエッチングにより実行してもよい。このため、実施形態の製造方法は、精密度が要求される度合いに応じて使用するエッチングの種類を使い分けて、精度の高い３次元半導体記憶装置を製造することができる。 In the method of manufacturing the three-dimensional semiconductor memory device according to the embodiment, the step of removing the sacrificial layer may be performed by wet etching, and the step of removing the first insulator layer may be performed by dry etching. Therefore, the manufacturing method of the embodiment can manufacture a highly accurate three-dimensional semiconductor memory device by properly using the type of etching used depending on the degree of precision required.
　また、実施形態にかかる３次元半導体記憶装置の製造方法において、犠牲層は、タングステン、シリコンドープドタングステン、窒化チタンの３層で形成されてもよい。このため、実施形態の製造方法は、犠牲層をスリット形成時のエッチングストッパ層として利用してスリットの深さを制御することができる。また、実施形態の製造方法は、犠牲層に複数の機能を持たせることで効率的に３次元半導体記憶装置を製造することができる。 In the method for manufacturing a three-dimensional semiconductor memory device according to the embodiment, the sacrificial layer may be formed of three layers of tungsten, silicon doped tungsten, and titanium nitride. For this reason, the manufacturing method of the embodiment can control the depth of the slit by using the sacrificial layer as an etching stopper layer when forming the slit. In addition, the manufacturing method of the embodiment can efficiently manufacture a three-dimensional semiconductor memory device by providing the sacrificial layer with a plurality of functions.
１　３次元半導体記憶装置
１０　基板
３０　コンタクト層
３１　犠牲層
４０，４０ａ　スタック
４１　絶縁体層
４２　導電体層
５０　スリット
６０　チャネル構造
６１　第１の絶縁体層
６２　チャネル層
６３　第２の絶縁体層
ＣＨ　チャネルホール 1 three-dimensional semiconductor memory device 10 substrate 30 contact layer 31 sacrificial layer 40, 40a stack 41 insulator layer 42 conductor layer 50 slit 60 channel structure 61 first insulator layer 62 channel layer 63 second insulator layer CH channel hole

Claims (7)

  1. 　基板と、当該基板上に形成される、酸化物層と窒化物層とが交互に複数積層されるスタックと、の間に形成される犠牲層を、当該スタックを貫通するスリットを介して除去する工程と、
    　前記スリットを介して前記犠牲層を除去することで形成される空隙を埋めることで、前記スタックを貫通するチャネルホール内に形成されるチャネル層に電気的に接続するコンタクト層を形成する工程と、
    　を含む３次元半導体記憶装置の製造方法。     A sacrificial layer formed between the substrate and a stack formed by alternately stacking a plurality of oxide layers and nitride layers formed on the substrate is removed through a slit penetrating the stack. Process,
    Forming a contact layer electrically connected to a channel layer formed in a channel hole penetrating the stack by filling a void formed by removing the sacrificial layer through the slit;
    A method for manufacturing a three-dimensional semiconductor memory device.
  2. 　前記スタックを貫通して前記犠牲層が形成される高さに底面が達するチャネルホールを形成する工程と、
    　前記チャネルホールの内面上に、第１の絶縁体層と、チャネル層と、第２の絶縁体層と、を形成する工程と、
    　をさらに備える請求項１に記載の３次元半導体記憶装置の製造方法。     Forming a channel hole through which the bottom surface reaches the height at which the sacrificial layer is formed through the stack;
    Forming a first insulator layer, a channel layer, and a second insulator layer on the inner surface of the channel hole;
    The method of manufacturing a three-dimensional semiconductor memory device according to claim 1, further comprising:
  3. 　前記チャネルホールの内面上に形成される第１の絶縁体層を、エッチングにより前記スリットを介して除去する工程をさらに含むことを特徴とする請求項２に記載の３次元半導体記憶装置の製造方法。 3. The method for manufacturing a three-dimensional semiconductor memory device according to claim 2, further comprising a step of removing the first insulator layer formed on the inner surface of the channel hole through the slit by etching. .
  4. 　前記犠牲層を除去する工程はウェットエッチングにより実行し、
    　前記第１の絶縁体層を除去する工程はドライエッチングにより実行する、
    　ことを特徴とする請求項３に記載の３次元半導体記憶装置の製造方法。     The step of removing the sacrificial layer is performed by wet etching,
    The step of removing the first insulator layer is performed by dry etching;
    The method of manufacturing a three-dimensional semiconductor memory device according to claim 3.
  5. 　前記犠牲層は、タングステン、シリコンドープドタングステン、窒化チタンの３層で形成される、請求項１～４のいずれか１項に記載の３次元半導体記憶装置の製造方法。 5. The method of manufacturing a three-dimensional semiconductor memory device according to claim 1, wherein the sacrificial layer is formed of three layers of tungsten, silicon-doped tungsten, and titanium nitride.
  6. 　前記犠牲層を除去する工程は、硫酸と過酸化水素水とを各モル混合比＝４：１～１：５で混合して調整されるエッチング液を、８０℃以上２００℃未満の温度で用いることで前記犠牲層を除去する請求項１～５のいずれか１項に記載の３次元半導体記憶装置の製造方法。 In the step of removing the sacrificial layer, an etching solution prepared by mixing sulfuric acid and hydrogen peroxide solution at a molar mixing ratio = 4: 1 to 1: 5 is used at a temperature of 80 ° C. or higher and lower than 200 ° C. 6. The method for manufacturing a three-dimensional semiconductor memory device according to claim 1, wherein the sacrificial layer is removed.
  7. 　前記犠牲層を除去する工程は、燐酸、酢酸、硝酸をそれぞれ２～３０ｍｏｌ／Ｌ、０．２～１０ｍｏｌ／Ｌ、０．１～５ｍｏｌ／Ｌの混合比で混合して調整されるエッチング液を、室温以上１００℃未満の温度で用いることで前記犠牲層を除去する請求項１～５のいずれか１項に記載の３次元半導体記憶装置の製造方法。 The step of removing the sacrificial layer includes an etching solution prepared by mixing phosphoric acid, acetic acid, and nitric acid at a mixing ratio of 2 to 30 mol / L, 0.2 to 10 mol / L, and 0.1 to 5 mol / L, respectively. The method for manufacturing a three-dimensional semiconductor memory device according to any one of claims 1 to 5, wherein the sacrificial layer is removed by using at a temperature of room temperature or higher and lower than 100 ° C.
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