WO2019159472A1 - Memory management device, memory management method, and information processing device - Google Patents

Abstract

Provided is a memory management device which performs an address conversion by a page unit. The memory management device is provided with: a region information holding unit which holds, in an entry for each region, a basic virtual address for each region defined on a virtual address space, an address of a page table for each region put on a physical memory, and information on the page size defined in the region and the region size; and a search unit which searches, on the basis of the page table address corresponding to the region including the virtual address, for information on the physical address corresponding to the virtual address from a corresponding page table on the physical memory.

Description

Memory management device, memory management method, and information processing device

The technology disclosed in this specification relates to a memory management device, a memory management method, and an information processing device that perform address conversion in units of pages.

A memory management unit (MMU) is hardware that performs address conversion from a virtual address to a physical address using a page table. Normally, the MMU performs such an address conversion on the entire virtual address space, thereby realizing a virtual address space for each process and providing a virtual memory larger than the real memory capacity.

However, when a mechanism that performs address translation in units of pages over the entire virtual address space is applied to devices that have only a small amount of memory, such as embedded devices, the area actually used in the virtual address space is small. In the page table, there are many places that are not used at all, resulting in unnecessary memory consumption.

Also, in the existing MMU, the page size as a unit of address translation is fixed (typically, one page is about 4 KB). In order to suppress fragmentation that occurs in small-capacity heap memory management, it is desirable that the page size be small. On the other hand, if the page size is small, a page table necessary for performing address conversion in the same address range becomes large, and wasteful memory consumption occurs here.

For example, a sequencer address management that performs different address conversion using a plurality of page tables has been proposed (see, for example, Patent Document 1). According to this sequencer address management, each thread to be executed has its own page table. Therefore, when a small memory system has a large number of threads, the amount of necessary page table becomes large. There is a concern that

Also, a memory management method has been proposed that realizes a variable page size by treating a memory that is an integral multiple of the basic page size as one page (see, for example, Patent Document 2). According to this memory management method, since a plurality of page table entries are necessary even on the page table for address conversion, there is a concern that the page table size for page conversion becomes large.

Special table 2008-536224 JP-A-9-319658

An object of the technology disclosed in the present specification is to provide a memory management device, a memory management method, and an information processing device that efficiently perform address conversion in units of pages even on a small-capacity memory system.

The technology disclosed in the present specification has been made in consideration of the above problems, and the first aspect thereof is a memory management device that performs address conversion from a virtual address to a physical address in units of pages,
Region address translation information defined in the virtual address space, a region information holding unit for holding a unique page size of the region,
A search unit that searches for information of a physical address corresponding to the virtual address using the address conversion information of the region including the virtual address;
Is a memory management device.

The region information holding unit includes a base virtual address of each region defined on the virtual address space, an address of a page table for each region placed on the physical memory, a page size defined in the region, and a region size Is stored in the entry for each region. Therefore, the search unit includes a page table address of a region including the virtual address from the base virtual address in the region information holding unit and an entry including the virtual address in an address range obtained by adding the page size of the region to the base virtual address. And the physical address information can be acquired from the page specified by dividing the difference between the virtual address and the base virtual address by the page size on the page table specified by the page table address.

In addition, the memory management device according to the first aspect includes an address conversion that holds information indicating a correspondence relationship between a base virtual address and a base physical address in page units and information on a page size defined in a region including the virtual address. A buffer and an address conversion unit that converts a base physical address and a virtual address acquired from an entry that hits a virtual address in the address conversion buffer into a physical address corresponding to the virtual address are further provided. The address conversion unit can search the address conversion buffer for a base virtual address and an entry including the virtual address in the address range obtained by adding the region page size to the base virtual address.

Also, the memory management device according to the first aspect assigns different regions on the virtual address space to a plurality of memory areas storing data having different uses. Specifically, the memory management device allocates different regions each having a unique page size in the virtual address space to the text area, the heap area, and the stack area.

The second aspect of the technology disclosed in the present specification is a memory management method for performing address conversion from a virtual address to a physical address in units of pages,
Using the address translation information of the region defined in the virtual address space and the address translation information held in the region information holding unit holding the unique page size of the region, information on the physical address corresponding to the virtual address is obtained. A search step for searching;
It is obtained from the entry that hits the virtual address in the address translation buffer that holds the information indicating the correspondence between the base virtual address and the base physical address in page units and the page size information defined in the region that includes the virtual address. An address conversion step of converting a base physical address and a virtual address into a physical address corresponding to the virtual address;
Is a memory management method.

In addition, the third aspect of the technology disclosed in this specification is:
Physical memory,
A region information holding unit that holds the address translation information of the region defined in the virtual address space and a unique page size of the region, and a physical address corresponding to the virtual address using the address translation information of the region including the virtual address. A memory management unit having a search unit for searching for information, and performing address conversion from a virtual address to a physical address in units of pages;
Is an information processing apparatus.

According to the technology disclosed in this specification, by defining a plurality of regions that are subject to address translation and defining a page size for each region, address translation can be efficiently performed on a page basis even on a small-capacity memory system. A memory management device, a memory management method, and an information processing device can be provided.

In addition, the effect described in this specification is an illustration to the last, and the effect of this invention is not limited to this. In addition to the above effects, the present invention may have additional effects.

Other objects, features, and advantages of the technology disclosed in the present specification will become apparent from a more detailed description based on embodiments to be described later and the accompanying drawings.

FIG. 1 is a diagram schematically illustrating a configuration example of a system 1 including an embedded device to which the technology disclosed in this specification can be applied. FIG. 2 is a diagram illustrating a hardware configuration example of the sensing device 100. FIG. 3 is a diagram illustrating a configuration example of the MMU 102 together with an address translation mechanism. FIG. 4 is a flowchart showing a processing procedure for initializing the MMU 102. FIG. 5 is a flowchart showing a processing procedure for converting a virtual address to a physical address in the MMU 102 after initialization. FIG. 6 is a flowchart showing a processing procedure for the address translation mechanism 303 to translate a virtual address into a physical address. FIG. 7 is a flowchart showing a processing procedure for the page walk mechanism 304 to refer to the page table on the physical memory 305. FIG. 8 is a diagram illustrating a specific example in which address translation is performed using the MMU 102. FIG. 9 is a diagram illustrating a specific example in which address translation is performed using the MMU 102. FIG. 10 is a diagram illustrating a specific example in which address translation is performed using the MMU 102. FIG. 11 is a diagram illustrating a specific example in which address translation is performed using the MMU 102. FIG. 12 is a diagram showing a configuration example of a region in the virtual address space realized by using the MMU 102. FIG. 13 is a diagram illustrating a configuration example of software that operates on hardware that implements the embedded device illustrated in FIGS. 1 and 2. FIG. 14 is a diagram for explaining a memory management method using an operating system. FIG. 15 is a diagram showing the relationship between the virtual address space provided by the virtual memory manager and each task executed on the virtual address space. FIG. 16 is a diagram for explaining a mechanism for using Region # 0 as a text area among the regions provided by the virtual memory manager. FIG. 17 is a flowchart showing a processing procedure for mapping a file in the flash memory 104 to a memory space. FIG. 18 is a flowchart showing a processing procedure for releasing a file mapped to the memory space. FIG. 19 is a diagram for explaining a mechanism for using Region # 1 and Region # 2 as heap areas. FIG. 20 is a flowchart showing a processing procedure for securing memory from the heap area. FIG. 21 is a flowchart showing a processing procedure for releasing the memory secured in the heap area. FIG. 22 is a flowchart showing a process of allocating a memory from Region # 1 in which the page size is defined as 4 KB. FIG. 23 is a flowchart showing a process of releasing the memory secured in Region # 1 where the page size is defined as 4 KB. FIG. 24 is a flowchart showing a process of allocating memory from Region # 2 in which the page size is defined as 1 KB. FIG. 25 is a flowchart showing a process of releasing the memory secured in Region # 2 where the page size is defined as 1 KB. FIG. 26 is a flowchart showing a processing procedure for acquiring an empty memory block from the memory block manager. FIG. 27 is a flowchart showing a processing procedure for returning a memory block to the memory block manager. FIG. 28 is a diagram for explaining a mechanism for using Region # 3 as a stack area among the regions provided by the virtual memory manager. FIG. 29 is a diagram showing a processing procedure for dynamically allocating the stack area. FIG. 30 is a flowchart showing a processing procedure for releasing the stack at the end of the task.

Hereinafter, embodiments of the technology disclosed in this specification will be described in detail with reference to the drawings.

In this specification, when the memory management method for performing address translation for the entire virtual address space is applied to a device having only a small amount of memory, the area actually used in the virtual address space is small, which is wasteful. A new memory management method is proposed in view of the fact that unnecessary memory consumption occurs and that the page table becomes large and wasteful memory consumption occurs when the page size is fixed to prevent fragmentation.

According to the technology disclosed in this specification, a plurality of regions (regions) that are subject to address translation are defined in the virtual address space, and address translation is performed in units of pages in each region. A unique page size can be defined, and therefore, address translation using the MMU can be efficiently realized even in a small-capacity memory system. Further, according to the technique disclosed in this specification, each page has a fixed page size, and one page uses one entry regardless of the page size on the page table that performs address conversion of each region. Address translation can be performed efficiently.

Generally, when a program operates, a plurality of types of areas such as a text area, a heap area, and a stack area are used, but these areas have different characteristics.

The text area includes instruction codes and read-only data that is referenced during program execution. In the case of an embedded device, data stored in a nonvolatile memory such as a flash memory is often used for this. Considering that writing to the flash memory is performed in units of a specific block size (typically about 64 KB), it is efficient to treat the text area in units of such block sizes.

The heap area is an area that is dynamically secured and released during execution in order to place data that needs to be retained during program execution. The unit in which the memory is secured from the heap area largely depends on the processing contents and the way of writing the program, and may be several bytes or may exceed several hundred KB. If securing and releasing of memories of different sizes are repeated, memory fragmentation may occur, and it may not be possible to secure a continuous memory that satisfies the request even though there is a free space as a whole. In order to avoid the situation of memory fragmentation, a method of classifying the heap area into several areas and using them properly depending on the size of the memory to be secured can be considered.

The stack area is an area where the amount of usage increases dynamically due to the progress of function calls during program execution, etc., but the amount of usage varies greatly depending on how the program is written and the contents of processing. It is difficult to leave. Therefore, it is possible to dynamically allocate memory for each page size depending on the usage status, but if the average stack consumption of tasks running on the system is small, the page that is the allocation unit accordingly It is desirable that the size is small.

Thus, even for a plurality of memory areas having different characteristics, a region having an appropriate page size can be allocated to each of the memory areas by the MMU to which the technology disclosed in this specification is applied. Efficient memory management that matches the characteristics of

FIG. 1 schematically shows a configuration example of a system 1 including an embedded device to which the technology disclosed in this specification can be applied. The illustrated system 1 includes a sensing device 100 corresponding to an embedded device, a base station 200, and a server 202 installed on a cloud 201. The sensing device 100 can wirelessly connect to the base station 200 and access the server 202 via the cloud 201.

The sensing device 100 includes a CPU (Central Processing Unit) 101, an MMU 102, an SRAM (Static RAM (Random Access Memory)) 103, a memory such as a flash memory 104, a sensor 105, and a communication module 106, and is a device driven by a battery 107. is there.

The sensing device 100 is used by being worn by a wearer, for example. The CPU 101 analyzes the wearer's behavior (stopped, walking, running, etc.) based on the detection signal of the sensor 105. Then, the analysis result is wirelessly transmitted from the communication module 106 to the base station 200 and recorded in the server 202 via the cloud 201. The server 202 uses the data received from the sensing device 100 for monitoring the wearer.

FIG. 2 shows a hardware configuration example of the sensing device 100 as an example of an embedded device.

The CPU 101 is connected to the system bus 110 via the MMU 102. On the system bus 110, devices such as an SRAM 103, a flash memory 104, a sensor 105, and a communication module 106 are connected.

The flash memory 104 stores, for example, data such as an application that estimates the wearer's behavior based on a signal from the sensor 105, a library used when executing the application, and a behavior estimation dictionary for estimating the wearer's behavior. Storing. The sensor 105 includes one or more sensor devices such as an acceleration sensor, an atmospheric pressure sensor, a gyro, a GPS (Global Positioning System), a TOF (Time Of Flight) image distance sensor, and a LIDAR (Light Detection and Ranging) sensor. .

The physical address space in which these devices connected to the system bus 110 are arranged is a target of address conversion by the MMU 102. In this physical address space, the SRAM 103 is arranged, and the flash memory 104 is arranged so that the contents can be directly seen from the CPU 101 or the MMU 102, or the I / O of various sensor devices included in the communication module 106 or the sensor 105. O port is arranged.

FIG. 3 shows a configuration example of the MMU 102 according to the present embodiment. In the figure, the flow of conversion from a virtual address (Virtual Address: VA) to a physical address (Physical Address: PA) by the MMU 102 is also shown.

The illustrated MMU 102 includes two blocks, a translation lookaside buffer (TLB) 301 and a region descriptor 302.

The TLB 301 is used to hold information for converting a virtual address to a physical address in units of pages, like a general MMU. The number of entries in the TLB 301 is arbitrary. For example, the MMU designer determines the number of TLB entries based on the tradeoff between the efficiency of address translation and the circuit scale for realizing the MMU.

Each entry T ₀ to T _{n of the} TLB 301 has a base virtual address TB ₀ to TB _n , a base physical address TT ₀ to TT _n , a page size TP ₀ to TP _n , and entry valid flags TV ₀ to TV _n , respectively. In the base virtual addresses TB ₀ to TB _n , virtual addresses of pages whose addresses are converted by the respective TLB entries T ₀ to T _n are stored. In the base physical addresses TT ₀ to TT _n , converted physical addresses corresponding to the base virtual addresses TB ₀ to TB _n of the respective TLB entries T ₀ to T _n are stored. The page sizes TP ₀ to TP _n store the size of the page indicated by each TLB entry T ₀ to T _n (that is, the size of the page defined in the region to which the virtual addresses TB ₀ to TB _n belong). . The entry valid flags TV ₀ to TV _n store flags indicating the validity (valid or invalid) of the respective TLB entries T ₀ to T _n themselves.

The region descriptor 302 is used to set a region (region) that is a target of address conversion by the MMU 102. Therefore, the region descriptor 302 has as many entries as the number of regions that the MMU 102 can provide. In the example shown in FIG. 3, the region descriptor 302 has four entries R ₀ to R ₃ .

Each entry R ₀ to R ₃ of the region descriptor 302 has a base virtual address RB ₀ to RB ₃ , a page table address RT ₀ to RT ₃ , a page size RP ₀ to RP ₃ , and a region size RS ₀ to RS ₃ . The base virtual addresses RB ₀ to RB ₃ store the head addresses in the virtual address space where the regions R ₀ to R ₃ are arranged. The page table addresses RT ₀ to RT ₃ store the physical addresses where the page tables P ₀ to P ₃ used for the conversion from the virtual address to the physical address are stored for each region R ₀ to R _3. . The page sizes RP ₀ to RP ₃ store the size of the page size of each page constituting each region R ₀ to R ₃ . The region sizes RS ₀ to RS ₃ store the sizes of the regions R ₀ to R ₃ themselves.

On the physical memory 305, there are as many page tables P ₀ to P _{3 as} there are regions. The page tables P ₀ to P ₃ for each region have the same number of entries as the number of pages in the corresponding region, and each entry stores the physical address of the page conversion destination in the corresponding region. A value obtained by dividing the region size by the page size of the region is the number of pages in the region (in the case of region R _x , RS _x / RP _x is the number of pages in the region).

The address translation from the virtual address to the physical address in the illustrated MMU 102 is performed by comparing the virtual address with the base address of each entry of the TLB 301 and the region descriptor 302, and whether or not a matching entry exists. A flow for converting a virtual address to a physical address will be described.

The CPU 101 accesses the memory space using a virtual address. The MMU 102 compares the base address portion of the virtual address requested to be accessed with the base virtual addresses TB ₀ to TB _n of the entries T ₀ to T _n of the TLB 301. Here, when a corresponding entry is found, that is, when a TLB hit occurs, the address translation mechanism 303 translates the base virtual address into a base physical address using the entry. Then, the physical address can be obtained by combining the base physical address and the offset address of the virtual address requested to be accessed.

On the other hand, if an entry corresponding to the base address portion of the virtual address requested to be accessed is not found in the TLB 301, that is, if a TLB miss is found, the MMU 102 determines the base address portion of the virtual address requested to be accessed and the region descriptor. compared to the base virtual address RB ₀ ~ RB ₃ in each entry R ₀ ~ R ₃ 302, referring to the page table address RT _X in the corresponding entry. When the page walk mechanism 304 finds a page table entry corresponding to the requested virtual address by referring to the corresponding page table P _X on the physical memory 305 using the page table address RT _X , it is obtained. An arbitrary entry in the TLB 301 is updated based on the content. In this way, a new entry for mapping the virtual address and physical address requested for access is stored in the TLB 301.

4 to 7 show processing procedures related to address conversion in the form of flowcharts.

FIG. 4 shows a processing procedure for initializing the MMU 102 in the form of a flowchart. The initialization of the MMU 102 is basically performed when the operating system (OS) is started.

First, all entries in the TLB 301 are set to be invalid (step S401). Specifically, False is assigned to the entry valid flags TV ₀ to TV _n of all entries.

For each entry R ₀ to R ₃ in the region descriptor 302, base virtual addresses RB ₀ to RB ₃ , page table addresses RT ₀ to RT ₃ , page sizes RP ₀ to RP ₃ for defining each region. Region sizes RS ₀ to RS ₃ are set (step S402).

Although detailed explanation is omitted, when the OS is started, the page tables P ₀ to P ₃ for each region on the physical memory 305 are also initialized.

FIG. 5 shows a processing procedure for converting a virtual address to a physical address in the MMU 102 after initialization in the form of a flowchart.

First, the requested virtual address is compared with each entry T ₀ to T _{n in the} TLB 301 (step S501), and it is checked whether any entry matches (step S502). Here, the x-th entry T _x, the base virtual address TB _x, if it contains the virtual address VA is in the range obtained by adding the page size TP _x to the base virtual address TB _x (i.e., TB _x ≦ VA <TB _x + TP _x and TV _x = True), the virtual address VA matches the entry T _x .

If an entry that matches the requested virtual address is found in the TLB 301 (Yes in step S502), the address conversion mechanism 303 performs a conversion process from the virtual address to the physical address (step S503). Refer to FIG. 6 for details of the conversion process from the virtual address to the physical address by the address translation mechanism 303.

On the other hand, if an entry that matches the requested virtual address is not found in the TLB 301 (No in step S502), that is, if a TLB miss occurs, the requested virtual address and each entry in the region descriptor 302 are subsequently continued. R ₀ to R _n are compared (step S504), and it is checked whether any entry matches (step S505). Here, the x-th entry R _x, base and virtual address RB _x, if it contains the virtual address VA is in the range obtained by adding the page size RS _x to the base virtual address RB _x (i.e., RB _x ≦ VA <RB _x + RS _x ), the virtual address VA matches the entry R _x .

If an entry matching the requested virtual address is found in the region descriptor 302 (Yes in step S505), a page table reference process on the physical memory 305 by the page walk mechanism 304 is executed (step S506). ), A new entry is created in the TLB 301 for mapping the requested virtual address and physical address. Thereafter, the process returns to step S501, and the conversion process from the virtual address to the physical address by the address conversion mechanism 303 is executed again. Refer to FIG. 7 for details of the page table reference processing on the physical memory 305 by the page walk mechanism 304.

If no entry matching the requested virtual address is found in the region descriptor 302 (No in step S505), a bus fault error occurs and the physical address is changed from the virtual address to the physical address. Cancel the conversion process.

FIG. 6 shows a processing procedure for converting the virtual address to the physical address by the address translation mechanism 303 executed in step S506 in the flowchart shown in FIG. 5 in the form of a flowchart.

When the address translation mechanism 303 obtains the base physical address TT _x from the entry T _x that matches the requested virtual address in the TLB 301 (step S601), the base physical address and the offset address of the requested virtual address are accessed. Are combined to calculate the physical address (step S602).

In step S602, specifically, the physical address TT _x acquired from the entry T _x in TLB301, by adding the difference between the requested virtual address VA and the base virtual address TB _x, be determined physical address PA (Ie, PA ← TT _x + (VA−TB _x )).

In FIG. 7, the page walk mechanism 304 executed in step S506 in the flowchart shown in FIG. 5 refers to the page table on the physical memory 305, and a new entry for mapping the virtual address and the physical address is displayed in the TLB 301. The processing procedure for creating the data is shown in the form of a flowchart.

The page walk mechanism 304 first determines the page number of the corresponding page table in the physical memory 305 based on the information stored in the corresponding entry _Rx of the region descriptor 302 and the requested virtual address VA. Is to be acquired (step S701). Specifically, a value n obtained by dividing the difference between the virtual address VA and the base virtual address RB _x by the page size RP _x of the region and rounding it to an integer becomes an entry in the page table (that is, n ← int (( VA-RB _x ) / RP _x )).

Next, the page walk mechanism 304 requests the value PP of the nth entry from the page table located at the physical address of the page table address RT _x stored in the corresponding entry R _x of the region descriptor 302, that is, requested. The base physical address corresponding to the virtual address VA is acquired (that is, PP ← P _xn ) (step S702).

Next, the page walk mechanism 304 checks whether there is an invalid entry TV _{y in} the TLB 301 (ie, TV _y = False) (step S703).

If there is no invalid entry TV _{y in} the TLB 301 (No in step S703), the page walk mechanism 304 selects an arbitrary y-th entry in the TLB 301 and sets it as an invalid entry ( That is, TV _y ← False) (step S704).

Then, the page walk mechanism 304 validates the invalid entry y found in the TLB 301 (or the invalid entry y) and sets new address translation information for the entry (step S705). Specifically, the entry valid flag TV _y is validated, and a new base virtual address TB _y , base physical address TT _y , and page size TP _y are set (ie, TB _y ← RB _x + (RP _x × n)). TT _y ← PP, TP _y ← RP _x , TV _y ← True).

In this way, a new entry mapping the virtual address and physical address requested to be accessed is stored in the TLB 301.

8 to 11 show specific examples of performing address conversion using the MMU 102. FIG. Here, as an example, four regions as shown in Table 1 below are defined in the virtual address space (however, 0x indicates that the value is a hexadecimal number).

Each region has a page table (P ₀ to P ₃ ) at a physical address (RT ₀ to RT ₃ ) set as the page table address. Each page table (P ₀ to P ₃ ) stores a physical address (P ₀₀ to P _3n ) after the virtual address is converted in page units. In the example shown in Table 1 above, in the case of region R ₀ , the region size is RS ₀ = 16 MB and the page size is RP ₀ = 64 KB, so RS ₀ / RP ₀ = 256 is the number of entries in this page table.

Therefore, the entry R ₀ of the region descriptor 302 stores the base virtual address RB ₀ = 0x10000000, the page table address RT ₀ = 0x00010000, the page size RP ₀ = 64 KB, and the region size RS ₀ = 16 MB. In addition, the base virtual address RB ₁ = 0x20000000, page table address RT ₁ = 0x0020000, page size RP ₀ = 4 KB, and region size RS ₁ = 1 MB are stored in the entry R ₁ . In addition, the base virtual address RB ₂ = 0x30000000, page table address RT ₂ = 0x0030000, page size RP ₂ = 1 KB, and region size RS ₂ = 256 KB are stored in the entry R ₂ . In addition, the base virtual address RB ₂ = 0x40000000, page table address RT ₃ = 0x20040000, page size RP ₃ = 1 KB, and region size RS ₃ = 256 KB are stored in the entry R ₃ .

Further, it is assumed that the MMU 102 illustrated in FIG. 8 is in a state immediately after being initialized according to the processing procedure illustrated in FIG. Therefore, False indicating that the entry is invalid is substituted for the entry valid flags TV ₀ to TV _n of all entries 0 to n in the TLB 301.

FIG. 9 shows a specific example in which address conversion is performed when VA = 0x1002002010 is given as a virtual address before conversion to the MMU 102 immediately after initialization (see FIG. 8). The conversion from the virtual address to the physical address is executed according to the processing procedure shown in FIG.

In the initial state, since all entries of the TLB 301 are invalid (TV ₀ to TV _n = False), there is no entry that matches the requested virtual address. That is, since a TLB miss occurs, it is checked whether there is a region descriptor 302 that matches the requested virtual address. Here, the entry R ₀ of the region descriptor 302 satisfies RB ₀ ≦ VA <RB ₀ + RS ₀ (0x10000000 ≦ 0x10020010 <0x10000000 + 0x01000000), so this virtual address matches the entry R ₀ .

Next, the page walk mechanism 304 executes the page walk according to the processing procedure shown in FIG.

The page walk mechanism 304 first performs page table reference processing on the physical memory 305 based on information acquired from the entry R ₀ of the region descriptor 302, and maps the virtual address and physical address requested to be accessed. A new entry is created in the TLB 301. Specifically, the difference between the virtual address 0x10020010 and the base virtual address RB ₀ (= 0x10000000) is divided by the page size RP ₀ = 64 KB (0x00010000) of the region, and rounded down to an integer n = 2 (ie, n ← int ((VA-RB _x ) / RP _x )) is the page to be acquired from the corresponding page table on the physical memory 305.

Therefore, the page walk mechanism 304 sets the value P ₀₂ (= 0x0800000) of the second entry of the corresponding page table address RT ₀ on the physical memory 305 as the base physical address TT ₀ corresponding to the requested virtual address VA. get.

Then, the page walk mechanism 304 selects the entry T ₀ from the invalid entries in the TLB 301 and sets a new base virtual address TB ₀ , base physical address TT ₀ , and page size TP ₀ as follows. Thus, the entry T ₀ is validated. FIG. 10 shows a state where the entry T ₀ is set by the page walk.

TB ₀ (base virtual address) ← RB ₀ + (RP ₀ × n) = 0x10000000 + (0x00010000 × 2) = 0x10020000
TT ₀ (Base physical address) ← P ₀₂ = 0x0800000
TP ₀ (Page size) ← RP ₀ = 64KB
TV ₀ (entry valid flag) ← True

When a new entry for mapping the requested virtual address and physical address is created in the TLB 301 by the page walk as described above, the conversion process from the virtual address to the physical address by the address translation mechanism 303 is executed again.

FIG. 11 shows a state where the virtual address to physical address conversion process is re-executed for the requested virtual address VA (= 0x1002002010). This time, in addition to the region descriptor 302, an entry T ₀ matching the requested virtual address is found in the TLB 301 (ie, TB ₀ ≦ VA <TB ₀ + TP ₀ and TV ₀ = True). If the requested virtual address VA matches at both TLB301 and Region descriptor 302, entries T ₀ of TLB301 takes precedence. This is because when the TLB hits, the address translation mechanism 303 can directly translate the base virtual address into the base physical address using the entry, and address calculation for page walk is not necessary.

The address translation mechanism 303 calculates the physical address PA from the base physical address TT ₀ acquired from the entry T ₀ of the TLB 301 and the requested virtual address VA according to the processing procedure shown in FIG. ← TT ₀ + (VA−TB ₀ )). In this example, 0x0080000 + (0x10020010-0x10020000) = 0x00080010 is the physical address PA obtained by address translation using the TLB 301.

In short, the MMU 102 according to the present embodiment includes, in addition to the TLB 301 that holds information for converting a virtual address to a physical address, information for address conversion for each of a plurality of regions defined as address conversion targets, and A region descriptor 302 that holds page size information defined for each region is provided. In the above description, according to the MMU 102 according to the present embodiment, in the case of a TLB miss, even if a different page size is defined for each region, the address is efficiently addressed in units of pages using the region descriptor 302. It should be fully understood that conversion can be performed.

FIG. 12 shows a configuration example of a region in the virtual address space realized by using the MMU 102 according to the present embodiment.

In the illustrated virtual address space, four regions of Region # 0 to # 3 are defined. Each region has a page size of 64 KB, 4 KB, 1 KB, and 1 KB, respectively. Region # 0 is used as a text area, Region # 1 and Region # 2 are used as a heap area, and Region # 3 is used as a stack area. However, Region # 1 and Region # 2 use these two regions properly depending on the size of the memory block to be secured.

FIG. 13 shows a configuration example of software that operates on hardware that implements the embedded device (sensing device 100) shown in FIGS.

The sensing device 100 may be a device that a user holds or wears, such as a smart phone, a smart watch, a smart glass, or a smart headphone, or may be equipped in a mobile transportation means such as an electric vehicle.

An application that operates on hardware such as the sensing device 100 includes, for example, a sensing process for sensing a wearer's movement, a behavior estimation process that estimates a wearer's action based on the sensing result, and the estimated result in the cloud It is roughly divided into three communication processes for transmitting to the server 202 via 201. Moreover, the action dictionary used for the action estimation process is included in the application. These applications support the equipment hardware shown in FIG. 1 or FIG. 2, and are provided on the OS that provides the address space (see FIG. 12) realized by the MMU 102 shown in FIG. 3 to each task. Works with.

The sensing device 100 performs a sensing process based on the input from the sensor 105. The “behavior” of the sensing device 100 that can be recognized by the sensor 105 is associated with “behavior” and registered in the behavior dictionary as “behavior definition”, whereby “behavior” is recognized and recognized in the behavior estimation process. While performing the control process of the device itself based on the behavior, the estimated result may be transmitted to the server 202 via the cloud 201 as necessary. The behavior dictionary uses the results of sensing processing and behavior estimation processing, etc., to move the relationship between “action / situation” and “behavior” using artificial intelligence techniques such as deep neural network. You may be made to learn. Examples of the operation include “user operation measurement”. Examples of situations include “high acceleration” and “low acceleration”. For example, the action “user's running” is associated with the action “user's action measurement” and the situation “high acceleration”, and the action “user walks” with the action “user's action measurement” and the situation “low acceleration”. By performing the action recognition process in accordance with the input from the sensor 105, the action can be recognized.

The OS is task management that controls the operation of each task, a flash file manager that manages the file system on the flash memory 104, a virtual memory manager that controls the MMU 102 to configure a virtual address space, and a virtual memory that is allocated to the configured virtual memory A memory block manager for managing the physical memory. The OS also includes device drivers that control devices such as the connected sensor 105, communication module 106, and flash memory 104.

A memory management method using this OS will be described with reference to FIG.

The virtual memory manager mainly manages the page table of each region set in the MMU 102. When the virtual memory manager allocates physical memory to a page in a certain region, it calls the memory block manager to obtain the physical memory. Further, when the virtual memory manager allocates a file on the flash memory 104 to a page in a certain region, the flash file manager is used to store information on which block on the flash memory the corresponding file is located. The block of the corresponding file is placed on the corresponding virtual address by acquiring it from the file system management data in the system and setting the physical address where the block exists in the page table of the region to be placed. A memory management API (Application Programming Interface) for performing such memory management is used from the OS itself or an application running on the OS.

When the OS starts up, it initializes itself for application execution after completing its initialization. The application is stored in advance as file data on the flash memory 104, the file is placed in a virtual address space by calling a memory management API, and a task for executing from the execution start address is generated, thereby executing the application. Begins.

FIG. 15 shows the relationship between the virtual address space provided by the virtual memory manager and each task executed on the virtual address space. The virtual memory manager allocates a block on the physical memory 305 or the flash memory 104 as needed to a region corresponding to the request in accordance with a memory allocation and memory release request by a memory management API called by each task.

In the example shown in FIG. 15, it is assumed that the sensing task, behavior estimation task, and communication task managed by the OS according to the execution of the application process on the sensing device 100 are operating. The virtual address space is shared among a plurality of tasks operating simultaneously.

The instruction code of each application such as sensing processing, behavior estimation processing, and communication processing stored in the flash memory 104 and read-only data to be referred to when executing the program are used as a text area in the virtual address space. Maps to Region # 0. The behavior estimation dictionary used for the behavior estimation process is also mapped to Region # 0.

The sensing task operating on the sensing device 100 uses a sensing processing application mapped to Region # 0. In addition, the sensing task places data that needs to be held during execution of the program in Region # 1 used as a heap area, and memory is dynamically allocated and released in the area during execution. In addition, the sensing task places a function called during execution of the program in Region # 3 used as a stack area.

Similarly, a behavior estimation task operating on the sensing device 100 uses a behavior estimation processing application and a behavior estimation dictionary mapped to Region # 0. In addition, the behavior estimation task places data that needs to be held during execution of the program in Region # 1 used as a heap area, and memory is dynamically secured and released in the area during execution. Further, the behavior estimation task places a function called during execution of the program in Region # 3 used as a stack area.

Similarly, a communication task operating on the sensing device 100 uses a communication processing application mapped to Region # 0. Further, the communication task places data that needs to be held during execution of the program in Region # 1 used as a heap area, and memory is dynamically allocated and released in the area during execution. Further, the communication task places a function called during execution of the program in Region # 3 used as a stack area.

FIG. 16 shows a mechanism for using Region # 0 as a text area among the regions provided by the virtual memory manager.

In the page table for Region # 0 on the physical memory 305, for a specific file on the flash memory 104 to be pasted in the text area, the physical address of the block on the flash memory 104 of the file is set.

When the file system is configured on the flash memory 104, the blocks are not necessarily arranged as continuous blocks in the flash memory 104. However, even in such a case, the virtual address space is obtained by address conversion using the page table. A file can be pasted as a continuous virtual address in the text area (Region # 0).

In addition, the page size in Region # 0 is matched with the block size (typically 64 KB) of the flash memory 104. Therefore, for example, for a file (192 KB) that occupies three blocks on the flash memory 104, this file can be mapped to a text area if there are three entries on the page table.

FIG. 17 shows a processing procedure for mapping the file in the flash memory 104 to the memory space (text area of the virtual address space) by the virtual memory manager in the form of a flowchart.

The virtual memory manager first tries to acquire a free address space of the mapping destination region (Region # 0) (step S1701).

Here, if an empty address space cannot be obtained from the mapping destination region (No in step S1702), the file mapping is given up as an address space shortage error, and this processing is terminated.

If a free address space can be acquired from the mapping destination region (Yes in step S1702), the virtual memory manager attempts to acquire arrangement information in the flash memory 104 of the file mapped to the region (step S1702). S1703). The processing in step S1703 corresponds to the processing indicated by reference numeral 1402 in FIG.

Here, if the placement information of the file to be mapped to the region cannot be obtained, that is, there is no file to be mapped (No in step S1704), the file mapping is given as a file nonexistence error, and this processing is performed. finish.

When the placement information of the file to be mapped to the region can be acquired, that is, when there is a file to be mapped (Yes in step S1704), the virtual memory manager displays the page of the region on the physical memory 305. The in-memory arrangement information of the file is written in the table (step S1705), and the file mapping process is terminated. The processing in step S1705 corresponds to the processing indicated by reference numeral 1403 in FIG.

FIG. 18 shows a processing procedure for releasing a file mapped to the memory space (text area of the virtual address space) by the virtual memory manager in the form of a flowchart.

The virtual memory manager checks whether the address designated to be released is a file mapping destination (step S1801).

If the address designated for release is the file mapping destination (Yes in step S1801), the virtual memory manager returns the page table of the region to unused (step S1802), and ends this processing. . The process in step S1802 corresponds to the process indicated by reference numeral 1403 in FIG.

On the other hand, if the address designated to be released is not the mapping destination of the file (No in step S1801), the mapping is released as an address designation error, and this processing is terminated.

FIG. 19 shows a mechanism for using Region # 1 and Region # 2 among the regions provided by the virtual memory manager as heap areas.

As described above, the unit of memory allocation from the heap area largely depends on the processing contents and how to write the program. The memory to be secured may be several bytes or several hundred KB. In this embodiment, in order to prevent fragmentation due to mixing of memories of such sizes, in this embodiment, the heap allocator uses two regions, Region # 1 and Region # 2, depending on whether the memory to be secured is 4 KB or more. Yes.

"Malloc" is a function that dynamically secures memory, and "free" is a function that dynamically releases the secured memory. In the example shown in FIG. 19, the heap allocator selects a heap area to be used according to the memory size to be secured.

For small memory allocation requests less than 4 KB, the heap allocator allocates physical memory to Region # 2 with the page size set to 1 KB. However, for a memory request exceeding the page size of 1 KB, a plurality of pages are allocated and used. In response to a memory allocation request of 4 KB or more, the heap allocator allocates physical memory to Region # 1 in which the page size is set to 4 KB.

The number of memory requests for the heap area to be classified and the size set as the threshold when classifying vary depending on the memory request pattern of the application, but at least by classifying according to the secured size, the memory It becomes possible to suppress fragmentation.

FIG. 20 shows a processing procedure for securing memory from the heap area in the form of a flowchart.

For example, dynamic allocation of memory is required using a malloc function. When the memory size of the heap area to be secured is 4 KB or more (Yes in step S2001), the process of securing the memory is executed from Region # 1 where the page size is defined as 4 KB (step S2002). Details of the process of securing the memory from Region # 1 will be described later.

On the other hand, if the memory size of the heap area to be secured is less than 4 KB (No in step S2001), a process of securing the memory is executed from Region # 2 where the page size is defined as 1 KB (step S2003). Details of the process of allocating memory from Region # 2 will be described later.

FIG. 21 shows a processing procedure for releasing the memory secured in the heap area in the form of a flowchart.

For example, dynamic release of memory is requested using the free function. If the address of the memory requested to be released is Region # 1 defined with a page size of 4 KB (Yes in step S2101), the memory of Region # 1 (or an area with a page size of 4 KB) is released. The process is executed (step S2102). Details of the processing for releasing the memory secured in Region # 1 will be described later.

On the other hand, when the memory address requested to be released is not Region # 1 (No in step S2101), processing for releasing the memory in Region # 2 (or an area having a page size of 1 KB) is executed (step S2103). ). Details of the processing for releasing the memory secured in Region # 2 will be described later.

FIG. 22 shows, in the form of a flowchart, a processing procedure for securing a memory from Region # 1 defined with a page size of 4 KB, which is executed in step S2002 of the flowchart shown in FIG.

First, the virtual memory manager tries to acquire a free address space having a size specified in Region # 1 (step S2201).

Here, when an empty address space having the size specified in Region # 1 cannot be acquired (No in step S2202), the file mapping is given up as an address space shortage error, and this processing is terminated.

If a free address space having a size specified in Region # 1 can be acquired (Yes in step S2202), the virtual memory manager acquires a free memory block from the memory block manager (step S2203). Details of the process of acquiring an empty memory block from the memory manager will be described later.

If a free memory block can be acquired from the memory block manager (Yes in step S2204), the virtual memory manager stores the memory block acquired in step S2201 in the page table of the region on the physical memory 305. Is written (step S2205), and this process is terminated. The process in step S2205 corresponds to the process indicated by reference numeral 1403 in FIG.

If a free memory block cannot be obtained from the memory block manager (No in step S2204), the memory is given up as a memory shortage error, and this process is terminated.

FIG. 23 shows, in the form of a flowchart, the processing procedure for releasing the memory secured in Region # 1 defined in the page size of 4 KB, which is executed in step S2102 of the flowchart shown in FIG. .

The virtual memory manager checks whether or not the address designated to be released corresponds to Region # 1 (step S2301).

When the address designated to be released corresponds to Region # 1 (Yes in step S2301), the virtual memory manager executes processing for returning the memory block to the memory block manager (step S2302). Details of the process of returning the memory block to the memory block manager will be described later.

Then, the virtual memory manager returns the page table of the region to unused (step S2303) and ends this process. The process of step S2303 corresponds to the process indicated by reference numeral 1403 in FIG.

On the other hand, if the address designated to be released is not Region # 1 (No in step S2301), the memory release is given up as an address designation error, and this processing is terminated.

FIG. 24 shows, in the form of a flowchart, a processing procedure for securing a memory from Region # 2 in which the page size is defined as 1 KB, which is executed in step S2003 of the flowchart shown in FIG.

First, the virtual memory manager tries to acquire a free address space having a size specified in Region # 2 (step S2401).

Here, when an empty address space having the size specified in Region # 2 cannot be acquired (No in step S2402), the file mapping is abandoned as an address space shortage error, and this processing is terminated.

If a free address space having a size specified in Region # 2 can be acquired (Yes in step S2402), the virtual memory manager acquires a free memory block from the memory block manager (step S2403). Details of the process of acquiring an empty memory block from the memory manager will be described later.

If an empty memory block can be acquired from the memory block manager (Yes in step S2404), the virtual memory manager stores the memory block acquired in step S2401 in the page table of the region on the physical memory 305. Is written (step S2405), and the process is terminated. The processing in step S2405 corresponds to the processing indicated by reference numeral 1403 in FIG.

If a free memory block cannot be obtained from the memory block manager (No in step S2404), the memory is given up as a memory shortage error, and this process is terminated.

FIG. 25 shows, in the form of a flowchart, the processing procedure for releasing the memory secured in Region # 2 defined with the page size of 1 KB, which is executed in step S2103 of the flowchart shown in FIG. .

The virtual memory manager checks whether the address designated to be released corresponds to Region # 2 (step S2501).

If the address designated to be released corresponds to Region # 2 (Yes in step S2501), the virtual memory manager executes a process for returning the memory block to the memory block manager (step S2502). Details of the process of returning the memory block to the memory block manager will be described later.

Then, the virtual memory manager returns the page table of the region to unused (step S2503), and ends this process. The process of step S2303 corresponds to the process indicated by reference numeral 1403 in FIG.

On the other hand, if the address designated to be released is not Region # 2 (No in step S2501), the memory is given up as an address designation error, and this processing is terminated.

FIG. 26 shows a processing procedure for acquiring an empty memory block from the memory block manager executed in step S2203 of the flowchart shown in FIG. 22 and step S2403 of the flowchart shown in FIG. 24 in the form of a flowchart. ing.

The memory block manager checks whether there is a free physical memory block (step S2601).

If there is a free physical memory block (Yes in step S2601), the memory block manager changes the state of the free memory block to used (step S2602), and ends this process.

On the other hand, if there is no free space in the physical memory block (No in step S2601), it gives up the acquisition of the free memory block as a memory shortage error, and ends this processing.

FIG. 27 shows a processing procedure for returning a memory block to the memory block manager executed in step S2302 of the flowchart shown in FIG. 23 and step S2503 of the flowchart shown in FIG. 25 in the form of a flowchart. .

The memory block manager changes the state of the memory block returned from the virtual memory manager to empty (step S2701), and ends this process.

FIG. 28 shows a mechanism for using Region # 3 as a stack area among the regions provided by the virtual memory manager.

There is one stack area for each task that implements the program. The stack area is an area in which the usage amount increases dynamically due to the progress of function calls during program execution. In this embodiment, considering the case where the average stack consumption of tasks operating in the system is small, the page size of Region # 3 used as the stack area is set to 1 KB.

When initializing a task, the physical memory for one page is first allocated to the virtual address space as the stack area of the task. When the page is used up during the operation of the task, the physical memory is dynamically added one page at a time. Are allocated to the virtual address space.

If the allocated physical memory is exhausted due to the progress of stack consumption of a task, access to a virtual address to which no memory has been allocated occurs, so that the task causes a bus fault. The OS dynamically extends the stack area by allocating the physical memory secured from the memory block manager to the virtual address where the bus fault has occurred in the handler of the bus fault.

FIG. 29 shows a processing procedure for dynamically allocating a stack area as a task bus fault process in the form of a flowchart.

When a task bus fault occurs, the bus fault handler checks whether the fault occurrence address is Region # 3 used as a stack area (step S2901).

If the fault occurrence address is not Region # 3 (No in step S2901), the task is stopped due to a bus error, and this process is terminated.

If the fault occurrence address is Region # 3 (Yes in step S2901), the bus fault handler acquires an empty memory block from the memory block manager (step S2902). The process of acquiring an empty memory block from the memory manager is executed according to the processing procedure (described above) shown in FIG.

If a free memory block can be acquired from the memory block manager (Yes in step S2903), the bus fault handler stores the memory block acquired in step S2902 in the page table of the region on the physical memory 305. Is written (step S2904), and the processing by the bus fault handler is terminated. The processing in step S2904 corresponds to the processing indicated by reference numeral 1403 in FIG.

If a free memory block cannot be obtained from the memory block manager (No in step S2903), the memory is given up as a memory shortage error, and this processing is terminated.

Also, when the task is finished, a process to release the stack allocated so far is executed.

FIG. 30 shows a processing procedure for releasing the stack at the end of the task in the form of a flowchart.

At the end of the task, the virtual memory manager executes a process for returning the memory block to the memory block manager (step S3001). The process of returning the memory block to the memory block manager is executed according to the processing procedure (described above) shown in FIG.

Then, the virtual memory manager returns the page table of the region to unused (step S3002), and ends this process. The process in step S3002 corresponds to the process indicated by reference numeral 1403 in FIG.

The setting of the page size of each region (text area: 64 KB, heap area: 4 KB or 1 KB, stack area: 1 KB) in the present embodiment is merely an example. The appropriate page size in each region varies depending on conditions such as the scale and nature of the application task to be executed and the memory capacity installed in the device (sensing device 100). The important point is that the requirements for the text, heap, and stack areas are different, and according to the technique disclosed herein, an appropriate page size can be used with less memory for such requests. .

In the present embodiment, it is assumed that a sensing task, a behavior estimation task, and a communication task are operating on the sensing device 100 (see, for example, FIG. 15). In this embodiment, it is assumed that these tasks have the following properties and memory requirements.

(1) Sensing task The sensing task periodically acquires information from the various sensors 105 at a constant cycle, and passes the sensor value to the behavior estimation task. The instruction code of the sensing task is only about one block (64 KB) of the flash memory 104, and several memory areas of about 1 KB are used from the heap area. The consumption of the stack area is about 1 KB.

(2) Behavior estimation task The behavior estimation task executes an algorithm that periodically performs behavior estimation using the sensor value passed from the sensing task and the behavior estimation dictionary on the flash memory 104, and uses the estimated result as a communication task. hand over. The instruction code of the action estimation task and the action estimation dictionary are only enough to fit in one block (64 KB) of the flash memory, and the memory area of about 16 KB and several memory areas of about 1 KB are used from the heap area. The consumption of the stack area is about 4 KB.

(3) Communication task The communication task transmits the estimation result of the behavior estimation task to the server 202 on the cloud 202. Although the transmission data is periodically received from the behavior estimation task, exception processing such as error processing may be required irregularly such as connection disconnection during communication with the server 202 or subsequent retry. The instruction code of the communication task is about 256 KB (4 blocks) on the flash memory 104. From the heap area, several memory areas of about 4 KB and ten memory areas of about 1 KB are used. The consumption amount of the stack area is about 2 KB in the normal state, but may increase to about 4 KB by exception processing or the like.

Based on the premise as described above, according to the technique disclosed in this specification, each region can be realized in the virtual address space as follows.

(1) Text Area Region # 0 that provides a text area has a page size of 64 KB, which is the block size of the flash memory 104. The number of pages required for each task is 1 page, 2 pages, and 4 pages, respectively. If there is a page table for a total of 7 pages, the text area for all tasks can be provided.

(2) Heap area Region # 1 and Region # 2 providing the heap area use two page sizes of 4 KB page and 1 KB page in order to satisfy various memory securing requests as described above. In the embodiment described above, memory requests can be broadly classified into two types, those having a size of about 1 KB and those exceeding 4 KB. Therefore, it is effective in preventing memory fragmentation by using different regions.

(3) Stack area Region # 3 providing the stack area uses 1 KB, which is the minimum value of the stack consumption required in the task, as the page size. Each task allocates a maximum of one page, four pages, and four pages of physical memory as a stack. For example, when the page size is specified as 4 KB, only 1 KB is used for the sensing task, and 3 KB is wasted. However, such waste can be suppressed.

Using an appropriate page size according to the application in this way leads to reducing memory waste and page table size. In addition, the number of TLB entries required for address translation in the MMU 102 is also suppressed. In the address translation by the MMU 102, it is finally necessary that the translation source virtual address (base virtual address TB) and the translation destination physical address (base physical address TT) are placed in the TLB 301. However, the number of entries in the TLB 301 is limited, and when the base virtual address comparison in the TLB 301 does not match (that is, when a TLB miss occurs), an additional process called page walk processing using the region descriptor 302 is performed. (Address translation using the TLB 301 and page walk processing using the region descriptor 302 at the time of a TLB miss are as already described with reference to FIGS. 3 to 7). Reducing the size of the page table also reduces the frequency of such page walk processing.

As described above, the technology disclosed in this specification has been described in detail with reference to specific embodiments. However, it is obvious that those skilled in the art can make modifications and substitutions of the embodiments without departing from the scope of the technology disclosed in this specification.

The memory management technology disclosed in this specification is applied to, for example, an embedded device having only a small amount of memory, and defines a plurality of regions to be subjected to address conversion, and also defines a page size for each region. Thus, it is possible to suppress unnecessary memory consumption and to efficiently perform address conversion in units of pages. Of course, the memory management technique disclosed in this specification can be similarly applied to an information processing apparatus equipped with a normal or large-capacity memory.

In short, the technology disclosed in the present specification has been described in the form of examples, and the description content of the present specification should not be interpreted in a limited manner. In order to determine the gist of the technology disclosed in this specification, the claims should be taken into consideration.

Note that the technology disclosed in the present specification can also be configured as follows.
(1) A memory management device that performs address conversion from a virtual address to a physical address in page units,
Region address translation information defined in the virtual address space, a region information holding unit for holding a unique page size of the region,
A search unit that searches for information of a physical address corresponding to the virtual address using the address conversion information of the region including the virtual address;
A memory management device comprising:
(2) The region information holding unit includes a base virtual address of each region defined on the virtual address space, a page table address for each region placed on the physical memory, a page size defined for the region, And information about the region size in the entry for each region,
The search unit searches for information on the physical address corresponding to the virtual address from the corresponding page table on the physical memory based on the page table address corresponding to the region including the virtual address.
The memory management device according to (1) above.
(3) The search unit
From the entry containing the virtual address in the base virtual address and the address range obtained by adding the page size of the region to the base virtual address in the region information holding unit, specify the page table address of the region including the virtual address,
The physical address information is obtained from the page specified by dividing the difference between the virtual address and the base virtual address by the page size on the page table specified by the page table address.
The memory management device according to (2) above.
(4) Information indicating a correspondence relationship between the base virtual address and the base physical address in page units, and an address translation buffer that holds information on the page size defined in the region including the virtual address;
An address translation unit that combines a base physical address and a virtual address obtained from an entry that hits a virtual address in the address translation buffer, and translates the physical address corresponding to the virtual address;
The memory management device according to any one of (1) to (3), further including:
(5) The address translation unit searches the address translation buffer for an entry including a virtual address in a base virtual address and an address range obtained by adding the page size of the region to the base virtual address.
The memory management device according to (4) above.
(6) Assign different regions in the virtual address space to a plurality of memory areas storing data having different uses.
The memory management device according to any one of (1) to (5) above.
(7) Assign different regions in the virtual address space to the text area, heap area, and stack area.
The memory management device according to any one of (1) to (6) above.
(8) Assign a region in which the page size is defined based on a predetermined block size to the text area.
The memory management device according to any one of (1) to (7).
(9) Allocate two or more regions with different page sizes to the heap area.
The memory management device according to any one of (1) to (8).
(10) When allocating a memory area from the heap area, assign a region in which a page size that does not exceed the memory size to be allocated is defined,
The memory management device according to (9) above.
(11) In response to a bus fault occurring in the region allocated to the stack area, physical memory is allocated in page size units.
The memory management device according to any one of (1) to (10) above.
(12) A memory management method for performing address conversion from a virtual address to a physical address in page units,
Using the address translation information of the region defined in the virtual address space and the address translation information held in the region information holding unit holding the unique page size of the region, information on the physical address corresponding to the virtual address is obtained. A search step for searching;
It is obtained from the entry that hits the virtual address in the address translation buffer that holds the information indicating the correspondence between the base virtual address and the base physical address in page units and the page size information defined in the region that includes the virtual address. An address conversion step of converting a base physical address and a virtual address into a physical address corresponding to the virtual address;
A memory management method.
(13) physical memory;
A region information holding unit that holds the address translation information of the region defined in the virtual address space and a unique page size of the region, and a physical address corresponding to the virtual address using the address translation information of the region including the virtual address. A memory management unit having a search unit for searching for information, and performing address conversion from a virtual address to a physical address in units of pages;
An information processing apparatus comprising:

DESCRIPTION OF SYMBOLS 100 ... Sensing device 101 ... CPU, 102 ... MMU, 103 ... SRAM
104 ... Flash memory, 105 ... Sensor 106 ... Communication module, 107 ... Battery, 110 ... Bus 200 ... Base station, 201 ... Cloud, 202 ... Server

Claims (13)

1. A memory management device that performs address conversion from a virtual address to a physical address in page units,
   Region address translation information defined in the virtual address space, a region information holding unit for holding a unique page size of the region,
   A search unit that searches for information of a physical address corresponding to the virtual address using the address conversion information of the region including the virtual address;
   A memory management device comprising:
2. The region information holding unit includes a base virtual address of each region defined on the virtual address space, an address of a page table for each region placed on the physical memory, a page size defined in the region, and a region size Information about the
   The search unit searches for information on the physical address corresponding to the virtual address from the corresponding page table on the physical memory based on the page table address corresponding to the region including the virtual address.
   The memory management device according to claim 1.
3. The search unit
   From the entry containing the virtual address in the base virtual address and the address range obtained by adding the page size of the region to the base virtual address in the region information holding unit, specify the page table address of the region including the virtual address,
   The physical address information is obtained from the page specified by dividing the difference between the virtual address and the base virtual address by the page size on the page table specified by the page table address.
   The memory management device according to claim 2.
4. Information indicating the correspondence between the base virtual address and the base physical address in page units, and an address translation buffer that holds information on the page size defined in the region including the virtual address;
   An address translation unit that combines a base physical address and a virtual address obtained from an entry that hits a virtual address in the address translation buffer, and translates the physical address corresponding to the virtual address;
   The memory management device according to claim 1, further comprising:
5. The address translation unit searches the address translation buffer for an entry including a virtual address in a base virtual address and an address range obtained by adding a region page size to the base virtual address.
   The memory management device according to claim 4.
6. Assign different regions in the virtual address space to multiple memory areas that store data for different purposes.
   The memory management device according to claim 1.
7. Assign different regions in the virtual address space to the text area, heap area, and stack area.
   The memory management device according to claim 1.
8. Assign a region with a defined page size to the text area based on a given block size,
   The memory management device according to claim 1.
9. Allocate two or more regions with different page sizes to the heap area.
   The memory management device according to claim 1.
10. When allocating a memory area from the heap area, assign a region with a page size that does not exceed the memory size you want to allocate,
    The memory management device according to claim 9.
11. In response to a bus fault occurring in the region allocated to the stack area, physical memory is allocated in page size units.
    The memory management device according to claim 1.
12. A memory management method for performing address conversion from a virtual address to a physical address in page units,
    Using the address translation information of the region defined in the virtual address space and the address translation information held in the region information holding unit holding the unique page size of the region, information on the physical address corresponding to the virtual address is obtained. A search step for searching;
    It is obtained from the entry that hits the virtual address in the address translation buffer that holds the information indicating the correspondence between the base virtual address and the base physical address in page units and the page size information defined in the region that includes the virtual address. An address conversion step of converting a base physical address and a virtual address into a physical address corresponding to the virtual address;
    A memory management method.
13. Physical memory,
    A region information holding unit that holds the address translation information of the region defined in the virtual address space and a unique page size of the region, and a physical address corresponding to the virtual address using the address translation information of the region including the virtual address. A memory management unit having a search unit for searching for information, and performing address conversion from a virtual address to a physical address in units of pages;
    An information processing apparatus comprising:

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