WO2019155575A1 - Display device - Google Patents

Display device Download PDF

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Publication number
WO2019155575A1
WO2019155575A1 PCT/JP2018/004419 JP2018004419W WO2019155575A1 WO 2019155575 A1 WO2019155575 A1 WO 2019155575A1 JP 2018004419 W JP2018004419 W JP 2018004419W WO 2019155575 A1 WO2019155575 A1 WO 2019155575A1
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Prior art keywords
frame
common voltage
display device
value
length
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PCT/JP2018/004419
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French (fr)
Japanese (ja)
Inventor
三上　浩
Original Assignee
堺ディスプレイプロダクト株式会社
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Priority to PCT/JP2018/004419 priority Critical patent/WO2019155575A1/en
Publication of WO2019155575A1 publication Critical patent/WO2019155575A1/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals

Definitions

  • the present invention relates to a display device that displays an image.
  • Patent Document 1 discloses a liquid crystal display device that adjusts a common voltage in order to reduce flicker of a display image due to burn-in of a liquid crystal panel.
  • the liquid crystal display device of Patent Document 1 determines a set value of a common voltage to be applied to a common electrode of a liquid crystal panel based on input image data, and drives at least one of a scanning line and a signal line of the liquid crystal panel. Based on the timing, the timing for changing the common voltage to the set value is determined. As a result, the common voltage can be adjusted in the blanking period of the predetermined frame period.
  • An object of the present invention is to provide a display device capable of suppressing flicker when displaying an image with a changed frame rate.
  • the display device includes a plurality of pixels, a voltage source, a source driver, and a controller.
  • the voltage source supplies a common voltage common to the plurality of pixels.
  • the source driving unit outputs a source signal having a positive polarity indicating a voltage higher than the common voltage or a negative polarity indicating a low voltage to each pixel for each frame.
  • the control unit controls display of an image for each frame based on a video signal having a variable frame period.
  • the control unit detects a length of a frame period in which an image for each frame is displayed with a positive polarity and a length of a frame period displayed with a negative polarity.
  • the control unit corrects the common voltage according to the deviation of the length of the frame period detected in each polarity.
  • flickering when displaying an image whose frame rate changes can be suppressed by correcting the common voltage according to the deviation of the length of the frame period.
  • FIG. 1 is a diagram illustrating a configuration of a display device according to a first embodiment.
  • FIG. 7 is a diagram illustrating a circuit configuration of a pixel in a display device.
  • the block diagram which shows the structure of the control part in a display apparatus Block diagram showing the configuration of the common voltage correction processing unit in the control unit
  • the figure which illustrates the correction table in the recording part of a control part Diagram for explaining the problem with variable frame rate 7 is a flowchart for explaining common voltage correction processing in the display device according to the first embodiment. Timing chart for explaining common voltage correction processing in the display device of Embodiment 1
  • FIG. 1 is a diagram illustrating a configuration of a display device 1 according to the present embodiment.
  • the display device 1 constitutes a liquid crystal display device such as a liquid crystal monitor conforming to the HDMI 2.1 standard (“HDMI” is a registered trademark), for example.
  • the display device 1 includes a liquid crystal panel 10, a control unit 2, a gate drive unit 11, a source drive unit 12, a common voltage source 13, and a memory 10a.
  • the liquid crystal panel 10 has a predetermined specification such as 8K, 4K, or 2K, and is configured by an active matrix method. As shown in FIG. 1, the liquid crystal panel 10 includes a plurality of pixels 3, a plurality of gate lines GL, and a plurality of source lines SL.
  • the liquid crystal panel 10 includes, for example, a TFT (thin film transistor) substrate having a pixel electrode, a CF (color filter) substrate having a common electrode, a liquid crystal layer sealed between the two substrates, a polarizing plate, and the like.
  • the plurality of pixels 3 are arranged in a matrix and form a display area for displaying an image.
  • the row direction (x) of the matrix of the pixels 3 is referred to as “horizontal direction”
  • the column direction (y) is referred to as “vertical direction”.
  • the plurality of pixels 3 each include an active element TFT or the like.
  • the gate is connected to the gate line GL, and the source is connected to the source line SL (see FIG. 2).
  • the gate line GL is a signal line wired in the row direction of the matrix of the pixels 3 and connected to the pixels 3 one by one.
  • the source line SL is a signal line wired in the column direction of the matrix of the pixels 3.
  • the memory 10a is a flash ROM, for example, and stores information unique to the liquid crystal panel 10 and the like.
  • the control unit 2 is composed of one or a plurality of semiconductor integrated circuits such as LSIs. As a timing controller, the control unit 2 generates various signals for controlling the operation timing of each unit of the display device 1. The control unit 2 may control the overall operation of the display device 1. Details of the configuration of the control unit 2 will be described later.
  • the gate drive unit 11 generates a gate signal for sequentially selecting the gate lines GL of each row in the matrix of the pixels 3 under the control of the control unit 2, and drives the plurality of gate lines GL at a predetermined frame period.
  • the frame period is dynamically set by the video signal, for example, within a range of 1/120 to 1/30 seconds.
  • the gate drive unit 11 is configured by a drive circuit such as an IC to which a plurality of gate lines GL are connected, for example.
  • the source driver 12 supplies a source signal having a voltage corresponding to the gradation to be displayed for each pixel 3 to the plurality of source lines SL in synchronization with the operation of the gate driver 11 under the control of the controller 2. .
  • the source driving unit 12 is configured by a driving circuit such as an IC to which a plurality of source lines SL are connected, for example.
  • the source driver 12 drives by a frame inversion method that switches the voltage of the source signal between positive polarity and negative polarity for each frame.
  • the common voltage source 13 supplies a common voltage Vcom to the common electrode of the pixel 3 in the liquid crystal panel 10.
  • the common voltage Vcom is a reference for the positive and negative polarities of the source signal.
  • the common voltage Vcom is set, for example, within a range of 5.5 to 8.2V.
  • the common voltage source 13 includes a voltage generation circuit that generates a set voltage. In the present embodiment, the set value of the common voltage Vcom is controlled by the control unit 2.
  • the common voltage source 13 is an example of a voltage source in the display device 1 of the present embodiment.
  • FIG. 2 is a diagram illustrating a circuit configuration of the pixel 3 in the display device 1.
  • FIG. 2 shows an equivalent circuit of the pixel 3 (hereinafter referred to as “pixel circuit” 30).
  • the pixel circuit 30 includes a TFT 31, a pixel capacitor 32, and a storage capacitor 33.
  • the gate is connected to the gate line GL
  • the source is connected to the source line SL
  • the drain is connected to one end of each of the pixel capacitor 32 and the storage capacitor 33.
  • the other ends of the pixel capacitor 32 and the storage capacitor 33 are connected to, for example, a common electrode in the liquid crystal panel 10.
  • a common voltage source 13 is connected to the common electrode, and a common voltage Vcom is supplied.
  • the TFT 31 is turned on when the voltage applied to the gate based on the gate signal from the gate line GL is equal to or higher than a predetermined threshold voltage, and turned off when the voltage is lower than the threshold voltage.
  • the TFT 31 is an example of a transistor connected to the gate line GL.
  • the pixel capacitor 32 includes a liquid crystal layer and a pixel electrode, and changes the alignment state of the liquid crystal layer according to the amount of charge.
  • the pixel capacitor 32 charges or discharges charges based on the voltage of the source signal Sout input from the source line SL while the TFT 31 is on.
  • the pixel capacitor 32 holds the charge amount obtained by charging / discharging before the TFT 31 is switched off during the period in which the TFT 31 is off.
  • the storage capacitor 33 is a capacitive element for holding the charge amount (charge voltage) held by the pixel capacitor 32.
  • the storage capacitor 33 charges and discharges charges at the same timing as the charge and discharge by the pixel capacitor 32.
  • FIG. 3 is a block diagram illustrating a configuration of the control unit 2 in the display device 1.
  • control unit 2 includes a video input unit 21, a gamma conversion unit 22, a gate drive I / F (interface) 23, a source drive I / F 24, a memory I / F 25, and a recording unit. 26, a common voltage correction processing unit 4, and a voltage source control unit 27.
  • the video input unit 21 is an input interface circuit that conforms to a predetermined communication standard such as the HDMI 2.1 standard.
  • the video input unit 21 receives an external video signal and outputs image data indicating an image for each frame in the video signal, a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a clock signal Clk.
  • the vertical synchronization signal Vsync indicates the timing at which the operations of the drive units 11 and 12 are synchronized for each frame of image data.
  • the horizontal synchronization signal Hsync indicates a synchronization timing for each horizontal synchronization period 1H in which operations for each row in the frame are performed in synchronization.
  • the clock signal Clk indicates a reference operation cycle of the pixel 3.
  • the gamma conversion unit 22 inputs image data from the video input unit 21 and executes gamma conversion processing for performing gamma correction.
  • the gamma conversion unit 22 includes, for example, an LUT (Look Up Table) in which digital values for gamma correction are stored.
  • the gamma conversion unit 22 outputs the converted image data D (N) to the source drive I / F 24. N indicates a frame number.
  • the image data D (N) is not limited to gamma conversion processing but may be subjected to various conversion processing such as dither processing.
  • the gate drive I / F 23 is an interface circuit connected to the gate drive unit 11.
  • the gate drive I / F 23 receives the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, and the clock signal Clk from the video input unit 21 and outputs a control signal including various synchronization signals to the gate drive unit 11.
  • the source drive I / F 24 is an interface circuit connected to the source drive unit 12.
  • the source drive I / F 24 receives the image data D (N) after conversion such as gamma conversion, and outputs a control signal for displaying an image indicated by the image data D (N) to the source drive unit 12.
  • the source drive I / F 24 may generate various control signals from the video input unit 21 and generate a control signal for the source drive unit 12. For example, the source drive I / F 24 sets polarity information P (N) indicating the polarity of the voltage of the source signal in the frame inversion method.
  • the memory I / F 25 is an interface circuit that reads data from an external memory, and is connected to the memory 10a of the liquid crystal panel 10, for example.
  • the memory I / F 25 acquires information on the common voltage Vcom in the liquid crystal panel 10 and the like.
  • the recording unit 26 stores information acquired from the memory I / F 25.
  • the recording unit 26 includes a register circuit.
  • the recording unit 26 stores, for example, a standard value V0 of the common voltage Vcom, a correction table 26a (see FIG. 5) described later, and the like.
  • the common voltage correction processing unit 4 executes a common voltage correction process for correcting the common voltage Vcom in the display device 1 of the present embodiment.
  • the common voltage correction processing unit 4 receives various synchronization signals Vsync, Hsync, and Clk from the video input unit 21, receives image data D (N) from the gamma conversion unit 22, and receives from the source driving I / F 24.
  • the polarity information P (N) is acquired, and the information stored in the recording unit 26 is read out. Details of the common voltage correction processing unit 4 will be described later.
  • the voltage source control unit 27 is configured by an external device control circuit and is connected to the common voltage source 13.
  • the voltage source control unit 27 outputs a control signal for setting the common voltage Vcom to the common voltage source 13 based on the processing result of the common voltage correction processing unit 4.
  • the control unit 2 is a hardware circuit such as a dedicated electronic circuit or a reconfigurable electronic circuit designed to realize predetermined functions such as the gamma conversion unit 22 and the common voltage correction processing unit 4 described above. Also good.
  • the control unit 2 may include a CPU or the like that realizes various functions as described above in cooperation with software.
  • the control unit 2 may be configured by various semiconductor integrated circuits such as a CPU, MPU, microcomputer, DSP, FPGA, ASIC and the like.
  • FIG. 4 is a block diagram showing the configuration of the common voltage correction processing unit 4.
  • the common voltage correction processing unit 4 includes a frame length detection unit 41, a pixel average calculation unit 42, an accumulation management unit 43, and a common voltage setting unit 44, for example, as a functional configuration of the control unit 2.
  • the frame length detection unit 41 detects the frame length T (N) based on various synchronization signals Vsync, Hsync, and Clk.
  • the frame length is a length of a frame period including a blanking period in one frame.
  • the frame length detection unit 41 includes, for example, a counter that can count the frame length of two frames.
  • the pixel average calculation unit 42 calculates a pixel average value G (N) based on the image data D (N).
  • the pixel average value G (N) indicates the average value of the gradation of each pixel in one frame image.
  • the pixel average calculation unit 42 outputs the pixel average value G (N) in a predetermined range such as 8 bits.
  • the accumulation management unit 43 acquires the frame length T (N), the pixel average value G (N), and the polarity information P (N) for each frame, and sequentially calculates and stores the accumulation value A (N).
  • the accumulated value A (N) indicates a deviation between frame periods having different polarities in a period in which an image is displayed in the past, and is managed for each frame.
  • the common voltage setting unit 44 sets the set value Vcom (N + 1) of the common voltage Vcom of the next frame in the voltage source control unit 27 based on the current accumulated value A (N). Further, the common voltage setting unit 44 outputs the feedback value F (N) regarding the current cumulative value A (N) to the cumulative management unit 43.
  • the common voltage setting unit 44 uses various information such as the correction table 26a and the standard value V0 for calculation of the set value Vcom (N + 1) and the feedback value F (N).
  • the common voltage setting unit 44 may use polarity information P (N).
  • correction Table The correction table 26a stored in the recording unit 26 of the control unit 2 will be described with reference to FIG.
  • FIG. 5 is a diagram illustrating a correction table 26 a in the recording unit 26.
  • the correction table 26 a is a data table that is referred to by the common voltage setting unit 44 of the common voltage correction processing unit 4 in the control unit 2.
  • the correction table 26a is configured by an LUT, for example.
  • FIG. 5 illustrates the correction table 26a when the maximum frame length is 4500 times the horizontal synchronization period 1H (corresponding to 30 Hz) and the pixel average value has 8 bits.
  • the correction table 26a illustrated in FIG. 5 records the range of the accumulated value A (N), the correction value ⁇ V of the common voltage Vcom, and the feedback coefficient Cf corresponding to the feedback value F (N) in association with each other.
  • a video signal generated in an external GPU or the like is input to the display device 1 according to the present embodiment.
  • the length of the frame period in the video signal is set for each frame by adjusting the blanking period of each frame.
  • the control unit 2 of the display device 1 generates each control signal so as to synchronously control the gate driving unit 11 and the source driving unit 12 based on the input video signal.
  • the source driver 12 sequentially outputs source signals while inverting the polarity in the frame inversion method. As a result, a display image for each frame corresponding to the video signal is displayed on the liquid crystal panel 10.
  • FIG. 6 is a diagram for explaining a problem due to a variable frame rate.
  • FIG. 6A is a timing chart illustrating a source signal having a constant frame rate.
  • FIG. 6B is a timing chart showing an example of a source signal whose frame rate changes.
  • FIG. 6C is a timing chart illustrating the correction of the common voltage Vcom during the operation of FIG.
  • FIGS. 6A to 6C illustrate the voltage of the source signal in the frame inversion method.
  • the frame inversion method inverts the polarity of the voltage of the source signal between successive frames in order to extend the life of the liquid crystal.
  • FIGS. 6A to 6C illustrate source signals when an image with a predetermined gradation (the entire image is white or the like) is displayed.
  • the source signal alternately has a positive voltage VH higher than the common voltage Vcom and a negative voltage VL lower than the common voltage Vcom between adjacent frames.
  • FIG. 6A illustrates a case where the frame rate is constant as a normal frame inversion method.
  • the polarity of the source signal changes every time the same period elapses, such as 16.7 milliseconds at 60 Hz.
  • the positive frame period T1 and the negative frame period T2 are equal, liquid crystal burn-in or the like hardly occurs.
  • an image having a predetermined gradation can be displayed as a constant luminance between the positive voltage VH and the negative voltage VL without causing any flicker.
  • FIG. 6B shows an example in which flicker or the like due to a non-uniform frame rate is assumed.
  • FIG. 6B illustrates a source signal when the same image as that in FIG. 6A is displayed while changing the frame rate.
  • the frame rate is changed for each frame, so that the positive frame period T21 after the negative frame period T11 is longer than the negative frame period T11. Further, the positive frame period T22 after the next negative frame period T12 is also longer than the negative frame period T12.
  • the display device 1 of the present embodiment detects the lengths of the frame periods T11 to T22 of each polarity from the input video signal, and has positive frame periods T21 and T22 and negative frame periods T11 and T12.
  • the common voltage Vcom is corrected according to the bias between the two.
  • FIG. 6C shows an example of a method for correcting the common voltage Vcom.
  • FIG. 6C illustrates a case where the common voltage Vcom is corrected with respect to the source signal of FIG.
  • the display device 1 of the present embodiment increases the common voltage Vcom when the positive frame periods T21 and T22 are detected to be longer than the negative frame periods T11 and T12, as in the example of FIG. 6C. To correct. As a result, the effective DC component remaining in the liquid crystal panel 10 can be offset to suppress liquid crystal burn-in, and flicker can be reduced.
  • details of the operation of the display device 1 according to the present embodiment will be described.
  • the common voltage correction process in the display device 1 according to the present embodiment will be described below.
  • the common voltage correction processing according to the present embodiment is a cumulative value A (N) indicating a cumulative total of deviations between a positive frame period and a negative frame period in synchronization with display of an image whose frame rate can change. By managing this, the common voltage Vcom is dynamically corrected. Details of the common voltage correction processing will be described with reference to FIGS.
  • FIG. 7 is a flowchart for explaining the common voltage correction processing in the display device 1 of the present embodiment.
  • FIG. 8 is a timing chart for explaining the common voltage correction processing.
  • FIGS. 8A and 8B show the input timing of the vertical synchronization signal Vsync and the image data D (N) from the outside, respectively.
  • FIG. 8C shows the calculation timing of the accumulated value A (N) in the display device 1.
  • FIG. 8D shows the correction timing of the common voltage Vcom.
  • control unit 2 functions as the frame length detection unit 41 of the common voltage correction processing unit 4 (FIG. 4), and detects the length of the current frame period, that is, the frame length (S1).
  • the frame length detector 41 receives the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, and the clock signal Clk, and performs the process of step S1.
  • FIG. 8A illustrates the vertical synchronization signal Vsync to be processed in step S1.
  • the frame length detection unit 41 counts the period from the time t1 when the vertical synchronization signal Vsync indicates the start of the (N ⁇ 1) th frame to the time t2 when the start of the Nth frame indicates the horizontal synchronization period 1H.
  • the frame length T (N ⁇ 1) of the (N ⁇ 1) th frame is detected.
  • the control unit 2 calculates the pixel average value G (N ⁇ 1) based on the image data D (N ⁇ 1) of the (N ⁇ 1) th frame as the pixel average calculation unit 42 (S2). For example, as shown in FIG. 8B, the pixel average calculation unit 42 sequentially adds the gradation values of the respective pixels input as the image data D (N ⁇ 1) from time t11 after time t1. Then, the pixel average value G (N ⁇ 1) is calculated by dividing the total value by the number of pixels.
  • control unit 2 functions as the accumulation management unit 43, and acquires the polarity information P (N-1) of the (N-1) th frame from the source drive I / F 24 (S3).
  • the polarity information P (N-1) indicates whether the source signal of the (N-1) th frame is positive or negative.
  • the order of the processes in steps S1 to S3 is not particularly limited, and for example, each process may be executed in parallel.
  • step S4 the control unit 2 as the accumulation management unit 43 calculates the accumulated value A ((N ⁇ 1) th frame) from the past accumulated value A (N ⁇ 2) up to the (N ⁇ 2) th frame.
  • Update to (N-1) is performed (S4).
  • the process of step S4 is based on the current frame length T (N-1), pixel average value G (N-1) and polarity information P (N-1), and a feedback value F (N-2) described later. The calculation is performed by the following equation (1).
  • a (N-1) A (N-2) + B (N-1) -F (N-2) (1)
  • the accumulation management unit 43 adds the current addition value B (N ⁇ 1) to the past accumulation value A (N ⁇ 2), and further the previous feedback value F (N ⁇ ). 2) is subtracted to calculate the updated accumulated value A (N ⁇ 1).
  • the added value B (N ⁇ 1) indicates the amount of the DC component that is estimated to be generated in the liquid crystal panel 10 by, for example, the (N ⁇ 1) th frame image display.
  • the addition value B (N ⁇ 1) is expressed as the following equation (2).
  • B (N ⁇ 1) ⁇ G (N ⁇ 1) ⁇ T (N ⁇ 1) (2)
  • the sign on the right side is “+” when the polarity information P (N ⁇ 1) of the (N ⁇ 1) th frame indicates positive polarity, and “+” when the polarity information P (N ⁇ 1) indicates negative polarity.
  • the added value B (N ⁇ 1) of the above equation (2) is proportional to the frame length T (N ⁇ 1) in the same positive / negative polarity as the polarity of the (N ⁇ 1) th frame, and the pixel average value G (N ⁇ Weighted in 1).
  • control unit 2 functions as the common voltage setting unit 44, and sets the common voltage Vcom of the Nth frame according to the updated accumulated value A (N-1) (S5).
  • the common voltage setting unit 44 reads the correction value ⁇ V associated with the range including the updated cumulative value A (N ⁇ 1) in the correction table 26a (FIG. 5) of the recording unit 26, thereby obtaining the following equation (3 ) Is used to determine the correction value ⁇ V [A (N ⁇ 1)].
  • Vcom (N) V0 + ⁇ V [A (N-1)] (3)
  • the common voltage setting unit 44 corrects the correction value ⁇ V [A (N ⁇ 1)] from the standard value V0 of the common voltage Vcom as shown in the above equation (3), and sets the common voltage Vcom for the Nth frame.
  • the value Vcom (N) is calculated.
  • the common voltage setting unit 44 sets the calculated setting value Vcom (N) in the voltage source control unit 27.
  • the control unit 2 as the common voltage setting unit 44 determines a feedback coefficient Cf [A (N ⁇ 1)] corresponding to the correction value ⁇ V [A (N ⁇ 1)] of the common voltage Vcom of the Nth frame.
  • the feedback value F (N ⁇ 1) is calculated (S6).
  • the control unit 2 reads the feedback coefficient Cf based on the same accumulated value A (N ⁇ 1) as the correction value ⁇ V [A (N ⁇ 1)] of the common voltage Vcom of the Nth frame in the correction table 26a.
  • Expression (4) is performed.
  • the frame length T (N ⁇ 1) detected in step S1 is set to the pixel average value G (N ⁇ 1) calculated in step S2 and the feedback coefficient Cf [A (N ⁇ 1). ] Is weighted to calculate the feedback value F (N-1) (S6).
  • the common voltage setting unit 44 outputs the calculated feedback value F (N ⁇ 1) to the accumulation management unit 43 so as to be used in step S4 in the next control cycle (frame).
  • control unit 2 controls the common voltage source 13 in accordance with the set value Vcom (N) as the voltage source control unit 27, and displays an image of the Nth frame (S7).
  • the voltage source control unit 27 controls the common voltage Vcom to the set value Vcom (N) at time t20 before the start of image display of the Nth frame.
  • the set value Vcom (N) of the common voltage Vcom is used until, for example, the start time t3 of the (N + 1) th frame.
  • the control unit 2 repeats the above steps S1 to S7 for each frame.
  • the frame length T (N ⁇ 1) is detected for each frame of the image display (S1), and the added value corresponding to the length of the frame length T (N ⁇ 1) is the same as the polarity of each frame.
  • a cumulative value A (N-1) obtained by accumulating B (N-1) is obtained (S4). According to such accumulated value A (N ⁇ 1), the effective DC component currently stored in the liquid crystal panel 10 can be estimated, and the common voltage Vcom can be dynamically optimized. The optimization of the common voltage Vcom with the accumulated value A (N ⁇ 1) will be described using FIGS. 8A to 8D.
  • FIG. 8A to 8D illustrate the case where the (N-1) th frame is positive.
  • the accumulated values A (N ⁇ 2) to A (N) are obtained for each frame in which the sign is inverted depending on the frame length and the pixel average value of each frame (S1, S2). It changes sequentially (S3, S4).
  • the control unit 2 increases the common voltage Vcom of the Nth frame by the correction value ⁇ V from the standard value V0 based on the accumulated value A (N ⁇ 1) (S5). As a result, the DC component in the liquid crystal panel 10 is canceled, and the burn-in and flicker of the liquid crystal panel 10 can be suppressed.
  • the common voltage correction processing (FIG. 7) of the present embodiment corrects the feedback value F (N ⁇ 1) so that the accumulated value A (N) of the next frame is reduced by the amount corresponding to the correction of the common voltage Vcom. ) Is used (see S6, S4, equation (1)).
  • the cumulative value A (N) can be appropriately managed without divergence in consideration of the effect of correcting the common voltage Vcom.
  • the common voltage Vcom can be optimized by setting values Vcom (N ⁇ 1) to Vcom (N + 1) of each frame based on the accumulated values A (N ⁇ 2) to A (N).
  • the display device 1 includes the plurality of pixels 3, the common voltage source 13, the source driving unit 12, and the control unit 2.
  • the common voltage source 13 supplies a common voltage Vcom to the plurality of pixels 3.
  • the source driver 12 outputs a source signal having a positive polarity indicating a voltage higher than the common voltage Vcom or a negative polarity indicating a low voltage to each pixel 3 for each frame.
  • the control unit 2 controls display of an image for each frame based on a video signal having a variable frame period.
  • the control unit 2 detects the length of the frame period in which the image for each frame is displayed with the positive polarity and the length of the frame period displayed with the negative polarity (S1).
  • the control unit 2 corrects the common voltage Vcom according to the deviation of the length of the frame period detected in each polarity (S5).
  • flickering when displaying an image with a changed frame rate can be suppressed by correcting the common voltage Vcom according to the deviation of the length of the frame period.
  • control unit 2 increases the common voltage Vcom as the length of the positive frame period is larger than the length of the negative frame period.
  • the control unit 2 decreases the common voltage Vcom as the length of the negative frame period is larger than the length of the positive frame period.
  • control unit 2 manages the accumulated value A (N) indicating the cumulative deviation between the positive frame period and the negative frame period (S4).
  • the controller 2 determines the correction value ⁇ V of the common voltage Vcom based on the accumulated value A (N) (S5). Thereby, the common voltage Vcom can be dynamically corrected according to the accumulated value A (N).
  • control unit 2 feeds back the accumulated value A (N) so as to decrease according to the correction value of the common voltage Vcom (S6, S4).
  • the cumulative value A (N) can be appropriately managed in consideration of the effect of correcting the common voltage Vcom.
  • control unit 2 calculates a pixel average value G (N) that is an average value of gradations of the plurality of pixels 3 in the frame image in each frame, and sets the pixel average value G (N). Based on this, the addition value B (N) for each frame is added to the accumulated value A (N) (S2, S3). As a result, the accumulated value A (N) can be accumulated according to the gradation of the image displayed for each frame, and the common voltage Vcom can be accurately corrected.
  • control unit 2 detects the length of each frame period based on the vertical synchronization signal Vsync that synchronizes the display of the video signal (S1). This makes it possible to easily detect the length of each frame period in a situation where the frame rate can change dynamically.
  • the video signal input to the display device 1 conforms to the HDMI 2.1 standard. According to the display device 1 of the present embodiment, it is possible to solve the problem of flicker that may occur in a video signal of the HDMI 2.1 standard.
  • the feedback value F (N ⁇ 1) is calculated based on the equation (4) in the common voltage correction process (FIG. 7) (S6), but the feedback value F (N) is not limited to this. Absent.
  • the feedback value F (N ⁇ 1) may be calculated based on the following equation (4 ′) instead of the equation (4).

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Abstract

A display device (1) comprises: a plurality of pixels (3); a voltage source (13); a source driving unit (12); and a control unit (2). The voltage source supplies a common voltage (Vcom) to the plurality of pixels. The source driving unit outputs, to each pixel and for every frame, a source signal having a positive polarity and exhibiting a higher voltage than the common voltage, or a source signal having a negative polarity and exhibiting a lower voltage than the common voltage. The control unit controls the display of the image of each frame on the basis of a video signal having a variable frame period length. The control unit detects the lengths of frame periods where the images of the frames are displayed with a positive polarity, and the lengths of frame periods where the images of the frames are displayed with a negative polarity (S1). The control unit corrects the common voltage in accordance with deviations in the lengths of the frame periods detected in each polarity (S5).

Description

表示装置Display device
　本発明は、画像を表示する表示装置に関する。 The present invention relates to a display device that displays an image.
　特許文献１は、液晶パネルの焼き付きによる表示画像のフリッカを低減するために、コモン電圧を調整する液晶表示装置を開示している。特許文献１の液晶表示装置は、入力された画像データに基づいて、液晶パネルの共通電極に印加するコモン電圧の設定値を決定し、液晶パネルの走査線及び信号線のうち少なくとも一方を駆動するタイミングに基づいて、コモン電圧を当該設定値に変更するタイミングを決定している。これにより、所定のフレーム期間のうちのブランキング期間の中で、コモン電圧を調整することを可能にしている。 Patent Document 1 discloses a liquid crystal display device that adjusts a common voltage in order to reduce flicker of a display image due to burn-in of a liquid crystal panel. The liquid crystal display device of Patent Document 1 determines a set value of a common voltage to be applied to a common electrode of a liquid crystal panel based on input image data, and drives at least one of a scanning line and a signal line of the liquid crystal panel. Based on the timing, the timing for changing the common voltage to the set value is determined. As a result, the common voltage can be adjusted in the blanking period of the predetermined frame period.
特開２００６－１９５１５２号公報JP 2006-195152 A
　本発明の目的は、フレームレートが変化する画像を表示する際のフリッカを抑制することができる表示装置を提供することにある。 An object of the present invention is to provide a display device capable of suppressing flicker when displaying an image with a changed frame rate.
　本発明に係る表示装置は、複数の画素と、電圧源と、ソース駆動部と、制御部とを備える。電圧源は、複数の画素に共通のコモン電圧を供給する。ソース駆動部は、コモン電圧よりも高い電圧を示す正極性又は低い電圧を示す負極性を有するソース信号をフレーム毎に各画素に出力する。制御部は、フレーム期間の長さが可変の映像信号に基づいて、フレーム毎の画像の表示を制御する。制御部は、フレーム毎の画像が正極性で表示されたフレーム期間の長さと、負極性で表示されたフレーム期間の長さとを検出する。制御部は、各極性で検出したフレーム期間の長さの偏りに応じて、コモン電圧を補正する。 The display device according to the present invention includes a plurality of pixels, a voltage source, a source driver, and a controller. The voltage source supplies a common voltage common to the plurality of pixels. The source driving unit outputs a source signal having a positive polarity indicating a voltage higher than the common voltage or a negative polarity indicating a low voltage to each pixel for each frame. The control unit controls display of an image for each frame based on a video signal having a variable frame period. The control unit detects a length of a frame period in which an image for each frame is displayed with a positive polarity and a length of a frame period displayed with a negative polarity. The control unit corrects the common voltage according to the deviation of the length of the frame period detected in each polarity.
　本発明に係る表示装置によると、フレーム期間の長さの偏りに応じてコモン電圧を補正することにより、フレームレートが変化する画像を表示する際のフリッカを抑制することができる。 According to the display device according to the present invention, flickering when displaying an image whose frame rate changes can be suppressed by correcting the common voltage according to the deviation of the length of the frame period.
実施形態１に係る表示装置の構成を示す図1 is a diagram illustrating a configuration of a display device according to a first embodiment. 表示装置における画素の回路構成を示す図FIG. 7 is a diagram illustrating a circuit configuration of a pixel in a display device. 表示装置における制御部の構成を示すブロック図The block diagram which shows the structure of the control part in a display apparatus 制御部におけるコモン電圧補正処理部の構成を示すブロック図Block diagram showing the configuration of the common voltage correction processing unit in the control unit 制御部の記録部における補正テーブルを例示する図The figure which illustrates the correction table in the recording part of a control part 可変のフレームレートによる課題を説明するための図Diagram for explaining the problem with variable frame rate 実施形態１の表示装置におけるコモン電圧補正処理を説明するためのフローチャート7 is a flowchart for explaining common voltage correction processing in the display device according to the first embodiment. 実施形態１の表示装置におけるコモン電圧補正処理を説明するためのタイミングチャートTiming chart for explaining common voltage correction processing in the display device of Embodiment 1
　以下、添付の図面を参照して本発明に係る表示装置の実施の形態を説明する。なお、以下の各実施形態において、同様の構成要素については同一の符号を付している。 Hereinafter, an embodiment of a display device according to the present invention will be described with reference to the accompanying drawings. In addition, in each following embodiment, the same code | symbol is attached | subjected about the same component.
（実施形態１）
１．構成
　実施形態１に係る表示装置の構成を以下に説明する。 (Embodiment 1)
1. Configuration The configuration of the display device according to the first embodiment will be described below.
　実施形態１に係る表示装置の構成について、図１を用いて説明する。図１は、本実施形態に係る表示装置１の構成を示す図である。 The configuration of the display device according to Embodiment 1 will be described with reference to FIG. FIG. 1 is a diagram illustrating a configuration of a display device 1 according to the present embodiment.
　本実施形態に係る表示装置１は、例えばＨＤＭＩ２．１規格（「ＨＤＭＩ」は登録商標）に準拠した液晶モニタなどの液晶表示装置を構成する。表示装置１は、図１に示すように、液晶パネル１０と、制御部２と、ゲート駆動部１１と、ソース駆動部１２と、コモン電圧源１３と、メモリ１０ａとを備える。 The display device 1 according to the present embodiment constitutes a liquid crystal display device such as a liquid crystal monitor conforming to the HDMI 2.1 standard (“HDMI” is a registered trademark), for example. As shown in FIG. 1, the display device 1 includes a liquid crystal panel 10, a control unit 2, a gate drive unit 11, a source drive unit 12, a common voltage source 13, and a memory 10a.
　液晶パネル１０は、例えば８Ｋ或いは４Ｋ、２Ｋなどの所定仕様を有し、アクティブマトリクス方式で構成される。液晶パネル１０は、図１に示すように、複数の画素３と、複数のゲート線ＧＬと、複数のソース線ＳＬとを備える。また、液晶パネル１０は、例えば、画素電極を有するＴＦＴ（薄膜トランジスタ）基板、共通電極を有するＣＦ（カラーフィルタ）基板、両基板間に封入された液晶層、及び偏光板などを含む。 The liquid crystal panel 10 has a predetermined specification such as 8K, 4K, or 2K, and is configured by an active matrix method. As shown in FIG. 1, the liquid crystal panel 10 includes a plurality of pixels 3, a plurality of gate lines GL, and a plurality of source lines SL. The liquid crystal panel 10 includes, for example, a TFT (thin film transistor) substrate having a pixel electrode, a CF (color filter) substrate having a common electrode, a liquid crystal layer sealed between the two substrates, a polarizing plate, and the like.
　液晶パネル１０において、複数の画素３は、マトリクス状に配置され、画像を表示する表示領域を形成する。以下、画素３のマトリクスの行方向（ｘ）を「水平方向」とし、列方向（ｙ）を「垂直方向」とする。 In the liquid crystal panel 10, the plurality of pixels 3 are arranged in a matrix and form a display area for displaying an image. Hereinafter, the row direction (x) of the matrix of the pixels 3 is referred to as “horizontal direction”, and the column direction (y) is referred to as “vertical direction”.
　複数の画素３は、それぞれアクティブ素子のＴＦＴ等を備える。各画素３のＴＦＴにおいては、ゲートがゲート線ＧＬに接続され、ソースがソース線ＳＬに接続される（図２参照）。ゲート線ＧＬは、画素３のマトリクスの行方向に配線され、１行ずつ画素３が接続された信号線である。ソース線ＳＬは、画素３のマトリクスの列方向に配線された信号線である。メモリ１０ａは、例えばフラッシュＲＯＭであり、液晶パネル１０の固有の情報等を格納する。 The plurality of pixels 3 each include an active element TFT or the like. In the TFT of each pixel 3, the gate is connected to the gate line GL, and the source is connected to the source line SL (see FIG. 2). The gate line GL is a signal line wired in the row direction of the matrix of the pixels 3 and connected to the pixels 3 one by one. The source line SL is a signal line wired in the column direction of the matrix of the pixels 3. The memory 10a is a flash ROM, for example, and stores information unique to the liquid crystal panel 10 and the like.
　制御部２は、例えばＬＳＩなどの一つ又は複数の半導体集積回路で構成される。制御部２は、タイミングコントローラとして、表示装置１の各部の動作タイミングを制御するための種々の信号を生成する。制御部２は、表示装置１の全体動作を制御してもよい。制御部２の構成の詳細については後述する。 The control unit 2 is composed of one or a plurality of semiconductor integrated circuits such as LSIs. As a timing controller, the control unit 2 generates various signals for controlling the operation timing of each unit of the display device 1. The control unit 2 may control the overall operation of the display device 1. Details of the configuration of the control unit 2 will be described later.
　ゲート駆動部１１は、制御部２の制御により、画素３のマトリクスにおいて各行のゲート線ＧＬを順番に選択するためのゲート信号を生成し、所定のフレーム周期で複数のゲート線ＧＬを駆動する。フレーム周期は、例えば１／１２０～１／３０秒の範囲内で、映像信号によって動的に設定される。ゲート駆動部１１は、例えば複数のゲート線ＧＬが接続されたＩＣ等の駆動回路で構成される。 The gate drive unit 11 generates a gate signal for sequentially selecting the gate lines GL of each row in the matrix of the pixels 3 under the control of the control unit 2, and drives the plurality of gate lines GL at a predetermined frame period. The frame period is dynamically set by the video signal, for example, within a range of 1/120 to 1/30 seconds. The gate drive unit 11 is configured by a drive circuit such as an IC to which a plurality of gate lines GL are connected, for example.
　ソース駆動部１２は、制御部２の制御により、ゲート駆動部１１の動作に同期して、複数のソース線ＳＬに、画素３毎に表示する階調に応じた電圧を有するソース信号を供給する。ソース駆動部１２は、例えば複数のソース線ＳＬが接続されたＩＣ等の駆動回路で構成される。本実施形態において、ソース駆動部１２は、フレーム毎にソース信号の電圧を正極性と負極性とに切り替えるフレーム反転方式で駆動する。 The source driver 12 supplies a source signal having a voltage corresponding to the gradation to be displayed for each pixel 3 to the plurality of source lines SL in synchronization with the operation of the gate driver 11 under the control of the controller 2. . The source driving unit 12 is configured by a driving circuit such as an IC to which a plurality of source lines SL are connected, for example. In the present embodiment, the source driver 12 drives by a frame inversion method that switches the voltage of the source signal between positive polarity and negative polarity for each frame.
　コモン電圧源１３は、液晶パネル１０中の画素３の共通電極にコモン電圧Ｖｃｏｍを供給する。コモン電圧Ｖｃｏｍは、ソース信号の正極性及び負極性の基準となる。コモン電圧Ｖｃｏｍは、例えば５．５～８．２Ｖの範囲内で設定される。コモン電圧源１３は、設定された電圧を発生させる電圧発生回路などを含む。本実施形態において、コモン電圧Ｖｃｏｍの設定値は、制御部２によって制御される。コモン電圧源１３は、本実施形態の表示装置１における電圧源の一例である。 The common voltage source 13 supplies a common voltage Vcom to the common electrode of the pixel 3 in the liquid crystal panel 10. The common voltage Vcom is a reference for the positive and negative polarities of the source signal. The common voltage Vcom is set, for example, within a range of 5.5 to 8.2V. The common voltage source 13 includes a voltage generation circuit that generates a set voltage. In the present embodiment, the set value of the common voltage Vcom is controlled by the control unit 2. The common voltage source 13 is an example of a voltage source in the display device 1 of the present embodiment.
１－１．画素の回路構成
　表示装置１の液晶パネル１０における画素３の回路構成について、図２を参照して説明する。図２は、表示装置１における画素３の回路構成を示す図である。 1-1. Circuit Configuration of Pixel A circuit configuration of the pixel 3 in the liquid crystal panel 10 of the display device 1 will be described with reference to FIG. FIG. 2 is a diagram illustrating a circuit configuration of the pixel 3 in the display device 1.
　図２では、画素３の等価回路（以下、「画素回路」３０という）を示している。画素回路３０は、図２に示すように、ＴＦＴ３１と、画素容量３２と、蓄積容量３３とを備える。 FIG. 2 shows an equivalent circuit of the pixel 3 (hereinafter referred to as “pixel circuit” 30). As shown in FIG. 2, the pixel circuit 30 includes a TFT 31, a pixel capacitor 32, and a storage capacitor 33.
　画素回路３０のＴＦＴ３１において、ゲートはゲート線ＧＬに接続され、ソースはソース線ＳＬに接続され、ドレインは画素容量３２及び蓄積容量３３のそれぞれの一端に接続される。画素容量３２及び蓄積容量３３のそれぞれの他端は、例えば液晶パネル１０における共通電極に接続される。共通電極には、コモン電圧源１３が接続され、コモン電圧Ｖｃｏｍが供給される。 In the TFT 31 of the pixel circuit 30, the gate is connected to the gate line GL, the source is connected to the source line SL, and the drain is connected to one end of each of the pixel capacitor 32 and the storage capacitor 33. The other ends of the pixel capacitor 32 and the storage capacitor 33 are connected to, for example, a common electrode in the liquid crystal panel 10. A common voltage source 13 is connected to the common electrode, and a common voltage Vcom is supplied.
　ＴＦＴ３１は、ゲート線ＧＬからのゲート信号に基づきゲートに印加される電圧が所定のしきい値電圧以上であるときにオンし、しきい値電圧未満であるときにオフする。ＴＦＴ３１は、ゲート線ＧＬに接続されたトランジスタの一例である。 The TFT 31 is turned on when the voltage applied to the gate based on the gate signal from the gate line GL is equal to or higher than a predetermined threshold voltage, and turned off when the voltage is lower than the threshold voltage. The TFT 31 is an example of a transistor connected to the gate line GL.
　画素容量３２は、液晶層及び画素電極で構成され、充電量に応じて液晶層の配向状態を変化させる。画素容量３２は、ＴＦＴ３１がオンの期間中にソース線ＳＬから入力されるソース信号Ｓｏｕｔの電圧に基づき電荷を充電又は放電する。画素容量３２は、ＴＦＴ３１がオフの期間中には、ＴＦＴ３１がオフに切り替わる前の充放電によって得られた充電量を保持する。 The pixel capacitor 32 includes a liquid crystal layer and a pixel electrode, and changes the alignment state of the liquid crystal layer according to the amount of charge. The pixel capacitor 32 charges or discharges charges based on the voltage of the source signal Sout input from the source line SL while the TFT 31 is on. The pixel capacitor 32 holds the charge amount obtained by charging / discharging before the TFT 31 is switched off during the period in which the TFT 31 is off.
　蓄積容量３３は、画素容量３２が保持する充電量（充電電圧）を保持するための容量素子である。蓄積容量３３は、画素容量３２による充放電と同じタイミングにおいて電荷を充放電する。 The storage capacitor 33 is a capacitive element for holding the charge amount (charge voltage) held by the pixel capacitor 32. The storage capacitor 33 charges and discharges charges at the same timing as the charge and discharge by the pixel capacitor 32.
１－２．制御部について
　制御部２の構成の詳細について、図３を参照して説明する。図３は、表示装置１における制御部２の構成を示すブロック図である。 1-2. About a control part The detail of a structure of the control part 2 is demonstrated with reference to FIG. FIG. 3 is a block diagram illustrating a configuration of the control unit 2 in the display device 1.
　制御部２は、図３に示すように、映像入力部２１と、ガンマ変換部２２と、ゲート駆動Ｉ／Ｆ（インタフェース）２３と、ソース駆動Ｉ／Ｆ２４と、メモリＩ／Ｆ２５と、記録部２６と、コモン電圧補正処理部４と、電圧源制御部２７とを備える。 As shown in FIG. 3, the control unit 2 includes a video input unit 21, a gamma conversion unit 22, a gate drive I / F (interface) 23, a source drive I / F 24, a memory I / F 25, and a recording unit. 26, a common voltage correction processing unit 4, and a voltage source control unit 27.
　映像入力部２１は、ＨＤＭＩ２．１規格などの所定の通信規格に従う入力インタフェース回路である。映像入力部２１は、外部からの映像信号を入力し、映像信号におけるフレーム毎の画像を示す画像データ、垂直同期信号Ｖｓｙｎｃ、水平同期信号Ｈｓｙｎｃ及びクロック信号Ｃｌｋを出力する。 The video input unit 21 is an input interface circuit that conforms to a predetermined communication standard such as the HDMI 2.1 standard. The video input unit 21 receives an external video signal and outputs image data indicating an image for each frame in the video signal, a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a clock signal Clk.
　垂直同期信号Ｖｓｙｎｃは、画像データのフレーム毎に各駆動部１１，１２等の動作を同期するタイミングを示す。水平同期信号Ｈｓｙｎｃは、フレーム中の１行毎の動作が同期して行われる水平同期期間１Ｈ毎の同期タイミングを示す。クロック信号Ｃｌｋは、画素３の基準の動作周期を示す。 The vertical synchronization signal Vsync indicates the timing at which the operations of the drive units 11 and 12 are synchronized for each frame of image data. The horizontal synchronization signal Hsync indicates a synchronization timing for each horizontal synchronization period 1H in which operations for each row in the frame are performed in synchronization. The clock signal Clk indicates a reference operation cycle of the pixel 3.
　ガンマ変換部２２は、映像入力部２１から画像データを入力して、ガンマ補正を施すガンマ変換処理を実行する。ガンマ変換部２２は、例えばガンマ補正のデジタル値が格納されたＬＵＴ（ルックアップテーブル）等を含む。ガンマ変換部２２は、例えば変換後の画像データＤ（Ｎ）をソース駆動Ｉ／Ｆ２４に出力する。Ｎは、フレーム番号を示す。画像データＤ（Ｎ）には、ガンマ変換処理に限らず、例えばディザ処理など各種の変換処理が施されてもよい。 The gamma conversion unit 22 inputs image data from the video input unit 21 and executes gamma conversion processing for performing gamma correction. The gamma conversion unit 22 includes, for example, an LUT (Look Up Table) in which digital values for gamma correction are stored. For example, the gamma conversion unit 22 outputs the converted image data D (N) to the source drive I / F 24. N indicates a frame number. The image data D (N) is not limited to gamma conversion processing but may be subjected to various conversion processing such as dither processing.
　ゲート駆動Ｉ／Ｆ２３は、ゲート駆動部１１に接続するインタフェース回路である。ゲート駆動Ｉ／Ｆ２３は、映像入力部２１から垂直同期信号Ｖｓｙｎｃ、水平同期信号Ｈｓｙｎｃ及びクロック信号Ｃｌｋを入力し、各種同期信号を含む制御信号をゲート駆動部１１に出力する。 The gate drive I / F 23 is an interface circuit connected to the gate drive unit 11. The gate drive I / F 23 receives the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, and the clock signal Clk from the video input unit 21 and outputs a control signal including various synchronization signals to the gate drive unit 11.
　ソース駆動Ｉ／Ｆ２４は、ソース駆動部１２に接続するインタフェース回路である。ソース駆動Ｉ／Ｆ２４は、ガンマ変換等の変換後の画像データＤ（Ｎ）を入力し、画像データＤ（Ｎ）が示す画像を表示するための制御信号をソース駆動部１２に出力する。ソース駆動Ｉ／Ｆ２４は、映像入力部２１から各種同期信号を入力して、ソース駆動部１２の制御信号を生成してもよい。ソース駆動Ｉ／Ｆ２４は、例えば、フレーム反転方式におけるソース信号の電圧の極性を示す極性情報Ｐ（Ｎ）を設定する。 The source drive I / F 24 is an interface circuit connected to the source drive unit 12. The source drive I / F 24 receives the image data D (N) after conversion such as gamma conversion, and outputs a control signal for displaying an image indicated by the image data D (N) to the source drive unit 12. The source drive I / F 24 may generate various control signals from the video input unit 21 and generate a control signal for the source drive unit 12. For example, the source drive I / F 24 sets polarity information P (N) indicating the polarity of the voltage of the source signal in the frame inversion method.
　メモリＩ／Ｆ２５は、外部のメモリからデータを読み出すインタフェース回路であり、例えば液晶パネル１０のメモリ１０ａに接続される。例えば、メモリＩ／Ｆ２５は、液晶パネル１０におけるコモン電圧Ｖｃｏｍに関する情報等を取得する。 The memory I / F 25 is an interface circuit that reads data from an external memory, and is connected to the memory 10a of the liquid crystal panel 10, for example. For example, the memory I / F 25 acquires information on the common voltage Vcom in the liquid crystal panel 10 and the like.
　記録部２６は、メモリＩ／Ｆ２５から取得された情報を格納する。記録部２６は、レジスタ回路で構成される。記録部２６は、例えばコモン電圧Ｖｃｏｍの標準値Ｖ０、及び後述する補正テーブル２６ａ（図５参照）などを格納する。 The recording unit 26 stores information acquired from the memory I / F 25. The recording unit 26 includes a register circuit. The recording unit 26 stores, for example, a standard value V0 of the common voltage Vcom, a correction table 26a (see FIG. 5) described later, and the like.
　コモン電圧補正処理部４は、本実施形態の表示装置１においてコモン電圧Ｖｃｏｍを補正するためのコモン電圧補正処理を実行する。当該処理において、コモン電圧補正処理部４は、映像入力部２１から各種同期信号Ｖｓｙｎｃ，Ｈｓｙｎｃ，Ｃｌｋを入力し、ガンマ変換部２２から画像データＤ（Ｎ）を入力し、ソース駆動Ｉ／Ｆ２４から極性情報Ｐ（Ｎ）を取得し、記録部２６に格納された情報を読み出す。コモン電圧補正処理部４の詳細については後述する。 The common voltage correction processing unit 4 executes a common voltage correction process for correcting the common voltage Vcom in the display device 1 of the present embodiment. In this processing, the common voltage correction processing unit 4 receives various synchronization signals Vsync, Hsync, and Clk from the video input unit 21, receives image data D (N) from the gamma conversion unit 22, and receives from the source driving I / F 24. The polarity information P (N) is acquired, and the information stored in the recording unit 26 is read out. Details of the common voltage correction processing unit 4 will be described later.
　電圧源制御部２７は、外部デバイスの制御回路で構成され、コモン電圧源１３に接続する。電圧源制御部２７は、コモン電圧補正処理部４の処理結果に基づいて、コモン電圧Ｖｃｏｍを設定する制御信号をコモン電圧源１３に出力する。 The voltage source control unit 27 is configured by an external device control circuit and is connected to the common voltage source 13. The voltage source control unit 27 outputs a control signal for setting the common voltage Vcom to the common voltage source 13 based on the processing result of the common voltage correction processing unit 4.
　制御部２は、上記のガンマ変換部２２及びコモン電圧補正処理部４等の所定の機能を実現するように設計された専用の電子回路や再構成可能な電子回路などのハードウェア回路であってもよい。また、制御部２は、上記のような各種機能をソフトウェアと協働して実現するＣＰＵ等を含んでもよい。制御部２は、ＣＰＵ、ＭＰＵ、マイコン、ＤＳＰ、ＦＰＧＡ、ＡＳＩＣ等の種々の半導体集積回路で構成されてもよい。 The control unit 2 is a hardware circuit such as a dedicated electronic circuit or a reconfigurable electronic circuit designed to realize predetermined functions such as the gamma conversion unit 22 and the common voltage correction processing unit 4 described above. Also good. In addition, the control unit 2 may include a CPU or the like that realizes various functions as described above in cooperation with software. The control unit 2 may be configured by various semiconductor integrated circuits such as a CPU, MPU, microcomputer, DSP, FPGA, ASIC and the like.
１－２－１．コモン電圧補正処理部について
　制御部２におけるコモン電圧補正処理部４の詳細について、図４を用いて説明する。 1-2-1. About Common Voltage Correction Processing Unit Details of the common voltage correction processing unit 4 in the control unit 2 will be described with reference to FIG.
　図４は、コモン電圧補正処理部４の構成を示すブロック図である。コモン電圧補正処理部４は、例えば制御部２の機能的構成として、フレーム長検出部４１と、画素平均計算部４２と、累積管理部４３と、コモン電圧設定部４４とを備える。 FIG. 4 is a block diagram showing the configuration of the common voltage correction processing unit 4. The common voltage correction processing unit 4 includes a frame length detection unit 41, a pixel average calculation unit 42, an accumulation management unit 43, and a common voltage setting unit 44, for example, as a functional configuration of the control unit 2.
　フレーム長検出部４１は、各種同期信号Ｖｓｙｎｃ，Ｈｓｙｎｃ，Ｃｌｋに基づいて、フレーム長Ｔ（Ｎ）を検出する。フレーム長は、１フレーム中のブランキング期間を含むフレーム期間の長さである。フレーム長検出部４１は、例えば２フレーム分のフレーム長を計数可能なカウンタ等を含む。 The frame length detection unit 41 detects the frame length T (N) based on various synchronization signals Vsync, Hsync, and Clk. The frame length is a length of a frame period including a blanking period in one frame. The frame length detection unit 41 includes, for example, a counter that can count the frame length of two frames.
　画素平均計算部４２は、画像データＤ（Ｎ）に基づいて、画素平均値Ｇ（Ｎ）を算出する。画素平均値Ｇ（Ｎ）は、１フレームの画像中の各画素の階調の平均値を示す。画素平均計算部４２は、８ビット等の所定範囲において画素平均値Ｇ（Ｎ）を出力する。 The pixel average calculation unit 42 calculates a pixel average value G (N) based on the image data D (N). The pixel average value G (N) indicates the average value of the gradation of each pixel in one frame image. The pixel average calculation unit 42 outputs the pixel average value G (N) in a predetermined range such as 8 bits.
　累積管理部４３は、フレーム毎にフレーム長Ｔ（Ｎ）と画素平均値Ｇ（Ｎ）と極性情報Ｐ（Ｎ）を取得し、累積値Ａ（Ｎ）を逐次、計算して記憶する。累積値Ａ（Ｎ）は、過去に画像の表示が行われた期間において、互いに異なる極性のフレーム期間の間の偏りを示し、フレーム毎に管理される。 The accumulation management unit 43 acquires the frame length T (N), the pixel average value G (N), and the polarity information P (N) for each frame, and sequentially calculates and stores the accumulation value A (N). The accumulated value A (N) indicates a deviation between frame periods having different polarities in a period in which an image is displayed in the past, and is managed for each frame.
　コモン電圧設定部４４は、現在の累積値Ａ（Ｎ）に基づいて、次のフレームのコモン電圧Ｖｃｏｍの設定値Ｖｃｏｍ（Ｎ＋１）を電圧源制御部２７に設定する。また、コモン電圧設定部４４は、現在の累積値Ａ（Ｎ）に関するフィードバック値Ｆ（Ｎ）を累積管理部４３に出力する。コモン電圧設定部４４は、設定値Ｖｃｏｍ（Ｎ＋１）及びフィードバック値Ｆ（Ｎ）の算出に、補正テーブル２６ａ及び標準値Ｖ０等の各種情報を用いる。コモン電圧設定部４４は、極性情報Ｐ（Ｎ）を用いてもよい。 The common voltage setting unit 44 sets the set value Vcom (N + 1) of the common voltage Vcom of the next frame in the voltage source control unit 27 based on the current accumulated value A (N). Further, the common voltage setting unit 44 outputs the feedback value F (N) regarding the current cumulative value A (N) to the cumulative management unit 43. The common voltage setting unit 44 uses various information such as the correction table 26a and the standard value V0 for calculation of the set value Vcom (N + 1) and the feedback value F (N). The common voltage setting unit 44 may use polarity information P (N).
１－２－２．補正テーブルについて
　制御部２の記録部２６に格納される補正テーブル２６ａについて、図５を用いて説明する。 1-2-2. Correction Table The correction table 26a stored in the recording unit 26 of the control unit 2 will be described with reference to FIG.
　図５は、記録部２６における補正テーブル２６ａを例示する図である。補正テーブル２６ａは、制御部２において、コモン電圧補正処理部４のコモン電圧設定部４４に参照されるデータテーブルである。補正テーブル２６ａは、例えばＬＵＴで構成される。 FIG. 5 is a diagram illustrating a correction table 26 a in the recording unit 26. The correction table 26 a is a data table that is referred to by the common voltage setting unit 44 of the common voltage correction processing unit 4 in the control unit 2. The correction table 26a is configured by an LUT, for example.
　図５では、最大のフレーム長が水平同期期間１Ｈの４５００倍であり（３０Ｈｚ相当）、画素平均値が８ビットを有する場合の補正テーブル２６ａを例示している。図５に例示する補正テーブル２６ａは、累積値Ａ（Ｎ）の範囲と、コモン電圧Ｖｃｏｍの補正値ΔＶと、フィードバック値Ｆ（Ｎ）に対応するフィードバック係数Ｃｆとを関連付けて記録する。 FIG. 5 illustrates the correction table 26a when the maximum frame length is 4500 times the horizontal synchronization period 1H (corresponding to 30 Hz) and the pixel average value has 8 bits. The correction table 26a illustrated in FIG. 5 records the range of the accumulated value A (N), the correction value ΔV of the common voltage Vcom, and the feedback coefficient Cf corresponding to the feedback value F (N) in association with each other.
　例えば、図５の補正テーブル２６ａは、－１Ｍ（メガ）以上で且つ１Ｍ未満の累積値Ａ（Ｎ）に、補正値ΔＶ＝０と、フィードバック係数Ｃｆ＝０とを関連付けている。また、１Ｍ以上の累積値Ａ（Ｎ）には「０」よりも大きい補正値ΔＶ及びフィードバック係数Ｃｆが関連付けられ、－１Ｍ未満の累積値Ａ（Ｎ）には「０」よりも小さい補正値ΔＶ及びフィードバック係数Ｃｆが関連付けられている。補正値ΔＶ及びフィードバック係数Ｃｆの値は、表示装置１の仕様等に応じて適宜、設定可能である。 For example, the correction table 26a in FIG. 5 associates a correction value ΔV = 0 and a feedback coefficient Cf = 0 with a cumulative value A (N) that is greater than or equal to −1M (mega) and less than 1M. Further, a correction value ΔV greater than “0” and a feedback coefficient Cf are associated with an accumulated value A (N) of 1M or more, and a correction value smaller than “0” is associated with an accumulated value A (N) of less than −1M. ΔV and feedback coefficient Cf are associated with each other. The values of the correction value ΔV and the feedback coefficient Cf can be set as appropriate according to the specifications of the display device 1 and the like.
２．動作
　以上のように構成される表示装置１の動作について、以下説明する。 2. Operation The operation of the display device 1 configured as described above will be described below.
　本実施形態に係る表示装置１には、例えば外部のＧＰＵ等において生成される映像信号が入力される。例えば映像信号におけるフレーム期間の長さは、各フレームのブランキング期間を調整することによってフレーム毎に設定される。 For example, a video signal generated in an external GPU or the like is input to the display device 1 according to the present embodiment. For example, the length of the frame period in the video signal is set for each frame by adjusting the blanking period of each frame.
　表示装置１の制御部２は、入力された映像信号に基づいて、ゲート駆動部１１とソース駆動部１２とを同期制御するように各々の制御信号を生成する。ソース駆動部１２は、フレーム反転方式においてソース信号を順次、極性を反転させながら出力する。これにより、映像信号に応じたフレーム毎の表示画像が液晶パネル１０に表示される。 The control unit 2 of the display device 1 generates each control signal so as to synchronously control the gate driving unit 11 and the source driving unit 12 based on the input video signal. The source driver 12 sequentially outputs source signals while inverting the polarity in the frame inversion method. As a result, a display image for each frame corresponding to the video signal is displayed on the liquid crystal panel 10.
２－１．可変のフレームレートによる課題について
　本実施形態では、以上のように表示装置１に入力される映像信号のフレームレートが、ＧＰＵ等の制御により動的に変化することを想定している。この場合、下記のように表示画像のフリッカの課題が想定されることから、本実施形態の表示装置１は、本課題を解決するためにコモン電圧Ｖｃｏｍを制御する。フレームレートの変化による課題について、図６を用いて説明する。 2-1. Regarding Problems with Variable Frame Rate In the present embodiment, it is assumed that the frame rate of the video signal input to the display device 1 dynamically changes by controlling the GPU or the like as described above. In this case, since the problem of flicker of the display image is assumed as described below, the display device 1 of the present embodiment controls the common voltage Vcom in order to solve this problem. A problem caused by a change in the frame rate will be described with reference to FIG.
　図６は、可変のフレームレートによる課題を説明するための図である。図６（ａ）は、一定のフレームレートのソース信号を例示するタイミングチャートである。図６（ｂ）は、フレームレートが変化するソース信号の一例を示すタイミングチャートである。図６（ｃ）は、図６（ｂ）の動作時におけるコモン電圧Ｖｃｏｍの補正を例示するタイミングチャートである。 FIG. 6 is a diagram for explaining a problem due to a variable frame rate. FIG. 6A is a timing chart illustrating a source signal having a constant frame rate. FIG. 6B is a timing chart showing an example of a source signal whose frame rate changes. FIG. 6C is a timing chart illustrating the correction of the common voltage Vcom during the operation of FIG.
　図６（ａ）～（ｃ）は、フレーム反転方式におけるソース信号の電圧を例示している。フレーム反転方式は、液晶の長寿命化等のために、連続するフレーム間でソース信号の電圧の極性を反転させる。図６（ａ）～（ｃ）では、所定階調の画像（画像全体が白色など）が表示される場合のソース信号を例示している。当該ソース信号は、隣接するフレーム間において交互に、コモン電圧Ｖｃｏｍよりも高い正電圧ＶＨと、コモン電圧Ｖｃｏｍよりも低い負電圧ＶＬとを有する。 FIGS. 6A to 6C illustrate the voltage of the source signal in the frame inversion method. The frame inversion method inverts the polarity of the voltage of the source signal between successive frames in order to extend the life of the liquid crystal. FIGS. 6A to 6C illustrate source signals when an image with a predetermined gradation (the entire image is white or the like) is displayed. The source signal alternately has a positive voltage VH higher than the common voltage Vcom and a negative voltage VL lower than the common voltage Vcom between adjacent frames.
　図６（ａ）では、通常のフレーム反転方式として、フレームレートが一定の場合を例示している。例えば６０Ｈｚにおいて１６．７ミリ秒など、常に同じ期間の経過毎にソース信号の極性が変化する。このように、正極性のフレーム期間Ｔ１と負極性のフレーム期間Ｔ２とが均等である場合、液晶の焼き付き等は生じにくい。例えば所定階調の画像が、正電圧ＶＨと負電圧ＶＬとの間で一定の輝度として、特にフリッカを生じずに表示可能である。 FIG. 6A illustrates a case where the frame rate is constant as a normal frame inversion method. For example, the polarity of the source signal changes every time the same period elapses, such as 16.7 milliseconds at 60 Hz. Thus, when the positive frame period T1 and the negative frame period T2 are equal, liquid crystal burn-in or the like hardly occurs. For example, an image having a predetermined gradation can be displayed as a constant luminance between the positive voltage VH and the negative voltage VL without causing any flicker.
　一方、例えばＨＤＭＩ２．１規格のように、映像信号におけるフレームレートが動的に変化する場合、フレームレートの変化に起因して液晶の焼き付き及びフリッカが生じることが想定される。図６（ｂ）に、不均一なフレームレートに依るフリッカ等が想定される一例を示す。 On the other hand, when the frame rate in the video signal changes dynamically as in the HDMI 2.1 standard, for example, it is assumed that liquid crystal burn-in and flicker occur due to the change in the frame rate. FIG. 6B shows an example in which flicker or the like due to a non-uniform frame rate is assumed.
　図６（ｂ）は、図６（ａ）と同様の画像が、フレームレートを変化させながら表示される場合のソース信号を例示している。図６（ｂ）では、フレーム毎にフレームレートが変化することで、負極性のフレーム期間Ｔ１１の後の正極性のフレーム期間Ｔ２１が、負極性のフレーム期間Ｔ１１よりも長くなっている。さらに、次の負極性のフレーム期間Ｔ１２の後の正極性のフレーム期間Ｔ２２も、負極性のフレーム期間Ｔ１２よりも長くなっている。 FIG. 6B illustrates a source signal when the same image as that in FIG. 6A is displayed while changing the frame rate. In FIG. 6B, the frame rate is changed for each frame, so that the positive frame period T21 after the negative frame period T11 is longer than the negative frame period T11. Further, the positive frame period T22 after the next negative frame period T12 is also longer than the negative frame period T12.
　上記のように長いフレーム期間Ｔ２１，Ｔ２２が正極性に偏ると、実効的に正極性のＤＣ成分が、液晶パネル１０の液晶層中の不純物等に電気的に残り、液晶の焼き付きが生じることが想定される。この場合、負電圧ＶＬに対する液晶の反応が鈍くなり、負極性のフレーム期間Ｔ１１，Ｔ１２中の負電圧ＶＬによる輝度と正極性のフレーム期間Ｔ２１，Ｔ２２中の正電圧ＶＨ間による輝度との間の輝度差、即ちフリッカが発生してしまう。 When the long frame periods T21 and T22 are biased to the positive polarity as described above, the positive DC component is effectively electrically left in the impurities and the like in the liquid crystal layer of the liquid crystal panel 10, and liquid crystal burn-in occurs. is assumed. In this case, the response of the liquid crystal to the negative voltage VL becomes dull, and between the luminance due to the negative voltage VL during the negative frame periods T11 and T12 and the luminance due to the positive voltage VH during the positive frame periods T21 and T22. A luminance difference, that is, flicker occurs.
　そこで、本実施形態の表示装置１は、入力される映像信号から各極性のフレーム期間Ｔ１１～Ｔ２２の長さを検出し、正極性のフレーム期間Ｔ２１，Ｔ２２と負極性のフレーム期間Ｔ１１，Ｔ１２との間の偏りに応じてコモン電圧Ｖｃｏｍを補正する。図６（ｃ）に、コモン電圧Ｖｃｏｍの補正方法の一例を示す。 Therefore, the display device 1 of the present embodiment detects the lengths of the frame periods T11 to T22 of each polarity from the input video signal, and has positive frame periods T21 and T22 and negative frame periods T11 and T12. The common voltage Vcom is corrected according to the bias between the two. FIG. 6C shows an example of a method for correcting the common voltage Vcom.
　図６（ｃ）は、図６（ｂ）のソース信号に対してコモン電圧Ｖｃｏｍを補正した場合を例示している。本実施形態の表示装置１は、図６（ｃ）の例のように、正極性のフレーム期間Ｔ２１，Ｔ２２が負極性のフレーム期間Ｔ１１，Ｔ１２よりも長い偏りを検知すると、コモン電圧Ｖｃｏｍを増大させる補正を行う。これにより、液晶パネル１０に残存する実効的なＤＣ成分を相殺して液晶の焼き付きを抑制し、フリッカを低減することができる。以下、本実施形態に係る表示装置１の動作の詳細について説明する。 FIG. 6C illustrates a case where the common voltage Vcom is corrected with respect to the source signal of FIG. The display device 1 of the present embodiment increases the common voltage Vcom when the positive frame periods T21 and T22 are detected to be longer than the negative frame periods T11 and T12, as in the example of FIG. 6C. To correct. As a result, the effective DC component remaining in the liquid crystal panel 10 can be offset to suppress liquid crystal burn-in, and flicker can be reduced. Hereinafter, details of the operation of the display device 1 according to the present embodiment will be described.
２－２．コモン電圧補正処理
　本実施形態に係る表示装置１におけるコモン電圧補正処理について、以下説明する。本実施形態のコモン電圧補正処理は、フレームレートが変化し得る画像の表示に同期して、正極性のフレーム期間と負極性のフレーム期間との間の偏りの累計を示す累積値Ａ（Ｎ）を管理することにより、コモン電圧Ｖｃｏｍを動的に補正する。コモン電圧補正処理の詳細について、図７，８を用いて説明する。 2-2. Common Voltage Correction Process The common voltage correction process in the display device 1 according to the present embodiment will be described below. The common voltage correction processing according to the present embodiment is a cumulative value A (N) indicating a cumulative total of deviations between a positive frame period and a negative frame period in synchronization with display of an image whose frame rate can change. By managing this, the common voltage Vcom is dynamically corrected. Details of the common voltage correction processing will be described with reference to FIGS.
　図７は、本実施形態の表示装置１におけるコモン電圧補正処理を説明するためのフローチャートである。図８は、コモン電圧補正処理を説明するためのタイミングチャートである。 FIG. 7 is a flowchart for explaining the common voltage correction processing in the display device 1 of the present embodiment. FIG. 8 is a timing chart for explaining the common voltage correction processing.
　図７に示すフローチャートの各処理は、表示装置１の制御部２によって実行される。制御部２は、外部からの映像信号に基づく画像表示の１フレームを制御周期として本フローチャートを実行する。図８（ａ），（ｂ）は、それぞれ外部からの垂直同期信号Ｖｓｙｎｃ及び画像データＤ（Ｎ）の入力タイミングを示す。図８（ｃ）は、表示装置１における累積値Ａ（Ｎ）の計算タイミングを示す。図８（ｄ）は、コモン電圧Ｖｃｏｍの補正タイミングを示す。 7 is executed by the control unit 2 of the display device 1. The control unit 2 executes this flowchart using one frame of image display based on an external video signal as a control cycle. FIGS. 8A and 8B show the input timing of the vertical synchronization signal Vsync and the image data D (N) from the outside, respectively. FIG. 8C shows the calculation timing of the accumulated value A (N) in the display device 1. FIG. 8D shows the correction timing of the common voltage Vcom.
　図７のフローチャートにおいて、制御部２は、コモン電圧補正処理部４（図４）のフレーム長検出部４１として機能し、現在のフレーム期間の長さ即ちフレーム長を検出する（Ｓ１）。フレーム長検出部４１は、垂直同期信号Ｖｓｙｎｃ、水平同期信号Ｈｓｙｎｃ及びクロック信号Ｃｌｋを入力してステップＳ１の処理を行う。 7, the control unit 2 functions as the frame length detection unit 41 of the common voltage correction processing unit 4 (FIG. 4), and detects the length of the current frame period, that is, the frame length (S1). The frame length detector 41 receives the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, and the clock signal Clk, and performs the process of step S1.
　図８（ａ）に、ステップＳ１の処理対象の垂直同期信号Ｖｓｙｎｃを例示する。例えば、フレーム長検出部４１は、垂直同期信号Ｖｓｙｎｃが（Ｎ－１）フレーム目の開始を示す時刻ｔ１からＮフレーム目の開始を示す時刻ｔ２までの期間を水平同期期間１Ｈ単位で計数する。これにより、（Ｎ－１）フレーム目のフレーム長Ｔ（Ｎ－１）が検出される。 FIG. 8A illustrates the vertical synchronization signal Vsync to be processed in step S1. For example, the frame length detection unit 41 counts the period from the time t1 when the vertical synchronization signal Vsync indicates the start of the (N−1) th frame to the time t2 when the start of the Nth frame indicates the horizontal synchronization period 1H. As a result, the frame length T (N−1) of the (N−1) th frame is detected.
　図７に戻り、制御部２は、画素平均計算部４２として（Ｎ－１）フレーム目の画像データＤ（Ｎ－１）に基づく画素平均値Ｇ（Ｎ－１）を算出する（Ｓ２）。画素平均計算部４２は、例えば図８（ｂ）に示すように、時刻ｔ１後の時刻ｔ１１から順次、画像データＤ（Ｎ－１）として入力される各画素の階調値を合算していき、合算値を画素数で除算することで画素平均値Ｇ（Ｎ－１）を算出する。 Referring back to FIG. 7, the control unit 2 calculates the pixel average value G (N−1) based on the image data D (N−1) of the (N−1) th frame as the pixel average calculation unit 42 (S2). For example, as shown in FIG. 8B, the pixel average calculation unit 42 sequentially adds the gradation values of the respective pixels input as the image data D (N−1) from time t11 after time t1. Then, the pixel average value G (N−1) is calculated by dividing the total value by the number of pixels.
　また、制御部２は、累積管理部４３として機能し、ソース駆動Ｉ／Ｆ２４から（Ｎ－１）フレーム目の極性情報Ｐ（Ｎ－１）を取得する（Ｓ３）。極性情報Ｐ（Ｎ－１）は、（Ｎ－１）フレーム目のソース信号が正極性であるか負極性であるかを示す。ステップＳ１～Ｓ３の処理の順序は特に限定されず、例えば各処理が並列的に実行されてもよい。 Further, the control unit 2 functions as the accumulation management unit 43, and acquires the polarity information P (N-1) of the (N-1) th frame from the source drive I / F 24 (S3). The polarity information P (N-1) indicates whether the source signal of the (N-1) th frame is positive or negative. The order of the processes in steps S1 to S3 is not particularly limited, and for example, each process may be executed in parallel.
　次に、累積管理部４３としての制御部２は、（Ｎ－２）フレーム目までの過去の累積値Ａ（Ｎ－２）から、現在（（Ｎ－１）フレーム目）の累積値Ａ（Ｎ－１）への更新を行う（Ｓ４）。ステップＳ４の処理は、現在のフレーム長Ｔ（Ｎ－１）、画素平均値Ｇ（Ｎ－１）及び極性情報Ｐ（Ｎ－１）、並びに後述するフィードバック値Ｆ（Ｎ－２）に基づき、次式（１）の演算によって行われる。 Next, the control unit 2 as the accumulation management unit 43 calculates the accumulated value A ((N−1) th frame) from the past accumulated value A (N−2) up to the (N−2) th frame. Update to (N-1) is performed (S4). The process of step S4 is based on the current frame length T (N-1), pixel average value G (N-1) and polarity information P (N-1), and a feedback value F (N-2) described later. The calculation is performed by the following equation (1).
Ａ（Ｎ－１）＝Ａ（Ｎ－２）＋Ｂ（Ｎ－１）－Ｆ（Ｎ－２）　　　　　…（１）
　上式（１）のように、累積管理部４３は、過去の累積値Ａ（Ｎ－２）に、現在の加算値Ｂ（Ｎ－１）を加算し、更に前回のフィードバック値Ｆ（Ｎ－２）を減算して、更新後の累積値Ａ（Ｎ－１）を算出する。加算値Ｂ（Ｎ－１）は、例えば（Ｎ－１）フレーム目の画像表示によって液晶パネル１０に生じることが推定されるＤＣ成分の量を示す。本実施形態において、加算値Ｂ（Ｎ－１）は、次式（２）のように表される。 A (N-1) = A (N-2) + B (N-1) -F (N-2) (1)
As shown in the above equation (1), the accumulation management unit 43 adds the current addition value B (N−1) to the past accumulation value A (N−2), and further the previous feedback value F (N−). 2) is subtracted to calculate the updated accumulated value A (N−1). The added value B (N−1) indicates the amount of the DC component that is estimated to be generated in the liquid crystal panel 10 by, for example, the (N−1) th frame image display. In the present embodiment, the addition value B (N−1) is expressed as the following equation (2).
Ｂ（Ｎ－１）＝±Ｇ（Ｎ－１）×Ｔ（Ｎ－１）　　　　　　　　　　　…（２）
　上式（２）において、右辺の符号は、（Ｎ－１）フレーム目の極性情報Ｐ（Ｎ－１）が正極性を示す場合には「＋」であり、負極性を示す場合には「－」である。上式（２）の加算値Ｂ（Ｎ－１）は、（Ｎ－１）フレーム目の極性と同じ正負においてフレーム長Ｔ（Ｎ－１）に比例しており、画素平均値Ｇ（Ｎ－１）で重み付けされている。 B (N−1) = ± G (N−1) × T (N−1) (2)
In the above equation (2), the sign on the right side is “+” when the polarity information P (N−1) of the (N−1) th frame indicates positive polarity, and “+” when the polarity information P (N−1) indicates negative polarity. -". The added value B (N−1) of the above equation (2) is proportional to the frame length T (N−1) in the same positive / negative polarity as the polarity of the (N−1) th frame, and the pixel average value G (N− Weighted in 1).
　次に、制御部２は、コモン電圧設定部４４として機能し、更新後の累積値Ａ（Ｎ－１）に応じて、Ｎフレーム目のコモン電圧Ｖｃｏｍを設定する（Ｓ５）。コモン電圧設定部４４は、記録部２６の補正テーブル２６ａ（図５）において、更新後の累積値Ａ（Ｎ－１）を含む範囲に関連付けされた補正値ΔＶを読み出すことにより、次式（３）に用いる補正値ΔＶ［Ａ（Ｎ－１）］を決定する。 Next, the control unit 2 functions as the common voltage setting unit 44, and sets the common voltage Vcom of the Nth frame according to the updated accumulated value A (N-1) (S5). The common voltage setting unit 44 reads the correction value ΔV associated with the range including the updated cumulative value A (N−1) in the correction table 26a (FIG. 5) of the recording unit 26, thereby obtaining the following equation (3 ) Is used to determine the correction value ΔV [A (N−1)].
Ｖｃｏｍ（Ｎ）＝Ｖ０＋ΔＶ［Ａ（Ｎ－１）］　　　　　　　　　　　…（３）
　コモン電圧設定部４４は、上式（３）のようにコモン電圧Ｖｃｏｍの標準値Ｖ０から補正値ΔＶ［Ａ（Ｎ－１）］の分を補正して、Ｎフレーム目のコモン電圧Ｖｃｏｍの設定値Ｖｃｏｍ（Ｎ）を算出する。コモン電圧設定部４４は、算出した設定値Ｖｃｏｍ（Ｎ）を電圧源制御部２７に設定する。 Vcom (N) = V0 + ΔV [A (N-1)] (3)
The common voltage setting unit 44 corrects the correction value ΔV [A (N−1)] from the standard value V0 of the common voltage Vcom as shown in the above equation (3), and sets the common voltage Vcom for the Nth frame. The value Vcom (N) is calculated. The common voltage setting unit 44 sets the calculated setting value Vcom (N) in the voltage source control unit 27.
　また、コモン電圧設定部４４としての制御部２は、Ｎフレーム目のコモン電圧Ｖｃｏｍの補正値ΔＶ［Ａ（Ｎ－１）］に対応するフィードバック係数Ｃｆ［Ａ（Ｎ－１）］を決定して、フィードバック値Ｆ（Ｎ－１）を算出する（Ｓ６）。制御部２は、補正テーブル２６ａにおいて、Ｎフレーム目のコモン電圧Ｖｃｏｍの補正値ΔＶ［Ａ（Ｎ－１）］と同じ蓄積値Ａ（Ｎ－１）に基づくフィードバック係数Ｃｆを読み出して、例えば次式（４）の演算を行う。 The control unit 2 as the common voltage setting unit 44 determines a feedback coefficient Cf [A (N−1)] corresponding to the correction value ΔV [A (N−1)] of the common voltage Vcom of the Nth frame. The feedback value F (N−1) is calculated (S6). The control unit 2 reads the feedback coefficient Cf based on the same accumulated value A (N−1) as the correction value ΔV [A (N−1)] of the common voltage Vcom of the Nth frame in the correction table 26a. The calculation of Expression (4) is performed.
Ｆ（Ｎ－１）＝Ｃｆ［Ａ（Ｎ－１）］×Ｇ（Ｎ－１）×Ｔ（Ｎ－１）　…（４）
　上式（４）のように、ステップＳ１で検出されたフレーム長Ｔ（Ｎ－１）を、ステップＳ２で算出された画素平均値Ｇ（Ｎ－１）とフィードバック係数Ｃｆ［Ａ（Ｎ－１）］とで重み付けすることにより、フィードバック値Ｆ（Ｎ－１）が算出される（Ｓ６）。コモン電圧設定部４４は、算出したフィードバック値Ｆ（Ｎ－１）を、次の制御周期（フレーム）におけるステップＳ４で用いられるように、累積管理部４３に出力する。 F (N−1) = Cf [A (N−1)] × G (N−1) × T (N−1) (4)
As shown in the above equation (4), the frame length T (N−1) detected in step S1 is set to the pixel average value G (N−1) calculated in step S2 and the feedback coefficient Cf [A (N−1). ] Is weighted to calculate the feedback value F (N-1) (S6). The common voltage setting unit 44 outputs the calculated feedback value F (N−1) to the accumulation management unit 43 so as to be used in step S4 in the next control cycle (frame).
　また、制御部２は、電圧源制御部２７として設定値Ｖｃｏｍ（Ｎ）に従ってコモン電圧源１３を制御し、Ｎフレーム目の画像表示を行う（Ｓ７）。電圧源制御部２７は、例えば図８（ｄ）に示すように、Ｎフレーム目の画像表示の開始前の時刻ｔ２０にコモン電圧Ｖｃｏｍを設定値Ｖｃｏｍ（Ｎ）に制御する。 Further, the control unit 2 controls the common voltage source 13 in accordance with the set value Vcom (N) as the voltage source control unit 27, and displays an image of the Nth frame (S7). For example, as illustrated in FIG. 8D, the voltage source control unit 27 controls the common voltage Vcom to the set value Vcom (N) at time t20 before the start of image display of the Nth frame.
　制御部２は、例えば図８（ｄ）に示すように、時刻ｔ２０後の時刻ｔ２１から、コモン電圧Ｖｃｏｍ＝Ｖｃｏｍ（Ｎ）の状態でＮフレーム目の画像データＤ（Ｎ）が示す画像を液晶パネル１０に表示させる。コモン電圧Ｖｃｏｍの設定値Ｖｃｏｍ（Ｎ）は、例えば（Ｎ＋１）フレーム目の開始の時刻ｔ３まで用いられる。 For example, as illustrated in FIG. 8D, the control unit 2 displays the image indicated by the Nth frame image data D (N) in the state of the common voltage Vcom = Vcom (N) from the time t21 after the time t20. Display on the panel 10. The set value Vcom (N) of the common voltage Vcom is used until, for example, the start time t3 of the (N + 1) th frame.
　制御部２は、以上のステップＳ１～Ｓ７の処理をフレーム毎に繰り返す。 The control unit 2 repeats the above steps S1 to S7 for each frame.
　以上の処理によると、画像表示のフレーム毎にフレーム長Ｔ（Ｎ－１）が検出され（Ｓ１）、各フレームの極性と同じ正負でフレーム長Ｔ（Ｎ－１）の長さ分の加算値Ｂ（Ｎ－１）を累積した累積値Ａ（Ｎ－１）が得られる（Ｓ４）。このような累積値Ａ（Ｎ－１）によると、液晶パネル１０に現在、蓄積された実効的なＤＣ成分を推定して、コモン電圧Ｖｃｏｍを動的に最適化することができる。図８（ａ）～（ｄ）を用いて、累積値Ａ（Ｎ－１）によるコモン電圧Ｖｃｏｍの最適化について説明する。 According to the above processing, the frame length T (N−1) is detected for each frame of the image display (S1), and the added value corresponding to the length of the frame length T (N−1) is the same as the polarity of each frame. A cumulative value A (N-1) obtained by accumulating B (N-1) is obtained (S4). According to such accumulated value A (N−1), the effective DC component currently stored in the liquid crystal panel 10 can be estimated, and the common voltage Vcom can be dynamically optimized. The optimization of the common voltage Vcom with the accumulated value A (N−1) will be described using FIGS. 8A to 8D.
　図８（ａ）～（ｄ）では、（Ｎ－１）フレーム目が正極性である場合を例示している。図８（ｃ）に示すように、累積値Ａ（Ｎ－２）～Ａ（Ｎ）は、各フレームのフレーム長及び画素平均値に応じて（Ｓ１，Ｓ２）、正負が反転するフレーム毎に逐次、推移する（Ｓ３，Ｓ４）。 8A to 8D illustrate the case where the (N-1) th frame is positive. As shown in FIG. 8C, the accumulated values A (N−2) to A (N) are obtained for each frame in which the sign is inverted depending on the frame length and the pixel average value of each frame (S1, S2). It changes sequentially (S3, S4).
　図８（ｃ）の例では、（Ｎ－１）フレーム目において累積値Ａ（Ｎ－１）がしきい値１Ｍを超えている。このとき、液晶パネル１０には実効的に正のＤＣ成分が蓄積されていると推定される。そこで、制御部２は、当該累積値Ａ（Ｎ－１）に基づいて、Ｎフレーム目のコモン電圧Ｖｃｏｍを、標準値Ｖ０よりも補正値ΔＶ分、増大させる（Ｓ５）。これにより、液晶パネル１０中のＤＣ成分を相殺して、液晶パネル１０の焼き付き及びフリッカを抑制できる。 In the example of FIG. 8C, the accumulated value A (N-1) exceeds the threshold value 1M in the (N-1) th frame. At this time, it is estimated that the positive DC component is effectively accumulated in the liquid crystal panel 10. Therefore, the control unit 2 increases the common voltage Vcom of the Nth frame by the correction value ΔV from the standard value V0 based on the accumulated value A (N−1) (S5). As a result, the DC component in the liquid crystal panel 10 is canceled, and the burn-in and flicker of the liquid crystal panel 10 can be suppressed.
　また、図８（ｃ）の例では、時刻ｔ２０からコモン電圧Ｖｃｏｍを補正した影響により、液晶パネル１０中のＤＣ成分が変動すると考えられる。そこで、本実施形態のコモン電圧補正処理（図７）は、コモン電圧Ｖｃｏｍを補正した分、次のフレームの累積値Ａ（Ｎ）の大きさを小さくするように、フィードバック値Ｆ（Ｎ－１）を用いたフィードバックを行う（Ｓ６，Ｓ４，式（１）参照）。 In the example of FIG. 8C, it is considered that the DC component in the liquid crystal panel 10 fluctuates due to the influence of correcting the common voltage Vcom from time t20. Therefore, the common voltage correction processing (FIG. 7) of the present embodiment corrects the feedback value F (N−1) so that the accumulated value A (N) of the next frame is reduced by the amount corresponding to the correction of the common voltage Vcom. ) Is used (see S6, S4, equation (1)).
　フィードバック値Ｆ（Ｎ－１）によると、コモン電圧Ｖｃｏｍを補正した影響を考慮して、累積値Ａ（Ｎ）を発散させず適切に管理することができる。累積値Ａ（Ｎ－２）～Ａ（Ｎ）に基づく各フレームの設定値Ｖｃｏｍ（Ｎ－１）～Ｖｃｏｍ（Ｎ＋１）により、コモン電圧Ｖｃｏｍを最適化することができる。 フ ィ ー ド バ ッ ク According to the feedback value F (N−1), the cumulative value A (N) can be appropriately managed without divergence in consideration of the effect of correcting the common voltage Vcom. The common voltage Vcom can be optimized by setting values Vcom (N−1) to Vcom (N + 1) of each frame based on the accumulated values A (N−2) to A (N).
３．まとめ
　以上のように、本実施形態に係る表示装置１は、複数の画素３と、コモン電圧源１３と、ソース駆動部１２と、制御部２とを備える。コモン電圧源１３は、複数の画素３に共通のコモン電圧Ｖｃｏｍを供給する。ソース駆動部１２は、コモン電圧Ｖｃｏｍよりも高い電圧を示す正極性又は低い電圧を示す負極性を有するソース信号をフレーム毎に各画素３に出力する。制御部２は、フレーム期間の長さが可変の映像信号に基づいて、フレーム毎の画像の表示を制御する。制御部２は、フレーム毎の画像が正極性で表示されたフレーム期間の長さと、負極性で表示されたフレーム期間の長さとを検出する（Ｓ１）。制御部２は、各極性で検出したフレーム期間の長さの偏りに応じて、コモン電圧Ｖｃｏｍを補正する（Ｓ５）。 3. Summary As described above, the display device 1 according to the present embodiment includes the plurality of pixels 3, the common voltage source 13, the source driving unit 12, and the control unit 2. The common voltage source 13 supplies a common voltage Vcom to the plurality of pixels 3. The source driver 12 outputs a source signal having a positive polarity indicating a voltage higher than the common voltage Vcom or a negative polarity indicating a low voltage to each pixel 3 for each frame. The control unit 2 controls display of an image for each frame based on a video signal having a variable frame period. The control unit 2 detects the length of the frame period in which the image for each frame is displayed with the positive polarity and the length of the frame period displayed with the negative polarity (S1). The control unit 2 corrects the common voltage Vcom according to the deviation of the length of the frame period detected in each polarity (S5).
　以上の表示装置１によると、フレーム期間の長さの偏りに応じてコモン電圧Ｖｃｏｍを補正することにより、フレームレートが変化する画像を表示する際のフリッカを抑制することができる。 According to the display device 1 described above, flickering when displaying an image with a changed frame rate can be suppressed by correcting the common voltage Vcom according to the deviation of the length of the frame period.
　本実施形態において、制御部２は、正極性のフレーム期間の長さが、負極性のフレーム期間の長さよりも大きいほど、コモン電圧Ｖｃｏｍを増大させる。制御部２は、負極性のフレーム期間の長さが、正極性のフレーム期間の長さよりも大きいほど、コモン電圧Ｖｃｏｍを減少させる。これにより、フレーム期間の長さが正極性と負極性の何れに偏った場合も、液晶パネル１０中のＤＣ成分を適切に相殺して、フリッカを抑制できる。 In the present embodiment, the control unit 2 increases the common voltage Vcom as the length of the positive frame period is larger than the length of the negative frame period. The control unit 2 decreases the common voltage Vcom as the length of the negative frame period is larger than the length of the positive frame period. As a result, even when the length of the frame period is biased to be positive or negative, the DC component in the liquid crystal panel 10 can be canceled appropriately and flicker can be suppressed.
　また、本実施形態において、制御部２は、正極性のフレーム期間と負極性のフレーム期間との間の偏りの累計を示す累積値Ａ（Ｎ）を管理する（Ｓ４）。制御部２は、累積値Ａ（Ｎ）に基づいて、コモン電圧Ｖｃｏｍの補正値ΔＶを決定する（Ｓ５）。これにより、累積値Ａ（Ｎ）に応じてコモン電圧Ｖｃｏｍを動的に補正することができる。 Further, in the present embodiment, the control unit 2 manages the accumulated value A (N) indicating the cumulative deviation between the positive frame period and the negative frame period (S4). The controller 2 determines the correction value ΔV of the common voltage Vcom based on the accumulated value A (N) (S5). Thereby, the common voltage Vcom can be dynamically corrected according to the accumulated value A (N).
　また、本実施形態において、制御部２は、コモン電圧Ｖｃｏｍの補正値の大きさに応じて、累積値Ａ（Ｎ）を減らすようにフィードバックする（Ｓ６，Ｓ４）。これにより、コモン電圧Ｖｃｏｍが補正された影響を考慮して、累積値Ａ（Ｎ）を適切に管理することができる。 In the present embodiment, the control unit 2 feeds back the accumulated value A (N) so as to decrease according to the correction value of the common voltage Vcom (S6, S4). Thereby, the cumulative value A (N) can be appropriately managed in consideration of the effect of correcting the common voltage Vcom.
　また、本実施形態において、制御部２は、各フレームにおいて、フレーム画像における複数の画素３の階調の平均値である画素平均値Ｇ（Ｎ）を計算し、画素平均値Ｇ（Ｎ）に基づきフレーム毎の加算値Ｂ（Ｎ）を累積値Ａ（Ｎ）に加算する（Ｓ２，Ｓ３）。これにより、フレーム毎に表示された画像の階調に応じて累積値Ａ（Ｎ）を蓄積し、コモン電圧Ｖｃｏｍを精度良く補正することができる。 Further, in the present embodiment, the control unit 2 calculates a pixel average value G (N) that is an average value of gradations of the plurality of pixels 3 in the frame image in each frame, and sets the pixel average value G (N). Based on this, the addition value B (N) for each frame is added to the accumulated value A (N) (S2, S3). As a result, the accumulated value A (N) can be accumulated according to the gradation of the image displayed for each frame, and the common voltage Vcom can be accurately corrected.
　また、本実施形態において、制御部２は、映像信号の表示を同期する垂直同期信号Ｖｓｙｎｃに基づいて、各フレーム期間の長さを検出する（Ｓ１）。これにより、フレームレートが動的に変化し得る状況において各フレーム期間の長さを簡単に検出することができる。 In the present embodiment, the control unit 2 detects the length of each frame period based on the vertical synchronization signal Vsync that synchronizes the display of the video signal (S1). This makes it possible to easily detect the length of each frame period in a situation where the frame rate can change dynamically.
　また、本実施形態において、表示装置１に入力される映像信号は、ＨＤＭＩ２．１規格に準拠する。本実施形態の表示装置１によると、ＨＤＭＩ２．１規格の映像信号において生じ得るフリッカの課題を解決することができる。 In this embodiment, the video signal input to the display device 1 conforms to the HDMI 2.1 standard. According to the display device 1 of the present embodiment, it is possible to solve the problem of flicker that may occur in a video signal of the HDMI 2.1 standard.
（他の実施形態）
　上記の実施形態１では、コモン電圧補正処理（図７）においてフィードバック値Ｆ（Ｎ－１）が、式（４）に基づき算出されたが（Ｓ６）、フィードバック値Ｆ（Ｎ）はこれに限らない。例えば、フィードバック値Ｆ（Ｎ－１）は、式（４）の代わりに次式（４’）に基づき算出されてもよい。 (Other embodiments)
In the first embodiment, the feedback value F (N−1) is calculated based on the equation (4) in the common voltage correction process (FIG. 7) (S6), but the feedback value F (N) is not limited to this. Absent. For example, the feedback value F (N−1) may be calculated based on the following equation (4 ′) instead of the equation (4).
Ｆ（Ｎ－１）＝Ｃｆ［Ａ（Ｎ－１）］×Ｇ（Ｎ）×Ｔ（Ｎ）　　　…（４’）
　上式（４’）によると、フィードバック係数Ｃｆ［Ａ（Ｎ－１）］に対応する補正値ΔＶ［Ａ（Ｎ－１）］がコモン電圧Ｖｃｏｍに適用されるＮフレーム目の画像表示の状態を考慮して、フィードバックを行うことができる。この場合、制御部２は、例えばステップＳ６でフィードバック係数Ｃｆ［Ａ（Ｎ－１）］を読み出して、次の制御周期のステップＳ４で上式（４’）の演算を行うことにより、フィードバック値Ｆ（Ｎ－１）を算出することができる。 F (N−1) = Cf [A (N−1)] × G (N) × T (N) (4 ′)
According to the above equation (4 ′), the image display state of the Nth frame in which the correction value ΔV [A (N−1)] corresponding to the feedback coefficient Cf [A (N−1)] is applied to the common voltage Vcom. Can be considered in consideration of feedback. In this case, for example, the control unit 2 reads the feedback coefficient Cf [A (N−1)] in step S6 and performs the calculation of the above equation (4 ′) in step S4 of the next control cycle, thereby obtaining the feedback value. F (N-1) can be calculated.
　以上のように、本発明の具体的な実施形態及び変形例について説明したが、本発明は上記形態に限定されるものではなく、本発明の範囲内で種々の変更を行って実施することができる。例えば、上記の個々の実施形態の内容を適宜組み合わせたものを本発明の一実施形態としてもよい。 As described above, specific embodiments and modifications of the present invention have been described. However, the present invention is not limited to the above-described embodiments, and various modifications can be made within the scope of the present invention. it can. For example, a combination of the contents of the individual embodiments described above may be used as an embodiment of the present invention.
　　１　　表示装置
　　１０　　液晶パネル
　　１１　　ゲート駆動部
　　１２　　ソース駆動部
　　１３　　コモン電圧源
　　２　　制御部
　　３　　画素 DESCRIPTION OF SYMBOLS 1 Display apparatus 10 Liquid crystal panel 11 Gate drive part 12 Source drive part 13 Common voltage source 2 Control part 3 Pixel

Claims (7)

  1. 　複数の画素と、
    　前記複数の画素に共通のコモン電圧を供給する電圧源と、
    　前記コモン電圧よりも高い電圧を示す正極性又は低い電圧を示す負極性を有するソース信号をフレーム毎に各画素に出力するソース駆動部と、
    　フレーム期間の長さが可変の映像信号に基づいて、フレーム毎の画像の表示を制御する制御部とを備え、
    　前記制御部は、
    　前記フレーム毎の画像が前記正極性で表示されたフレーム期間の長さと、前記負極性で表示されたフレーム期間の長さとを検出し、
    　各極性で検出したフレーム期間の長さの偏りに応じて、前記コモン電圧を補正する
    表示装置。     A plurality of pixels;
    A voltage source for supplying a common voltage common to the plurality of pixels;
    A source driver that outputs a source signal having a positive polarity indicating a voltage higher than the common voltage or a negative polarity indicating a low voltage to each pixel for each frame;
    A control unit that controls display of an image for each frame based on a video signal having a variable frame period length;
    The controller is
    Detecting the length of the frame period in which the image for each frame is displayed with the positive polarity and the length of the frame period displayed with the negative polarity;
    A display device that corrects the common voltage according to a deviation in the length of a frame period detected in each polarity.
  2. 　前記制御部は、
    　前記正極性のフレーム期間の長さが、前記負極性のフレーム期間の長さよりも大きいほど、前記コモン電圧を増大させ、
    　前記負極性のフレーム期間の長さが、前記正極性のフレーム期間の長さよりも大きいほど、前記コモン電圧を減少させる
    請求項１に記載の表示装置。     The controller is
    As the length of the positive polarity frame period is larger than the length of the negative polarity frame period, the common voltage is increased.
    The display device according to claim 1, wherein the common voltage is decreased as the length of the negative frame period is longer than the length of the positive frame period.
  3. 　前記制御部は、
    　前記正極性のフレーム期間と前記負極性のフレーム期間との間の偏りの累計を示す累積値を管理し、
    　前記累積値に基づいて、前記コモン電圧の補正値を決定する
    請求項１又は２に記載の表示装置。     The controller is
    Managing a cumulative value indicating a cumulative deviation between the positive frame period and the negative frame period;
    The display device according to claim 1, wherein a correction value of the common voltage is determined based on the accumulated value.
  4. 　前記制御部は、前記コモン電圧の補正値の大きさに応じて、前記累積値を減らすようにフィードバックする
    請求項３に記載の表示装置。     The display device according to claim 3, wherein the control unit feeds back the accumulated value in accordance with the correction value of the common voltage.
  5. 　前記制御部は、各フレームにおいて、フレーム画像における複数の画素の階調の平均値を計算し、前記平均値に基づきフレーム毎の加算値を前記累積値に加算する
    請求項３又は４に記載の表示装置。     The said control part calculates the average value of the gradation of the some pixel in a frame image in each flame | frame, and adds the addition value for every flame | frame to the said cumulative value based on the said average value. Display device.
  6. 　前記制御部は、前記映像信号の表示を同期する垂直同期信号に基づいて、各フレーム期間の長さを検出する
    請求項１～５のいずれか１項に記載の表示装置。     6. The display device according to claim 1, wherein the control unit detects a length of each frame period based on a vertical synchronization signal that synchronizes display of the video signal.
  7. 　前記映像信号は、ＨＤＭＩ２．１規格に準拠する
    請求項１～６のいずれか１項に記載の表示装置。     The display device according to any one of claims 1 to 6, wherein the video signal conforms to an HDMI 2.1 standard.
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010072393A (en) * 2008-09-19 2010-04-02 Seiko Epson Corp Electrooptical device, driving method thereof, and electronic equipment
JP2011197384A (en) * 2010-03-19 2011-10-06 Seiko Epson Corp Liquid crystal driving device, liquid crystal display device, and projector
JP2014164017A (en) * 2013-02-22 2014-09-08 Seiko Epson Corp Drive device of electro-optic device, drive method of electro-optic device, electro-optic device and electronic equipment

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010072393A (en) * 2008-09-19 2010-04-02 Seiko Epson Corp Electrooptical device, driving method thereof, and electronic equipment
JP2011197384A (en) * 2010-03-19 2011-10-06 Seiko Epson Corp Liquid crystal driving device, liquid crystal display device, and projector
JP2014164017A (en) * 2013-02-22 2014-09-08 Seiko Epson Corp Drive device of electro-optic device, drive method of electro-optic device, electro-optic device and electronic equipment

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