WO2019153683A1 - Programmateur d'instructions configurable et flexible - Google Patents

Programmateur d'instructions configurable et flexible Download PDF

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Publication number
WO2019153683A1
WO2019153683A1 PCT/CN2018/099749 CN2018099749W WO2019153683A1 WO 2019153683 A1 WO2019153683 A1 WO 2019153683A1 CN 2018099749 W CN2018099749 W CN 2018099749W WO 2019153683 A1 WO2019153683 A1 WO 2019153683A1
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WO
WIPO (PCT)
Prior art keywords
module
instruction
instruction queue
queue
configurable
Prior art date
Application number
PCT/CN2018/099749
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English (en)
Chinese (zh)
Inventor
洪振洲
李庭育
陈育鸣
Original Assignee
江苏华存电子科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 江苏华存电子科技有限公司 filed Critical 江苏华存电子科技有限公司
Publication of WO2019153683A1 publication Critical patent/WO2019153683A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3856—Reordering of instructions, e.g. using queues or age tags
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching

Definitions

  • the invention relates to the technical field of instruction scheduling, in particular to a configurable and flexible instruction scheduler.
  • Instruction scheduling is a technique in which instructions are executed in parallel.
  • the compiler or machine hardware increases the number of machine execution instructions per beat by adjusting the order of instructions.
  • the shot is the machine execution instruction that the compiler simulates when compiling the source program. Clock cycle.
  • a table scheduling algorithm is usually used to implement instruction scheduling, and a candidate instruction queue is usually adopted.
  • the data dependency graph is composed of a plurality of nodes, each node represents an instruction, and the data dependency graph can be used to represent a dependency between the instructions. relationship.
  • the priority of each instruction is then calculated, and then the instructions in the data dependency graph are scheduled on a beat-by-shot basis.
  • Instruction scheduling is an effective means of compiler-level mining of program-level parallelism. It improves the number of instructions that the target machine can execute in a cycle by re-adjusting the order of instructions without changing the semantics of the program and satisfying the dependencies and resource dependencies of the target machine. Instruction scheduling is a key technology of modern high-performance compilers. It determines the relative execution order of each operation, the specific execution time and which hardware resources are used. From the perspective of code block partitioning, instruction scheduling can be divided into local instruction scheduling and global instruction scheduling, where local instruction scheduling refers to instruction scheduling within a basic block, and global scheduling refers to instruction scheduling between basic blocks.
  • the existing system-level single-chip architecture consists of a plurality of sub-modules including a central microprocessor and is connected by an external bus.
  • the central controller separately performs an operation via an external bus, so that the performance of each subsequent instruction is degraded via the bus.
  • a configurable and flexible instruction scheduler including a central microprocessor, a memory, a first hardware module, and a second hardware module, the central microprocessor passing the bus
  • the memory, the first hardware module and the second hardware module are respectively connected, and the memory is provided with an instruction queue unit and an instruction queue setting unit, and the instruction queue setting unit is respectively connected to the first hardware module and the second hardware module.
  • the instruction queue unit includes a first instruction queue module, a second instruction queue module, a third instruction queue module, and an Nth instruction queue module, where N is an integer greater than 3.
  • the instruction queue setting unit includes a first instruction queue setting module, a second instruction queue setting module, a third instruction queue setting module, and an Mth instruction queue setting module, where M is an integer greater than 3.
  • the first instruction queue setting module is connected to the first instruction queue module
  • the second instruction queue setting module is connected to the second instruction queue module
  • the third instruction queue setting module is connected to the third instruction queue module.
  • the Mth instruction queue setting module is connected to the Nth instruction queue module.
  • the beneficial effects of the present invention are: in the present invention, the central microprocessor can give each sub-module a more flexible instruction length and instruction queue depth, thereby making it easier for the microprocessor to independently command.
  • Figure 1 is a schematic diagram of the structure of the present invention.
  • a configurable and flexible instruction scheduler including a central microprocessor 1, a memory 2, a first hardware module 3, and a second hardware module 4, the central The microprocessor 1 is respectively connected to the memory 2, the first hardware module 3 and the second hardware module 4 via a bus.
  • the memory 2 is provided with an instruction queue unit 5 and an instruction queue setting unit 6, and the instruction queue setting unit 5
  • the first hardware module 3 and the second hardware module 4 are connected, respectively.
  • the instruction queue unit 5 includes a first instruction queue module 7, a second instruction queue module 8, a third instruction queue module 9, and an Nth instruction queue module, where N is an integer greater than 3;
  • the instruction queue setting unit 6 includes The first instruction queue setting module 10, the second instruction queue setting module 11, the third instruction queue setting module 12, and the Mth instruction queue setting module, M is an integer greater than 3;
  • the first instruction queue is set The module 10 is connected to the first instruction queue module 7, the second instruction queue setting module 11 is connected to the second instruction queue module 8, and the third instruction queue setting module 12 is connected to the third instruction queue module 9, the Mth The instruction queue setting module is connected to the Nth instruction queue module.
  • the microprocessor commands the central control module via the external bus, and the commands corresponding to the different modules are written to the respective defined addresses in the memory, and each command queue corresponds to a different module in the system, and has different meanings, and
  • the instruction length and the number are set in the instruction queue setting register.
  • the microprocessor can issue multiple instructions at a time, and then write the register to inform the queue how many instructions have been written for the external hardware sub-module to execute.
  • Each hardware sub-module knows how many instructions need to be processed and fetches instructions through the external bus according to the instruction queue setting signal. Once the fetching is completed, the microprocessor rewrites the register to notify the microprocessor that many instructions have been fetched. This will optimize the memory usage of this instruction and adjust the instruction queue depth according to the actual hardware requirements, which is flexible.
  • the external hardware sub-module can also write commands in this way for the microprocessor to execute.
  • the central microprocessor can give each sub-module a more flexible instruction length and instruction queue depth, thereby making it easier for the microprocessor to independently command.

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)

Abstract

La présente invention concerne un programmateur d'instructions configurable et flexible, comprenant un microprocesseur central, une mémoire, un premier module matériel et un second module matériel. Le microprocesseur central est connecté à la mémoire, au premier module matériel et au second module matériel au moyen d'un bus. La mémoire comporte une unité de file d'attente d'instructions et une unité de réglage de file d'attente d'instructions. L'unité de réglage de file d'attente d'instructions est connectée au premier module matériel et au second module matériel. Dans la présente invention, le microprocesseur central peut fournir à chaque sous-module une longueur d'instruction et une profondeur de file d'attente d'instructions plus flexibles, de telle sorte que le microprocesseur peut émettre plus facilement une instruction.
PCT/CN2018/099749 2018-02-06 2018-08-09 Programmateur d'instructions configurable et flexible WO2019153683A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201810118967.8A CN108228242B (zh) 2018-02-06 2018-02-06 一种可配置且具弹性的指令调度器
CN201810118967.8 2018-02-06

Publications (1)

Publication Number Publication Date
WO2019153683A1 true WO2019153683A1 (fr) 2019-08-15

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CN (1) CN108228242B (fr)
WO (1) WO2019153683A1 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108228242B (zh) * 2018-02-06 2020-02-07 江苏华存电子科技有限公司 一种可配置且具弹性的指令调度器
US20220374237A1 (en) * 2021-05-21 2022-11-24 Telefonaktiebolaget Lm Ericsson (Publ) Apparatus and method for identifying and prioritizing certain instructions in a microprocessor instruction pipeline

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030163671A1 (en) * 2002-02-26 2003-08-28 Gschwind Michael Karl Method and apparatus for prioritized instruction issue queue
CN101710272A (zh) * 2009-10-28 2010-05-19 北京龙芯中科技术服务中心有限公司 指令调度装置和方法
CN102495724A (zh) * 2011-11-04 2012-06-13 杭州中天微系统有限公司 一种加快存储指令执行效率的数据处理器
CN108228242A (zh) * 2018-02-06 2018-06-29 江苏华存电子科技有限公司 一种可配置且具弹性的指令调度器

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US7130990B2 (en) * 2002-12-31 2006-10-31 Intel Corporation Efficient instruction scheduling with lossy tracking of scheduling information
US7613904B2 (en) * 2005-02-04 2009-11-03 Mips Technologies, Inc. Interfacing external thread prioritizing policy enforcing logic with customer modifiable register to processor internal scheduler
CN104424026B (zh) * 2013-08-21 2017-11-17 华为技术有限公司 一种指令调度方法及装置
US10175988B2 (en) * 2015-06-26 2019-01-08 Microsoft Technology Licensing, Llc Explicit instruction scheduler state information for a processor

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030163671A1 (en) * 2002-02-26 2003-08-28 Gschwind Michael Karl Method and apparatus for prioritized instruction issue queue
CN101710272A (zh) * 2009-10-28 2010-05-19 北京龙芯中科技术服务中心有限公司 指令调度装置和方法
CN102495724A (zh) * 2011-11-04 2012-06-13 杭州中天微系统有限公司 一种加快存储指令执行效率的数据处理器
CN108228242A (zh) * 2018-02-06 2018-06-29 江苏华存电子科技有限公司 一种可配置且具弹性的指令调度器

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CN108228242A (zh) 2018-06-29

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