WO2019153681A1 - 一种智能指令调度器 - Google Patents

一种智能指令调度器 Download PDF

Info

Publication number
WO2019153681A1
WO2019153681A1 PCT/CN2018/099742 CN2018099742W WO2019153681A1 WO 2019153681 A1 WO2019153681 A1 WO 2019153681A1 CN 2018099742 W CN2018099742 W CN 2018099742W WO 2019153681 A1 WO2019153681 A1 WO 2019153681A1
Authority
WO
WIPO (PCT)
Prior art keywords
instruction
instruction queue
module
hardware modules
central microprocessor
Prior art date
Application number
PCT/CN2018/099742
Other languages
English (en)
French (fr)
Inventor
洪振洲
李庭育
陈育鸣
Original Assignee
江苏华存电子科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 江苏华存电子科技有限公司 filed Critical 江苏华存电子科技有限公司
Publication of WO2019153681A1 publication Critical patent/WO2019153681A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3818—Decoding for concurrent execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3877—Concurrent instruction execution, e.g. pipeline, look ahead using a slave processor, e.g. coprocessor

Definitions

  • the invention relates to the technical field of instruction scheduling, in particular to an intelligent instruction scheduler.
  • Instruction scheduling is a technique in which instructions are executed in parallel.
  • the compiler or machine hardware increases the number of machine execution instructions per beat by adjusting the order of instructions.
  • the shot is the machine execution instruction that the compiler simulates when compiling the source program. Clock cycle.
  • a table scheduling algorithm is usually used to implement instruction scheduling, and a candidate instruction queue is usually adopted.
  • the data dependency graph is composed of a plurality of nodes, each node represents an instruction, and the data dependency graph can be used to represent a dependency between the instructions. relationship.
  • the priority of each instruction is then calculated, and then the instructions in the data dependency graph are scheduled on a beat-by-shot basis.
  • Instruction scheduling is an effective means of compiler-level mining of program-level parallelism. It improves the number of instructions that the target machine can execute in a cycle by re-adjusting the order of instructions without changing the semantics of the program and satisfying the dependencies and resource dependencies of the target machine. Instruction scheduling is a key technology of modern high-performance compilers. It determines the relative execution order of each operation, the specific execution time and which hardware resources are used. From the perspective of code block partitioning, instruction scheduling can be divided into local instruction scheduling and global instruction scheduling, where local instruction scheduling refers to instruction scheduling within a basic block, and global scheduling refers to instruction scheduling between basic blocks.
  • the existing central instruction allocator is still a simple microprocessor to send instructions, and the sub-module receives the instruction execution. If the priority is to be prioritized, multiple instructions are added to the sub-module.
  • the interface or the self-designed sequence queue is stored separately and executed, and the sub-module capture instruction may also be through the external bus.
  • Such a method has the following disadvantages: 1. Grab the instruction through the external bus to increase the complexity and cost of the sub-module design. 2. If the instruction is obtained through a specific instruction bus, the cost of the sub-module is increased to store various priorities. The complexity is increased to determine the order of priority of the instructions.
  • an intelligent instruction scheduler including a central microprocessor and a plurality of hardware modules, the central microprocessor connecting a plurality of hardware modules through a bus, the central microprocessor Automatically managing modules through a bus; the automatic management module is respectively connected to an instruction queue setting unit and a memory, the memory is connected to a service quality control unit, and the service quality control unit is respectively connected to a plurality of hardware modules; the plurality of hardware modules include A hardware module and a second hardware module.
  • the instruction queue setting unit includes a first instruction queue setting module, a second instruction queue setting module, a third instruction queue setting module, and an Nth instruction queue setting module, where N is an integer greater than 3.
  • the memory includes a low priority instruction queue, a medium priority instruction queue, a high priority instruction queue, and an instruction queue data module, wherein the low priority instruction queue, the medium priority instruction queue, and the high priority instruction queue are respectively connected to the first instruction queue setting.
  • Fixed module a low priority instruction queue, a medium priority instruction queue, a high priority instruction queue, and an instruction queue data module, wherein the low priority instruction queue, the medium priority instruction queue, and the high priority instruction queue are respectively connected to the first instruction queue setting.
  • the method of using the method comprises the following steps:
  • the central microprocessor randomly sets the instruction queue parameters required for each sub-view when you turn on the power
  • the central microprocessor writes instructions to queue positions of different priority levels according to quality requirements
  • the quality of service control module then sends an instruction to the sub-module through the instruction interface according to the set weight.
  • the invention has the beneficial effects that the present invention uniformly manages the instruction priority execution order, and avoids that multiple sub-modules need to be designed for the same purpose, and provides a specially designed single instruction interface when the central microprocessor When the command is issued, the command is sent to the sub-module through the command interface according to the set weight, so as to achieve the purpose of ensuring service quality and high performance.
  • Figure 1 is a schematic diagram of the present invention.
  • an intelligent instruction scheduler including a central microprocessor 1 and a plurality of hardware modules, wherein the central microprocessor 1 connects a plurality of hardware modules through a bus, the central The microprocessor 1 is connected to the automatic management module 3 via a bus; the automatic management module 3 is connected to the instruction queue setting unit 4 and the memory 5, respectively, and the memory 5 is connected to the service quality control unit 6, and the quality of service control unit 6 is respectively connected.
  • a plurality of hardware modules; the plurality of hardware modules include a first hardware module 7 and a second hardware module 8.
  • the instruction queue setting unit 4 includes a first instruction queue setting module 9, a second instruction queue setting module 10, a third instruction queue setting module 11, and an Nth instruction queue setting module, where N is greater than 3.
  • the integer 5; the memory 5 includes a low priority instruction queue 12, a medium priority instruction queue 13, a high priority instruction queue 14 and an instruction queue data module 2, wherein the low priority instruction queue 12, the medium priority instruction queue 13, and the high priority instruction queue 14 respectively
  • the first instruction queue setting module 9 is connected.
  • each command queue setting can be set to a single or multiple priorities, and the respective instruction queue depths, and sent to the system via the quality of service control module according to the set weights and priorities.
  • the word module is executed, which will save the hardware cost and development time of other hardware modules in the instruction arbitration and access instructions, and improve the performance, while ensuring the quality requirements of the instruction operation.
  • the method of use of the present invention comprises the following steps:
  • the central microprocessor randomly sets the instruction queue parameters required for each sub-view when you turn on the power
  • the central microprocessor writes instructions to queue positions of different priority levels according to quality requirements
  • the quality of service control module then sends an instruction to the sub-module through the instruction interface according to the set weight.
  • the invention uniformly manages the instruction priority execution order, and avoids that multiple sub-modules need to be designed for the same purpose, and provides a single instruction interface specially designed.
  • the central microprocessor issues an instruction, the instruction is transmitted according to the set weight.
  • the interface sends instructions to the sub-modules, thus achieving the purpose of ensuring service quality and high performance.

Abstract

本发明公开了一种智能指令调度器，包括中央微处理器和多个硬件模块，中央微处理器通过总线连接多个硬件模块，所述中央微处理器通过总线连接自动管理模块；所述自动管理模块分别连接指令队列设定单元和内存,所述内存连接服务质量控制单元，所述服务质量控制单元分别连接多个硬件模块；多个硬件模块包括第一硬件模块和第二硬件模块。本发明将指令优先执行顺序统一管理，而避免多个子模块需要各自做相同目的设计，并提供特别设计之单一指令接口，当中央微处理器下达指令时，即根据所设定之权重透过指令接口送出指令给子模块，如此达到保证服务质量与高效能之目的。

Description

一种智能指令调度器 技术领域
本发明涉及指令调度技术领域，具体为一种智能指令调度器。
背景技术
指令调度是一种指令并行执行的技术，编译器或者机器硬件通过调整指令的顺序来提高每拍内机器执行指令的数量，所述拍为编译器在编译源程序时所模拟的机器执行指令的时钟周期。现有编译技术中通常采用表调度算法来实现指令调度，通常采用一个候选指令队列。具体的，在进行指令调度时，首先对需要调度的指令构建数据依赖图，该数据依赖图由若干个节点组成，每个节点代表一条指令，该数据依赖图可以用来表示指令之间的依赖关系。然后计算各条指令的优先级，接着逐拍对数据依赖图中的指令进行调度。指令调度是编译器挖掘程序潜在的指令级并行的有效手段。它是在不改变程序语义，满足目标机器的相关性和资源依赖性的前提下，通过重新调整指令顺序来提高一个周期内目标机器能够执行的指令数目。指令调度是现代高性能编译器的一项关键技术，它决定各操作的相对执行顺序，具体执行时间及使用哪些硬件资源等。从代码块划分角度来看，指令调度可以分为局部指令调度和全局指令调度，其中局部指令调度是指基本块内的指令调度，而全局调度是指基本块间的指令调度。
现有中央指令分配器不管连接于外部总线或是低延迟总线，都还是单纯的微处理器送指令，子模块收下指令执行，如果要分优先级，则是在子模块中加入多个指令接口或是自行设计顺序队列分别存放后执行，而子模块抓取指令方式也可能是透过外部总线。如此的方式有以下缺点:1.透过外部总线抓取指令将增加子模块设计复杂度与成本 2.如透过特定指令总线取得指令，子模块成本增加以存放各种不同优先级之指令，复杂度增加以决定指令之优先执行顺序。
发明内容
本发明的目的在于提供一种智能指令调度器，以解决上述背景技术中提出的问题。
为实现上述目的，本发明提供如下技术方案：一种智能指令调度器,包括中央微处理器和多个硬件模块，所述中央微处理器通过总线连接多个硬件模块，所述中央微处理器通过总线连接自动管理模块；所述自动管理模块分别连接指令队列设定单元和内存,所述内存连接服务质量控制单元，所述服务质量控制单元分别连接多个硬件模块；多个硬件模块包括第一硬件模块和第二硬件模块。
优选的，所述指令队列设定单元包括第一指令队列设定模块、第二指令队列设定模块、第三指令队列设定模块，第N指令队列设定模块，N为大于3的整数。
优选的，所述内存包括低优先指令队列、中优先指令队列、高优先指令队列和指令队列数据模块，所述低优先指令队列、中优先指令队列、高优先指令队列分别连接第一指令队列设定模块。
优选的，其使用方法包括以下步骤：
A、中央微处理器在开机时随机先设定好每个子你看所需的指令队列参数；
B、中央微处理器根据质量需求对不同优先级别队列位置写入指令；
C、服务质量控制模块随即根据所设定之权重透过指令接口送出指令给子模块。
与现有技术相比，本发明的有益效果是：本发明将指令优先执行顺序统一管理，而避免多个子模块需要各自做相同目的设计，并提供特别设计之单一指令接口，当中央微处理器下达指令时，即根据所设定之权重透过指令接口送出指令给子模块，如此达到保证服务质量与高效能之目的。
附图说明
图1为本发明原理图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参阅图1，本发明提供一种技术方案：一种智能指令调度器,包括中央微处理器1和多个硬件模块，所述中央微处理器1通过总线连接多个硬件模块，所述中央微处理器1通过总线连接自动管理模块3；所述自动管理模块3分别连接指令队列设定单元4和内存5,所述内存5连接服务质量控制单元6，所述服务质量控制单元6分别连接多个硬件模块；多个硬件模块包括第一硬件模块7和第二硬件模块8。
本发明中，指令队列设定单元4包括第一指令队列设定模块9、第二指令队列设定模块10、第三指令队列设定模块11，第N指令队列设定模块，N为大于3的整数；内存5包括低优先指令队列12、中优先指令队列13、高优先指令队列14和指令队列数据模块2，所述低优先指令队列12、中优先指令队列13、高优先指令队列14分别连接第一指令队列设定模块9。
本发明中，每个指令队列设定可以设定单一或多种优先级，与各自的指令队列深度，并经由服务质量控制模块根据设定的权重与优先级选出要执行的指令送出给系统字模块执行，如此将可省去其他硬件模块在指令仲裁与存取指令的硬件成本与研发时间，并提高效能，同时保证指令运行的质量需求。
本发明的使用方法包括以下步骤：
A、中央微处理器在开机时随机先设定好每个子你看所需的指令队列参数；
B、中央微处理器根据质量需求对不同优先级别队列位置写入指令；
C、服务质量控制模块随即根据所设定之权重透过指令接口送出指令给子模块。
本发明将指令优先执行顺序统一管理，而避免多个子模块需要各自做相同目的设计，并提供特别设计之单一指令接口，当中央微处理器下达指令时，即根据所设定之权重透过指令接口送出指令给子模块，如此达到保证服务质量与高效能之目的。
尽管已经示出和描述了本发明的实施例，对于本领域的普通技术人员而言，可以理解在不脱离本发明的原理和精神的情况下可以对这些实施例进行多种变化、修改、替换和变型，本发明的范围由所附权利要求及其等同物限定。

Claims (4)

  1. 一种智能指令调度器,包括中央微处理器(1)和多个硬件模块，其特征在于：所述中央微处理器(1)通过总线连接多个硬件模块，所述中央微处理器(1)通过总线连接自动管理模块(3)；所述自动管理模块(3)分别连接指令队列设定单元(4)和内存(5),所述内存(5)连接服务质量控制单元(6)，所述服务质量控制单元(6)分别连接多个硬件模块；多个硬件模块包括第一硬件模块(7)和第二硬件模块(8)。
  2. 根据权利要求1所述的一种智能指令调度器，其特征在于：所述指令队列设定单元(4)包括第一指令队列设定模块(9)、第二指令队列设定模块(10)、第三指令队列设定模块(11)，第N指令队列设定模块，N为大于3的整数。
  3. 根据权利要求2所述的一种智能指令调度器，其特征在于：所述内存(5)包括低优先指令队列(12)、中优先指令队列(13)、高优先指令队列(14)和指令队列数据模块(2)，所述低优先指令队列(12)、中优先指令队列(13)、高优先指令队列(14)分别连接第一指令队列设定模块(9)。
  4. 实现权利要求1所述的一种智能指令调度器的使用方法，其特征在于：其使用方法包括以下步骤：
    A、中央微处理器在开机时随机先设定好每个子你看所需的指令队列参数；
    B、中央微处理器根据质量需求对不同优先级别队列位置写入指令；
    C、服务质量控制模块随即根据所设定之权重透过指令接口送出指令给子模块。
PCT/CN2018/099742 2018-02-06 2018-08-09 一种智能指令调度器 WO2019153681A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201810118954.0A CN108196883A (zh) 2018-02-06 2018-02-06 一种智能指令调度器
CN201810118954.0 2018-02-06

Publications (1)

Publication Number Publication Date
WO2019153681A1 true WO2019153681A1 (zh) 2019-08-15

Family

ID=62592995

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/099742 WO2019153681A1 (zh) 2018-02-06 2018-08-09 一种智能指令调度器

Country Status (2)

Country Link
CN (1) CN108196883A (zh)
WO (1) WO2019153681A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108196883A (zh) * 2018-02-06 2018-06-22 江苏华存电子科技有限公司 一种智能指令调度器
CN109032672A (zh) * 2018-07-19 2018-12-18 江苏华存电子科技有限公司 低延迟指令调度器及过滤猜测访问方法
CN112987868B (zh) * 2021-03-03 2022-08-19 江苏华存电子科技有限公司 一种便于安装的指令调度器设备

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104915256A (zh) * 2015-06-05 2015-09-16 惠州Tcl移动通信有限公司 一种任务的实时调度实现方法及其系统
CN106775990A (zh) * 2016-12-31 2017-05-31 中国移动通信集团江苏有限公司 请求调度方法和装置
US9824225B1 (en) * 2013-09-20 2017-11-21 EMC IP Holding Company LLC Protecting virtual machines processing sensitive information
CN108196883A (zh) * 2018-02-06 2018-06-22 江苏华存电子科技有限公司 一种智能指令调度器

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9824225B1 (en) * 2013-09-20 2017-11-21 EMC IP Holding Company LLC Protecting virtual machines processing sensitive information
CN104915256A (zh) * 2015-06-05 2015-09-16 惠州Tcl移动通信有限公司 一种任务的实时调度实现方法及其系统
CN106775990A (zh) * 2016-12-31 2017-05-31 中国移动通信集团江苏有限公司 请求调度方法和装置
CN108196883A (zh) * 2018-02-06 2018-06-22 江苏华存电子科技有限公司 一种智能指令调度器

Also Published As

Publication number Publication date
CN108196883A (zh) 2018-06-22

Similar Documents

Publication Publication Date Title
JP5658365B2 (ja) ハイブリッド・コンピューティング環境における高スループット・コンピューティングの方法、システム及びプログラム
KR101332840B1 (ko) 병렬 컴퓨팅 프레임워크 기반의 클러스터 시스템, 호스트 노드, 계산 노드 및 어플리케이션 실행 방법
CN109992407B (zh) 一种yarn集群gpu资源调度方法、装置和介质
Hu et al. Scheduling real-time parallel applications in cloud to minimize energy consumption
US9652243B2 (en) Predicting out-of-order instruction level parallelism of threads in a multi-threaded processor
US20120054771A1 (en) Rescheduling workload in a hybrid computing environment
US8997071B2 (en) Optimized division of work among processors in a heterogeneous processing system
RU2012127578A (ru) Анализатор применимости программного модуля для разработки и тестирования программного обеспечения для многопроцессорных сред
WO2019153681A1 (zh) 一种智能指令调度器
US9417930B2 (en) Time slack application pipeline balancing for multi/many-core PLCs
JP2009519513A (ja) 専用スレッド管理を用いたマルチコアの演算処理方法及び装置
US9141436B2 (en) Apparatus and method for partition scheduling for a processor with cores
US11687771B2 (en) Platform for concurrent execution of GPU operations
Hennig et al. Towards parallelizing legacy embedded control software using the LET programming paradigm
CN104536937A (zh) 基于cpu-gpu异构集群的大数据一体机实现方法
US10083066B2 (en) Processing data by using simultaneous multithreading
Fan Job scheduling in high performance computing
Zhao et al. Tacker: Tensor-cuda core kernel fusion for improving the gpu utilization while ensuring qos
Feljan et al. Task allocation optimization for multicore embedded systems
KR101770234B1 (ko) 소프트웨어 프로그램의 연산 블록을 멀티-프로세서 시스템의 코어에 할당하는 방법 및 시스템
CN108228242B (zh) 一种可配置且具弹性的指令调度器
Halimi et al. FoREST-mn: Runtime DVFS beyond communication slack
Hussain et al. AMMC: Advanced multi-core memory controller
WO2019153684A1 (zh) 一种低延迟指令调度器的自动管理方法
De Sensi et al. State-aware concurrency throttling

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18904844

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 18904844

Country of ref document: EP

Kind code of ref document: A1