WO2019151042A1 - Photoelectric conversion element, solid-state imaging device, and electronic apparatus - Google Patents

Photoelectric conversion element, solid-state imaging device, and electronic apparatus Download PDF

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Publication number
WO2019151042A1
WO2019151042A1 PCT/JP2019/001841 JP2019001841W WO2019151042A1 WO 2019151042 A1 WO2019151042 A1 WO 2019151042A1 JP 2019001841 W JP2019001841 W JP 2019001841W WO 2019151042 A1 WO2019151042 A1 WO 2019151042A1
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photoelectric conversion
layer
electrode
formula
work function
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PCT/JP2019/001841
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French (fr)
Japanese (ja)
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陽介 齊藤
雅史 坂東
治典 塩見
知佳 大橋
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ソニー株式会社
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y20/00—Nanooptics, e.g. quantum optics or photonic crystals
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
    • H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by at least one potential-jump barrier or surface barrier, e.g. phototransistors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/30—Transforming light or analogous information into electric information
    • H04N5/33—Transforming infrared radiation

Definitions

  • This technology relates to a photoelectric conversion element, a solid-state imaging device, and an electronic device.
  • CCD Charge Coupled Device
  • CMOS Complementary Metal Oxide Semiconductor
  • a first electrode, a second electrode formed opposite to the first electrode, and a narrow gap semiconductor quantum dot dispersed in the conductive film formed between the first electrode and the second electrode For example, a first electrode, a second electrode formed opposite to the first electrode, and a narrow gap semiconductor quantum dot dispersed in the conductive film formed between the first electrode and the second electrode.
  • a solid-state imaging device is proposed in which one of the first electrode and the second electrode is formed of a transparent electrode, and the other electrode is formed of a metal electrode or a transparent electrode. (See Patent Document 1).
  • the charge generated by the photoelectric conversion is once accumulated in the photoelectric conversion unit in the semiconductor substrate and then transferred to the FD. For this reason, a photoelectric conversion part can be completely depleted.
  • the photoelectric conversion unit provided outside the semiconductor substrate the charge generated by the photoelectric conversion unit is directly accumulated in the FD as described above, so that the photoelectric conversion unit is completely depleted. It was difficult, kTC noise became large, random noise worsened, and the picked-up image quality was reduced.
  • an image pickup device that includes a charge storage electrode that is disposed so as to face a photoelectric conversion layer with an insulating layer interposed therebetween (see Patent Document 2).
  • a charge storage electrode that is disposed so as to face a photoelectric conversion layer with an insulating layer interposed therebetween (see Patent Document 2).
  • Patent Document 1 the photoelectric conversion element technology using quantum dots proposed in Patent Document 1 may not be able to further improve image quality and reliability.
  • the present technology has been made in view of such a situation, and provides a photoelectric conversion element, a solid-state imaging device, and an electronic device that can realize further improvement in image quality and further improvement in reliability.
  • the main purpose is a photoelectric conversion element, a solid-state imaging device, and an electronic device that can realize further improvement in image quality and further improvement in reliability.
  • first, at least a first function, a work function adjustment layer, a photoelectric conversion layer, a charge storage layer, and a second electrode are provided in this order, and the first electrode is an anode,
  • the second electrode is a cathode,
  • the photoelectric conversion layer includes a quantum dot material,
  • the work function adjustment layer is disposed in contact with the first electrode, includes an organic compound, and satisfies the following formula 1.
  • An element is provided.
  • E A1 in the formula 1 represents the electron affinity of the work function adjusting layer
  • WF 2 in the formula 1 represents the work function of the second electrode.
  • the work function adjustment layer and the photoelectric conversion layer may satisfy the following Expression 2.
  • I P3 in the formula 2 represents the ionization potential of the quantum dot material of the photoelectric conversion layer.
  • the photoelectric conversion element according to the present technology may further include a p-type buffer layer between the work function adjustment layer and the photoelectric conversion layer, and may satisfy Equation 3 below.
  • E A1 in the equation 3 represents the electron affinity of the work function adjusting layer
  • I P2 in the equation 3 represents the ionization potential of the p-type buffer layer.
  • the photoelectric conversion element according to the present technology may further satisfy the following formula 4.
  • E A2 ⁇ E A3 ... Formula 4 E A2 in the formula 4 represents the electron affinity of the p-type buffer layer, and E A3 in the formula 4 represents the electron affinity of the quantum dot material of the photoelectric conversion layer.
  • the photoelectric conversion element according to the present technology may further include an n-type buffer layer between the photoelectric conversion layer and the charge storage layer.
  • the photoelectric conversion element according to the present technology has an insulating layer between the second electrode and the charge storage layer, is opposed to the second electrode and the insulating layer, and is provided in the insulating layer.
  • a third electrode that is electrically connected to the photoelectric conversion layer through the opening may be further provided.
  • the first electrode, the work function adjustment layer, the photoelectric conversion layer, the charge storage layer, and the second electrode are provided in this order, and the first electrode is an anode, and the second electrode
  • WF 0 in Equation 5 represents the work function of the work function adjusting layer
  • WF 2 in Equation 5 represents the work function of the second electrode
  • the work function adjustment layer and the photoelectric conversion layer may satisfy Expression 6 below. WF 0 ⁇ I P3 ... Formula 6
  • I P3 in the formula 6 represents an ionization potential of the quantum dot material of the photoelectric conversion layer.
  • the photoelectric conversion element according to the present technology may further include a p-type buffer layer between the work function adjustment layer and the photoelectric conversion layer, and may satisfy Equation 7 below.
  • Formula WF 0 in 7 indicates the work function of the work function adjustment layer
  • I P2 in formula 7 indicates the ionization potential of the p-type buffer layer.
  • the photoelectric conversion element according to the present technology may further satisfy the following formula 8.
  • E A2 ⁇ E A3 ... Formula 8 E A2 in the equation 8 represents the electron affinity of the p-type buffer layer, and E A3 in the equation 8 represents the electron affinity of the quantum dot material of the photoelectric conversion layer.
  • the photoelectric conversion element according to the present technology may further include an n-type buffer layer between the photoelectric conversion layer and the charge storage layer.
  • the photoelectric conversion element according to the present technology has an insulating layer between the second electrode and the charge storage layer, is opposed to the second electrode and the insulating layer, and is provided in the insulating layer.
  • a third electrode that is electrically connected to the photoelectric conversion layer through the opening may be further provided.
  • the present technology provides a solid-state imaging device in which at least one or a plurality of photoelectric conversion elements according to the present technology and a semiconductor substrate are stacked for each of a plurality of pixels arranged one-dimensionally or two-dimensionally.
  • one or a plurality of the photoelectric conversion elements may perform infrared photoelectric conversion.
  • the present technology provides an electronic device including the solid-state imaging device according to the present technology.
  • This technique can improve image quality and reliability.
  • the effect described here is not necessarily limited, and may be any effect described in the present technology.
  • FIG. 1 is a cross-sectional view illustrating a configuration example of the photoelectric conversion element according to the first embodiment to which the present technology is applied.
  • FIG. 2 is a cross-sectional view illustrating a configuration example of the photoelectric conversion element according to the first embodiment to which the present technology is applied.
  • FIG. 3 shows a second electrode (Cathode), a photoelectric conversion layer (i-Layer (QD layer)), a p-type buffer layer (P-Buffer) in the photoelectric conversion element of the first embodiment to which the present technology is applied. It is a figure which shows the relationship between a work function adjustment layer (WCL) and a 1st electrode (Anode), and an energy level.
  • WCL work function adjustment layer
  • Au 1st electrode
  • FIG. 4 is a diagram showing a relationship between ITO, ICZO, TiO 2 , PbS, 2T-NATA, HATCN, and ITO and energy levels in the photoelectric conversion element according to the first embodiment to which the present technology is applied.
  • FIG. 5 is a cross-sectional view illustrating a configuration example of the photoelectric conversion element according to the second embodiment to which the present technology is applied.
  • FIG. 6 is a cross-sectional view illustrating a configuration example of the photoelectric conversion element according to the second embodiment to which the present technology is applied.
  • FIG. 7 shows a second electrode (Cathode), a photoelectric conversion layer (i-Layer (QD layer)), a p-type buffer layer (P-Buffer), in the photoelectric conversion element of the second embodiment to which the present technology is applied. It is a figure which shows the relationship between a work function adjustment layer (WCL) and a 1st electrode (Anode), and an energy level.
  • FIG. 8 is a diagram showing a relationship between ITO, ICZO, TiO 2 , PbS, 2T-NATA, MoO 3, and ITO and energy levels in the photoelectric conversion element of the second embodiment to which the present technology is applied. .
  • FIG. 1 work function adjustment layer
  • FIG. 9 is a schematic cross-sectional view of an image sensor that constitutes the solid-state imaging device according to the third embodiment to which the present technology is applied.
  • FIG. 10 is a schematic sectional view of the first photoelectric conversion element shown in FIG.
  • FIG. 11 is an equivalent circuit diagram of the imaging device shown in FIG.
  • FIG. 12 is a schematic diagram showing the arrangement of the transistors constituting the lower electrode and control unit of the image sensor shown in FIG.
  • FIG. 13 is a diagram for explaining the operating principle of the first photoelectric conversion element shown in FIG. 9.
  • FIG. 14 is a schematic cross-sectional view for explaining a method of manufacturing the image sensor shown in FIG.
  • FIG. 15 is a schematic cross-sectional view illustrating a process following FIG. FIG.
  • FIG. 16 is a schematic cross-sectional view illustrating a process following FIG.
  • FIG. 17 is a schematic cross-sectional view illustrating a process following FIG.
  • FIG. 18 is a schematic cross-sectional view illustrating a process following FIG.
  • FIG. 19 is a timing chart illustrating an operation example of the first photoelectric conversion element illustrated in FIG. 9.
  • FIG. 20 is a block diagram illustrating a configuration of a solid-state imaging device according to the third embodiment of the present technology using the imaging device illustrated in FIG. 9 as a pixel.
  • FIG. 21 is a diagram illustrating a usage example of the solid-state imaging device to which the present technology is applied.
  • FIG. 22 is a functional block diagram of an example of an electronic apparatus to which the present technology is applied.
  • the photoelectric conversion element according to the first embodiment (Example 1 of the photoelectric conversion element) according to the present technology includes a first electrode, a work function adjustment layer, a photoelectric conversion layer, a charge accumulation layer, and a second electrode. At least in order, the first electrode is an anode, the second electrode is a cathode, the photoelectric conversion layer includes a quantum dot material, and a work function adjusting layer is disposed in contact with the first electrode, and an organic compound is provided.
  • a photoelectric conversion element including and satisfying the following formula 1 is provided.
  • E A1 in the formula 1 represents the electron affinity of the work function adjusting layer
  • WF 2 in the formula 1 represents the work function of the second electrode.
  • the pn polarity is inverted and the dark current can be reduced.
  • components of dark current a component in which electrons flow from the first electrode to the photoelectric conversion layer (quantum dot material), a hole in the work function adjustment layer or a hole in the P-type buffer layer, and a photoelectric conversion layer (quantum dot material)
  • a component that recombines with other electrons There is a component that recombines with other electrons.
  • the photoelectric conversion element of the first embodiment according to the present technology can suppress these two components.
  • FIG. 1 shows a photoelectric conversion element 100 that is an example of the photoelectric conversion element according to the first embodiment of the present technology.
  • FIG. 1 is a cross-sectional view of the photoelectric conversion element 100.
  • the photoelectric conversion element 100 includes at least a first electrode 101, a work function adjustment layer 102, a photoelectric conversion layer 103, a charge storage layer 104, and a second electrode 105 in this order, and the first electrode 101 is an anode.
  • the second electrode 105 is a cathode.
  • the second electrode 105 is formed apart from the third electrode 107 and is formed to face the charge storage layer 104 with the first insulating layer 106 interposed therebetween.
  • the third electrode 107 includes a first insulating layer 106 between the second electrode 105 and the charge storage layer 104, and is disposed to face the second electrode 105 and the first insulating layer 106.
  • the photoelectric conversion layer 103 is electrically connected through an opening provided in the one insulating layer 106.
  • the work function adjusting layer 102 is disposed in contact with the first electrode 101 and contains an organic compound.
  • the photoelectric conversion layer 103 includes a quantum dot material.
  • the work function adjustment layer and the photoelectric conversion layer may satisfy the following Expression 2.
  • I P3 in the formula 2 represents the ionization potential of the quantum dot material of the photoelectric conversion layer.
  • the photoelectric conversion element according to the first embodiment of the present technology may further include a p-type buffer layer between the work function adjustment layer and the photoelectric conversion layer, and may satisfy Equation 3 below.
  • E A1 in the equation 3 represents the electron affinity of the work function adjusting layer
  • I P2 in the equation 3 represents the ionization potential of the p-type buffer layer.
  • the photoelectric conversion element of the first embodiment according to the present technology may satisfy the following Expression 4.
  • E A2 in the formula 4 represents the electron affinity of the p-type buffer layer
  • E A3 in the formula 4 represents the electron affinity of the quantum dot material of the photoelectric conversion layer.
  • the electron affinity (E A2 ) of the p-type buffer layer is desirably smaller than the electron affinity (E A3 ) of the quantum dot material, more preferably 0.5 eV or more, and even more preferably 1.0 eV. It is preferable that it is smaller.
  • the ionization potential (I P2 ) of the p-type buffer is preferably larger than the electron affinity (E A3 ) of the quantum dot material, and more preferably 0.5 eV or more.
  • the photoelectric conversion element according to the first embodiment of the present technology may further include an n-type buffer layer between the photoelectric conversion layer and the charge storage layer.
  • FIG. 2 shows a photoelectric conversion element 200 that is an example of the photoelectric conversion element according to the first embodiment of the present technology.
  • FIG. 2 is a cross-sectional view of the photoelectric conversion element 200.
  • the photoelectric conversion element 200 includes a first electrode 201, a work function adjustment layer 202, a p-type buffer layer 208, a photoelectric conversion layer 203, an n-type buffer layer 209, a charge storage layer 204, a second electrode 205,
  • the first electrode 201 is an anode
  • the second electrode 205 is a cathode.
  • the second electrode 205 is formed away from the third electrode 207 and is formed to face the charge storage layer 204 with the first insulating layer 206 interposed therebetween.
  • the third electrode 207 has a first insulating layer 206 between the second electrode 205 and the charge storage layer 204, is opposed to the second electrode 205 and the first insulating layer 206, and The photoelectric conversion layer 203 is electrically connected through an opening provided in the one insulating layer 206.
  • the work function adjusting layer 202 is disposed in contact with the first electrode 201 and contains an organic compound.
  • the photoelectric conversion layer 203 includes quantum dots.
  • the work function adjusting layers 102 and 202 contain an organic compound as described above, and examples of organic compounds that function as a work function adjusting layer (WCL) include 2,3,5,6-tetrafluoro-tetracyanoquinodimethane.
  • F4-TCNQ 2,3,5-trifluoro-tetracyanoquinodimethane
  • F3-TCNQ 2,5-difluoro-tetracyanoquinodimethane
  • F2-TCNQ 2-fluoro-tetracyanoquino Dimethane
  • F1-TCNQ 2-trifluoromethyl-tetracyanoquinodimethane
  • CF3-TCNQ 1,3,4,5,7,8-hexafluoro-tetracyanonaphthoquinodimethane
  • F6-TCNQ tetracyanoquinodimethane derivatives and hexaaza such as 1,4,5,8,9,12-hexaazatriphenylene-2,3,6,7
  • the quantum dot material contained in the photoelectric conversion layers 103 and 203 is, for example, at least one of TiO 2 , ZnO, WO 3 , NiO, MoO 3 , CuO, Ga 2 O 3 , SrTiO 3 , SnO 2 , InSnOx, Nb 2 O.
  • the particle size of the quantum dot material may be any size, but the particle size of the quantum dot material may be changed as appropriate in accordance with the light to be absorbed (absorbing wavelength band).
  • a core-shell structure in which the periphery of the particle is covered with another material may be used, and examples of the material constituting the shell include PbO, PbO 2 , Pb 3 O 4 , ZnS, ZnSe, and ZnTe.
  • the surface of the semiconductor nanoparticles constituting the quantum dots may be coordinated with ligands that interact, thereby controlling the particle size of the semiconductor nanoparticles and suppressing deactivation from surface defect sites, or The effect of controlling the conduction path is expected.
  • the ligand is composed of an adsorbing group that interacts and an alkyl chain bonded thereto, and the number of carbons in the alkyl chain is, for example, 2 to 50. , Hydroxyl, thiol.
  • halogen elements such as chlorine (Cl), bromine (Br), and iodine (I) may be used.
  • materials constituting the charge storage layer 104 and the charge storage layer 204 include oxide semiconductor materials such as IGZO; transition metal dichalcogenide; silicon carbide; diamond; graphene; carbon nanotubes; And organic semiconductor materials such as condensed heterocyclic compounds.
  • oxide semiconductor materials such as IGZO
  • transition metal dichalcogenide silicon carbide
  • diamond diamond
  • graphene carbon nanotubes
  • organic semiconductor materials such as condensed heterocyclic compounds.
  • the third electrodes 107 and 207 and the second electrodes 105 and 205 are preferably transparent electrodes made of a transparent conductive material.
  • the third electrodes 107 and 207 and the second electrode 105 and 205 may be made of the same material, or may be made of different materials.
  • the third electrodes 107 and 207 and the second electrodes 105 and 205 can be formed by sputtering or chemical vapor deposition (CVD).
  • the photoelectric conversion element according to the first embodiment of the present technology may include the transfer electrode 11C between the third electrodes 107 and 207 and the second electrodes 105 and 205.
  • the transfer electrode is preferably a transparent electrode made of a transparent conductive material.
  • the third electrodes 107 and 207 and the second electrode 105 and 205 may be made of the same material, or may be made of different materials.
  • the third electrodes 107 and 207 and the second electrodes 105 and 205 can be formed by sputtering or chemical vapor deposition (CVD).
  • transparent conductive materials examples include indium oxide, indium-tin oxide (including ITO, Indium Tin Oxide, Sn-doped In 2 O 3 , crystalline ITO, and amorphous ITO), and zinc oxide with indium added as a dopant.
  • Indium-zinc oxide IZO
  • indium-gallium oxide IGO
  • indium-gallium-zinc oxide indium and gallium are added as dopants in zinc oxide
  • indium-tin-zinc oxide indium and tin are added as dopants to zinc oxide
  • IFO F-doped In 2 O 3
  • tin oxide SnO 2
  • ATO SnO and Sb-doped 2
  • SnO 2 of FTO F doped
  • acid Zinc including ZnO doped with other elements
  • aluminum-zinc oxide AZO
  • AZO aluminum-zinc oxide
  • AZO aluminum-zinc oxide
  • gallium-zinc oxide GaZO
  • titanium oxide examples thereof include (TiO 2 ), niobium-titanium oxide (TNO)
  • the first electrodes 101 and 201 are formed of a transparent conductive film such as an indium tin oxide film or an indium zinc oxide film, for example.
  • an insulating dielectric such as a silicon oxide film or TEOS can be adopted.
  • the p-type buffer layer 208 is for accelerating the supply of holes generated in the photoelectric conversion layer 203 to the first electrode 201.
  • molybdenum oxide (MoO 3 ), nickel oxide (NiO), or vanadium oxide is used. (V 2 O 5 ) or the like may be used.
  • PEDOT Poly (3,4-ethylenedithiothiophene)
  • TPD N, N′-Bis (3-methylphenyl) -N, N′-diphenylbenzidine
  • 2T-NATA (4,4 ′, 4 ′′ -Tris
  • the hole transport layer may be composed of an organic material such as -naphthyl (phenyl) amino] triphenylamine).
  • the n-type buffer layer 209 is for accelerating the supply of electrons generated in the photoelectric conversion layer 203 to the third electrode 207, and is made of, for example, titanium oxide (TiO 2 ), zinc oxide (ZnO), or the like. It may be.
  • the n-type buffer layer 209 may be configured by stacking titanium oxide and zinc oxide.
  • the n-type buffer layer 209 may be made of a polymer semiconductor material.
  • polymer semiconductor material examples include compounds represented by the following general formula (1) and general formula (2) (naphthalenediimide derivatives) containing naphthalenediimide as a mother skeleton.
  • naphthalenediimide derivatives examples include compounds represented by the following formula (1-1).
  • R 1 in the formula (1) is each independently a hydrogen atom, a linear, branched or cyclic alkyl group, a phenyl group, a group having a linear or condensed aromatic compound, or a group having a heterocyclic compound.
  • R 1 and R 2 in the formula (2) are each independently a hydrogen atom, a linear, branched or cyclic alkyl group, a phenyl group, a group having a linear or condensed aromatic compound, a heterocyclic compound , A group having a halide, a partial fluoroalkyl group, a perfluoroalkyl group, a silylalkyl group, a silylalkoxy group, an arylsilyl group, or a derivative thereof.
  • X is a compound in which one or more, five or less heteroaromatic ring compounds are aromatic compounds, heteroaromatic compounds, polycyclic aromatic ring compounds, or heteropolycyclic aromatic ring compounds, and may have a substituent. .
  • FIG. 3 shows a second electrode (Cathode), a photoelectric conversion layer (i-Layer (QD layer)), a p-type buffer layer (P-Buffer), a work in the photoelectric conversion element according to the first embodiment of the present technology. It is a figure which shows the relationship between a function adjustment layer (WCL) and a 1st electrode (Anode), and an energy level.
  • FIG. 4 is a diagram illustrating the relationship between ITO, IGZO, TiO 2 , PbS, 2T-NATA, HATCN, and ITO and energy levels in the photoelectric conversion element according to the first embodiment of the present technology.
  • the signal charges (electrons) flow from the higher energy level to the lower energy level in FIG. Conversely, holes flow from the lower energy level to the higher energy level in FIG.
  • the photoelectric conversion element according to the first embodiment of the present technology includes E A1 ⁇ I P3 (Equation 1), E A1 ⁇ WF 2 (Equation 2), E Since at least A1 ⁇ I P2 (Formula 3) and E A2 ⁇ E A3 (Formula 4) are satisfied, the pn polarity is inverted, and the reduction of dark current can be further promoted.
  • the photoelectric conversion element of the first embodiment according to the present technology can be manufactured using a known method, for example, a sputtering method, a method of patterning by a photolithography technique, dry etching or wet etching, or a wet film forming method. it can.
  • wet film formation methods include spin coating, dipping, casting, screen printing, inkjet printing, offset printing, gravure printing, various printing methods, stamping, spraying, air doctor coater, Blade coater method, rod coater method, knife coater method, squeeze coater method, reverse roll coater method, transfer roll coater method, gravure coater method, kiss coater method, cast coater method, spray coater method, slit orifice coater method, calendar coater method, etc.
  • Various coating methods are mentioned.
  • the photoelectric conversion element according to the second embodiment (photoelectric conversion element example 2) according to the present technology includes a first electrode, a work function adjustment layer, a photoelectric conversion layer, a charge accumulation layer, and a second electrode. At least in order, the first electrode is an anode, the second electrode is a cathode, the photoelectric conversion layer includes a quantum dot material, and the work function adjusting layer is disposed in contact with the first electrode.
  • fills following formula 5 is provided.
  • WF 0 in Equation 5 represents the work function of the work function adjusting layer
  • WF 2 in Equation 5 represents the work function of the second electrode
  • the pn polarity is inverted and the dark current can be reduced.
  • components of dark current a component in which electrons flow from the first electrode to the photoelectric conversion layer (quantum dot material), a hole in the work function adjustment layer or a hole in the p-type buffer layer, and a photoelectric conversion layer (quantum dot material)
  • a component that recombines with other electrons There is a component that recombines with other electrons.
  • the photoelectric conversion element of the second embodiment according to the present technology can suppress these two components.
  • FIG. 5 shows a photoelectric conversion element 500 which is an example of the photoelectric conversion element of the second embodiment according to the present technology.
  • FIG. 5 is a cross-sectional view of the photoelectric conversion element 500.
  • the photoelectric conversion element 500 includes at least a first electrode 501, a work function adjustment layer 502, a photoelectric conversion layer 503, a charge storage layer 504, and a second electrode 505 in this order, and the first electrode 501 is an anode.
  • the second electrode 505 is a cathode.
  • the second electrode 505 is formed to be separated from the third electrode 507 and is opposed to the charge storage layer 504 with the first insulating layer 506 interposed therebetween.
  • the third electrode 507 includes a first insulating layer 506 between the second electrode 505 and the charge storage layer 504, and is disposed to face the second electrode 505 and the first insulating layer 506.
  • the photoelectric conversion layer 503 is electrically connected through an opening provided in the one insulating layer 506.
  • the work function adjusting layer 502 is disposed in contact with the first electrode 501 and contains an inorganic compound.
  • the photoelectric conversion layer 503 includes quantum dots.
  • the work function adjustment layer and the photoelectric conversion layer may satisfy Expression 6 below. WF 0 ⁇ I P3 ... Formula 6
  • I P3 in the formula 6 represents an ionization potential of the quantum dot material of the photoelectric conversion layer.
  • the photoelectric conversion element according to the second embodiment of the present technology may further include a p-type buffer layer between the work function adjustment layer and the photoelectric conversion layer, and may satisfy the following Expression 7.
  • Formula WF 0 in 7 indicates the work function of the work function adjustment layer
  • I P2 in formula 7 indicates the ionization potential of the p-type buffer layer.
  • the photoelectric conversion element of the first embodiment according to the present technology may satisfy the following Expression 8.
  • E A2 in the equation 8 represents the electron affinity of the p-type buffer layer
  • E A3 in the equation 4 represents the electron affinity of the quantum dot material of the photoelectric conversion layer.
  • the electron affinity (E A2 ) of the p-type buffer layer is desirably smaller than the electron affinity (E A3 ) of the quantum dot material, more preferably 0.5 eV or more, and even more preferably 1.0 eV. It is preferable that it is smaller.
  • the ionization potential (I P2 ) of the p-type buffer is preferably larger than the electron affinity (E A3 ) of the quantum dot material, and more preferably 0.5 eV or more.
  • the photoelectric conversion element according to the second embodiment of the present technology may further include an n-type buffer layer between the photoelectric conversion layer and the charge storage layer.
  • FIG. 6 shows a photoelectric conversion element 600 that is an example of the photoelectric conversion element according to the second embodiment of the present technology.
  • FIG. 6 is a cross-sectional view of the photoelectric conversion element 600.
  • the photoelectric conversion element 600 includes a first electrode 601, a work function adjustment layer 602, a p-type buffer layer 608, a photoelectric conversion layer 603, an n-type buffer layer 609, a charge storage layer 604, and a second electrode 605.
  • the first electrode 601 is an anode
  • the second electrode 605 is a cathode.
  • the second electrode 605 is formed to be separated from the third electrode 607 and is formed to face the charge storage layer 604 with the first insulating layer 606 interposed therebetween.
  • the third electrode 607 includes a first insulating layer 606 between the second electrode 605 and the charge storage layer 604, and is disposed to face the second electrode 605 and the first insulating layer 606.
  • the photoelectric conversion layer 603 is electrically connected through an opening provided in the one insulating layer 606.
  • the work function adjusting layer 602 is disposed in contact with the first electrode 201 and contains an inorganic compound.
  • the photoelectric conversion layer 603 includes quantum dots.
  • the work function adjustment layers 502 and 602 include an inorganic compound as described above, and examples of inorganic compounds that function as the work function adjustment layer (WCL) include molybdenum oxide (MoO 3 ), tungsten oxide (WO 3 ), and vanadium oxide. (V 2 O 5 ), transition metal oxides such as rhenium oxide (ReO 3 ), and copper iodide (CuI), antimony chloride (SbCl 5 ), iron oxide (FeCl 3 ), sodium chloride (NaCl), etc. Examples include, but are not limited to, salts.
  • the photoelectric conversion element of the second embodiment according to the present technology is patterned by a known method, for example, a sputtering method, a photolithography technique, and is dry-etched. Alternatively, it can be manufactured using a wet etching method or a wet film forming method.
  • wet film formation methods include spin coating, dipping, casting, screen printing, inkjet printing, offset printing, gravure printing, various printing methods, stamping, spraying, air doctor coater, Blade coater method, rod coater method, knife coater method, squeeze coater method, reverse roll coater method, transfer roll coater method, gravure coater method, kiss coater method, cast coater method, spray coater method, slit orifice coater method, calendar coater method, etc.
  • Various coating methods are mentioned.
  • FIG. 7 shows a second electrode (Cathode), a photoelectric conversion layer (i-Layer (QD layer)), a p-type buffer layer (P-Buffer), a work in the photoelectric conversion element of the second embodiment according to the present technology. It is a figure which shows the relationship between a function adjustment layer (WCL) and a 1st electrode (Anode), and an energy level.
  • FIG. 8 is a diagram illustrating a relationship between ITO, IGZO, TiO 2 , PbS, 2T-NATA, MoO 3, and ITO and energy levels in the photoelectric conversion element according to the second embodiment of the present technology.
  • the signal charges (electrons) flow from the higher energy level to the lower energy level in FIG. Conversely, holes flow from the lowest energy level to the higher energy level in FIG.
  • the photoelectric conversion element according to the second embodiment of the present technology has WF 0 ⁇ I P3 (Formula 5), WF 0 ⁇ WF 2 (Formula 6), WF Since at least 0 ⁇ I P2 (Equation 7) and E A2 ⁇ E A3 (Equation 8) are satisfied, the pn polarity is inverted, and the reduction of dark current can be further promoted.
  • FIG. 9 schematically illustrates a cross-sectional configuration of the imaging element 1 that configures the solid-state imaging device according to the third embodiment of the present technology.
  • FIG. 10 schematically shows an enlarged cross-sectional configuration of a main part (photoelectric conversion element 10) of the imaging element 1 shown in FIG.
  • FIG. 11 is an equivalent circuit diagram of the image sensor 1 shown in FIG.
  • FIG. 12 schematically shows the arrangement of the transistors constituting the lower electrode 11 and the control unit of the image sensor 1 shown in FIG.
  • the imaging device 1 constitutes one pixel (unit pixel P) in a solid-state imaging device (imaging device 1001; see FIG. 20) such as a CMOS image sensor.
  • the imaging element 1 is, for example, one in which the photoelectric conversion element 10 is provided on the first surface (back surface) 30 ⁇ / b> A side of the semiconductor substrate 30.
  • the photoelectric conversion element 10 has a photoelectric conversion layer 15 formed using semiconductor nanoparticles between a lower electrode 11 and an upper electrode 16 (first electrode) arranged to face each other. Between the lower electrode 11 and the photoelectric conversion layer 15, a first semiconductor layer (charge storage layer) 13 is provided via an insulating layer (first insulating layer) 12.
  • the lower electrode 11 includes a readout electrode (third electrode) 11A, a storage electrode (second electrode) 11B, for example, a readout electrode (third electrode) 11A and a storage electrode (second electrode) 11B as a plurality of independent electrodes.
  • the storage electrode 11B and the transfer electrode 11C are covered with the insulating layer 12, and the readout electrode 11A is connected to the first semiconductor layer through the opening 12H provided in the insulating layer 12. 13 is electrically connected.
  • the photoelectric conversion element 10 has a configuration in which a second semiconductor layer 14 that satisfies formulas (1) to (3) described later is provided between the first semiconductor layer 13 and the photoelectric conversion layer 15. Have.
  • the photoelectric conversion element 10 is a photoelectric conversion element that absorbs light corresponding to a part or all of a selective wavelength range (for example, 700 nm to 2500 nm) and generates electron-hole pairs.
  • the photoelectric conversion element 10 includes, for example, a lower electrode 11, an insulating layer 12, a first semiconductor layer 13, a second semiconductor layer 14, and a photoelectric conversion layer 15 on the first surface 30 ⁇ / b> A side of the semiconductor substrate 30.
  • the upper electrode 16 has the structure laminated
  • the fixed charge layer 17A, the dielectric layer 17B, the interlayer insulating layer 18 and the like are omitted.
  • the lower electrode 11 is separately formed for each unit pixel P, and will be described in detail later.
  • the lower electrode 11 includes a readout electrode 11A, a storage electrode 11B, and a transfer electrode 11C that are separated from each other with an insulating layer 12 therebetween.
  • the first semiconductor layer 13, the second semiconductor layer 14, the photoelectric conversion layer 15, and the upper electrode 16 are illustrated as being separately formed for each image sensor 1. It may be provided as a common continuous layer.
  • the lower electrode 11 includes, for example, mutually independent readout electrodes (third electrodes) 11A, storage electrodes (second electrodes) 11B, and transfer electrodes 11C.
  • the lower electrode 11 can be formed using, for example, a light-transmitting conductive material (transparent conductive material).
  • the band gap energy of the transparent conductive material is preferably 2.5 eV or more, for example, and preferably 3.1 eV or more.
  • a metal oxide can be raised as the transparent conductive material.
  • indium-zinc oxide indium-tin oxide (including ITO, Indium Tin Oxide, Sn-doped In 2 O 3 , crystalline ITO and amorphous ITO), indium-zinc added with indium as a dopant to zinc oxide Oxide (IZO), Indium-gallium oxide (IGO) with gallium oxide added with indium as a dopant, Indium-gallium-zinc oxide with zinc oxide added with indium and gallium (IGZO, In -GaZnO 4) , indium-tin-zinc oxide (ITZO) obtained by adding indium and tin as dopants to zinc oxide, IFO (F-doped In 2 O 3 ), tin oxide (SnO 2 ), ATO (Sb-doped SnO 2 ), FTO (F-doped SnO 2 ), zinc oxide (Including ZnO doped with other elements), aluminum-zinc oxide (AZO) obtained by adding aluminum as a dopant
  • the transparent electrode which uses gallium oxide, titanium oxide, niobium oxide, nickel oxide etc. as a base layer can be mentioned.
  • the film thickness of the lower electrode 11 in the Y-axis direction (hereinafter simply referred to as thickness) is, for example, 2 ⁇ 10 ⁇ 8 m or more and 2 ⁇ 10 ⁇ 7 m or less, preferably 3 ⁇ 10 ⁇ 8 m or more and 1 ⁇ . 10 ⁇ 7 m or less.
  • the lower electrode 11 is formed of, for example, platinum (Pt), gold (Au), palladium (Pd), chromium (Cr), nickel (Ni), aluminum ( Al), silver (Ag), tantalum (Ta), tungsten (W), copper (Cu), titanium (Ti), indium (In), tin (Sn), iron (Fe), cobalt (Co) and molybdenum ( It can be formed as a single layer film or a laminated film using a metal such as Mo) or an alloy thereof. Specifically, it can be formed using Al—Nd (alloy of aluminum and neodymium), ASC (alloy of aluminum, samarium and copper) or the like.
  • the lower electrode 11 is formed using a conductive material such as the above-described metal or an alloy thereof, polysilicon containing impurities, a carbon-based material, an oxide semiconductor material, a carbon nanotube, and graphene. It may be.
  • the lower electrode 11 may be formed using an organic material (conductive polymer) such as poly (3,4-ethylenedioxythiophene) / polystyrene sulfonic acid [PEDOT / PSS]. The material may be mixed with a binder (polymer) to form a paste or ink, which may be cured.
  • the readout electrode 11A is for transferring the signal charge generated in the photoelectric conversion layer 15 to the floating diffusion FD1.
  • the readout electrode 11A is provided on the second surface (front surface) 30B side of the semiconductor substrate 20 via, for example, the upper first contact 18A, the pad portion 39A, the through electrode 34, the connection portion 41A, and the lower second contact 46. It is connected to the floating diffusion FD1.
  • the storage electrode 11 ⁇ / b> B is for storing signal charges (electrons) in the first semiconductor layer 13 among the charges generated in the photoelectric conversion layer 15.
  • the storage electrode 11B is preferably larger than the readout electrode 11A, so that a large amount of charge can be stored.
  • the transfer electrode 11C is for improving the efficiency of transferring the charge accumulated in the storage electrode 11B to the read electrode 11A, and is provided between the read electrode 11A and the storage electrode 11B.
  • the transfer electrode 11C is connected to, for example, a pixel drive circuit constituting a drive circuit via the upper third contact 18C and the pad portion 39C.
  • the readout electrode 11A, the storage electrode 11B, and the transfer electrode 11C can apply a voltage independently.
  • the insulating layer (first insulating layer) 12 is for electrically separating the storage electrode 11B and the transfer electrode 11C from the first semiconductor layer (charge storage layer) 13.
  • the insulating layer 12 is provided on the interlayer insulating layer 18 so as to cover the lower electrode 11.
  • the insulating layer 12 is provided with an opening 12H on the readout electrode 11A of the lower electrode 11, and the readout electrode 11A and the first semiconductor layer 13 are electrically connected through the opening 12H.
  • the side surface of the opening 12H preferably has an inclination that widens toward the light incident side S1. Thereby, the movement of charges from the first semiconductor layer 13 to the readout electrode 11A becomes smoother.
  • Examples of the material of the insulating layer 12 include inorganic insulating materials such as silicon oxide materials, metal oxide high dielectric insulating materials such as silicon nitride (SiN x ), and aluminum oxide (Al 2 O 3 ).
  • inorganic insulating materials such as silicon oxide materials, metal oxide high dielectric insulating materials such as silicon nitride (SiN x ), and aluminum oxide (Al 2 O 3 ).
  • PMMA polymethyl methacrylate
  • PVP polyvinylphenol
  • PVA polyvinyl alcohol
  • PET polyethylene terephthalate
  • sirene N-2 (aminoethyl) 3-aminopropyltrimethoxy
  • Silanol derivatives silane coupling agents
  • silane AEAPTMS
  • MPTMS 3-mercaptopropyltrimethoxysilane
  • OTS octadecyltrichlorosilane
  • novolac-type phenol resin fluorine-based resin
  • organic insulating material exemplified by linear hydrocarbons having a functional group capable of binding to the control electrode at one end can be given, and these can also be used in combination.
  • silicon oxide-based material include silicon oxide (SiO x ), BPSG, PSG, BSG, AsSG, PbSG, silicon oxynitride (SiON), SOG (spin-on-glass), low dielectric constant materials (for example, polyaryl ether, Cycloperfluorocarbon polymer and benzocyclobutene, cyclic fluororesin, polytetrafluoroethylene, fluorinated aryl ether, fluorinated polyimide, amorphous carbon and organic SOG).
  • the first semiconductor layer (charge storage layer) 13 is for accumulating signal charges generated in the photoelectric conversion layer 15 and transferring them to the readout electrode 11A.
  • the first semiconductor layer 13 is preferably formed using a material having a charge mobility higher than that of the photoelectric conversion layer 15 and a large band gap. Thereby, for example, the charge transfer rate can be improved, and the injection of holes from the read electrode 11A to the first semiconductor layer 13 is suppressed.
  • the first semiconductor layer 13 includes, for example, an oxide semiconductor material.
  • the oxide semiconductor material include IGZO (In—Ga—Zn—O-based oxide semiconductor), ZTO (Zn—Sn—O-based oxide semiconductor), and IGZTO (In—Ga—Zn—Sn—O-based oxide).
  • Oxide semiconductor Ga—Sn—O-based oxide semiconductor
  • IGO In—Ga—O-based oxide semiconductor.
  • the thickness of the first semiconductor layer 13 is, for example, 30 nm to 200 nm, preferably 60 nm to 150 nm.
  • the second semiconductor layer (n-type buffer layer) 14 is for promoting the supply of electrons generated in the photoelectric conversion layer 15 to the first semiconductor layer.
  • ZnO, TiO 2 , IGZO, ZTO, Zn 2 SnO 4 , InGaZnSnO, GTO, Ga 2 O 3 : SnO 2, IGO, or the like may be used, and the second semiconductor layer 14 may be formed by stacking a plurality of the above materials.
  • the thickness of the second semiconductor layer 14 is, for example, not less than 1 nm and not more than 20 nm, preferably not less than 3 nm and not more than 10 nm.
  • the second semiconductor layer 14 may be made of a polymer semiconductor material.
  • polymer semiconductor material examples include compounds represented by the following general formula (1) and general formula (2) (naphthalenediimide derivatives) containing naphthalenediimide as a mother skeleton.
  • naphthalenediimide derivatives examples include compounds represented by the following formula (1-1).
  • R 1 in the formula (1) is each independently a hydrogen atom, a linear, branched or cyclic alkyl group, a phenyl group, a group having a linear or condensed aromatic compound, or a group having a heterocyclic compound.
  • R 1 and R 2 in the formula (2) are each independently a hydrogen atom, a linear, branched or cyclic alkyl group, a phenyl group, a group having a linear or condensed aromatic compound, a heterocyclic compound , A group having a halide, a partial fluoroalkyl group, a perfluoroalkyl group, a silylalkyl group, a silylalkoxy group, an arylsilyl group, or a derivative thereof.
  • X is a compound in which one or more, five or less heteroaromatic ring compounds are aromatic compounds, heteroaromatic compounds, polycyclic aromatic ring compounds, or heteropolycyclic aromatic ring compounds, and may have a substituent. .
  • the photoelectric conversion layer 15 converts light energy into electrical energy, and provides, for example, a field where excitons generated when absorbing light in a wavelength range of 400 nm to 2500 nm are separated into electrons and holes. Is.
  • the thickness of the photoelectric conversion layer 15 is, for example, not less than 100 nm and not more than 1000 nm, preferably not less than 300 nm and not more than 800 nm.
  • the photoelectric conversion layer 15 is formed including semiconductor nanoparticles constituting quantum dots.
  • Semiconductor nanoparticles are generally particles having a particle size of several to several tens of nm. Examples of the material constituting the semiconductor nanoparticles include at least one of TiO 2 , ZnO, WO 3 , NiO, MoO 3 , CuO, Ga 2 O 3 , SrTiO 3 , SnO 2 , InSnOx, Nb 2 O 3 , MnO 2.
  • the particle size of the quantum dot material may be any size, but the particle size of the quantum dot material may be changed as appropriate in accordance with the light to be absorbed (absorbing wavelength band).
  • a core-shell structure in which the periphery of the particle is covered with another material may be used, and examples of the material constituting the shell include PbO, PbO 2 , Pb 3 O 4 , ZnS, ZnSe, and ZnTe.
  • Semiconductor nanoparticles have a larger band gap due to the quantum confinement effect when the particle size is smaller than twice the exciton-bohr radius of the material.
  • the semiconductor nanoparticles which comprise the photoelectric converting layer 15 are 3 nm or more and 6 nm or less in average particle diameter in PbS, for example.
  • the surface of the semiconductor nanoparticle may be coordinated with an interacting ligand, which controls the particle size of the semiconductor nanoparticle, suppresses deactivation from surface defect sites, or controls the conduction path. Such effects are expected.
  • the ligand is composed of an adsorbing group that interacts and an alkyl chain bonded thereto, and the number of carbons in the alkyl chain is, for example, 2 to 50. , Hydroxyl, thiol.
  • halogen elements such as chlorine (Cl), bromine (Br), and iodine (I) may be used.
  • a work function adjusting layer is disposed between the upper electrode (first electrode) 16 and the photoelectric conversion layer 15.
  • the work function adjusting layer may contain an organic compound.
  • the organic compound functioning as the work function adjusting layer (WCL) include 2,3,5,6-tetrafluoro-tetracyanoquinodimethane (F4-TCNQ).
  • the work function adjusting layer may contain an inorganic compound.
  • inorganic compounds that function as the work function adjusting layer include molybdenum oxide (MoO 3 ), tungsten oxide (WO 3 ), and vanadium oxide (V 2 O 5 ), transition metal oxides such as rhenium oxide (ReO 3 ), and salts such as copper iodide (CuI), antimony chloride (SbCl 5 ), iron oxide (FeCl 3 ), and sodium chloride (NaCl). Although it is mentioned, it is not limited to these.
  • the image sensor 1 may include a p-type buffer layer.
  • the p-type buffer layer is for accelerating the supply of holes generated in the photoelectric conversion layer 15 to the first electrode 201.
  • MoO 3 molybdenum oxide
  • NiO nickel oxide
  • V 2 O 5 vanadium oxide
  • PEDOT Poly (3,4-ethylenedithiothiophene)
  • TPD N, N′-Bis (3-methylphenyl) -N, N′-diphenylbenzidine
  • 2T-NATA 4,4 ′, 4 ′′ -Tris
  • the p-type buffer layer may be composed of an organic material such as (naphthyl (phenyl) amino] triphenylamine).
  • the upper electrode (first electrode) 16 is made of a light-transmitting conductive material.
  • the upper electrode 16 may be separated for each unit pixel P, or may be formed as a common electrode for each unit pixel P.
  • the thickness of the upper electrode 16 is, for example, 10 nm to 200 nm.
  • the near infrared light L incident on the photoelectric conversion element 10 from the upper electrode 16 side is absorbed by the photoelectric conversion layer 15.
  • the excitons generated thereby are separated into electrons and holes by exciton separation as shown in FIG. 13A, for example.
  • the charges (electrons and holes) generated here are caused by diffusion due to the carrier concentration difference or an internal electric field due to the work function difference between the anode (here, the upper electrode 16) and the cathode (here, the lower electrode 11). For example, as shown in FIG. 13B, they are conveyed to different electrodes.
  • the transport direction of electrons and holes is controlled by applying a potential between the lower electrode 11 and the upper electrode 16.
  • the electrons are carried as signal charges to the lower electrode 11 side.
  • the electrons carried to the lower electrode 11 side are accumulated in the first semiconductor layer 13 on the storage electrode 11B, and then transferred toward the readout electrode 11A and detected as a photocurrent, as shown in FIG. 13C.
  • the second surface 30B of the semiconductor substrate 30 includes, for example, a floating diffusion (floating diffusion layer) FD1 (region 36B in the semiconductor substrate 30) an amplifier transistor (modulation element) AMP, a reset transistor RST, a selection transistor SEL, and a multilayer Wiring 40 is provided.
  • the multilayer wiring 40 has a configuration in which, for example, wiring layers 41, 42, and 43 are laminated in an insulating layer 44.
  • the first surface 30A side of the semiconductor substrate 30 is represented as the light incident side S1
  • the second surface 30B side is represented as the wiring layer side S2.
  • a layer (fixed charge layer) 17A having a fixed charge, a dielectric layer 17B having insulating properties, and an interlayer insulating layer 18 are provided between the first surface 30A of the semiconductor substrate 30 and the lower electrode 11, for example.
  • a protective layer 19 is provided on the upper electrode 16.
  • a light shielding film 21 is provided on the readout electrode 11A, for example.
  • the light shielding film 21A may be provided so as not to cover at least the storage electrode 11B but to cover at least the region of the readout electrode 11A in direct contact with the photoelectric conversion layer 15.
  • the electrode is provided slightly larger than the readout electrode 11A formed in the same layer as the storage electrode 11B.
  • a color filter 22 is provided on the storage electrode 11B, for example.
  • the color filter 22 is for preventing visible light from entering the photoelectric conversion layer 15, for example, and may be provided so as to cover at least the region of the storage electrode 11 ⁇ / b> B.
  • FIG. 9 shows an example in which the light shielding film 21 and the color filter 22 are provided at different positions in the film thickness direction of the protective layer 19, they may be provided at the same position.
  • an optical member such as a planarizing layer (not shown) and an on-chip lens 23 is disposed above the protective layer 19.
  • the fixed charge layer 17A may be a film having a positive fixed charge or a film having a negative fixed charge.
  • the material of the film having a negative fixed charge include hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, and titanium oxide.
  • lanthanum oxide praseodymium oxide, cerium oxide, neodymium oxide, promethium oxide, samarium oxide, europium oxide, gadolinium oxide, terbium oxide, dysprosium oxide, holeium oxide, thulium oxide, ytterbium oxide, lutetium oxide
  • an yttrium oxide, an aluminum nitride film, a hafnium oxynitride film, an aluminum oxynitride film, or the like may be used.
  • the fixed charge layer 17A may have a configuration in which two or more kinds of films are stacked. Thereby, for example, in the case of a film having a negative fixed charge, the function as the hole accumulation layer can be further enhanced.
  • the material of the dielectric layer 17B is not particularly limited.
  • the dielectric layer 17B is formed of a silicon oxide film, TEOS, a silicon nitride film, a silicon oxynitride film, or the like.
  • the interlayer insulating layer (sometimes referred to as a second insulating layer) 18 is, for example, a single layer film made of one of silicon oxide, silicon nitride, silicon oxynitride (SiON), or the like, or these It is comprised by the laminated film which consists of 2 or more types of them.
  • the protective layer 19 is made of a light-transmitting material.
  • the protective layer 19 is a single-layer film made of any of silicon oxide, silicon nitride, silicon oxynitride, or the like, or a laminated film made of two or more of them. It is comprised by.
  • the thickness of the protective layer 19 is, for example, 100 nm to 30000 nm.
  • a through electrode 34 is provided between the first surface 30A and the second surface 30B of the semiconductor substrate 30.
  • the photoelectric conversion element 10 is connected to the gate Gamp of the amplifier transistor AMP and one source / drain region 36B of the reset transistor RST (reset transistor Tr1rst) that also serves as the floating diffusion FD1 through the through electrode 34.
  • the signal charge generated in the photoelectric conversion element 10 on the first surface 30A side of the semiconductor substrate 30 is favorably transferred to the second surface 30B side of the semiconductor substrate 30 through the through electrode 34, It is possible to improve the characteristics.
  • the lower end of the through electrode 34 is connected to a connection portion 41A in the wiring layer 41, and the connection portion 41A and the gate Gamp of the amplifier transistor AMP are connected via a lower first contact 45.
  • the connection portion 41A and the floating diffusion FD1 (region 36B) are connected via, for example, the lower second contact 46.
  • the upper end of the through electrode 34 is connected to the readout electrode 11A via, for example, the pad portion 39A and the upper first contact 18A.
  • the through electrode 34 has a function as a connector between the photoelectric conversion element 10 and the gate Gamp of the amplifier transistor AMP and the floating diffusion FD1, and serves as a transmission path for electric charges (here, electrons) generated in the photoelectric conversion element 10. It is.
  • the reset gate Grst of the reset transistor RST is arranged. Thereby, the charge accumulated in the floating diffusion FD1 can be reset by the reset transistor RST.
  • the semiconductor substrate 30 is composed of, for example, an n-type silicon (Si) substrate and has a p-well 31 in a predetermined region. On the second surface 30B of the p-well 31, the above-described amplifier transistor AMP, reset transistor RST, selection transistor SEL, and the like are provided. In addition, a peripheral circuit (not shown) including a logic circuit or the like is provided in the peripheral portion of the semiconductor substrate 30.
  • the reset transistor RST reset transistor Tr1rst resets the charge transferred from the photoelectric conversion element 10 to the floating diffusion FD1, and is configured by a MOS transistor, for example.
  • the reset transistor Tr1rst includes a reset gate Grst, a channel formation region 36A, and source / drain regions 36B and 36C.
  • the reset gate Grst is connected to the reset line RST1, and one source / drain region 36B of the reset transistor Tr1rst also serves as the floating diffusion FD1.
  • the other source / drain region 36C constituting the reset transistor Tr1rst is connected to the power supply VDD.
  • the amplifier transistor AMP is a modulation element that modulates the amount of charge generated in the photoelectric conversion element 10 into a voltage, and is configured by, for example, a MOS transistor.
  • the amplifier transistor AMP includes a gate Gamp, a channel formation region 35A, and source / drain regions 35B and 35C.
  • the gate Gamp is connected to the read electrode 11A and one source / drain region 36B (floating diffusion FD1) of the reset transistor Tr1rst through the lower first contact 45, the connecting portion 41A, the lower second contact 46, the through electrode 34, and the like.
  • one source / drain region 35B shares a region with the other source / drain region 36C constituting the reset transistor Tr1rst and is connected to the power supply VDD.
  • the selection transistor SEL selection transistor TR1sel
  • the selection transistor SEL includes a gate Gsel, a channel formation region 34A, and source / drain regions 34B and 34C.
  • the gate Gsel is connected to the selection line SEL1.
  • One source / drain region 34B shares a region with the other source / drain region 35C constituting the amplifier transistor AMP, and the other source / drain region 34C is a signal line (data output line) VSL1. It is connected to the.
  • the image sensor 1 of the present embodiment can be manufactured as follows, for example.
  • a p-well 31 is formed in the semiconductor substrate 30 as a first conductivity type well.
  • a p + region is formed in the vicinity of the first surface 30 ⁇ / b> A of the semiconductor substrate 30.
  • an n + region that becomes the floating diffusion FD ⁇ b> 1 is formed on the second surface 30 ⁇ / b> B of the semiconductor substrate 30, and then the gate insulating layer 32, the selection transistor SEL, the amplifier transistor AMP, and the reset transistor are formed.
  • a gate wiring layer 47 including each gate of RST is formed.
  • the selection transistor SEL, the amplifier transistor AMP, and the reset transistor RST are formed.
  • the multilayer wiring 40 including the wiring layers 41 to 43 including the lower first contact 45, the lower second contact 46, and the connecting portion 41A and the insulating layer 44 is formed on the second surface 30B of the semiconductor substrate 30.
  • an SOI (Silicon On Insulator) substrate in which a semiconductor substrate 30, a buried oxide film (not shown), and a holding substrate (not shown) are stacked is used.
  • the buried oxide film and the holding substrate are bonded to the first surface 30 ⁇ / b> A of the semiconductor substrate 30. After ion implantation, annealing is performed.
  • a support substrate (not shown) or another semiconductor substrate is joined to the second surface 30B side (multilayer wiring 40 side) of the semiconductor substrate 30 and turned upside down.
  • the semiconductor substrate 30 is separated from the buried oxide film of the SOI substrate and the holding substrate, and the first surface 30A of the semiconductor substrate 30 is exposed.
  • the above steps can be performed by techniques used in a normal CMOS process, such as ion implantation and CVD (Chemical Vapor Deposition).
  • the semiconductor substrate 30 is processed from the first surface 30A side by, for example, dry etching to form, for example, an annular opening 34H.
  • the depth of the opening 34H penetrates from the first surface 30A to the second surface 30B of the semiconductor substrate 30 and reaches, for example, the connecting portion 41A.
  • a negative fixed charge layer 17A is formed on the first surface 30A of the semiconductor substrate 30 and the side surface of the opening 34H. Two or more types of films may be stacked as the negative fixed charge layer 17A. Thereby, the function as a hole accumulation layer can be further enhanced.
  • the dielectric layer 17B is formed.
  • the interlayer insulating layer 18 is formed on the dielectric layer 17B and the pad portions 39A, 39B, and 39C.
  • the interlayer insulating layer 1 is formed by using, for example, a CMP (Chemical Mechanical Polishing) method. The surface of 8 is flattened.
  • openings 18H1, 18H2, and 18H3 are respectively formed in the interlayer insulating layer 18 on the pad portions 39A, 39B, and 39C, and then, for example, Al or the like is formed in the openings 18H1, 18H2, and 18H3. Then, the upper first contact 18A, the upper second contact 18B, and the upper third contact 18C are formed.
  • the conductive film 11x is formed on the interlayer insulating layer 18, the conductive film 21x is placed at predetermined positions (for example, on the pad portion 39A, the pad portion 39B, and the pad portion 39C).
  • a photoresist PR is formed.
  • the read electrode A, the storage electrode 11B, and the transfer electrode 11C shown in FIG. 18 are patterned by etching and removing the photoresist PR.
  • the photoelectric conversion element 10 is connected to the gate Gamp of the amplifier transistor AMP and the floating diffusion FD1 through the through electrode 34. Therefore, electrons (signal charges) of the electron-hole pairs generated in the photoelectric conversion element 10 are taken out from the lower electrode 11 side and transferred to the second surface 30B side of the semiconductor substrate 30 through the through electrode 34. Are accumulated in the floating diffusion FD1. At the same time, the charge amount generated in the photoelectric conversion element 10 is modulated into a voltage by the amplifier transistor AMP.
  • a reset gate Grst of the reset transistor RST is disposed next to the floating diffusion FD1. Thereby, the electric charge accumulated in the floating diffusion FD1 is reset by the reset transistor RST.
  • the photoelectric conversion element 10 is connected not only to the amplifier transistor AMP but also to the floating diffusion FD1 through the through electrode 34, the charge accumulated in the floating diffusion FD1 can be easily obtained by the reset transistor RST. It becomes possible to reset to.
  • FIG. 19 illustrates an operation example of the photoelectric conversion element 10.
  • A shows the potential at the storage electrode 11B
  • B shows the potential at the floating diffusion FD1 (reading electrode 11A)
  • C shows the potential at the gate (Gsel) of the reset transistor TR1rst. It is.
  • voltages are individually applied to the readout electrode 11A, the storage electrode 11B, and the transfer electrode 11C.
  • the potential V1 is applied from the drive circuit to the readout electrode 11A, and the potential V2 is applied to the storage electrode 11B.
  • the potentials V1 and V2 satisfy V1> V2.
  • signal charges (electrons here) generated by the photoelectric conversion are attracted to the storage electrode 11B and stored in the region of the first semiconductor layer 13 facing the storage electrode 11B (storage period).
  • the potential of the region of the first semiconductor layer 13 facing the storage electrode 11B becomes a more positive value as the photoelectric conversion time elapses.
  • the holes are sent from the upper electrode 16 to the drive circuit.
  • a reset operation is performed in the later stage of the accumulation period. Specifically, at timing t1, the scanning unit changes the voltage of the reset signal RST from a low level to a high level. Thereby, in the unit pixel P, the reset transistor TR1rst is turned on. As a result, the voltage of the floating diffusion FD1 is set to the power supply voltage VDD, and the voltage of the floating diffusion FD1 is reset (reset period).
  • the charge is read out. Specifically, at timing t2, the potential V3 is applied from the drive circuit to the readout electrode 11A, the potential V4 is applied to the storage electrode 11B, and the potential V5 is applied to the transfer electrode 11C.
  • the potentials V3, V4, and V5 satisfy V4> V5> V6.
  • the signal charge accumulated in the region corresponding to the storage electrode 11B moves from the storage electrode 11B to the transfer electrode 11C and the readout electrode 11A in this order, and is read from the readout electrode 11A to the floating diffusion FD1. That is, the charge accumulated in the first semiconductor layer 13 is read out to the control unit (transfer period).
  • the potential V1 is again applied from the drive circuit to the read electrode 11A, and the potential V2 is applied to the storage electrode 11B. Thereby, the signal charge generated by the photoelectric conversion is attracted to the storage electrode 11B and stored in the region of the first semiconductor layer 13 facing the storage electrode 11B (storage period).
  • FIG. 20 is a functional block diagram illustrating the solid-state image sensor 1001.
  • the solid-state imaging device 1001 is a CMOS image sensor, and includes a pixel unit 101a as an imaging area, and includes a circuit unit 130 including, for example, a row scanning unit 131, a horizontal selection unit 133, a column scanning unit 134, and a system control unit 132.
  • the circuit unit 130 may be provided in the peripheral region of the pixel unit 1a or the pixel unit 101a, and may be provided in the peripheral region of the pixel unit 101a, or may be stacked with the pixel unit 101a (opposite the pixel unit 101a). May be provided).
  • the pixel unit 101a has, for example, a plurality of unit pixels P (for example, corresponding to solid-state imaging devices (for one pixel) 10, 10A, and 10B) that are two-dimensionally arranged in a matrix.
  • a pixel drive line Lread (specifically, a row selection line and a reset control line) is wired for each pixel row, and a vertical signal line Lsig is wired for each pixel column.
  • the pixel drive line Lread transmits a drive signal for reading a signal from the pixel.
  • One end of the pixel drive line Lread is connected to an output end corresponding to each row of the row scanning unit 131.
  • the row scanning unit 131 includes a shift register, an address decoder, and the like, and is a pixel driving unit that drives each pixel P of the pixel unit 101a, for example, in units of rows.
  • a signal output from each pixel P in the pixel row selected and scanned by the row scanning unit 131 is supplied to the horizontal selection unit 133 through each of the vertical signal lines Lsig.
  • the horizontal selection unit 133 is configured by an amplifier, a horizontal selection switch, and the like provided for each vertical signal line Lsig.
  • the column scanning unit 134 includes a shift register, an address decoder, and the like, and drives the horizontal selection switches in the horizontal selection unit 133 in order while scanning. By the selective scanning by the column scanning unit 134, the signal of each pixel transmitted through each of the vertical signal lines Lsig is sequentially transmitted to the horizontal signal line 135 and output to the outside through the horizontal signal line 135.
  • the system control unit 132 receives a clock given from the outside, data for instructing an operation mode, and the like, and outputs data such as internal information of the solid-state imaging device 101.
  • the system control unit 132 further includes a timing generator that generates various timing signals.
  • the row scanning unit 131, the horizontal selection unit 133, the column scanning unit 134, and the like are based on the various timing signals generated by the timing generator. Drive control is performed.
  • the electronic device according to the fourth embodiment of the present technology is an electronic device including the solid-state imaging device according to at least one embodiment of the third embodiment according to the present technology. Since the solid-state imaging device according to the third embodiment of the present technology is as described above, the description thereof is omitted here. Since the electronic device according to the fourth embodiment of the present technology includes the solid-state imaging device having excellent image quality and reliability, the image quality performance and the like can be improved.
  • FIG. 21 is a diagram illustrating a usage example of the solid-state imaging device according to the third embodiment of the present technology as an image sensor.
  • the solid-state imaging device of the third embodiment described above can be used in various cases for sensing light such as visible light, infrared light, ultraviolet light, and X-ray as follows. That is, as shown in FIG. 21, for example, the field of appreciation for taking images for appreciation, the field of transportation, the field of consumer electronics, the field of medical / healthcare, the field of security, the field of beauty, sports
  • the solid-state imaging device of the third embodiment can be used for devices (for example, the electronic device of the fourth embodiment described above) used in the field of agriculture, the field of agriculture, and the like.
  • the solid-state display according to the third embodiment is applied to an apparatus for shooting an image provided for viewing, such as a digital camera, a smartphone, or a mobile phone with a camera function.
  • An imaging device can be used.
  • in-vehicle sensors that capture images of the front, rear, surroundings, and interior of a vehicle for safe driving such as automatic stop and recognition of the driver's condition, traveling vehicles and roads are monitored.
  • the solid-state imaging device according to the third embodiment can be used as a device used for traffic, such as a monitoring camera that performs distance measurement between vehicles, a distance measurement sensor that performs distance measurement between vehicles, and the like.
  • a device used for home appliances such as a television receiver, a refrigerator, and an air conditioner to photograph a user's gesture and perform device operations in accordance with the gesture.
  • the solid-state imaging device of the embodiment can be used.
  • the solid state of the third embodiment is applied to a device used for medical treatment or health care such as an endoscope or a device that performs angiography by receiving infrared light.
  • a device used for medical treatment or health care such as an endoscope or a device that performs angiography by receiving infrared light.
  • An imaging device can be used.
  • the solid-state imaging device according to the third embodiment can be used for devices used for security, such as surveillance cameras for crime prevention and cameras for personal authentication.
  • the solid-state imaging device of the third embodiment may be used for a device used for beauty, such as a skin measuring device for photographing the skin or a microscope for photographing the scalp. it can.
  • the solid-state imaging device according to the third embodiment can be used in devices used for sports such as action cameras and wearable cameras for sports applications.
  • the solid-state imaging device of the third embodiment can be used for an apparatus used for agriculture, such as a camera for monitoring the state of fields and crops.
  • FIG. 22 shows a schematic configuration of an electronic device 1002 (camera) as an example.
  • the electronic device 1002 is, for example, a video camera capable of shooting a still image or a moving image, and drives the solid-state imaging device 399, the optical system (optical lens) 310, the shutter device 311, the solid-state imaging device 399, and the shutter device 311.
  • the optical system 310 guides image light (incident light) from the subject to the pixel portion of the solid-state imaging device 399.
  • the optical system 310 may be composed of a plurality of optical lenses.
  • the shutter device 311 controls a light irradiation period and a light shielding period for the solid-state imaging device 399.
  • the drive unit 313 controls the transfer operation of the solid-state imaging device 399 and the shutter operation of the shutter device 311.
  • the signal processing unit 312 performs various types of signal processing on the signal output from the solid-state imaging device 399.
  • the video signal Dout after the signal processing is stored in a storage medium such as a memory, or is output to a monitor or the like.
  • Example 1 First, as Experimental Example 1, a glass substrate provided with an ITO electrode having a thickness of 50 nm was cleaned by UV / ozone treatment, and then a first 100 nm thick made of IGZO was formed on the ITO electrode using a sputtering method. A semiconductor layer was formed. Subsequently, the substrate was subjected to heat treatment at 350 ° C. for 1 hour in the atmosphere to deplete IGZO.
  • the first semiconductor at a rotational speed of 2500 rpm by spin coating using an ink in which PbS nanoparticles in which oleic acid is coordinated on the nanoparticle surface is dispersed in an octane solvent at a concentration of 50 mg / ml as a photoelectric conversion layer. Coated on the layer. Thereafter, a solution in which iodine (I) was dispersed in a methanol solvent at a concentration of 1% by weight was added dropwise to perform ligand exchange from oleic acid to I. After ligand exchange, methanol was added dropwise to wash away excess organic materials such as oleic acid.
  • I iodine
  • a photoelectric conversion layer having a thickness of about 300 nm was formed.
  • heat treatment was performed at 120 ° C. for 5 minutes in an inert gas atmosphere to remove the residual solvent.
  • a HATCN film having a thickness of 10 nm is formed on the photoelectric conversion layer as a work function adjusting layer by vacuum deposition using a vacuum deposition method, and an ITO film having a thickness of 50 nm is further stacked by sputtering. Formed.
  • a photoelectric conversion element having a 1 mm ⁇ 1 mm photoelectric conversion region was produced.
  • Example 2 Photoelectric conversion element using the same method as in Experimental Example 1, except that after the photoelectric conversion layer was formed, heat treatment was performed, and then a 2T-NATA film was formed by vacuum deposition at a thickness of 10 nm. (Experimental example 2) was produced.
  • Example 3 A photoelectric conversion element (Experimental Example 3) was produced using the same method as in Experimental Example 1 except that a MoO 3 film was formed by a vacuum vapor deposition method with a thickness of 10 nm instead of the HATCN film as a work function adjusting layer. did.
  • Example 4 Photoelectric conversion element using the same method as in Experimental Example 3, except that after the photoelectric conversion layer was formed, heat treatment was performed, and then a 2T-NATA film was formed by vacuum deposition at a thickness of 10 nm. (Experimental example 4) was produced.
  • Example 5 A photoelectric conversion element (Experimental Example 5) was produced using the same method as in Experimental Example 1 except that the step of forming the HATCN film of the work function adjusting layer was omitted.
  • Example 7 As a work function adjusting layer, a photoelectric conversion element (experiment) was performed using the same method as in Experimental Example 1 except that a C 60 fullerene (C 60 ) film was formed by vacuum deposition at a thickness of 10 nm instead of the HATCN film. Example 7) was prepared.
  • Example 8 After adding a step of forming a [4,4′-bis (carbazol-9-yl) biphenyl (CBP) film with a thickness of 10 nm by vacuum deposition after the photoelectric conversion layer was formed and heat-treated. Produced a photoelectric conversion element (Experimental Example 8) using the same method as in Experimental Example 1.
  • Example 9 A photoelectric conversion element (Experimental Example 9) was produced using the same method as in Experimental Example 8 except that a MoO 3 film was formed by a vacuum deposition method with a thickness of 10 nm instead of the HATCN film as a work function adjusting layer. did.
  • Table 1 shows materials used for the work function adjusting layer, the p-type buffer layer, the photoelectric conversion layer, the charge storage layer, and the second electrode in Experimental Examples 1 to 9, the work function adjusting layer, the p-type buffer layer, and the photoelectric conversion.
  • the values of the electron affinity, work function and ionization potential of the layer and the second electrode, and the relative values of dark current and quantum efficiency in Experimental Examples 2 to 9 based on the results of Experimental Example 1 are summarized.
  • the work function and ionization potential are measured using ultraviolet spectroscopy, and the electron affinity is determined using the optical band gap obtained from the absorption spectral characteristics of the material and the ionization potential obtained by ultraviolet spectroscopy. Calculated.
  • the present disclosure is not limited to the above-described embodiments and the like, and various modifications are possible.
  • the example in which the photoelectric conversion element 10 that photoelectrically converts light having a wavelength in the near-infrared region is used alone in the imaging element 1 is shown.
  • visible light or the like other than the near-infrared region You may use in combination with the other photoelectric conversion element which photoelectrically converts the light of this wavelength.
  • the other photoelectric conversion element include a so-called inorganic photoelectric conversion element embedded in the semiconductor substrate 30 and a so-called organic photoelectric conversion element in which a photoelectric conversion layer is formed using an organic semiconductor material.
  • the configuration of the back-illuminated image sensor 1 is described as an example, but the present invention can also be applied to a front-illuminated image sensor.
  • it when used in combination with other photoelectric conversion elements, it may be configured as a so-called vertical spectral imaging element, or photoelectric conversion of light in other wavelength ranges on a semiconductor substrate.
  • the photoelectric conversion elements may be two-dimensionally arrayed (for example, Bayer array).
  • a substrate on which another functional element such as a memory element is provided on the multilayer wiring side may be laminated.
  • the photoelectric conversion element 10, the imaging element 1, and the imaging apparatus 1001 according to the present technology do not have to include all the components described in the above-described embodiments and the like, and conversely, may include other layers. Good.
  • this technique can also take the following structures.
  • the first electrode is an anode;
  • the second electrode is a cathode;
  • the photoelectric conversion layer includes a quantum dot material;
  • the work function adjusting layer is disposed in contact with the first electrode and includes an organic compound;
  • a photoelectric conversion element that satisfies the following formula 1. E A1 ⁇ WF 2 ...
  • Formula 1 (E A1 in the formula 1 represents the electron affinity of the work function adjusting layer, and WF 2 in the formula 1 represents the work function of the second electrode.) [2] The photoelectric conversion element according to [1], wherein the work function adjusting layer and the photoelectric conversion layer satisfy the following formula 2. E A1 ⁇ I P3 ... Formula 2 (I P3 in Formula 2 represents the ionization potential of the quantum dot material of the photoelectric conversion layer.) [3] A p-type buffer layer is further provided between the work function adjusting layer and the photoelectric conversion layer, The photoelectric conversion element according to [1], which satisfies the following formula 3. E A1 ⁇ I P2 ...
  • Formula 3 (E A1 in formula 3 represents the electron affinity of the work function adjustment layer, I P2 in formula 3 represents an ionization potential of the p-type buffer layer.) [4] Furthermore, the photoelectric conversion element according to [3], which satisfies the following formula 4. E A2 ⁇ E A3 ... Formula 4 (E A2 in the formula 4 represents the electron affinity of the p-type buffer layer, and E A3 in the formula 4 represents the electron affinity of the quantum dot material of the photoelectric conversion layer.) [5] The photoelectric conversion element according to any one of [1] to [4], further including an n-type buffer layer between the photoelectric conversion layer and the charge storage layer.
  • the photoelectric conversion layer has an insulating layer between the second electrode and the charge storage layer, is opposed to the second electrode and the insulating layer, and is provided through an opening provided in the insulating layer.
  • the photoelectric conversion element according to any one of [1] to [5], further including a third electrode electrically connected to the first electrode.
  • the first electrode is an anode;
  • the second electrode is a cathode;
  • the photoelectric conversion layer includes a quantum dot material;
  • the work function adjusting layer is disposed in contact with the first electrode and includes an inorganic compound;
  • WF 0 ⁇ WF 2 ... Formula 5 (WF 0 in Equation 5 represents the work function of the work function adjusting layer, and WF 2 in Equation 5 represents the work function of the second electrode.) [8] The photoelectric conversion element according to [7], wherein the work function adjustment layer and the photoelectric conversion layer satisfy the following formula 6. WF 0 ⁇ I P3 ... Formula 6 (I P3 in the equation 6 represents the ionization potential of the quantum dot material of the photoelectric conversion layer.) [9] A p-type buffer layer is further provided between the work function adjusting layer and the photoelectric conversion layer, The photoelectric conversion element according to [7], which satisfies the following formula 7. WF 0 ⁇ I P2 ...
  • Formula 7 (WF 0 in formula 7 indicates the work function of the work function adjusting layer, I P2 in formula 7 indicates the ionization potential of the p-type buffer layer.) [10] Furthermore, the photoelectric conversion element as described in [9] which satisfy
  • the photoelectric conversion layer has an insulating layer between the second electrode and the charge storage layer, is opposed to the second electrode and the insulating layer, and is provided through an opening provided in the insulating layer.
  • the photoelectric conversion element according to any one of [7] to [11], further including a third electrode electrically connected to the.
  • a solid-state imaging device in which at least one or a plurality of photoelectric conversion elements according to any one of [1] to [6] and a semiconductor substrate are stacked.
  • a solid-state imaging device in which at least one or a plurality of photoelectric conversion elements according to any one of [7] to [11] and a semiconductor substrate are stacked.
  • the solid-state imaging device according to [15] wherein the one or more photoelectric conversion elements perform photoelectric conversion of infrared light.
  • An electronic device comprising the solid-state imaging device according to any one of [16].
  • DESCRIPTION OF SYMBOLS 100 ... Photoelectric conversion element, 101 ... 1st electrode (anode), 102 ... Work function adjustment layer, 103 ... Photoelectric conversion layer, 104 ... Charge storage layer, 105 ... 2nd electrode (cathode), 106 ... 1st insulating layer, 107 ... Third electrode

Abstract

The present invention provides a photoelectric conversion element capable of further improving image quality or reliability. Provided is a photoelectric conversion element (100) comprising at least a first electrode (101), a work function adjustment layer (102), a photoelectric conversion layer (103), an electric charge accumulation layer (104), and a second electrode (105) in this order, wherein the first electrode (101) is an anode, the second electrode (105) is a cathode, the photoelectric conversion layer (103) includes a quantum dot material, the work function adjustment layer (102) is disposed in contact with the first electrode (101) and includes an organic compound, and equation 1 is satisfied. Equation 1: EA1 ≥ WF2 (EA1 in equation 1 represents the electron affinity of the work function adjustment layer, and WF2 in equation 1 represents the work function of the second electrode.)

Description

光電変換素子、固体撮像装置及び電子装置Photoelectric conversion element, solid-state imaging device, and electronic device
　本技術は、光電変換素子、固体撮像装置及び電子装置に関する。 This technology relates to a photoelectric conversion element, a solid-state imaging device, and an electronic device.
　近年、デジタルカメラ等の超小型化及び高画質化を実現するために、ＣＣＤ（Ｃｈａｒｇｅ Ｃｏｕｐｌｅｄ Ｄｅｖｉｃｅ）イメージセンサ、あるいはＣＭＯＳ（Ｃｏｍｐｌｅｍｅｎｔａｒｙ Ｍｅｔａｌ Ｏｘｉｄｅ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ）イメージセンサ等の固体撮像装置の研究が盛んに行われている。半導体基板の外部に光電変換部を有する撮像装置では、光電変換によって生成した電荷は、半導体基板内に形成された浮遊拡散層（フローティングディフュージョン；ＦＤ）内に電荷を蓄積することが一般的である。 2. Description of the Related Art In recent years, solid-state imaging devices such as CCD (Charge Coupled Device) image sensors or CMOS (Complementary Metal Oxide Semiconductor) image sensors have been actively studied in order to achieve ultra-miniaturization and high image quality of digital cameras and the like. ing. In an imaging device having a photoelectric conversion unit outside a semiconductor substrate, charges generated by photoelectric conversion are generally accumulated in a floating diffusion layer (floating diffusion; FD) formed in the semiconductor substrate. .
　例えば、第１電極と、第１電極に対向して形成された第２電極と、第１電極と第２電極との間に形成されていて、導電膜中にナローギャップ半導体の量子ドットを分散させた光電変換膜とを有し、第１電極および第２電極の一方の電極が透明電極で形成され、他方の電極が金属電極もしくは透明電極で形成されている、固体撮像装置が提案されている（特許文献１を参照。）。 For example, a first electrode, a second electrode formed opposite to the first electrode, and a narrow gap semiconductor quantum dot dispersed in the conductive film formed between the first electrode and the second electrode. A solid-state imaging device is proposed in which one of the first electrode and the second electrode is formed of a transparent electrode, and the other electrode is formed of a metal electrode or a transparent electrode. (See Patent Document 1).
　ところで、半導体基板内に光電変換部を設けた撮像装置では、光電変換によって生成した電荷は、半導体基板内の光電変換部に一旦蓄積されたのちＦＤに転送される。このため、光電変換部を完全空乏化することができる。これに対して、半導体基板の外部に設けられた光電変換部では、上記のように、光電変換部によって生成した電荷は直接ＦＤに蓄積されるため、光電変換部を完全に空乏化することは難しく、ｋＴＣノイズが大きくなり、ランダムノイズが悪化して撮像画質の低下をもたらしていた。 By the way, in an imaging device provided with a photoelectric conversion unit in a semiconductor substrate, the charge generated by the photoelectric conversion is once accumulated in the photoelectric conversion unit in the semiconductor substrate and then transferred to the FD. For this reason, a photoelectric conversion part can be completely depleted. On the other hand, in the photoelectric conversion unit provided outside the semiconductor substrate, the charge generated by the photoelectric conversion unit is directly accumulated in the FD as described above, so that the photoelectric conversion unit is completely depleted. It was difficult, kTC noise became large, random noise worsened, and the picked-up image quality was reduced.
　これに対して、例えば、光電変換層を間に対向配置された第１電極および第２電極のうち、光入射側とは反対側に配置された第２電極側に、第２電極とは離間して配置され、且つ、絶縁層を介して光電変換層に対向して配置された電荷蓄積用の電極を設けた撮像素子が開示されている（特許文献２を参照）。この撮像素子では、光電変換によって生成した電荷を光電変換層内に蓄積することができ、露光開始時に電荷蓄積部を完全空乏化することが可能となる。よって、撮像画質の低下を低減することが可能となる。 On the other hand, for example, among the first electrode and the second electrode disposed so as to face each other with the photoelectric conversion layer interposed therebetween, the second electrode side disposed on the side opposite to the light incident side is separated from the second electrode. In addition, an image pickup device is disclosed that includes a charge storage electrode that is disposed so as to face a photoelectric conversion layer with an insulating layer interposed therebetween (see Patent Document 2). In this imaging device, charges generated by photoelectric conversion can be stored in the photoelectric conversion layer, and the charge storage portion can be completely depleted at the start of exposure. Therefore, it is possible to reduce a decrease in image quality.
特開２０１０－１７７３９２号公報JP 2010-177392 A 特開２０１７－１５７８１６号公報JP 2017-157816 A
　しかしながら、特許文献１で提案された量子ドットを用いた光電変換素子技術では、画質の更なる向上や、信頼性の更なる向上が図れないおそれがある。 However, the photoelectric conversion element technology using quantum dots proposed in Patent Document 1 may not be able to further improve image quality and reliability.
　そこで、本技術は、このような状況に鑑みてなされたものであり、画質を更に向上させることや、信頼性を更に向上させることを実現できる光電変換素子、固体撮像装置及び電子装置を提供することを主目的とする。 Therefore, the present technology has been made in view of such a situation, and provides a photoelectric conversion element, a solid-state imaging device, and an electronic device that can realize further improvement in image quality and further improvement in reliability. The main purpose.
　本発明者らは、上述の目的を解決するために鋭意研究を行った結果、驚くべきことに、画質や信頼性を飛躍的に向上させることに成功し、本技術を完成するに至った。 As a result of intensive studies to solve the above-mentioned object, the present inventors have surprisingly succeeded in dramatically improving image quality and reliability, and have completed the present technology.
　すなわち、本技術では、まず、第１電極と、仕事関数調整層と、光電変換層と、電荷蓄積層と、第２電極とをこの順で少なくとも備え、該第１電極がアノードであり、該第２電極がカソードであり、該光電変換層が量子ドット材料を含み、該仕事関数調整層が、該第１電極と接して配されて、有機化合物を含み、下記の式１満たす、光電変換素子を提供する。 That is, in the present technology, first, at least a first function, a work function adjustment layer, a photoelectric conversion layer, a charge storage layer, and a second electrode are provided in this order, and the first electrode is an anode, The second electrode is a cathode, the photoelectric conversion layer includes a quantum dot material, the work function adjustment layer is disposed in contact with the first electrode, includes an organic compound, and satisfies the following formula 1. An element is provided.
　ＥＡ１≧ＷＦ２・・・・式１
　該式１中のＥＡ１は、該仕事関数調整層の電子親和力を示し、該式１中のＷＦ２は、該第２電極の仕事関数を示す。 E A1 ≧ WF 2 ... Formula 1
E A1 in the formula 1 represents the electron affinity of the work function adjusting layer, and WF 2 in the formula 1 represents the work function of the second electrode.
　本技術に係る光電変換素子は、前記仕事関数調整層と前記光電変換層とが、下記の式２を満たしてよい。
　ＥＡ１≧ＩＰ３・・・・式２ In the photoelectric conversion element according to the present technology, the work function adjustment layer and the photoelectric conversion layer may satisfy the following Expression 2.
E A1 ≧ I P3 ... Formula 2
　該式２中のＩＰ３は、該光電変換層の該量子ドット材料のイオン化ポテンシャルを示す。 I P3 in the formula 2 represents the ionization potential of the quantum dot material of the photoelectric conversion layer.
　本技術に係る光電変換素子は、前記仕事関数調整層と前記光電変換層との間に、ｐ型バッファ層を更に備えてよく、下記の式３を満たしてよい。 The photoelectric conversion element according to the present technology may further include a p-type buffer layer between the work function adjustment layer and the photoelectric conversion layer, and may satisfy Equation 3 below.
　ＥＡ１≧ＩＰ２・・・・式３
　該式３中のＥＡ１は、前記仕事関数調整層の電子親和力を示し、該式３中のＩＰ２は、該ｐ型バッファ層のイオン化ポテンシャルを示す。 E A1 ≧ I P2 ... Formula 3
E A1 in the equation 3 represents the electron affinity of the work function adjusting layer, and I P2 in the equation 3 represents the ionization potential of the p-type buffer layer.
　本技術に係る光電変換素子は、更に、下記の式４を満たしてよい。 The photoelectric conversion element according to the present technology may further satisfy the following formula 4.
　ＥＡ２≦ＥＡ３・・・・式４
　該式４中のＥＡ２は、前記ｐ型バッファ層の電子親和力を示し、該式４中のＥＡ３は、前記光電変換層の前記量子ドット材料の電子親和力を示す。 E A2 ≦ E A3 ... Formula 4
E A2 in the formula 4 represents the electron affinity of the p-type buffer layer, and E A3 in the formula 4 represents the electron affinity of the quantum dot material of the photoelectric conversion layer.
　本技術に係る光電変換素子は、前記光電変換層と前記電荷蓄積層との間に、ｎ型バッファ層を更に備えてよい。 The photoelectric conversion element according to the present technology may further include an n-type buffer layer between the photoelectric conversion layer and the charge storage layer.
　本技術に係る光電変換素子は、前記第２電極と前記電荷蓄積層との間に絶縁層を有し、前記第２電極と絶縁層を介して対抗配置され、かつ、前記絶縁層に設けられた開口を介して前記光電変換層と電気的に接続されている第３電極を更に備えてよい。 The photoelectric conversion element according to the present technology has an insulating layer between the second electrode and the charge storage layer, is opposed to the second electrode and the insulating layer, and is provided in the insulating layer. A third electrode that is electrically connected to the photoelectric conversion layer through the opening may be further provided.
　また、本技術では、第１電極と、仕事関数調整層と、光電変換層と、電荷蓄積層と、第２電極とをこの順で少なくとも備え、該第１電極がアノードであり、該第２電極がカソードであり、該光電変換層が量子ドット材料を含み、該仕事関数調整層が、該第１電極と接して配されて、無機化合物を含み、下記の式５を満たす、光電変換素子を提供する。 In the present technology, the first electrode, the work function adjustment layer, the photoelectric conversion layer, the charge storage layer, and the second electrode are provided in this order, and the first electrode is an anode, and the second electrode A photoelectric conversion element in which the electrode is a cathode, the photoelectric conversion layer includes a quantum dot material, the work function adjusting layer is disposed in contact with the first electrode, includes an inorganic compound, and satisfies the following formula 5 I will provide a.
　ＷＦ０≧ＷＦ２・・・・式５
　該式５中のＷＦ０は、該仕事関数調整層の仕事関数を示し、該式５中のＷＦ２は、該第２電極の仕事関数を示す。 WF 0 ≧ WF 2 ... Formula 5
WF 0 in Equation 5 represents the work function of the work function adjusting layer, and WF 2 in Equation 5 represents the work function of the second electrode.
　本技術に係る光電変換素子は、前記仕事関数調整層と前記光電変換層が、下記の式６を満たしてよい。
　ＷＦ０≧ＩＰ３・・・・式６ In the photoelectric conversion element according to the present technology, the work function adjustment layer and the photoelectric conversion layer may satisfy Expression 6 below.
WF 0 ≧ I P3 ... Formula 6
　該式６中のＩＰ３は、該光電変換層の該量子ドット材料のイオン化ポテンシャルを示す。 I P3 in the formula 6 represents an ionization potential of the quantum dot material of the photoelectric conversion layer.
　本技術に係る光電変換素子は、前記仕事関数調整層と前記光電変換層との間に、ｐ型バッファ層を更に備えてよく、下記の式７を満たしてよい。 The photoelectric conversion element according to the present technology may further include a p-type buffer layer between the work function adjustment layer and the photoelectric conversion layer, and may satisfy Equation 7 below.
　ＷＦ０≧ＩＰ２・・・・式７
　該式７中のＷＦ０は、前記仕事関数調整層の仕事関数を示し、該式７中のＩＰ２は、該ｐ型バッファ層のイオン化ポテンシャルを示す。 WF 0 ≧ I P2 ... Formula 7
Formula WF 0 in 7 indicates the work function of the work function adjustment layer, I P2 in formula 7 indicates the ionization potential of the p-type buffer layer.
　本技術に係る光電変換素子は、更に、下記の式８を満たしてよい。 The photoelectric conversion element according to the present technology may further satisfy the following formula 8.
　ＥＡ２≦ＥＡ３・・・・式８
　該式８中のＥＡ２は、前記ｐ型バッファ層の電子親和力を示し、該式８中のＥＡ３は、前記光電変換層の前記量子ドット材料の電子親和力を示す。 E A2 ≦ E A3 ... Formula 8
E A2 in the equation 8 represents the electron affinity of the p-type buffer layer, and E A3 in the equation 8 represents the electron affinity of the quantum dot material of the photoelectric conversion layer.
　本技術に係る光電変換素子は、前記光電変換層と前記電荷蓄積層との間に、ｎ型バッファ層を更に備えてよい。 The photoelectric conversion element according to the present technology may further include an n-type buffer layer between the photoelectric conversion layer and the charge storage layer.
　本技術に係る光電変換素子は、前記第２電極と前記電荷蓄積層との間に絶縁層を有し、前記第２電極と絶縁層を介して対抗配置され、かつ、前記絶縁層に設けられた開口を介して前記光電変換層と電気的に接続されている第３電極を更に備えてよい。 The photoelectric conversion element according to the present technology has an insulating layer between the second electrode and the charge storage layer, is opposed to the second electrode and the insulating layer, and is provided in the insulating layer. A third electrode that is electrically connected to the photoelectric conversion layer through the opening may be further provided.
　さらに、本技術では、１次元又は２次元に配列された複数の画素毎に、少なくとも、１又は複数の本技術に係る光電変換素子と、半導体基板とが積層された、固体撮像装置を提供する。
　そして、本技術に係る固体撮像装置において、１又は複数の前記光電変換素子が赤外光の光電変換を行ってもよい。 Furthermore, the present technology provides a solid-state imaging device in which at least one or a plurality of photoelectric conversion elements according to the present technology and a semiconductor substrate are stacked for each of a plurality of pixels arranged one-dimensionally or two-dimensionally. .
In the solid-state imaging device according to the present technology, one or a plurality of the photoelectric conversion elements may perform infrared photoelectric conversion.
　さらにまた、本技術では、本技術に係る固体撮像装置を備える、電子装置を提供する。 Furthermore, the present technology provides an electronic device including the solid-state imaging device according to the present technology.
　本技術によれば、画質や信頼性を向上させることができる。なお、ここに記載された効果は、必ずしも限定されるものではなく、本技術中に記載されたいずれかの効果であってもよい。 This technique can improve image quality and reliability. In addition, the effect described here is not necessarily limited, and may be any effect described in the present technology.
図１は、本技術を適用した第１の実施形態の光電変換素子の構成例を示す断面図である。FIG. 1 is a cross-sectional view illustrating a configuration example of the photoelectric conversion element according to the first embodiment to which the present technology is applied. 図２は、本技術を適用した第１の実施形態の光電変換素子の構成例を示す断面図である。FIG. 2 is a cross-sectional view illustrating a configuration example of the photoelectric conversion element according to the first embodiment to which the present technology is applied. 図３は、本技術を適用した第１の実施形態の光電変換素子における、第２電極（Ｃａｔｈｏｄｅ）、光電変換層（ｉ－Ｌａｙｅｒ（ＱＤ層））、ｐ型バッファ層（Ｐ-Ｂｕｆｆｅｒ）、仕事関数調整層（ＷＣＬ）及び第１電極（Ａｎｏｄｅ）と、エネルギー準位との関係を示す図である。FIG. 3 shows a second electrode (Cathode), a photoelectric conversion layer (i-Layer (QD layer)), a p-type buffer layer (P-Buffer) in the photoelectric conversion element of the first embodiment to which the present technology is applied. It is a figure which shows the relationship between a work function adjustment layer (WCL) and a 1st electrode (Anode), and an energy level. 図４は、本技術を適用した第１の実施形態の光電変換素子における、ＩＴＯ、ＩＣＺＯ、ＴｉＯ２、ＰｂＳ、２Ｔ－ＮＡＴＡ、ＨＡＴＣＮ及びＩＴＯと、エネルギー準位との関係を示す図である。FIG. 4 is a diagram showing a relationship between ITO, ICZO, TiO 2 , PbS, 2T-NATA, HATCN, and ITO and energy levels in the photoelectric conversion element according to the first embodiment to which the present technology is applied. 図５は、本技術を適用した第２の実施形態の光電変換素子の構成例を示す断面図である。FIG. 5 is a cross-sectional view illustrating a configuration example of the photoelectric conversion element according to the second embodiment to which the present technology is applied. 図６は、本技術を適用した第２の実施形態の光電変換素子の構成例を示す断面図である。FIG. 6 is a cross-sectional view illustrating a configuration example of the photoelectric conversion element according to the second embodiment to which the present technology is applied. 図７は、本技術を適用した第２の実施形態の光電変換素子における、第２電極（Ｃａｔｈｏｄｅ）、光電変換層（ｉ－Ｌａｙｅｒ（ＱＤ層））、ｐ型バッファ層（Ｐ-Ｂｕｆｆｅｒ）、仕事関数調整層（ＷＣＬ）及び第１電極（Ａｎｏｄｅ）と、エネルギー準位との関係を示す図である。FIG. 7 shows a second electrode (Cathode), a photoelectric conversion layer (i-Layer (QD layer)), a p-type buffer layer (P-Buffer), in the photoelectric conversion element of the second embodiment to which the present technology is applied. It is a figure which shows the relationship between a work function adjustment layer (WCL) and a 1st electrode (Anode), and an energy level. 図８は、本技術を適用した第２の実施形態の光電変換素子における、ＩＴＯ、ＩＣＺＯ、ＴｉＯ２、ＰｂＳ、２Ｔ－ＮＡＴＡ、ＭｏＯ３及びＩＴＯと、エネルギー準位との関係を示す図である。FIG. 8 is a diagram showing a relationship between ITO, ICZO, TiO 2 , PbS, 2T-NATA, MoO 3, and ITO and energy levels in the photoelectric conversion element of the second embodiment to which the present technology is applied. . 図９は、本技術を適用した第３の実施形態の固体撮像装置を構成する撮像素子の断面模式図である。FIG. 9 is a schematic cross-sectional view of an image sensor that constitutes the solid-state imaging device according to the third embodiment to which the present technology is applied. 図１０は、図９に示した第１光電変換素子の断面模式図である。FIG. 10 is a schematic sectional view of the first photoelectric conversion element shown in FIG. 図１１は、図９に示した撮像素子の等価回路図である。FIG. 11 is an equivalent circuit diagram of the imaging device shown in FIG. 図１２は、図９に示した撮像素子の下部電極および制御部を構成するトランジスタの配置を表す模式図である。FIG. 12 is a schematic diagram showing the arrangement of the transistors constituting the lower electrode and control unit of the image sensor shown in FIG. 図１３は、図９に示した第１光電変換素子の動作原理を説明する図である。FIG. 13 is a diagram for explaining the operating principle of the first photoelectric conversion element shown in FIG. 9. 図１４は、図９に示した撮像素子の製造方法を説明するための断面模式図である。FIG. 14 is a schematic cross-sectional view for explaining a method of manufacturing the image sensor shown in FIG. 図１５は、図１４に続く工程を表す断面模式図である。FIG. 15 is a schematic cross-sectional view illustrating a process following FIG. 図１６は、図１５に続く工程を表す断面模式図である。FIG. 16 is a schematic cross-sectional view illustrating a process following FIG. 図１７は、図１６に続く工程を表す断面模式図である。FIG. 17 is a schematic cross-sectional view illustrating a process following FIG. 図１８は、図１７に続く工程を表す断面模式図である。FIG. 18 is a schematic cross-sectional view illustrating a process following FIG. 図１９は、図９に示した第１光電変換素子の一動作例を表すタイミング図である。FIG. 19 is a timing chart illustrating an operation example of the first photoelectric conversion element illustrated in FIG. 9. 図２０は、図９に示した撮像素子を画素として用いた、本技術に係る第３の実施形態の固体撮像装置の構成を表すブロック図である。FIG. 20 is a block diagram illustrating a configuration of a solid-state imaging device according to the third embodiment of the present technology using the imaging device illustrated in FIG. 9 as a pixel. 図２１は、本技術を適用した固体撮像装置の使用例を示す図である。FIG. 21 is a diagram illustrating a usage example of the solid-state imaging device to which the present technology is applied. 図２２は、本技術を適用した電子装置の一例の機能ブロック図である。FIG. 22 is a functional block diagram of an example of an electronic apparatus to which the present technology is applied.
　以下、本技術を実施するための好適な形態について説明する。以下に説明する実施形態は、本技術の代表的な実施形態の一例を示したものであり、これにより本技術の範囲が狭く解釈されることはない。 Hereinafter, preferred embodiments for implementing the present technology will be described. The embodiment described below shows an example of a typical embodiment of the present technology, and the scope of the present technology is not interpreted narrowly.
　なお、説明は以下の順序で行う。
　１．第１の実施形態（光電変換素子の例１）
　２．第２の実施形態（光電変換素子の例２）
　３．第３の実施形態（固体撮像装置の例）
　４．第４の実施形態（電子装置の例）
　５．本技術を適用した固体撮像装置の使用例 The description will be given in the following order.
1. 1st Embodiment (Example 1 of a photoelectric conversion element)
2. Second Embodiment (Example 2 of photoelectric conversion element)
3. Third Embodiment (Example of Solid-State Imaging Device)
4). Fourth Embodiment (Example of Electronic Device)
5). Usage example of solid-state imaging device to which this technology is applied
＜１．第１の実施形態（光電変換素子の例１）＞
　本技術に係る第１の実施形態（光電変換素子の例１）の光電変換素子は、第１電極と、仕事関数調整層と、光電変換層と、電荷蓄積層と、第２電極とをこの順で少なくとも備え、第１電極がアノードであり、第２電極がカソードであり、光電変換層が量子ドット材料を含み、仕事関数調整層が、第１電極と接して配されて、有機化合物を含み、下記の式１満たす、光電変換素子を提供する。 <1. First Embodiment (Example 1 of Photoelectric Conversion Element)>
The photoelectric conversion element according to the first embodiment (Example 1 of the photoelectric conversion element) according to the present technology includes a first electrode, a work function adjustment layer, a photoelectric conversion layer, a charge accumulation layer, and a second electrode. At least in order, the first electrode is an anode, the second electrode is a cathode, the photoelectric conversion layer includes a quantum dot material, and a work function adjusting layer is disposed in contact with the first electrode, and an organic compound is provided. A photoelectric conversion element including and satisfying the following formula 1 is provided.
　ＥＡ１≧ＷＦ２・・・・式１
　該式１中のＥＡ１は、該仕事関数調整層の電子親和力を示し、該式１中のＷＦ２は、該第２電極の仕事関数を示す。 E A1 ≧ WF 2 ... Formula 1
E A1 in the formula 1 represents the electron affinity of the work function adjusting layer, and WF 2 in the formula 1 represents the work function of the second electrode.
　本技術に係る第１の実施形態の光電変換素子によれば、ｐｎ極性が反転し、暗電流を低減することができる。暗電流の成分としては、電子が第１電極から光電変換層（量子ドット材料）に流れる成分と、仕事関数調整層の正孔またはＰ型バッファ層の正孔と光電変換層（量子ドット材料）の電子とが再結合する成分がある。これらの２つの成分を本技術に係る第１の実施形態の光電変換素子は抑制することができる。 According to the photoelectric conversion element of the first embodiment according to the present technology, the pn polarity is inverted and the dark current can be reduced. As components of dark current, a component in which electrons flow from the first electrode to the photoelectric conversion layer (quantum dot material), a hole in the work function adjustment layer or a hole in the P-type buffer layer, and a photoelectric conversion layer (quantum dot material) There is a component that recombines with other electrons. The photoelectric conversion element of the first embodiment according to the present technology can suppress these two components.
　図１に、本技術に係る第１の実施形態の光電変換素子の一例である光電変換素子１００を示す。図１は、光電変換素子１００の断面図である。 FIG. 1 shows a photoelectric conversion element 100 that is an example of the photoelectric conversion element according to the first embodiment of the present technology. FIG. 1 is a cross-sectional view of the photoelectric conversion element 100.
　光電変換素子１００は、第１電極１０１と、仕事関数調整層１０２と、光電変換層１０３と、電荷蓄積層１０４と、第２電極１０５と、をこの順で少なくとも備え、第１電極１０１がアノードであり、第２電極１０５がカソードである。第２電極１０５は、第３電極１０７から離間して形成され、第１絶縁層１０６を介して電荷蓄積層１０４と対向して形成されている。また、第３電極１０７は、第２電極１０５と電荷蓄積層１０４との間に第１絶縁層１０６を有し、第２電極１０５と第１絶縁層１０６を介して対抗配置され、かつ、第１絶縁層１０６に設けられた開口を介して光電変換層１０３と電気的に接続されている。仕事関数調整層１０２は第１電極１０１と接して配され、有機化合物を含む。光電変換層１０３は量子ドット材料を含む。 The photoelectric conversion element 100 includes at least a first electrode 101, a work function adjustment layer 102, a photoelectric conversion layer 103, a charge storage layer 104, and a second electrode 105 in this order, and the first electrode 101 is an anode. The second electrode 105 is a cathode. The second electrode 105 is formed apart from the third electrode 107 and is formed to face the charge storage layer 104 with the first insulating layer 106 interposed therebetween. The third electrode 107 includes a first insulating layer 106 between the second electrode 105 and the charge storage layer 104, and is disposed to face the second electrode 105 and the first insulating layer 106. The photoelectric conversion layer 103 is electrically connected through an opening provided in the one insulating layer 106. The work function adjusting layer 102 is disposed in contact with the first electrode 101 and contains an organic compound. The photoelectric conversion layer 103 includes a quantum dot material.
　本技術に係る光電変換素子は、前記仕事関数調整層と前記光電変換層とが、下記の式２を満たしてよい。
　ＥＡ１≧ＩＰ３・・・・式２ In the photoelectric conversion element according to the present technology, the work function adjustment layer and the photoelectric conversion layer may satisfy the following Expression 2.
E A1 ≧ I P3 ... Formula 2
該式２中のＩＰ３は、該光電変換層の該量子ドット材料のイオン化ポテンシャルを示す。 I P3 in the formula 2 represents the ionization potential of the quantum dot material of the photoelectric conversion layer.
本技術に係る第１の実施形態の光電変換素子は、仕事関数調整層と光電変換層との間に、ｐ型バッファ層を更に備えてよく、下記の式３を満たしてよい。 The photoelectric conversion element according to the first embodiment of the present technology may further include a p-type buffer layer between the work function adjustment layer and the photoelectric conversion layer, and may satisfy Equation 3 below.
　ＥＡ１≧ＩＰ２・・・・式３ E A1 ≧ I P2 ... Formula 3
　該式３中のＥＡ１は、前記仕事関数調整層の電子親和力を示し、該式３中のＩＰ２は、該ｐ型バッファ層のイオン化ポテンシャルを示す。 E A1 in the equation 3 represents the electron affinity of the work function adjusting layer, and I P2 in the equation 3 represents the ionization potential of the p-type buffer layer.
更に、本技術に係る第１の実施形態の光電変換素子は、下記の式４を満たしてよい。 Furthermore, the photoelectric conversion element of the first embodiment according to the present technology may satisfy the following Expression 4.
　ＥＡ２≦ＥＡ３・・・・式４ E A2 ≦ E A3 ... Formula 4
　該式４中のＥＡ２は、前記ｐ型バッファ層の電子親和力を示し、該式４中のＥＡ３は、前記光電変換層の前記量子ドット材料の電子親和力を示す。 E A2 in the formula 4 represents the electron affinity of the p-type buffer layer, and E A3 in the formula 4 represents the electron affinity of the quantum dot material of the photoelectric conversion layer.
　ｐ型バッファ層の電子親和力（ＥＡ２）は、量子ドット材料の電子親和力（ＥＡ３）よりも小さいことが望ましく、より好ましくは、０．５ｅＶ以上小さいことが望ましく、さらに好ましくは、１．０ｅＶ以上小さいことが好ましい。また、ｐ型バッファのイオン化ポテンシャル（ＩＰ２）は、量子ドット材料の電子親和力（ＥＡ３）よりも大きいことが望ましく、より好ましくは、０．５ｅＶ以上大きいことが望ましい。 The electron affinity (E A2 ) of the p-type buffer layer is desirably smaller than the electron affinity (E A3 ) of the quantum dot material, more preferably 0.5 eV or more, and even more preferably 1.0 eV. It is preferable that it is smaller. The ionization potential (I P2 ) of the p-type buffer is preferably larger than the electron affinity (E A3 ) of the quantum dot material, and more preferably 0.5 eV or more.
　本技術に係る第１の実施形態の光電変換素子は、光電変換層と電荷蓄積層との間に、ｎ型バッファ層を更に備えていてもよい。 The photoelectric conversion element according to the first embodiment of the present technology may further include an n-type buffer layer between the photoelectric conversion layer and the charge storage layer.
　図２に、本技術に係る第１の実施形態の光電変換素子の一例である光電変換素子２００を示す。図２は、光電変換素子２００の断面図である。 FIG. 2 shows a photoelectric conversion element 200 that is an example of the photoelectric conversion element according to the first embodiment of the present technology. FIG. 2 is a cross-sectional view of the photoelectric conversion element 200.
　光電変換素子２００は、第１電極２０１と、仕事関数調整層２０２と、ｐ型バッファ層２０８と、光電変換層２０３と、ｎ型バッファ層２０９と、電荷蓄積層２０４と、第２電極２０５と、をこの順で少なくとも備え、第１電極２０１がアノードであり、第２電極２０５がカソードである。第２電極２０５は、第３電極２０７から離間して形成され、第１絶縁層２０６を介して電荷蓄積層２０４と対向して形成されている。また、第３電極２０７は、第２電極２０５と電荷蓄積層２０４との間に第１絶縁層２０６を有し、第２電極２０５と第１絶縁層２０６を介して対抗配置され、かつ、第１絶縁層２０６に設けられた開口を介して光電変換層２０３と電気的に接続されている。仕事関数調整層２０２は第１電極２０１と接して配され、有機化合物を含む。光電変換層２０３は量子ドットを含む。 The photoelectric conversion element 200 includes a first electrode 201, a work function adjustment layer 202, a p-type buffer layer 208, a photoelectric conversion layer 203, an n-type buffer layer 209, a charge storage layer 204, a second electrode 205, In this order, the first electrode 201 is an anode, and the second electrode 205 is a cathode. The second electrode 205 is formed away from the third electrode 207 and is formed to face the charge storage layer 204 with the first insulating layer 206 interposed therebetween. The third electrode 207 has a first insulating layer 206 between the second electrode 205 and the charge storage layer 204, is opposed to the second electrode 205 and the first insulating layer 206, and The photoelectric conversion layer 203 is electrically connected through an opening provided in the one insulating layer 206. The work function adjusting layer 202 is disposed in contact with the first electrode 201 and contains an organic compound. The photoelectric conversion layer 203 includes quantum dots.
　仕事関数調整層１０２及び２０２は、上記のとおり有機化合物を含み、仕事関数調整層（ＷＣＬ）として機能する有機化合物の例としては、2,3,5,6-テトラフルオロ-テトラシアノキノジメタン（Ｆ４－ＴＣＮＱ）、2,3,5-トリフルオロ-テトラシアノキノジメタン（Ｆ３－ＴＣＮＱ）、2,5-ジフルオロ-テトラシアノキノジメタン（Ｆ２－ＴＣＮＱ）、2-フルオロ-テトラシアノキノジメタン（Ｆ１－ＴＣＮＱ）、2-トリフルオロメチル-テトラシアノキノジメタン（ＣＦ３－ＴＣＮＱ）、1,3,4,5,7,8-ヘキサフルオロ-テトラシアノナフトキノジメタン（Ｆ６－ＴＣＮＱ）などのテトラシアノキノジメタン誘導体、及び、1,4,5,8,9,12‐ヘキサアザトリフェニレン‐2,3,6,7,10,11‐ヘキサカルボニトリル（ＨＡＴＣＮ）などのヘキサアザトリフェニレン誘導体、及び、2,3,8,9,14,15-ヘキサクロロ-5,6,11,12,17,18-ヘキサアザトリナフチレン（ＨＡＴＮＡ－Ｃｌ６）、2,3,8,9,14,15-ヘキサフルオロ-5,6,11,12,17,18-ヘキサアザトリナフチレン（ＨＡＴＮＡ－Ｆ６）などのヘキサアザトリナフチレン誘導体、及び、1,2,3,4,8,9,10,11,15,16,17,18,22,23,24,25-ヘキサデカフルオロ-銅フタロシアニン（Ｆ１６－ＣｕＰｃ）などのフタロシアニン誘導体、及び、Ｃ６０Ｆ３６やＣ６０Ｆ４８などのフッ化フラーレンが挙げられるが、これらに限定されるものではない。 The work function adjusting layers 102 and 202 contain an organic compound as described above, and examples of organic compounds that function as a work function adjusting layer (WCL) include 2,3,5,6-tetrafluoro-tetracyanoquinodimethane. (F4-TCNQ), 2,3,5-trifluoro-tetracyanoquinodimethane (F3-TCNQ), 2,5-difluoro-tetracyanoquinodimethane (F2-TCNQ), 2-fluoro-tetracyanoquino Dimethane (F1-TCNQ), 2-trifluoromethyl-tetracyanoquinodimethane (CF3-TCNQ), 1,3,4,5,7,8-hexafluoro-tetracyanonaphthoquinodimethane (F6-TCNQ) ) And other tetracyanoquinodimethane derivatives and hexaaza such as 1,4,5,8,9,12-hexaazatriphenylene-2,3,6,7,10,11-hexacarbonitrile (HATCN) A triphenylene derivative, and 2,3,8,9,14,15-hexachloro-5,6,11,12,17,18-hexaazatrinaphthylene (HATNA-Cl6), 2,3,8,9,14,15-hexa Hexaazatrinaphthylene derivatives such as fluoro-5,6,11,12,17,18-hexaazatrinaphthylene (HATNA-F6), and 1,2,3,4,8,9,10,11 , 15,16,17,18,22,23,24,25- phthalocyanine derivatives such as hexadecafluoro-copper phthalocyanine (F16-CuPc) and fluorinated fullerenes such as C 60 F 36 and C 60 F 48 Although it is mentioned, it is not limited to these.
　光電変換層１０３及び２０３に含まれる量子ドット材料は、例えば、少なくとも1つのＴｉＯ２、ＺｎＯ、ＷＯ３、ＮｉＯ、ＭｏＯ３、ＣｕＯ、Ｇａ２Ｏ３、ＳｒＴｉＯ３、ＳｎＯ２、ＩｎＳｎＯｘ、Ｎｂ２Ｏ３、ＭｎＯ２、Ｖ２Ｏ３、ＣｒＯ、ＣｕＩｎＳｅ２、ＣｕＩｎＳ２、ＣｕＺｎＣｕＳｎＳＳｅ、ＣｕＩｎＧａＳｅ、Ａｇ２Ｓ、ＡｇＩｎＳ２、ＡｌＳｅ２、ＡｌＧａＡｓ、Ｓｉ、Ｓｅ、ＰｂＳ、ＰｂＳｅ、ＰｂＴｅ、ＣｄＳ、ＣｄＳｅ、ＣｄＴｅ、Ｆｅ２Ｏ３、ＧａＡｓ、ＧａＰ、ＩｎＰ、ＩｎＡｓ、ＩｎＳｅ２、ＩｎＳｂ、Ｇｅ、Ｉｎ２Ｓ３、ＨｇＴｅ、Ｂｉ２Ｓ３、ＺｎＳｅ、ＺｎＴｅ、ＺｎＳ、ＺｎＣｕＩｎＳ等により構成されている。量子ドット材料の粒径は任意の大きさでよいが、吸収する光（吸収する波長帯）に応じて、量子ドット材料の粒径を適宜変更してよい。また、粒子の周囲を他材料で覆ったコアシェル構造をとってもよく、シェルを構成する材料としては、ＰｂＯ、ＰｂＯ２、Ｐｂ３Ｏ４、ＺｎＳ、ＺｎＳｅ、ＺｎＴｅなどが挙げられる。 The quantum dot material contained in the photoelectric conversion layers 103 and 203 is, for example, at least one of TiO 2 , ZnO, WO 3 , NiO, MoO 3 , CuO, Ga 2 O 3 , SrTiO 3 , SnO 2 , InSnOx, Nb 2 O. 3 , MnO 2 , V 2 O 3 , CrO, CuInSe 2 , CuInS 2 , CuZnCuSnSSe, CuInGaSe, Ag 2 S, AgInS 2 , AlSe 2 , AlGaAs, Si, Se, PbS, PbSe, PbTe, CdS, CdSe, CdSe Fe 2 O 3 , GaAs, GaP, InP, InAs, InSe 2 , InSb, Ge, In 2 S 3 , HgTe, Bi 2 S 3 , ZnSe, ZnTe, ZnS, ZnCuInS, and the like. The particle size of the quantum dot material may be any size, but the particle size of the quantum dot material may be changed as appropriate in accordance with the light to be absorbed (absorbing wavelength band). In addition, a core-shell structure in which the periphery of the particle is covered with another material may be used, and examples of the material constituting the shell include PbO, PbO 2 , Pb 3 O 4 , ZnS, ZnSe, and ZnTe.
　量子ドットを構成する半導体ナノ粒子の表面には、相互作用を及ぼす配位子が配位してもよく、これによって、半導体ナノ粒子の粒径制御や表面欠陥サイトからの失活の抑制、あるいは、伝導経路の制御といった効果が期待される。配位子は、相互作用を及ぼす吸着基と、それに結合するアルキル鎖とから構成されており、アルキル鎖の炭素の数は例えば２～５０であり、吸着基は例えばアミン、ホスホン、ホスフィン、カルボキシル、ヒドロキシル、チオールである。この他、塩素（Ｃｌ）、臭素（Ｂｒ）およびヨウ素（Ｉ）等のハロゲン元素を用いてもよい。 The surface of the semiconductor nanoparticles constituting the quantum dots may be coordinated with ligands that interact, thereby controlling the particle size of the semiconductor nanoparticles and suppressing deactivation from surface defect sites, or The effect of controlling the conduction path is expected. The ligand is composed of an adsorbing group that interacts and an alkyl chain bonded thereto, and the number of carbons in the alkyl chain is, for example, 2 to 50. , Hydroxyl, thiol. In addition, halogen elements such as chlorine (Cl), bromine (Br), and iodine (I) may be used.
　電荷蓄積層１０４及び電荷蓄積層２０４を構成する材料としては、具体的には、ＩＧＺＯ等の酸化物半導体材料；遷移金属ダイカルコゲナイド；シリコンカーバイド；ダイヤモンド；グラフェン；カーボンナノチューブ；縮合多環炭化水素化合物や縮合複素環化合物等の有機半導体材料を挙げることができる。電荷蓄積層１０４及び電荷蓄積層２０４を備えることで、電荷蓄積層１０４及び電荷蓄積層２０４に電荷を蓄積でき、電荷蓄積時の再結合を防止することができる。 Specific examples of materials constituting the charge storage layer 104 and the charge storage layer 204 include oxide semiconductor materials such as IGZO; transition metal dichalcogenide; silicon carbide; diamond; graphene; carbon nanotubes; And organic semiconductor materials such as condensed heterocyclic compounds. By providing the charge storage layer 104 and the charge storage layer 204, charges can be stored in the charge storage layer 104 and the charge storage layer 204, and recombination during charge storage can be prevented.
　第３電極１０７及び２０７、並びに第２電極１０５及び２０５は、透明導電材料からなる透明電極が好ましい。第３電極１０７及び２０７、並びに第２電極は１０５及び２０５のそれぞれは同じ材料から構成されてもよいし、異なる材料から構成されてもよい。第３電極１０７及び２０７、並びに第２電極１０５及び２０５は、スパッタリング法又は化学蒸着法（ＣＶＤ）によって形成することができる。 The third electrodes 107 and 207 and the second electrodes 105 and 205 are preferably transparent electrodes made of a transparent conductive material. The third electrodes 107 and 207 and the second electrode 105 and 205 may be made of the same material, or may be made of different materials. The third electrodes 107 and 207 and the second electrodes 105 and 205 can be formed by sputtering or chemical vapor deposition (CVD).
　本技術に係る第１の実施形態の光電変換素子は、第３電極１０７及び２０７、並びに第２電極１０５及び２０５の間に、転送電極１１Ｃを備えていてもよい。転送電極は、透明導電材料からなる透明電極が好ましい。第３電極１０７及び２０７、並びに第２電極は１０５及び２０５のそれぞれは同じ材料から構成されてもよいし、異なる材料から構成されてもよい。第３電極１０７及び２０７、並びに第２電極１０５及び２０５は、スパッタリング法又は化学蒸着法（ＣＶＤ）によって形成することができる。 The photoelectric conversion element according to the first embodiment of the present technology may include the transfer electrode 11C between the third electrodes 107 and 207 and the second electrodes 105 and 205. The transfer electrode is preferably a transparent electrode made of a transparent conductive material. The third electrodes 107 and 207 and the second electrode 105 and 205 may be made of the same material, or may be made of different materials. The third electrodes 107 and 207 and the second electrodes 105 and 205 can be formed by sputtering or chemical vapor deposition (CVD).
　透明導電材料としては、例えば、酸化インジウム、インジウム－錫酸化物（ＩＴＯ，Indium Tin Oxide，ＳｎドープのＩｎ2Ｏ3、結晶性ＩＴＯ及びアモルファスＩＴＯを含む）、酸化亜鉛にドーパントとしてインジウムを添加したインジウム－亜鉛酸化物（ＩＺＯ，Indium Zinc Oxide）、酸化ガリウムにドーパントとしてインジウムを添加したインジウム－ガリウム酸化物（ＩＧＯ）、酸化亜鉛にドーパントとしてインジウムとガリウムを添加したインジウム－ガリウム－亜鉛酸化物（ＩＧＺＯ，Ｉｎ－ＧａＺｎＯ4）、酸化亜鉛にドーパントとしてインジウムと錫を添加したインジウム－錫－亜鉛酸化物（ＩＴＺＯ）、ＩＦＯ（ＦドープのＩｎ2Ｏ3）、酸化錫（ＳｎＯ2）、ＡＴＯ（ＳｂドープのＳｎＯ2）、ＦＴＯ（ＦドープのＳｎＯ2）、酸化亜鉛（他元素をドープしたＺｎＯを含む）、酸化亜鉛にドーパントとしてアルミニウムを添加したアルミニウム－亜鉛酸化物（ＡＺＯ）、酸化亜鉛にドーパントとしてガリウムを添加したガリウム－亜鉛酸化物（ＧＺＯ）、酸化チタン（ＴｉＯ2）、酸化チタンにドーパントとしてニオブを添加したニオブ－チタン酸化物(ＴＮＯ)、酸化アンチモン、スピネル型酸化物、ＹｂＦｅ2Ｏ4構造を有する酸化物を例示することができる。 Examples of transparent conductive materials include indium oxide, indium-tin oxide (including ITO, Indium Tin Oxide, Sn-doped In 2 O 3 , crystalline ITO, and amorphous ITO), and zinc oxide with indium added as a dopant. Indium-zinc oxide (IZO), indium-gallium oxide (IGO) in which indium is added as a dopant to gallium oxide, indium-gallium-zinc oxide in which indium and gallium are added as dopants in zinc oxide ( IGZO, In-GaZnO 4 ), indium-tin-zinc oxide (ITZO) in which indium and tin are added as dopants to zinc oxide, IFO (F-doped In 2 O 3 ), tin oxide (SnO 2 ), ATO ( SnO and Sb-doped 2), SnO 2 of FTO (F doped), acid Zinc (including ZnO doped with other elements), aluminum-zinc oxide (AZO) in which aluminum is added as a dopant to zinc oxide, gallium-zinc oxide (GZO) in which gallium is added as a dopant to zinc oxide, titanium oxide Examples thereof include (TiO 2 ), niobium-titanium oxide (TNO) obtained by adding niobium as a dopant to titanium oxide, antimony oxide, spinel oxide, and oxide having a YbFe 2 O 4 structure.
　第１電極１０１及び２０１は、例えば、酸化インジウム錫膜、酸化インジウム亜鉛膜等の透明導電膜等で形成される。 The first electrodes 101 and 201 are formed of a transparent conductive film such as an indium tin oxide film or an indium zinc oxide film, for example.
　第１絶縁層１０６及び２０６は、シリコン酸化膜、ＴＥＯＳなどの絶縁性を有する誘電体を採用することができる。 As the first insulating layers 106 and 206, an insulating dielectric such as a silicon oxide film or TEOS can be adopted.
　ｐ型バッファ層２０８は、光電変換層２０３で生じた正孔の第１電極２０１への供給を促進するためのものであり、例えば、酸化モリブデン（ＭｏＯ３），酸化ニッケル（ＮｉＯ）又は酸化バナジウム（Ｖ２Ｏ５）等により構成されていてよい。ＰＥＤＯＴ（Ｐｏｌｙ(３，４-ｅｔｈｙｌｅｎｅｄｉｏｘｙｔｈｉｏｐｈｅｎｅ)）、ＴＰＤ（Ｎ，Ｎ'-Ｂｉｓ(３-ｍｅｔｈｙｌｐｈｅｎｙｌ)-Ｎ，Ｎ'-ｄｉｐｈｅｎｙｌｂｅｎｚｉｄｉｎｅ）、２Ｔ－ＮＡＴＡ（4,4',4''-トリス[2-ナフチル(フェニル)アミノ]トリフェニルアミン）等の有機材料により正孔輸送層を構成するようにしてもよい。 The p-type buffer layer 208 is for accelerating the supply of holes generated in the photoelectric conversion layer 203 to the first electrode 201. For example, molybdenum oxide (MoO 3 ), nickel oxide (NiO), or vanadium oxide is used. (V 2 O 5 ) or the like may be used. PEDOT (Poly (3,4-ethylenedithiothiophene)), TPD (N, N′-Bis (3-methylphenyl) -N, N′-diphenylbenzidine), 2T-NATA (4,4 ′, 4 ″ -Tris [2 The hole transport layer may be composed of an organic material such as -naphthyl (phenyl) amino] triphenylamine).
　ｎ型バッファ層２０９は、光電変換層２０３で生じた電子の第３電極２０７への供給を促進するためのものであり、例えば、酸化チタン（ＴｉＯ２）、酸化亜鉛（ＺｎＯ）等により構成されていてよい。酸化チタンと酸化亜鉛とを積層させてｎ型バッファ層２０９を構成するようにしてもよい。また、ｎ型バッファ層２０９は、高分子半導体材料から構成されてもよい。 The n-type buffer layer 209 is for accelerating the supply of electrons generated in the photoelectric conversion layer 203 to the third electrode 207, and is made of, for example, titanium oxide (TiO 2 ), zinc oxide (ZnO), or the like. It may be. The n-type buffer layer 209 may be configured by stacking titanium oxide and zinc oxide. The n-type buffer layer 209 may be made of a polymer semiconductor material.
　高分子半導体材料としては、例えば、母骨格としてナフタレンジイミドを含む下記一般式（１）及び一般式（２）に示した化合物（ナフタレンジイミド誘導体）が挙げられる。ナフタレンジイミド誘導体の具体例としては、例えば下記の式（１－１）に示した化合物が挙げられる。 Examples of the polymer semiconductor material include compounds represented by the following general formula (1) and general formula (2) (naphthalenediimide derivatives) containing naphthalenediimide as a mother skeleton. Specific examples of naphthalenediimide derivatives include compounds represented by the following formula (1-1).
Figure JPOXMLDOC01-appb-C000001
Figure JPOXMLDOC01-appb-C000001
　該式（１）中のＲ１は、各々独立して水素原子、直鎖，分岐または環状のアルキル基、フェニル基、直鎖または縮環した芳香族化合物を有する基、複素環化合物を有する基、ハロゲン化物を有する基、パーシャルフルオロアルキル基、パーフルオロアルキル基、シリルアルキル基、シリルアルコキシ基、アリールシリル基、を有する基、あるいはそれらの誘導体である。 R 1 in the formula (1) is each independently a hydrogen atom, a linear, branched or cyclic alkyl group, a phenyl group, a group having a linear or condensed aromatic compound, or a group having a heterocyclic compound. A group having a halide, a partial fluoroalkyl group, a perfluoroalkyl group, a silylalkyl group, a silylalkoxy group, an arylsilyl group, or a derivative thereof.
Figure JPOXMLDOC01-appb-C000002
Figure JPOXMLDOC01-appb-C000002
　該式（２）中のＲ１及びＲ２は、各々独立して水素原子、直鎖，分岐または環状のアルキル基、フェニル基、直鎖または縮環した芳香族化合物を有する基、複素環化合物を有する基、ハロゲン化物を有する基、パーシャルフルオロアルキル基、パーフルオロアルキル基、シリルアルキル基、シリルアルコキシ基、アリールシリル基、を有する基、あるいはそれらの誘導体である。Ｘは、芳香族化合物、ヘテロ芳香族化合物、多環芳香族環化合物、ヘテロ多環芳香族環化合物が、1つ以上、5つ以下連なった化合物であり、置換基を有していてもよい。 R 1 and R 2 in the formula (2) are each independently a hydrogen atom, a linear, branched or cyclic alkyl group, a phenyl group, a group having a linear or condensed aromatic compound, a heterocyclic compound , A group having a halide, a partial fluoroalkyl group, a perfluoroalkyl group, a silylalkyl group, a silylalkoxy group, an arylsilyl group, or a derivative thereof. X is a compound in which one or more, five or less heteroaromatic ring compounds are aromatic compounds, heteroaromatic compounds, polycyclic aromatic ring compounds, or heteropolycyclic aromatic ring compounds, and may have a substituent. .
Figure JPOXMLDOC01-appb-C000003
Figure JPOXMLDOC01-appb-C000003
　図３は、本技術に係る第１の実施形態の光電変換素子における、第２電極（Ｃａｔｈｏｄｅ）、光電変換層（ｉ－Ｌａｙｅｒ（ＱＤ層））、ｐ型バッファ層（Ｐ-Ｂｕｆｆｅｒ）、仕事関数調整層（ＷＣＬ）及び第１電極（Ａｎｏｄｅ）と、エネルギー準位との関係を示す図である。図４は、本技術に係る第１の実施形態の光電変換素子における、ＩＴＯ、ＩＧＺＯ、ＴｉＯ２、ＰｂＳ、２Ｔ－ＮＡＴＡ、ＨＡＴＣＮ及びＩＴＯと、エネルギー準位との関係を示す図である。信号電荷（電子）は、図４中のエネルギー準位の高い方から低い方に流れる。逆に、正孔は、図４中のエネルギー準位の低い方から高い方に流れる。 FIG. 3 shows a second electrode (Cathode), a photoelectric conversion layer (i-Layer (QD layer)), a p-type buffer layer (P-Buffer), a work in the photoelectric conversion element according to the first embodiment of the present technology. It is a figure which shows the relationship between a function adjustment layer (WCL) and a 1st electrode (Anode), and an energy level. FIG. 4 is a diagram illustrating the relationship between ITO, IGZO, TiO 2 , PbS, 2T-NATA, HATCN, and ITO and energy levels in the photoelectric conversion element according to the first embodiment of the present technology. The signal charges (electrons) flow from the higher energy level to the lower energy level in FIG. Conversely, holes flow from the lower energy level to the higher energy level in FIG.
　図３及び図４を参照すれば明らかなように、本技術に係る第１の実施形態の光電変換素子は、ＥＡ１≧ＩＰ３（式１）、ＥＡ１≧ＷＦ２（式２）、ＥＡ１≧ＩＰ２（式３）、及びＥＡ２≦ＥＡ３（式４）を少なくとも満たすので、ｐｎ極性が反転し、暗電流の低減をより促進することができる。 As is clear from FIGS. 3 and 4, the photoelectric conversion element according to the first embodiment of the present technology includes E A1 ≧ I P3 (Equation 1), E A1 ≧ WF 2 (Equation 2), E Since at least A1 ≧ I P2 (Formula 3) and E A2 ≦ E A3 (Formula 4) are satisfied, the pn polarity is inverted, and the reduction of dark current can be further promoted.
　本技術に係る第１の実施形態の光電変換素子は、公知の方法、例えば、スパッタ法、フォトリソグラフィ技術によりパターニングしてドライエッチング又はウェットエッチングする方法、湿式成膜法を用いて製造することができる。湿式成膜法としては、例えば、スピンコート法，浸漬法，キャスト法，スクリーン印刷法やインクジェット印刷法、オフセット印刷法、グラビア印刷法といった各種印刷法，スタンプ法，スプレー法，エアドクタコーター法，ブレードコーター法，ロッドコーター法，ナイフコーター法，スクイズコーター法，リバースロールコーター法，トランスファーロールコーター法，グラビアコーター法，キスコーター法，キャストコーター法，スプレーコーター法，スリットオリフィスコーター法，カレンダーコーター法といった各種コーティング法が挙げられる。 The photoelectric conversion element of the first embodiment according to the present technology can be manufactured using a known method, for example, a sputtering method, a method of patterning by a photolithography technique, dry etching or wet etching, or a wet film forming method. it can. Examples of wet film formation methods include spin coating, dipping, casting, screen printing, inkjet printing, offset printing, gravure printing, various printing methods, stamping, spraying, air doctor coater, Blade coater method, rod coater method, knife coater method, squeeze coater method, reverse roll coater method, transfer roll coater method, gravure coater method, kiss coater method, cast coater method, spray coater method, slit orifice coater method, calendar coater method, etc. Various coating methods are mentioned.
＜２．第２の実施形態（光電変換素子の例２）＞
　本技術に係る第２の実施形態（光電変換素子の例２）の光電変換素子は、第１電極と、仕事関数調整層と、光電変換層と、電荷蓄積層と、第２電極とをこの順で少なくとも備え、該第１電極がアノードであり、該第２電極がカソードであり、該光電変換層が量子ドット材料を含み、該仕事関数調整層が、該第１電極と接して配されて、無機化合物を含み、下記の式５を満たす、光電変換素子を提供する。 <2. Second Embodiment (Example 2 of Photoelectric Conversion Element)>
The photoelectric conversion element according to the second embodiment (photoelectric conversion element example 2) according to the present technology includes a first electrode, a work function adjustment layer, a photoelectric conversion layer, a charge accumulation layer, and a second electrode. At least in order, the first electrode is an anode, the second electrode is a cathode, the photoelectric conversion layer includes a quantum dot material, and the work function adjusting layer is disposed in contact with the first electrode. The photoelectric conversion element which contains an inorganic compound and satisfy | fills following formula 5 is provided.
　ＷＦ０≧ＷＦ２・・・・式５
　該式５中のＷＦ０は、該仕事関数調整層の仕事関数を示し、該式５中のＷＦ２は、該第２電極の仕事関数を示す。 WF 0 ≧ WF 2 ... Formula 5
WF 0 in Equation 5 represents the work function of the work function adjusting layer, and WF 2 in Equation 5 represents the work function of the second electrode.
　本技術に係る第２の実施形態の光電変換素子によれば、ｐｎ極性が反転し、暗電流を低減することができる。暗電流の成分としては、電子が第１電極から光電変換層（量子ドット材料）に流れる成分と、仕事関数調整層の正孔またはｐ型バッファ層の正孔と光電変換層（量子ドット材料）の電子とが再結合する成分がある。これらの２つの成分を本技術に係る第２の実施形態の光電変換素子は抑制することができる。 According to the photoelectric conversion element of the second embodiment according to the present technology, the pn polarity is inverted and the dark current can be reduced. As components of dark current, a component in which electrons flow from the first electrode to the photoelectric conversion layer (quantum dot material), a hole in the work function adjustment layer or a hole in the p-type buffer layer, and a photoelectric conversion layer (quantum dot material) There is a component that recombines with other electrons. The photoelectric conversion element of the second embodiment according to the present technology can suppress these two components.
　図５に、本技術に係る第２の実施形態の光電変換素子の一例である光電変換素子５００を示す。図５は、光電変換素子５００の断面図である。 FIG. 5 shows a photoelectric conversion element 500 which is an example of the photoelectric conversion element of the second embodiment according to the present technology. FIG. 5 is a cross-sectional view of the photoelectric conversion element 500.
　光電変換素子５００は、第１電極５０１と、仕事関数調整層５０２と、光電変換層５０３と、電荷蓄積層５０４と、第２電極５０５と、をこの順で少なくとも備え、第１電極５０１がアノードであり、第２電極５０５がカソードである。第２電極５０５は、第３電極５０７から離間して形成され、第１絶縁層５０６を介して電荷蓄積層５０４と対向して形成されている。また、第３電極５０７は、第２電極５０５と電荷蓄積層５０４との間に第１絶縁層５０６を有し、第２電極５０５と第１絶縁層５０６を介して対抗配置され、かつ、第１絶縁層５０６に設けられた開口を介して光電変換層５０３と電気的に接続されている。仕事関数調整層５０２は第１電極５０１と接して配され、無機化合物を含む。光電変換層５０３は量子ドットを含む。 The photoelectric conversion element 500 includes at least a first electrode 501, a work function adjustment layer 502, a photoelectric conversion layer 503, a charge storage layer 504, and a second electrode 505 in this order, and the first electrode 501 is an anode. The second electrode 505 is a cathode. The second electrode 505 is formed to be separated from the third electrode 507 and is opposed to the charge storage layer 504 with the first insulating layer 506 interposed therebetween. In addition, the third electrode 507 includes a first insulating layer 506 between the second electrode 505 and the charge storage layer 504, and is disposed to face the second electrode 505 and the first insulating layer 506. The photoelectric conversion layer 503 is electrically connected through an opening provided in the one insulating layer 506. The work function adjusting layer 502 is disposed in contact with the first electrode 501 and contains an inorganic compound. The photoelectric conversion layer 503 includes quantum dots.
　本技術に係る光電変換素子は、前記仕事関数調整層と前記光電変換層が、下記の式６を満たしてよい。
　ＷＦ０≧ＩＰ３・・・・式６ In the photoelectric conversion element according to the present technology, the work function adjustment layer and the photoelectric conversion layer may satisfy Expression 6 below.
WF 0 ≧ I P3 ... Formula 6
　該式６中のＩＰ３は、該光電変換層の該量子ドット材料のイオン化ポテンシャルを示す。 I P3 in the formula 6 represents an ionization potential of the quantum dot material of the photoelectric conversion layer.
　本技術に係る第２の実施形態の光電変換素子は、仕事関数調整層と光電変換層との間に、ｐ型バッファ層を更に備えてよく、下記の式７を満たしてよい。 The photoelectric conversion element according to the second embodiment of the present technology may further include a p-type buffer layer between the work function adjustment layer and the photoelectric conversion layer, and may satisfy the following Expression 7.
　ＷＦ０≧ＩＰ２・・・・式７ WF 0 ≧ I P2 ... Formula 7
　該式７中のＷＦ０は、前記仕事関数調整層の仕事関数を示し、該式７中のＩＰ２は、該ｐ型バッファ層のイオン化ポテンシャルを示す。 Formula WF 0 in 7 indicates the work function of the work function adjustment layer, I P2 in formula 7 indicates the ionization potential of the p-type buffer layer.
　更に、本技術に係る第１の実施形態の光電変換素子は、下記の式８を満たしてよい。 Furthermore, the photoelectric conversion element of the first embodiment according to the present technology may satisfy the following Expression 8.
　ＥＡ２≦ＥＡ３・・・・式８ E A2 ≦ E A3 ... Formula 8
　該式８中のＥＡ２は、前記ｐ型バッファ層の電子親和力を示し、該式４中のＥＡ３は、前記光電変換層の前記量子ドット材料の電子親和力を示す。 E A2 in the equation 8 represents the electron affinity of the p-type buffer layer, and E A3 in the equation 4 represents the electron affinity of the quantum dot material of the photoelectric conversion layer.
　ｐ型バッファ層の電子親和力（ＥＡ２）は、量子ドット材料の電子親和力（ＥＡ３）よりも小さいことが望ましく、より好ましくは、０．５ｅＶ以上小さいことが望ましく、さらに好ましくは、１．０ｅＶ以上小さいことが好ましい。また、ｐ型バッファのイオン化ポテンシャル（ＩＰ２）は、量子ドット材料の電子親和力（ＥＡ３）よりも大きいことが望ましく、より好ましくは、０．５ｅＶ以上大きいことが望ましい。 The electron affinity (E A2 ) of the p-type buffer layer is desirably smaller than the electron affinity (E A3 ) of the quantum dot material, more preferably 0.5 eV or more, and even more preferably 1.0 eV. It is preferable that it is smaller. The ionization potential (I P2 ) of the p-type buffer is preferably larger than the electron affinity (E A3 ) of the quantum dot material, and more preferably 0.5 eV or more.
　本技術に係る第２の実施形態の光電変換素子は、光電変換層と電荷蓄積層との間に、ｎ型バッファ層を更に備えていてもよい。 The photoelectric conversion element according to the second embodiment of the present technology may further include an n-type buffer layer between the photoelectric conversion layer and the charge storage layer.
　図６に、本技術に係る第２の実施形態の光電変換素子の一例である光電変換素子６００を示す。図６は、光電変換素子６００の断面図である。 FIG. 6 shows a photoelectric conversion element 600 that is an example of the photoelectric conversion element according to the second embodiment of the present technology. FIG. 6 is a cross-sectional view of the photoelectric conversion element 600.
　光電変換素子６００は、第１電極６０１と、仕事関数調整層６０２と、ｐ型バッファ層６０８と、光電変換層６０３と、ｎ型バッファ層６０９と、電荷蓄積層６０４と、第２電極６０５と、をこの順で少なくとも備え、第１電極６０１がアノードであり、第２電極６０５がカソードである。第２電極６０５は、第３電極６０７から離間して形成され、第１絶縁層６０６を介して電荷蓄積層６０４と対向して形成されている。また、第３電極６０７は、第２電極６０５と電荷蓄積層６０４との間に第１絶縁層６０６を有し、第２電極６０５と第１絶縁層６０６を介して対抗配置され、かつ、第１絶縁層６０６に設けられた開口を介して光電変換層６０３と電気的に接続されている。仕事関数調整層６０２は第１電極２０１と接して配され、無機化合物を含む。光電変換層６０３は量子ドットを含む。 The photoelectric conversion element 600 includes a first electrode 601, a work function adjustment layer 602, a p-type buffer layer 608, a photoelectric conversion layer 603, an n-type buffer layer 609, a charge storage layer 604, and a second electrode 605. In this order, the first electrode 601 is an anode, and the second electrode 605 is a cathode. The second electrode 605 is formed to be separated from the third electrode 607 and is formed to face the charge storage layer 604 with the first insulating layer 606 interposed therebetween. In addition, the third electrode 607 includes a first insulating layer 606 between the second electrode 605 and the charge storage layer 604, and is disposed to face the second electrode 605 and the first insulating layer 606. The photoelectric conversion layer 603 is electrically connected through an opening provided in the one insulating layer 606. The work function adjusting layer 602 is disposed in contact with the first electrode 201 and contains an inorganic compound. The photoelectric conversion layer 603 includes quantum dots.
　仕事関数調整層５０２及び６０２は、上記のとおり無機化合物を含み、仕事関数調整層（ＷＣＬ）として機能する無機化合物の例としては、酸化モリブデン（ＭｏＯ３）、酸化タングステン（ＷＯ３）、酸化バナジウム（Ｖ２Ｏ５）、酸化レニウム（ＲｅＯ３）などの遷移金属酸化物、及び、ヨウ化銅（ＣｕＩ）、塩化アンチモン（ＳｂＣｌ５）、酸化鉄（ＦｅＣｌ３）、塩化ナトリウム（ＮａＣｌ）などの塩が挙げられるが、これらに限定されるものではない。 The work function adjustment layers 502 and 602 include an inorganic compound as described above, and examples of inorganic compounds that function as the work function adjustment layer (WCL) include molybdenum oxide (MoO 3 ), tungsten oxide (WO 3 ), and vanadium oxide. (V 2 O 5 ), transition metal oxides such as rhenium oxide (ReO 3 ), and copper iodide (CuI), antimony chloride (SbCl 5 ), iron oxide (FeCl 3 ), sodium chloride (NaCl), etc. Examples include, but are not limited to, salts.
　第１電極５０１及び６０１、第２電極５０５及び６０５、第３電極５０７及び６０７、光電変換層５０３及び６０３、電荷蓄積層５０４及び６０４、第１絶縁層５０６及び６０６、ｐ型バッファ層６０８、並びにｎ型バッファ層６０９で用いられる材料は、本技術に係る第１の実施形態の光電変換素子の欄で述べたとおりであるので、ここでは詳細な説明は省略する。 First electrodes 501 and 601, second electrodes 505 and 605, third electrodes 507 and 607, photoelectric conversion layers 503 and 603, charge storage layers 504 and 604, first insulating layers 506 and 606, p-type buffer layer 608, and Since the material used for the n-type buffer layer 609 is as described in the section of the photoelectric conversion element of the first embodiment according to the present technology, detailed description thereof is omitted here.
　本技術に係る第２の実施形態の光電変換素子は、本技術に係る第１の実施形態の光電変換素子と同様に、公知の方法、例えば、スパッタ法、フォトリソグラフィ技術によりパターニングしてドライエッチング又はウェットエッチングする方法、湿式成膜法を用いて製造することができる。湿式成膜法としては、例えば、スピンコート法，浸漬法，キャスト法，スクリーン印刷法やインクジェット印刷法、オフセット印刷法、グラビア印刷法といった各種印刷法，スタンプ法，スプレー法，エアドクタコーター法，ブレードコーター法，ロッドコーター法，ナイフコーター法，スクイズコーター法，リバースロールコーター法，トランスファーロールコーター法，グラビアコーター法，キスコーター法，キャストコーター法，スプレーコーター法，スリットオリフィスコーター法，カレンダーコーター法といった各種コーティング法が挙げられる。 Similarly to the photoelectric conversion element of the first embodiment according to the present technology, the photoelectric conversion element of the second embodiment according to the present technology is patterned by a known method, for example, a sputtering method, a photolithography technique, and is dry-etched. Alternatively, it can be manufactured using a wet etching method or a wet film forming method. Examples of wet film formation methods include spin coating, dipping, casting, screen printing, inkjet printing, offset printing, gravure printing, various printing methods, stamping, spraying, air doctor coater, Blade coater method, rod coater method, knife coater method, squeeze coater method, reverse roll coater method, transfer roll coater method, gravure coater method, kiss coater method, cast coater method, spray coater method, slit orifice coater method, calendar coater method, etc. Various coating methods are mentioned.
　図７は、本技術に係る第２の実施形態の光電変換素子における、第２電極（Ｃａｔｈｏｄｅ）、光電変換層（ｉ－Ｌａｙｅｒ（ＱＤ層））、ｐ型バッファ層（Ｐ-Ｂｕｆｆｅｒ）、仕事関数調整層（ＷＣＬ）及び第１電極（Ａｎｏｄｅ）と、エネルギー準位との関係を示す図である。図８は、本技術に係る第２の実施形態の光電変換素子における、ＩＴＯ、ＩＧＺＯ、ＴｉＯ２、ＰｂＳ、２Ｔ－ＮＡＴＡ、ＭｏＯ３及びＩＴＯと、エネルギー準位との関係を示す図である。信号電荷（電子）は、図８中のエネルギー準位の高い方から低い方に流れる。逆に、正孔は、図８中のエネルギー準位の低い方から高い方に流れる。 FIG. 7 shows a second electrode (Cathode), a photoelectric conversion layer (i-Layer (QD layer)), a p-type buffer layer (P-Buffer), a work in the photoelectric conversion element of the second embodiment according to the present technology. It is a figure which shows the relationship between a function adjustment layer (WCL) and a 1st electrode (Anode), and an energy level. FIG. 8 is a diagram illustrating a relationship between ITO, IGZO, TiO 2 , PbS, 2T-NATA, MoO 3, and ITO and energy levels in the photoelectric conversion element according to the second embodiment of the present technology. The signal charges (electrons) flow from the higher energy level to the lower energy level in FIG. Conversely, holes flow from the lowest energy level to the higher energy level in FIG.
　図７及び図８を参照すれば明らかなように、本技術に係る第２の実施形態の光電変換素子は、ＷＦ０≧ＩＰ３（式５）、ＷＦ０≧ＷＦ２（式６）、ＷＦ０≧ＩＰ２（式７）、及びＥＡ２≦ＥＡ３（式８）を少なくとも満たすので、ｐｎ極性が反転し、暗電流の低減をより促進することができる。 As apparent from FIGS. 7 and 8, the photoelectric conversion element according to the second embodiment of the present technology has WF 0 ≧ I P3 (Formula 5), WF 0 ≧ WF 2 (Formula 6), WF Since at least 0 ≧ I P2 (Equation 7) and E A2 ≦ E A3 (Equation 8) are satisfied, the pn polarity is inverted, and the reduction of dark current can be further promoted.
＜３．第３の実施形態（固体撮像装置の例）＞
　図９は、本技術の第３の実施の形態に係る固体撮像装置を構成する撮像素子１の断面構成を模式的に表したものである。図１０は、図９に示した撮像素子１の要部（光電変換素子１０）の断面構成を拡大して模式的に表したものである。図１１は、図９に示した撮像素子１の等価回路図である。図１２は、図９に示した撮像素子１の下部電極１１および制御部を構成するトランジスタの配置を模式的に表したものである。この撮像素子１は、例えば、ＣＭＯＳイメージセンサ等の固体撮像装置（撮像装置１００１；図２０参照）において１つの画素（単位画素Ｐ）を構成するものである。 <3. Third Embodiment (Example of Solid-State Imaging Device)>
FIG. 9 schematically illustrates a cross-sectional configuration of the imaging element 1 that configures the solid-state imaging device according to the third embodiment of the present technology. FIG. 10 schematically shows an enlarged cross-sectional configuration of a main part (photoelectric conversion element 10) of the imaging element 1 shown in FIG. FIG. 11 is an equivalent circuit diagram of the image sensor 1 shown in FIG. FIG. 12 schematically shows the arrangement of the transistors constituting the lower electrode 11 and the control unit of the image sensor 1 shown in FIG. The imaging device 1 constitutes one pixel (unit pixel P) in a solid-state imaging device (imaging device 1001; see FIG. 20) such as a CMOS image sensor.
（３－１．撮像素子の構成）
　撮像素子１は、例えば、半導体基板３０の第１面（裏面）３０Ａ側に光電変換素子１０が設けられたものである。光電変換素子１０は、対向配置された下部電極１１と上部電極１６（第１電極）との間に、半導体ナノ粒子を用いて形成された光電変換層１５を有する。下部電極１１と光電変換層１５との間には、絶縁層（第１絶縁層）１２を介して第１半導体層（電荷蓄積層）１３が設けられている。下部電極１１は、互いに独立した複数の電極として読み出し電極（第３電極）１１Ａと、蓄積電極（第２電極）１１Ｂと、例えば読み出し電極（第３電極）１１Ａと蓄積電極（第２電極）１１Ｂとの間に配置された転送電極１１Ｃとを有し、蓄積電極１１Ｂおよび転送電極１１Ｃは絶縁層１２によって覆われ、読み出し電極１１Ａは絶縁層１２に設けられた開口１２Ｈを介して第１半導体層１３と電気的に接続されている。本実施の形態では、光電変換素子１０は、第１半導体層１３と光電変換層１５との間に、後述する式（１）～（３）を満たす第２半導体層１４が設けられた構成を有する。 (3-1. Configuration of image sensor)
The imaging element 1 is, for example, one in which the photoelectric conversion element 10 is provided on the first surface (back surface) 30 </ b> A side of the semiconductor substrate 30. The photoelectric conversion element 10 has a photoelectric conversion layer 15 formed using semiconductor nanoparticles between a lower electrode 11 and an upper electrode 16 (first electrode) arranged to face each other. Between the lower electrode 11 and the photoelectric conversion layer 15, a first semiconductor layer (charge storage layer) 13 is provided via an insulating layer (first insulating layer) 12. The lower electrode 11 includes a readout electrode (third electrode) 11A, a storage electrode (second electrode) 11B, for example, a readout electrode (third electrode) 11A and a storage electrode (second electrode) 11B as a plurality of independent electrodes. The storage electrode 11B and the transfer electrode 11C are covered with the insulating layer 12, and the readout electrode 11A is connected to the first semiconductor layer through the opening 12H provided in the insulating layer 12. 13 is electrically connected. In the present embodiment, the photoelectric conversion element 10 has a configuration in which a second semiconductor layer 14 that satisfies formulas (1) to (3) described later is provided between the first semiconductor layer 13 and the photoelectric conversion layer 15. Have.
　なお、本実施の形態では、光電変換によって生じる電子および正孔の対（電子－正孔対）のうち、電子を信号電荷として読み出す場合について説明する。また、図中において、「ｐ」「ｎ」に付した「＋（プラス）」は、ｐ型またはｎ型の不純物濃度が高いことを表し、「＋＋」はｐ型またはｎ型の不純物濃度が「＋」よりも更に高いことを表している。 In the present embodiment, a case will be described in which electrons are read out as signal charges out of electron-hole pairs (electron-hole pairs) generated by photoelectric conversion. In the figure, “+ (plus)” attached to “p” and “n” indicates that the p-type or n-type impurity concentration is high, and “++” indicates that the p-type or n-type impurity concentration is high. It is higher than “+”.
　光電変換素子１０は、選択的な波長域（例えば、７００ｎｍ以上２５００ｎｍ以下）の一部または全部の波長域に対応する光を吸収して、電子－正孔対を発生させる光電変換素子である。光電変換素子１０は、図１０に示したように、例えば、半導体基板３０の第１面３０Ａ側に下部電極１１、絶縁層１２、第１半導体層１３、第２半導体層１４、光電変換層１５および上部電極１６がこの順に積層された構成を有している。なお、図１０では、固定電荷層１７Ａ、誘電体層１７Ｂおよび層間絶縁層１８等は省略して表している。下部電極１１は、例えば、単位画素Ｐごとに分離形成されると共に、詳細は後述するが、絶縁層１２を間に互いに分離された読み出し電極１１Ａ、蓄積電極１１Ｂおよび転送電極１１Ｃから構成されている。第１半導体層１３、第２半導体層１４、光電変換層１５および上部電極１６は、図９では、撮像素子１ごとに分離形成されている例を示したが、例えば、複数の撮像素子１に共通した連続層として設けられていてもよい。 The photoelectric conversion element 10 is a photoelectric conversion element that absorbs light corresponding to a part or all of a selective wavelength range (for example, 700 nm to 2500 nm) and generates electron-hole pairs. As illustrated in FIG. 10, the photoelectric conversion element 10 includes, for example, a lower electrode 11, an insulating layer 12, a first semiconductor layer 13, a second semiconductor layer 14, and a photoelectric conversion layer 15 on the first surface 30 </ b> A side of the semiconductor substrate 30. And the upper electrode 16 has the structure laminated | stacked in this order. In FIG. 10, the fixed charge layer 17A, the dielectric layer 17B, the interlayer insulating layer 18 and the like are omitted. For example, the lower electrode 11 is separately formed for each unit pixel P, and will be described in detail later. The lower electrode 11 includes a readout electrode 11A, a storage electrode 11B, and a transfer electrode 11C that are separated from each other with an insulating layer 12 therebetween. . In FIG. 9, the first semiconductor layer 13, the second semiconductor layer 14, the photoelectric conversion layer 15, and the upper electrode 16 are illustrated as being separately formed for each image sensor 1. It may be provided as a common continuous layer.
　下部電極１１は、上記のように、例えば、互いに独立する読み出し電極（第３電極）１１Ａと、蓄積電極（第２電極）１１Ｂと、転送電極１１Ｃとから構成されている。下部電極１１は、例えば、光透過性を有する導電性材料（透明導電性材料）を用いて形成することができる。透明導電材料のバンドギャップエネルギーは、例えば、２．５ｅＶ以上であることが好ましく、３．１ｅＶ以上であることが望ましい。透明導電材料としては、金属酸化物を上げることができる。具体的には、酸化インジウム、インジウム－錫酸化物（ＩＴＯ，Indium Tin Oxide，ＳｎドープのＩｎ２Ｏ３、結晶性ＩＴＯおよびアモルファスＩＴＯを含む）、酸化亜鉛にドーパントとしてインジウムを添加したインジウム－亜鉛酸化物（ＩＺＯ，Indium Zinc Oxide）、酸化ガリウムにドーパントとしてインジウムを添加したインジウム－ガリウム酸化物（ＩＧＯ）、酸化亜鉛にドーパントとしてインジウムとガリウムを添加したインジウム－ガリウム－亜鉛酸化物（ＩＧＺＯ，Ｉｎ－ＧａＺｎＯ４）、酸化亜鉛にドーパントとしてインジウムと錫を添加したインジウム－錫－亜鉛酸化物（ＩＴＺＯ）、ＩＦＯ（ＦドープのＩｎ２Ｏ３）、酸化錫（ＳｎＯ２）、ＡＴＯ（ＳｂドープのＳｎＯ２）、ＦＴＯ（ＦドープのＳｎＯ２）、酸化亜鉛（他元素をドープしたＺｎＯを含む）、酸化亜鉛にドーパントとしてアルミニウムを添加したアルミニウム－亜鉛酸化物（ＡＺＯ）、酸化亜鉛にドーパントとしてガリウムを添加したガリウム－亜鉛酸化物（ＧＺＯ）、酸化チタン（ＴｉＯ２）、酸化チタンにドーパントとしてニオブを添加したニオブ－チタン酸化物（ＴＮＯ）、酸化アンチモン、スピネル型酸化物、ＹｂＦｅ２Ｏ４構造を有する酸化物を例示することができる。この他、ガリウム酸化物、チタン酸化物、ニオブ酸化物またはニッケル酸化物等を母層とする透明電極を挙げることができる。下部電極１１のＹ軸方向の膜厚（以下、単に厚みとする）は、例えば、２×１０－８ｍ以上２×１０－７ｍ以下であり、好ましくは３×１０－８ｍ以上１×１０－７ｍ以下である。 As described above, the lower electrode 11 includes, for example, mutually independent readout electrodes (third electrodes) 11A, storage electrodes (second electrodes) 11B, and transfer electrodes 11C. The lower electrode 11 can be formed using, for example, a light-transmitting conductive material (transparent conductive material). The band gap energy of the transparent conductive material is preferably 2.5 eV or more, for example, and preferably 3.1 eV or more. A metal oxide can be raised as the transparent conductive material. Specifically, indium-zinc oxide, indium-tin oxide (including ITO, Indium Tin Oxide, Sn-doped In 2 O 3 , crystalline ITO and amorphous ITO), indium-zinc added with indium as a dopant to zinc oxide Oxide (IZO), Indium-gallium oxide (IGO) with gallium oxide added with indium as a dopant, Indium-gallium-zinc oxide with zinc oxide added with indium and gallium (IGZO, In -GaZnO 4) , indium-tin-zinc oxide (ITZO) obtained by adding indium and tin as dopants to zinc oxide, IFO (F-doped In 2 O 3 ), tin oxide (SnO 2 ), ATO (Sb-doped SnO 2 ), FTO (F-doped SnO 2 ), zinc oxide (Including ZnO doped with other elements), aluminum-zinc oxide (AZO) obtained by adding aluminum as a dopant to zinc oxide, gallium-zinc oxide (GZO) obtained by adding gallium as a dopant to zinc oxide, titanium oxide ( Examples thereof include TiO 2 ), niobium-titanium oxide (TNO) obtained by adding niobium as a dopant to titanium oxide, antimony oxide, spinel oxide, and oxide having a YbFe 2 O 4 structure. In addition, the transparent electrode which uses gallium oxide, titanium oxide, niobium oxide, nickel oxide etc. as a base layer can be mentioned. The film thickness of the lower electrode 11 in the Y-axis direction (hereinafter simply referred to as thickness) is, for example, 2 × 10 −8 m or more and 2 × 10 −7 m or less, preferably 3 × 10 −8 m or more and 1 ×. 10 −7 m or less.
　なお、下部電極１１に透明性が不要である場合には、下部電極１１は、例えば、白金（Ｐｔ）、金（Ａｕ）、パラジウム（Ｐｄ）、クロム（Ｃｒ）、ニッケル（Ｎｉ）、アルミニウム（Ａｌ）、銀（Ａｇ）、タンタル（Ｔａ）、タングステン（Ｗ）、銅（Ｃｕ）、チタン（Ｔｉ）、インジウム（Ｉｎ）、錫（Ｓｎ）、鉄（Ｆｅ）、コバルト（Ｃｏ）およびモリブデン（Ｍｏ）等の金属あるいはそれらの合金を用いた単層膜または積層膜として形成することができる。具体的には、Ａｌ－Ｎｄ（アルミニウムとネオジウムとの合金）やＡＳＣ（アルミニウムとサマリウムと銅との合金）等を用いて形成することができる。また、下部電極１１は、上記金属あるいはそれらの合金からなる導電性粒子、不純物を含有したポリシリコン、炭素系材料、酸化物半導体材料、カーボンナノチューブおよびグラフェン等の導電性材料を用いて形成するようにしてもよい。この他、下部電極１１は、ポリ（３，４－エチレンジオキシチオフェン）／ポリスチレンスルホン酸［ＰＥＤＯＴ／ＰＳＳ］といった有機材料（導電性高分子）を用いて形成してもよく、これらの導電性材料をバインダー（高分子）に混合してペースト又はインクとしたものを硬化させて形成するようにしてもよい。 When the lower electrode 11 does not require transparency, the lower electrode 11 is formed of, for example, platinum (Pt), gold (Au), palladium (Pd), chromium (Cr), nickel (Ni), aluminum ( Al), silver (Ag), tantalum (Ta), tungsten (W), copper (Cu), titanium (Ti), indium (In), tin (Sn), iron (Fe), cobalt (Co) and molybdenum ( It can be formed as a single layer film or a laminated film using a metal such as Mo) or an alloy thereof. Specifically, it can be formed using Al—Nd (alloy of aluminum and neodymium), ASC (alloy of aluminum, samarium and copper) or the like. In addition, the lower electrode 11 is formed using a conductive material such as the above-described metal or an alloy thereof, polysilicon containing impurities, a carbon-based material, an oxide semiconductor material, a carbon nanotube, and graphene. It may be. In addition, the lower electrode 11 may be formed using an organic material (conductive polymer) such as poly (3,4-ethylenedioxythiophene) / polystyrene sulfonic acid [PEDOT / PSS]. The material may be mixed with a binder (polymer) to form a paste or ink, which may be cured.
　読み出し電極１１Ａは、光電変換層１５内で発生した信号電荷をフローティングディフュージョンＦＤ１に転送するためのものである。読み出し電極１１Ａは、例えば、上部第１コンタクト１８Ａ、パッド部３９Ａ、貫通電極３４、接続部４１Ａおよび下部第２コンタクト４６を介して、半導体基板２０の第２面（表面）３０Ｂ側に設けられたフローティングディフュージョンＦＤ１に接続されている。 The readout electrode 11A is for transferring the signal charge generated in the photoelectric conversion layer 15 to the floating diffusion FD1. The readout electrode 11A is provided on the second surface (front surface) 30B side of the semiconductor substrate 20 via, for example, the upper first contact 18A, the pad portion 39A, the through electrode 34, the connection portion 41A, and the lower second contact 46. It is connected to the floating diffusion FD1.
　蓄積電極１１Ｂは、光電変換層１５内で発生した電荷のうち、信号電荷（電子）を第１半導体層１３内に蓄積するためのものである。蓄積電極１１Ｂは、読み出し電極１１Ａよりも大きいことが好ましく、これにより、多くの電荷を蓄積することができる。 The storage electrode 11 </ b> B is for storing signal charges (electrons) in the first semiconductor layer 13 among the charges generated in the photoelectric conversion layer 15. The storage electrode 11B is preferably larger than the readout electrode 11A, so that a large amount of charge can be stored.
　転送電極１１Ｃは、蓄積電極１１Ｂで蓄積された電荷の読み出し電極１１Ａへの転送の効率を向上させるためのものであり、読み出し電極１１Ａと蓄積電極１１Ｂとの間に設けられている。この転送電極１１Ｃは、例えば、上部第３コンタクト１８Ｃおよびパッド部３９Ｃを介して駆動回路を構成する画素駆動回路に接続されている。読み出し電極１１Ａ、蓄積電極１１Ｂおよび転送電極１１Ｃは、各々独立して電圧を印加することが可能となっている。 The transfer electrode 11C is for improving the efficiency of transferring the charge accumulated in the storage electrode 11B to the read electrode 11A, and is provided between the read electrode 11A and the storage electrode 11B. The transfer electrode 11C is connected to, for example, a pixel drive circuit constituting a drive circuit via the upper third contact 18C and the pad portion 39C. The readout electrode 11A, the storage electrode 11B, and the transfer electrode 11C can apply a voltage independently.
　絶縁層（第１絶縁層）１２は、蓄積電極１１Ｂおよび転送電極１１Ｃと第１半導体層（電荷蓄積層）１３とを電気的に分離するためのものである。絶縁層１２は、下部電極１１を覆うように、例えば、層間絶縁層１８上に設けられている。また、絶縁層１２には、下部電極１１のうち、読み出し電極１１Ａ上に開口１２Ｈが設けられており、この開口１２Ｈを介して、読み出し電極１１Ａと第１半導体層１３とが電気的に接続されている。開口１２Ｈの側面は、例えば、図１０に示したように、光入射側Ｓ１に向かって広がる傾斜を有することが好ましい。これにより、第１半導体層１３から読み出し電極１１Ａへの電荷の移動がより滑らかとなる。 The insulating layer (first insulating layer) 12 is for electrically separating the storage electrode 11B and the transfer electrode 11C from the first semiconductor layer (charge storage layer) 13. For example, the insulating layer 12 is provided on the interlayer insulating layer 18 so as to cover the lower electrode 11. The insulating layer 12 is provided with an opening 12H on the readout electrode 11A of the lower electrode 11, and the readout electrode 11A and the first semiconductor layer 13 are electrically connected through the opening 12H. ing. For example, as shown in FIG. 10, the side surface of the opening 12H preferably has an inclination that widens toward the light incident side S1. Thereby, the movement of charges from the first semiconductor layer 13 to the readout electrode 11A becomes smoother.
　絶縁層１２の材料としては、酸化ケイ素系材料、窒化ケイ素（ＳｉＮｘ）、酸化アルミニウム（Ａｌ２Ｏ３）等の金属酸化物高誘電絶縁材料等の無機系絶縁材料が挙げられる。この他、ポリメチルメタクリレート（ＰＭＭＡ）、ポリビニルフェノール（ＰＶＰ）、ポリビニルアルコール（ＰＶＡ）、ポリイミド、ポリカーボネート（ＰＣ）、ポリエチレンテレフタレート（ＰＥＴ）、ポリスチレン、Ｎ－２（アミノエチル）３－アミノプロピルトリメトキシシラン（ＡＥＡＰＴＭＳ）、３－メルカプトプロピルトリメトキシシラン（ＭＰＴＭＳ）、オクタデシルトリクロロシラン（ＯＴＳ）等のシラノール誘導体（シランカップリング剤）、ノボラック型フェノール樹脂、フッ素系樹脂、オクタデカンチオール、ドデシルイソシアネイト等の一端に制御電極と結合可能な官能基を有する直鎖炭化水素類にて例示される有機系絶縁材料（有機ポリマー）を挙げることができ、これらを組み合わせて用いることもできる。なお、酸化ケイ素系材料としては、酸化シリコン（ＳｉＯｘ）、ＢＰＳＧ、ＰＳＧ、ＢＳＧ、ＡｓＳＧ、ＰｂＳＧ、酸化窒化シリコン（ＳｉＯＮ）、ＳＯＧ（スピンオングラス）、低誘電率材料（例えば、ポリアリールエーテル、シクロパーフルオロカーボンポリマーおよびベンゾシクロブテン、環状フッ素樹脂、ポリテトラフルオロエチレン、フッ化アリールエーテル、フッ化ポリイミド、アモルファスカーボンおよび有機ＳＯＧ）が挙げられる。 Examples of the material of the insulating layer 12 include inorganic insulating materials such as silicon oxide materials, metal oxide high dielectric insulating materials such as silicon nitride (SiN x ), and aluminum oxide (Al 2 O 3 ). In addition, polymethyl methacrylate (PMMA), polyvinylphenol (PVP), polyvinyl alcohol (PVA), polyimide, polycarbonate (PC), polyethylene terephthalate (PET), polystyrene, N-2 (aminoethyl) 3-aminopropyltrimethoxy Silanol derivatives (silane coupling agents) such as silane (AEAPTMS), 3-mercaptopropyltrimethoxysilane (MPTMS), octadecyltrichlorosilane (OTS), novolac-type phenol resin, fluorine-based resin, octadecanethiol, dodecyl isocyanate, etc. An organic insulating material (organic polymer) exemplified by linear hydrocarbons having a functional group capable of binding to the control electrode at one end can be given, and these can also be used in combination. Examples of the silicon oxide-based material include silicon oxide (SiO x ), BPSG, PSG, BSG, AsSG, PbSG, silicon oxynitride (SiON), SOG (spin-on-glass), low dielectric constant materials (for example, polyaryl ether, Cycloperfluorocarbon polymer and benzocyclobutene, cyclic fluororesin, polytetrafluoroethylene, fluorinated aryl ether, fluorinated polyimide, amorphous carbon and organic SOG).
　第１半導体層（電荷蓄積層）１３は、光電変換層１５内で発生した信号電荷を蓄積すると共に、読み出し電極１１Ａへ転送するためのものである。第１半導体層１３は、光電変換層１５よりも電荷の移動度が高く、且つ、バンドギャップが大きな材料を用いて形成されていることが好ましい。これにより、例えば、電荷の転送速度を向上させることが可能になる共に、読み出し電極１１Ａから第１半導体層１３への正孔の注入が抑制される。 The first semiconductor layer (charge storage layer) 13 is for accumulating signal charges generated in the photoelectric conversion layer 15 and transferring them to the readout electrode 11A. The first semiconductor layer 13 is preferably formed using a material having a charge mobility higher than that of the photoelectric conversion layer 15 and a large band gap. Thereby, for example, the charge transfer rate can be improved, and the injection of holes from the read electrode 11A to the first semiconductor layer 13 is suppressed.
　第１半導体層１３は、例えば、酸化物半導体材料を含んで構成されている。酸化物半導体材料としては、例えば、ＩＧＺＯ（Ｉｎ－Ｇａ－Ｚｎ－Ｏ系酸化物半導体），ＺＴＯ（Ｚｎ－Ｓｎ－Ｏ系酸化物半導体），ＩＧＺＴＯ（Ｉｎ－Ｇａ－Ｚｎ－Ｓｎ－Ｏ系酸化物半導体）、ＧＴＯ（Ｇａ－Ｓｎ－Ｏ系酸化物半導体）およびＩＧＯ（Ｉｎ－Ｇａ－Ｏ系酸化物半導体）が挙げられる。第１半導体層１３は、上記酸化物半導体材料を少なくとも１種用いることが好ましく、なかでもＩＧＺＯが好適に用いられる。第１半導体層１３の厚みは、例えば、３０ｎｍ以上２００ｎｍ以下であり、好ましくは６０ｎｍ以上１５０ｎｍ以下である。 The first semiconductor layer 13 includes, for example, an oxide semiconductor material. Examples of the oxide semiconductor material include IGZO (In—Ga—Zn—O-based oxide semiconductor), ZTO (Zn—Sn—O-based oxide semiconductor), and IGZTO (In—Ga—Zn—Sn—O-based oxide). Oxide semiconductor), GTO (Ga—Sn—O-based oxide semiconductor), and IGO (In—Ga—O-based oxide semiconductor). For the first semiconductor layer 13, it is preferable to use at least one of the above oxide semiconductor materials, and among them, IGZO is preferably used. The thickness of the first semiconductor layer 13 is, for example, 30 nm to 200 nm, preferably 60 nm to 150 nm.
　第２半導体層（ｎ型バッファ層）１４は、光電変換層１５で生じた電子の第１半導体層への供給を促進するためのものであり、例えば、ＺｎＯ、ＴｉＯ２、ＩＧＺＯ，ＺＴＯ，Ｚｎ２ＳｎＯ４，ＩｎＧａＺｎＳｎＯ，ＧＴＯ，Ｇａ２Ｏ３：ＳｎＯ２およびＩＧＯ等により構成されていてよく、前記の材料を複数積層させて第２半導体層１４を構成するようにしてもよい。第２半導体層１４の厚みは、例えば、１ｎｍ以上２０ｎｍ以下であり、好ましくは３ｎｍ以上１０ｎｍ以下である。また、第２半導体層１４は、高分子半導体材料から構成されてもよい。 The second semiconductor layer (n-type buffer layer) 14 is for promoting the supply of electrons generated in the photoelectric conversion layer 15 to the first semiconductor layer. For example, ZnO, TiO 2 , IGZO, ZTO, Zn 2 SnO 4 , InGaZnSnO, GTO, Ga 2 O 3 : SnO 2, IGO, or the like may be used, and the second semiconductor layer 14 may be formed by stacking a plurality of the above materials. The thickness of the second semiconductor layer 14 is, for example, not less than 1 nm and not more than 20 nm, preferably not less than 3 nm and not more than 10 nm. The second semiconductor layer 14 may be made of a polymer semiconductor material.
　高分子半導体材料としては、例えば、母骨格としてナフタレンジイミドを含む下記一般式（１）及び一般式（２）に示した化合物（ナフタレンジイミド誘導体）が挙げられる。ナフタレンジイミド誘導体の具体例としては、例えば下記の式（１－１）に示した化合物が挙げられる。 Examples of the polymer semiconductor material include compounds represented by the following general formula (1) and general formula (2) (naphthalenediimide derivatives) containing naphthalenediimide as a mother skeleton. Specific examples of naphthalenediimide derivatives include compounds represented by the following formula (1-1).
Figure JPOXMLDOC01-appb-C000004
Figure JPOXMLDOC01-appb-C000004
　該式（１）中のＲ１は、各々独立して水素原子、直鎖，分岐または環状のアルキル基、フェニル基、直鎖または縮環した芳香族化合物を有する基、複素環化合物を有する基、ハロゲン化物を有する基、パーシャルフルオロアルキル基、パーフルオロアルキル基、シリルアルキル基、シリルアルコキシ基、アリールシリル基、を有する基、あるいはそれらの誘導体である。 R 1 in the formula (1) is each independently a hydrogen atom, a linear, branched or cyclic alkyl group, a phenyl group, a group having a linear or condensed aromatic compound, or a group having a heterocyclic compound. A group having a halide, a partial fluoroalkyl group, a perfluoroalkyl group, a silylalkyl group, a silylalkoxy group, an arylsilyl group, or a derivative thereof.
Figure JPOXMLDOC01-appb-C000005
Figure JPOXMLDOC01-appb-C000005
　該式（２）中のＲ１及びＲ２は、各々独立して水素原子、直鎖，分岐または環状のアルキル基、フェニル基、直鎖または縮環した芳香族化合物を有する基、複素環化合物を有する基、ハロゲン化物を有する基、パーシャルフルオロアルキル基、パーフルオロアルキル基、シリルアルキル基、シリルアルコキシ基、アリールシリル基、を有する基、あるいはそれらの誘導体である。Ｘは、芳香族化合物、ヘテロ芳香族化合物、多環芳香族環化合物、ヘテロ多環芳香族環化合物が、1つ以上、5つ以下連なった化合物であり、置換基を有していてもよい。 R 1 and R 2 in the formula (2) are each independently a hydrogen atom, a linear, branched or cyclic alkyl group, a phenyl group, a group having a linear or condensed aromatic compound, a heterocyclic compound , A group having a halide, a partial fluoroalkyl group, a perfluoroalkyl group, a silylalkyl group, a silylalkoxy group, an arylsilyl group, or a derivative thereof. X is a compound in which one or more, five or less heteroaromatic ring compounds are aromatic compounds, heteroaromatic compounds, polycyclic aromatic ring compounds, or heteropolycyclic aromatic ring compounds, and may have a substituent. .
Figure JPOXMLDOC01-appb-C000006
Figure JPOXMLDOC01-appb-C000006
　光電変換層１５は、光エネルギーを電気エネルギーに変換するものであり、例えば、４００ｎｍ以上２５００ｎｍ以下の波長域の光を吸収した際に生じる励起子が電子と正孔とに分離する場を提供するものである。光電変換層１５の厚みは、例えば、１００ｎｍ以上１０００ｎｍ以下であり、好ましくは３００ｎｍ以上８００ｎｍ以下である。 The photoelectric conversion layer 15 converts light energy into electrical energy, and provides, for example, a field where excitons generated when absorbing light in a wavelength range of 400 nm to 2500 nm are separated into electrons and holes. Is. The thickness of the photoelectric conversion layer 15 is, for example, not less than 100 nm and not more than 1000 nm, preferably not less than 300 nm and not more than 800 nm.
　光電変換層１５は、量子ドットを構成する半導体ナノ粒子を含んで形成されている。半導体ナノ粒子は、一般に数～数十ｎｍの粒径を有する粒子である。半導体ナノ粒子を構成する材料としては、例えば、少なくとも1つのＴｉＯ２、ＺｎＯ、ＷＯ３、ＮｉＯ、ＭｏＯ３、ＣｕＯ、Ｇａ２Ｏ３、ＳｒＴｉＯ３、ＳｎＯ２、ＩｎＳｎＯｘ、Ｎｂ２Ｏ３、ＭｎＯ２、Ｖ２Ｏ３、ＣｒＯ、ＣｕＩｎＳｅ２、ＣｕＩｎＳ２、ＣｕＺｎＣｕＳｎＳＳｅ、ＣｕＩｎＧａＳｅ、Ａｇ２Ｓ、ＡｇＩｎＳ２、ＡｌＳｅ２、ＡｌＧａＡｓ、Ｓｉ、Ｓｅ、ＰｂＳ、ＰｂＳｅ、ＰｂＴｅ、ＣｄＳ、ＣｄＳｅ、ＣｄＴｅ、Ｆｅ２Ｏ３、ＧａＡｓ、ＧａＰ、ＩｎＰ、ＩｎＡｓ、ＩｎＳｅ２、ＩｎＳｂ、Ｇｅ、Ｉｎ２Ｓ３、ＨｇＴｅ、Ｂｉ２Ｓ３、ＺｎＳｅ、ＺｎＴｅ、ＺｎＳ、ＺｎＣｕＩｎＳ等により構成されている。量子ドット材料の粒径は任意の大きさでよいが、吸収する光（吸収する波長帯）に応じて、量子ドット材料の粒径を適宜変更してよい。また、粒子の周囲を他材料で覆ったコアシェル構造をとってもよく、シェルを構成する材料としては、ＰｂＯ、ＰｂＯ２、Ｐｂ３Ｏ４、ＺｎＳ、ＺｎＳｅ、ＺｎＴｅなどが挙げられる。 The photoelectric conversion layer 15 is formed including semiconductor nanoparticles constituting quantum dots. Semiconductor nanoparticles are generally particles having a particle size of several to several tens of nm. Examples of the material constituting the semiconductor nanoparticles include at least one of TiO 2 , ZnO, WO 3 , NiO, MoO 3 , CuO, Ga 2 O 3 , SrTiO 3 , SnO 2 , InSnOx, Nb 2 O 3 , MnO 2. , V 2 O 3, CrO, CuInSe 2, CuInS 2, CuZnCuSnSSe, CuInGaSe, Ag 2 S, AgInS 2, AlSe 2, AlGaAs, Si, Se, PbS, PbSe, PbTe, CdS, CdSe, CdTe, Fe 2 O 3 , GaAs, GaP, InP, InAs , InSe 2, InSb, Ge, in 2 S 3, HgTe, Bi 2 S 3, ZnSe, ZnTe, ZnS, is constituted by ZnCuInS like. The particle size of the quantum dot material may be any size, but the particle size of the quantum dot material may be changed as appropriate in accordance with the light to be absorbed (absorbing wavelength band). In addition, a core-shell structure in which the periphery of the particle is covered with another material may be used, and examples of the material constituting the shell include PbO, PbO 2 , Pb 3 O 4 , ZnS, ZnSe, and ZnTe.
　半導体ナノ粒子は、粒径が材料のエキシトンーボーア半径の２倍よりも小さくなると量子閉じ込め効果によってバンドギャップが大きくなる。本実施の形態では、光電変換層１５を構成する半導体ナノ粒子は、例えばＰｂＳでは平均粒径３ｎｍ以上６ｎｍ以下であることが好ましい。半導体ナノ粒子の表面には、相互作用を及ぼす配位子が配位してもよく、これによって、半導体ナノ粒子の粒径制御や表面欠陥サイトからの失活の抑制、あるいは、伝導経路の制御といった効果が期待される。配位子は、相互作用を及ぼす吸着基と、それに結合するアルキル鎖とから構成されており、アルキル鎖の炭素の数は例えば２～５０であり、吸着基は例えばアミン、ホスホン、ホスフィン、カルボキシル、ヒドロキシル、チオールである。この他、塩素（Ｃｌ）、臭素（Ｂｒ）およびヨウ素（Ｉ）等のハロゲン元素を用いてもよい。 Semiconductor nanoparticles have a larger band gap due to the quantum confinement effect when the particle size is smaller than twice the exciton-bohr radius of the material. In this Embodiment, it is preferable that the semiconductor nanoparticles which comprise the photoelectric converting layer 15 are 3 nm or more and 6 nm or less in average particle diameter in PbS, for example. The surface of the semiconductor nanoparticle may be coordinated with an interacting ligand, which controls the particle size of the semiconductor nanoparticle, suppresses deactivation from surface defect sites, or controls the conduction path. Such effects are expected. The ligand is composed of an adsorbing group that interacts and an alkyl chain bonded thereto, and the number of carbons in the alkyl chain is, for example, 2 to 50. , Hydroxyl, thiol. In addition, halogen elements such as chlorine (Cl), bromine (Br), and iodine (I) may be used.
　図示はされていないが、上部電極（第１電極）１６と、光電変換層１５との間には仕事関数調整層が配されている。仕事関数調整層は、有機化合物を含んでもよく、仕事関数調整層（ＷＣＬ）として機能する有機化合物の例としては、2,3,5,6-テトラフルオロ-テトラシアノキノジメタン（Ｆ４－ＴＣＮＱ）、2,3,5-トリフルオロ-テトラシアノキノジメタン（Ｆ３－ＴＣＮＱ）、2,5-ジフルオロ-テトラシアノキノジメタン（Ｆ２－ＴＣＮＱ）、2-フルオロ-テトラシアノキノジメタン（Ｆ１－ＴＣＮＱ）、2-トリフルオロメチル-テトラシアノキノジメタン（ＣＦ３－ＴＣＮＱ）、1,3,4,5,7,8-ヘキサフルオロ-テトラシアノナフトキノジメタン（Ｆ６－ＴＣＮＱ）などのテトラシアノキノジメタン誘導体、及び、1,4,5,8,9,12‐ヘキサアザトリフェニレン‐2,3,6,7,10,11‐ヘキサカルボニトリル（ＨＡＴＣＮ）などのヘキサアザトリフェニレン誘導体、及び、2,3,8,9,14,15-ヘキサクロロ-5,6,11,12,17,18-ヘキサアザトリナフチレン（ＨＡＴＮＡ－Ｃｌ６）、2,3,8,9,14,15-ヘキサフルオロ-5,6,11,12,17,18-ヘキサアザトリナフチレン（ＨＡＴＮＡ－Ｆ６）などのヘキサアザトリナフチレン誘導体、及び、1,2,3,4,8,9,10,11,15,16,17,18,22,23,24,25-ヘキサデカフルオロ-銅フタロシアニン（Ｆ１６－ＣｕＰｃ）などのフタロシアニン誘導体、及び、Ｃ６０Ｆ３６やＣ６０Ｆ４８などのフッ化フラーレンが挙げられるが、これらに限定されるものではない。 Although not shown, a work function adjusting layer is disposed between the upper electrode (first electrode) 16 and the photoelectric conversion layer 15. The work function adjusting layer may contain an organic compound. Examples of the organic compound functioning as the work function adjusting layer (WCL) include 2,3,5,6-tetrafluoro-tetracyanoquinodimethane (F4-TCNQ). ), 2,3,5-trifluoro-tetracyanoquinodimethane (F3-TCNQ), 2,5-difluoro-tetracyanoquinodimethane (F2-TCNQ), 2-fluoro-tetracyanoquinodimethane (F1) -TCNQ), 2-trifluoromethyl-tetracyanoquinodimethane (CF3-TCNQ), 1,3,4,5,7,8-hexafluoro-tetracyanonaphthoquinodimethane (F6-TCNQ) and other tetra Cyanoquinodimethane derivatives and hexaazatriphenylene derivatives such as 1,4,5,8,9,12-hexaazatriphenylene-2,3,6,7,10,11-hexacarbonitrile (HATCN), and 2,3,8,9,14,15-hexachrome B-5,6,11,12,17,18-hexaazatrinaphthylene (HATNA-Cl6), 2,3,8,9,14,15-hexafluoro-5,6,11,12,17, Hexaazatrinaphthylene derivatives such as 18-hexaazatrinaphthylene (HATNA-F6), and 1,2,3,4,8,9,10,11,15,16,17,18,22,23 , 24,25-hexadecafluoro-copper phthalocyanine (F16-CuPc) and other phthalocyanine derivatives and fluorinated fullerenes such as C 60 F 36 and C 60 F 48, but are not limited thereto. .
　また、仕事関数調整層は、無機化合物を含んでもよく、仕事関数調整層（ＷＣＬ）として機能する無機化合物の例としては、酸化モリブデン（ＭｏＯ３）、酸化タングステン（ＷＯ３）、酸化バナジウム（Ｖ２Ｏ５）、酸化レニウム（ＲｅＯ３）などの遷移金属酸化物、及び、ヨウ化銅（ＣｕＩ）、塩化アンチモン（ＳｂＣｌ５）、酸化鉄（ＦｅＣｌ３）、塩化ナトリウム（ＮａＣｌ）などの塩が挙げられるが、これらに限定されるものではない。 The work function adjusting layer may contain an inorganic compound. Examples of inorganic compounds that function as the work function adjusting layer (WCL) include molybdenum oxide (MoO 3 ), tungsten oxide (WO 3 ), and vanadium oxide (V 2 O 5 ), transition metal oxides such as rhenium oxide (ReO 3 ), and salts such as copper iodide (CuI), antimony chloride (SbCl 5 ), iron oxide (FeCl 3 ), and sodium chloride (NaCl). Although it is mentioned, it is not limited to these.
　撮像素子１はｐ型バッファ層を備えていてもよい。ｐ型バッファ層は、光電変換層１５で生じた正孔の第１電極２０１への供給を促進するためのものであり、例えば、酸化モリブデン（ＭｏＯ３），酸化ニッケル（ＮｉＯ）又は酸化バナジウム（Ｖ２Ｏ５）等により構成されていてよい。ＰＥＤＯＴ（Ｐｏｌｙ(３，４-ｅｔｈｙｌｅｎｅｄｉｏｘｙｔｈｉｏｐｈｅｎｅ)）、ＴＰＤ（Ｎ，Ｎ'-Ｂｉｓ(３-ｍｅｔｈｙｌｐｈｅｎｙｌ)-Ｎ，Ｎ'-ｄｉｐｈｅｎｙｌｂｅｎｚｉｄｉｎｅ）、２Ｔ－ＮＡＴＡ（4,4',4''-トリス[2-ナフチル(フェニル)アミノ]トリフェニルアミン）等の有機材料によりｐ型バッファ層（正孔輸送層）を構成するようにしてもよい。 The image sensor 1 may include a p-type buffer layer. The p-type buffer layer is for accelerating the supply of holes generated in the photoelectric conversion layer 15 to the first electrode 201. For example, molybdenum oxide (MoO 3 ), nickel oxide (NiO), or vanadium oxide ( V 2 O 5 ) or the like. PEDOT (Poly (3,4-ethylenedithiothiophene)), TPD (N, N′-Bis (3-methylphenyl) -N, N′-diphenylbenzidine), 2T-NATA (4,4 ′, 4 ″ -Tris [2 The p-type buffer layer (hole transport layer) may be composed of an organic material such as (naphthyl (phenyl) amino] triphenylamine).
　上部電極（第１電極）１６は、光透過性を有する導電性材料により構成されている。上部電極１６は単位画素Ｐ毎に分離されていてもよいし、各単位画素Ｐに共通の電極として形成されていてもよい。上部電極１６の厚みは、例えば、１０ｎｍ～２００ｎｍである。 The upper electrode (first electrode) 16 is made of a light-transmitting conductive material. The upper electrode 16 may be separated for each unit pixel P, or may be formed as a common electrode for each unit pixel P. The thickness of the upper electrode 16 is, for example, 10 nm to 200 nm.
　本実施の形態の光電変換素子１０では、上部電極１６側から光電変換素子１０に入射した近赤外光Ｌは光電変換層１５で吸収される。これによって生じた励起子は、例えば図１３Ａに示したように励起子分離して電子と正孔とに解離する。ここで発生した電荷（電子および正孔）は、キャリアの濃度差による拡散や、陽極（ここでは、上部電極１６）と陰極（ここでは、下部電極１１）との仕事関数の差による内部電界によって、例えば図１３Ｂに示したように、それぞれ異なる電極へ運ばれる。電子および正孔の輸送方向は、下部電極１１と上部電極１６との間に電位を印加することによって制御される。ここでは、電子が信号電荷として下部電極１１側に運ばれる。下部電極１１側に運ばれた電子は、蓄積電極１１Ｂ上の第１半導体層１３内に蓄積されたのち、図１３Ｃに示したように、読み出し電極１１Ａに向かって転送され、光電流として検出される。 In the photoelectric conversion element 10 of the present embodiment, the near infrared light L incident on the photoelectric conversion element 10 from the upper electrode 16 side is absorbed by the photoelectric conversion layer 15. The excitons generated thereby are separated into electrons and holes by exciton separation as shown in FIG. 13A, for example. The charges (electrons and holes) generated here are caused by diffusion due to the carrier concentration difference or an internal electric field due to the work function difference between the anode (here, the upper electrode 16) and the cathode (here, the lower electrode 11). For example, as shown in FIG. 13B, they are conveyed to different electrodes. The transport direction of electrons and holes is controlled by applying a potential between the lower electrode 11 and the upper electrode 16. Here, the electrons are carried as signal charges to the lower electrode 11 side. The electrons carried to the lower electrode 11 side are accumulated in the first semiconductor layer 13 on the storage electrode 11B, and then transferred toward the readout electrode 11A and detected as a photocurrent, as shown in FIG. 13C. The
　半導体基板３０の第２面３０Ｂには、例えば、フローティングディフュージョン（浮遊拡散層）ＦＤ１（半導体基板３０内の領域３６Ｂ）アンプトランジスタ（変調素子）ＡＭＰと、リセットトランジスタＲＳＴと、選択トランジスタＳＥＬと、多層配線４０とが設けられている。多層配線４０は、例えば、配線層４１，４２，４３が絶縁層４４内に積層された構成を有している。 The second surface 30B of the semiconductor substrate 30 includes, for example, a floating diffusion (floating diffusion layer) FD1 (region 36B in the semiconductor substrate 30) an amplifier transistor (modulation element) AMP, a reset transistor RST, a selection transistor SEL, and a multilayer Wiring 40 is provided. The multilayer wiring 40 has a configuration in which, for example, wiring layers 41, 42, and 43 are laminated in an insulating layer 44.
　なお、図面では、半導体基板３０の第１面３０Ａ側を光入射側Ｓ１、第２面３０Ｂ側を配線層側Ｓ２と表している。 In the drawing, the first surface 30A side of the semiconductor substrate 30 is represented as the light incident side S1, and the second surface 30B side is represented as the wiring layer side S2.
　半導体基板３０の第１面３０Ａと下部電極１１との間には、例えば、固定電荷を有する層（固定電荷層）１７Ａと、絶縁性を有する誘電体層１７Ｂと、層間絶縁層１８とが設けられている。上部電極１６の上には、保護層１９が設けられている。保護層１９内には、例えば、読み出し電極１１Ａ上に、例えば遮光膜２１が設けられている。この遮光膜２１Ａは、少なくとも蓄積電極１１Ｂにはかからず、少なくとも光電変換層１５と直接接している読み出し電極１１Ａの領域を覆うように設けられていればよい。例えば、蓄積電極１１Ｂと同じ層に形成されている読み出し電極１１Ａよりも一回り大きく設けられていることが好ましい。また、例えば、蓄積電極１１Ｂ上に、例えばカラーフィルタ２２が設けられている。カラーフィルタ２２は、例えば光電変換層１５への可視光の入射を防ぐためのものであり、少なくとも蓄積電極１１Ｂの領域を覆うように設けられていればよい。なお、図９では、遮光膜２１およびカラーフィルタ２２を保護層１９の膜厚方向において異なる位置に設けた例を示したが、同じ位置に設けるようにしてもよい。保護層１９の上方には、平坦化層（図示せず）やオンチップレンズ２３等の光学部材が配設されている。 Between the first surface 30A of the semiconductor substrate 30 and the lower electrode 11, for example, a layer (fixed charge layer) 17A having a fixed charge, a dielectric layer 17B having insulating properties, and an interlayer insulating layer 18 are provided. It has been. A protective layer 19 is provided on the upper electrode 16. In the protective layer 19, for example, a light shielding film 21 is provided on the readout electrode 11A, for example. The light shielding film 21A may be provided so as not to cover at least the storage electrode 11B but to cover at least the region of the readout electrode 11A in direct contact with the photoelectric conversion layer 15. For example, it is preferable that the electrode is provided slightly larger than the readout electrode 11A formed in the same layer as the storage electrode 11B. For example, a color filter 22 is provided on the storage electrode 11B, for example. The color filter 22 is for preventing visible light from entering the photoelectric conversion layer 15, for example, and may be provided so as to cover at least the region of the storage electrode 11 </ b> B. Although FIG. 9 shows an example in which the light shielding film 21 and the color filter 22 are provided at different positions in the film thickness direction of the protective layer 19, they may be provided at the same position. Above the protective layer 19, an optical member such as a planarizing layer (not shown) and an on-chip lens 23 is disposed.
　固定電荷層１７Ａは、正の固定電荷を有する膜でもよいし、負の固定電荷を有する膜でもよい。負の固定電荷を有する膜の材料としては、酸化ハフニウム、酸化アルミニウム、酸化ジルコニウム、酸化タンタル、酸化チタン等が挙げられる。また上記以外の材料としては酸化ランタン、酸化プラセオジム、酸化セリウム、酸化ネオジム、酸化プロメチウム、酸化サマリウム、酸化ユウロピウム、酸化ガドリニウム、酸化テルビウム、酸化ジスプロシウム、酸化正孔ミウム、酸化ツリウム、酸化イッテルビウム、酸化ルテチウム、酸化イットリウム、窒化アルミニウム膜、酸窒化ハフニウム膜または酸窒化アルミニウム膜等を用いてもよい。 The fixed charge layer 17A may be a film having a positive fixed charge or a film having a negative fixed charge. Examples of the material of the film having a negative fixed charge include hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, and titanium oxide. In addition to the above materials, lanthanum oxide, praseodymium oxide, cerium oxide, neodymium oxide, promethium oxide, samarium oxide, europium oxide, gadolinium oxide, terbium oxide, dysprosium oxide, holeium oxide, thulium oxide, ytterbium oxide, lutetium oxide Alternatively, an yttrium oxide, an aluminum nitride film, a hafnium oxynitride film, an aluminum oxynitride film, or the like may be used.
　固定電荷層１７Ａは、２種類以上の膜を積層した構成を有していてもよい。それにより、例えば負の固定電荷を有する膜の場合には正孔蓄積層としての機能をさらに高めることが可能である。 The fixed charge layer 17A may have a configuration in which two or more kinds of films are stacked. Thereby, for example, in the case of a film having a negative fixed charge, the function as the hole accumulation layer can be further enhanced.
　誘電体層１７Ｂの材料は特に限定されないが、例えば、シリコン酸化膜、ＴＥＯＳ、シリコン窒化膜、シリコン酸窒化膜等によって形成されている。 The material of the dielectric layer 17B is not particularly limited. For example, the dielectric layer 17B is formed of a silicon oxide film, TEOS, a silicon nitride film, a silicon oxynitride film, or the like.
　層間絶縁層（第２絶縁層と称される場合もある。）１８は、例えば、酸化シリコン、窒化シリコンおよび酸窒化シリコン（ＳｉＯＮ）等のうちの１種よりなる単層膜か、あるいはこれらのうちの２種以上よりなる積層膜により構成されている。 The interlayer insulating layer (sometimes referred to as a second insulating layer) 18 is, for example, a single layer film made of one of silicon oxide, silicon nitride, silicon oxynitride (SiON), or the like, or these It is comprised by the laminated film which consists of 2 or more types of them.
　保護層１９は、光透過性を有する材料により構成され、例えば、酸化シリコン、窒化シリコンおよび酸窒化シリコン等のうちのいずれかよりなる単層膜、あるいはそれらのうちの２種以上よりなる積層膜により構成されている。保護層１９の厚みは、例えば、１００ｎｍ～３００００ｎｍである。 The protective layer 19 is made of a light-transmitting material. For example, the protective layer 19 is a single-layer film made of any of silicon oxide, silicon nitride, silicon oxynitride, or the like, or a laminated film made of two or more of them. It is comprised by. The thickness of the protective layer 19 is, for example, 100 nm to 30000 nm.
　半導体基板３０の第１面３０Ａと第２面３０Ｂとの間には、貫通電極３４が設けられている。光電変換素子１０は、この貫通電極３４を介して、アンプトランジスタＡＭＰのゲートＧａｍｐと、フローティングディフュージョンＦＤ１を兼ねるリセットトランジスタＲＳＴ（リセットトランジスタＴｒ１ｒｓｔ）の一方のソース／ドレイン領域３６Ｂに接続されている。これにより、撮像素子１では、半導体基板３０の第１面３０Ａ側の光電変換素子１０で生じた信号電荷を、貫通電極３４を介して半導体基板３０の第２面３０Ｂ側に良好に転送し、特性を高めることが可能となっている。 A through electrode 34 is provided between the first surface 30A and the second surface 30B of the semiconductor substrate 30. The photoelectric conversion element 10 is connected to the gate Gamp of the amplifier transistor AMP and one source / drain region 36B of the reset transistor RST (reset transistor Tr1rst) that also serves as the floating diffusion FD1 through the through electrode 34. Thereby, in the imaging device 1, the signal charge generated in the photoelectric conversion element 10 on the first surface 30A side of the semiconductor substrate 30 is favorably transferred to the second surface 30B side of the semiconductor substrate 30 through the through electrode 34, It is possible to improve the characteristics.
　貫通電極３４の下端は、配線層４１内の接続部４１Ａに接続されており、接続部４１Ａと、アンプトランジスタＡＭＰのゲートＧａｍｐとは、下部第１コンタクト４５を介して接続されている。接続部４１Ａと、フローティングディフュージョンＦＤ１（領域３６Ｂ）とは、例えば、下部第２コンタクト４６を介して接続されている。貫通電極３４の上端は、例えば、パッド部３９Ａおよび上部第１コンタクト１８Ａを介して読み出し電極１１Ａに接続されている。 The lower end of the through electrode 34 is connected to a connection portion 41A in the wiring layer 41, and the connection portion 41A and the gate Gamp of the amplifier transistor AMP are connected via a lower first contact 45. The connection portion 41A and the floating diffusion FD1 (region 36B) are connected via, for example, the lower second contact 46. The upper end of the through electrode 34 is connected to the readout electrode 11A via, for example, the pad portion 39A and the upper first contact 18A.
　貫通電極３４は、光電変換素子１０とアンプトランジスタＡＭＰのゲートＧａｍｐおよびフローティングディフュージョンＦＤ１とのコネクタとしての機能を有すると共に、光電変換素子１０において生じた電荷（ここでは、電子）の伝送経路となるものである。 The through electrode 34 has a function as a connector between the photoelectric conversion element 10 and the gate Gamp of the amplifier transistor AMP and the floating diffusion FD1, and serves as a transmission path for electric charges (here, electrons) generated in the photoelectric conversion element 10. It is.
　フローティングディフュージョンＦＤ１（リセットトランジスタＲＳＴの一方のソース／ドレイン領域３６Ｂ）の隣にはリセットトランジスタＲＳＴのリセットゲートＧｒｓｔが配置されている。これにより、フローティングディフュージョンＦＤ１に蓄積された電荷を、リセットトランジスタＲＳＴによりリセットすることが可能となる。 Next to the floating diffusion FD1 (one source / drain region 36B of the reset transistor RST), the reset gate Grst of the reset transistor RST is arranged. Thereby, the charge accumulated in the floating diffusion FD1 can be reset by the reset transistor RST.
　半導体基板３０は、例えば、ｎ型のシリコン（Ｓｉ）基板により構成され、所定領域にｐウェル３１を有している。ｐウェル３１の第２面３０Ｂには、上述したアンプトランジスタＡＭＰと、リセットトランジスタＲＳＴと、選択トランジスタＳＥＬ等が設けられている。また、半導体基板３０の周辺部には、ロジック回路等からなる周辺回路（図示せず）が設けられている。 The semiconductor substrate 30 is composed of, for example, an n-type silicon (Si) substrate and has a p-well 31 in a predetermined region. On the second surface 30B of the p-well 31, the above-described amplifier transistor AMP, reset transistor RST, selection transistor SEL, and the like are provided. In addition, a peripheral circuit (not shown) including a logic circuit or the like is provided in the peripheral portion of the semiconductor substrate 30.
　リセットトランジスタＲＳＴ（リセットトランジスタＴｒ１ｒｓｔ）は、光電変換素子１０からフローティングディフュージョンＦＤ１に転送された電荷をリセットするものであり、例えばＭＯＳトランジスタにより構成されている。具体的には、リセットトランジスタＴｒ１ｒｓｔは、リセットゲートＧｒｓｔと、チャネル形成領域３６Ａと、ソース／ドレイン領域３６Ｂ，３６Ｃとから構成されている。リセットゲートＧｒｓｔは、リセット線ＲＳＴ１に接続され、リセットトランジスタＴｒ１ｒｓｔの一方のソース／ドレイン領域３６Ｂは、フローティングディフュージョンＦＤ１を兼ねている。リセットトランジスタＴｒ１ｒｓｔを構成する他方のソース／ドレイン領域３６Ｃは、電源ＶＤＤに接続されている。 The reset transistor RST (reset transistor Tr1rst) resets the charge transferred from the photoelectric conversion element 10 to the floating diffusion FD1, and is configured by a MOS transistor, for example. Specifically, the reset transistor Tr1rst includes a reset gate Grst, a channel formation region 36A, and source / drain regions 36B and 36C. The reset gate Grst is connected to the reset line RST1, and one source / drain region 36B of the reset transistor Tr1rst also serves as the floating diffusion FD1. The other source / drain region 36C constituting the reset transistor Tr1rst is connected to the power supply VDD.
　アンプトランジスタＡＭＰは、光電変換素子１０で生じた電荷量を電圧に変調する変調素子であり、例えばＭＯＳトランジスタにより構成されている。具体的には、アンプトランジスタＡＭＰは、ゲートＧａｍｐと、チャネル形成領域３５Ａと、ソース／ドレイン領域３５Ｂ，３５Ｃとから構成されている。ゲートＧａｍｐは、下部第１コンタクト４５、接続部４１Ａ、下部第２コンタクト４６および貫通電極３４等を介して、読み出し電極１１ＡおよびリセットトランジスタＴｒ１ｒｓｔの一方のソース／ドレイン領域３６Ｂ（フローティングディフュージョンＦＤ１）に接続されている。また、一方のソース／ドレイン領域３５Ｂは、リセットトランジスタＴｒ１ｒｓｔを構成する他方のソース／ドレイン領域３６Ｃと、領域を共有しており、電源ＶＤＤに接続されている。 The amplifier transistor AMP is a modulation element that modulates the amount of charge generated in the photoelectric conversion element 10 into a voltage, and is configured by, for example, a MOS transistor. Specifically, the amplifier transistor AMP includes a gate Gamp, a channel formation region 35A, and source / drain regions 35B and 35C. The gate Gamp is connected to the read electrode 11A and one source / drain region 36B (floating diffusion FD1) of the reset transistor Tr1rst through the lower first contact 45, the connecting portion 41A, the lower second contact 46, the through electrode 34, and the like. Has been. Also, one source / drain region 35B shares a region with the other source / drain region 36C constituting the reset transistor Tr1rst and is connected to the power supply VDD.
　選択トランジスタＳＥＬ（選択トランジスタＴＲ１ｓｅｌ）は、ゲートＧｓｅｌと、チャネル形成領域３４Ａと、ソース／ドレイン領域３４Ｂ，３４Ｃとから構成されている。ゲートＧｓｅｌは、選択線ＳＥＬ１に接続されている。また、一方のソース／ドレイン領域３４Ｂは、アンプトランジスタＡＭＰを構成する他方のソース／ドレイン領域３５Ｃと、領域を共有しており、他方のソース／ドレイン領域３４Ｃは、信号線（データ出力線）ＶＳＬ１に接続されている。 The selection transistor SEL (selection transistor TR1sel) includes a gate Gsel, a channel formation region 34A, and source / drain regions 34B and 34C. The gate Gsel is connected to the selection line SEL1. One source / drain region 34B shares a region with the other source / drain region 35C constituting the amplifier transistor AMP, and the other source / drain region 34C is a signal line (data output line) VSL1. It is connected to the.
（３－２．撮像素子の製造方法）
　本実施の形態の撮像素子１は、例えば、次のようにして製造することができる。 (3-2. Manufacturing Method of Image Sensor)
The image sensor 1 of the present embodiment can be manufactured as follows, for example.
　図１４～図１８は、撮像素子１の製造方法を工程順に表したものである。まず、図１４に示したように、半導体基板３０内に、第１の導電型のウェルとして例えばｐウェル３１を形成する。半導体基板３０の第１面３０Ａ近傍にはｐ＋領域を形成する。 14 to 18 show the manufacturing method of the image sensor 1 in the order of steps. First, as shown in FIG. 14, for example, a p-well 31 is formed in the semiconductor substrate 30 as a first conductivity type well. A p + region is formed in the vicinity of the first surface 30 </ b> A of the semiconductor substrate 30.
　半導体基板３０の第２面３０Ｂには、同じく、図１４に示したように、例えばフローティングディフュージョンＦＤ１となるｎ＋領域を形成したのち、ゲート絶縁層３２と、選択トランジスタＳＥＬ、アンプトランジスタＡＭＰおよびリセットトランジスタＲＳＴの各ゲートを含むゲート配線層４７とを形成する。これにより、選択トランジスタＳＥＬ、アンプトランジスタＡＭＰおよびリセットトランジスタＲＳＴを形成する。更に、半導体基板３０の第２面３０Ｂ上に、下部第１コンタクト４５、下部第２コンタクト４６および接続部４１Ａを含む配線層４１～４３および絶縁層４４からなる多層配線４０を形成する。 Similarly, as shown in FIG. 14, for example, an n + region that becomes the floating diffusion FD <b> 1 is formed on the second surface 30 </ b> B of the semiconductor substrate 30, and then the gate insulating layer 32, the selection transistor SEL, the amplifier transistor AMP, and the reset transistor are formed. A gate wiring layer 47 including each gate of RST is formed. Thereby, the selection transistor SEL, the amplifier transistor AMP, and the reset transistor RST are formed. Further, the multilayer wiring 40 including the wiring layers 41 to 43 including the lower first contact 45, the lower second contact 46, and the connecting portion 41A and the insulating layer 44 is formed on the second surface 30B of the semiconductor substrate 30.
　半導体基板３０の基体としては、例えば、半導体基板３０と、埋込み酸化膜（図示せず）と、保持基板（図示せず）とを積層したＳＯＩ（Silicon on Insulator）基板を用いる。埋込み酸化膜および保持基板は、図１４には図示しないが、半導体基板３０の第１面３０Ａに接合されている。イオン注入後、アニール処理を行う。 As the base of the semiconductor substrate 30, for example, an SOI (Silicon On Insulator) substrate in which a semiconductor substrate 30, a buried oxide film (not shown), and a holding substrate (not shown) are stacked is used. Although not shown in FIG. 14, the buried oxide film and the holding substrate are bonded to the first surface 30 </ b> A of the semiconductor substrate 30. After ion implantation, annealing is performed.
　次いで、半導体基板３０の第２面３０Ｂ側（多層配線４０側）に支持基板（図示せず）または他の半導体基体等を接合して、上下反転する。続いて、半導体基板３０をＳＯＩ基板の埋込み酸化膜および保持基板から分離し、半導体基板３０の第１面３０Ａを露出させる。以上の工程は、イオン注入およびＣＶＤ（Chemical Vapor Deposition）等、通常のＣＭＯＳプロセスで使用されている技術にて行うことが可能である。 Next, a support substrate (not shown) or another semiconductor substrate is joined to the second surface 30B side (multilayer wiring 40 side) of the semiconductor substrate 30 and turned upside down. Subsequently, the semiconductor substrate 30 is separated from the buried oxide film of the SOI substrate and the holding substrate, and the first surface 30A of the semiconductor substrate 30 is exposed. The above steps can be performed by techniques used in a normal CMOS process, such as ion implantation and CVD (Chemical Vapor Deposition).
　次いで、図１５に示したように、例えばドライエッチングにより半導体基板３０を第１面３０Ａ側から加工し、例えば環状の開口３４Ｈを形成する。開口３４Ｈの深さは、図１５に示したように、半導体基板３０の第１面３０Ａから第２面３０Ｂまで貫通すると共に、例えば、接続部４１Ａまで達するものである。 Next, as shown in FIG. 15, the semiconductor substrate 30 is processed from the first surface 30A side by, for example, dry etching to form, for example, an annular opening 34H. As shown in FIG. 15, the depth of the opening 34H penetrates from the first surface 30A to the second surface 30B of the semiconductor substrate 30 and reaches, for example, the connecting portion 41A.
　続いて、半導体基板３０の第１面３０Ａおよび開口３４Ｈの側面に、例えば負の固定電荷層１７Ａを形成する。負の固定電荷層１７Ａとして、２種類以上の膜を積層してもよい。それにより、正孔蓄積層としての機能をより高めることが可能となる。負の固定電荷層１７Ａを形成したのち、誘電体層１７Ｂを形成する。次に、誘電体層１７Ｂ上の所定の位置にパッド部３９Ａ，３９Ｂ，３９Ｃを形成したのち、誘電体層１７Ｂおよびパッド部３９Ａ，３９Ｂ，３９Ｃ上に、層間絶縁層１８を形成する。次いで、層間絶縁層１８を成膜したのち、例えば、ＣＭＰ（Chemical Mechanical Polishing）法を用いて層間絶縁層１
８の表面を平坦化する。 Subsequently, a negative fixed charge layer 17A, for example, is formed on the first surface 30A of the semiconductor substrate 30 and the side surface of the opening 34H. Two or more types of films may be stacked as the negative fixed charge layer 17A. Thereby, the function as a hole accumulation layer can be further enhanced. After forming the negative fixed charge layer 17A, the dielectric layer 17B is formed. Next, after forming pad portions 39A, 39B, and 39C at predetermined positions on the dielectric layer 17B, the interlayer insulating layer 18 is formed on the dielectric layer 17B and the pad portions 39A, 39B, and 39C. Next, after the interlayer insulating layer 18 is formed, the interlayer insulating layer 1 is formed by using, for example, a CMP (Chemical Mechanical Polishing) method.
The surface of 8 is flattened.
　続いて、図１６に示したように、パッド部３９Ａ，３９Ｂ，３９Ｃ上の層間絶縁層１８に、それぞれ開口１８Ｈ１，１８Ｈ２，１８Ｈ３を形成したのち、この開口１８Ｈ１，１８Ｈ２，１８Ｈ３に、例えばＡｌ等の導電材料を埋め込み、上部第１コンタクト１８Ａ、上部第２コンタクト１８Ｂおよび上部第３コンタクト１８Ｃを形成する。 Subsequently, as shown in FIG. 16, openings 18H1, 18H2, and 18H3 are respectively formed in the interlayer insulating layer 18 on the pad portions 39A, 39B, and 39C, and then, for example, Al or the like is formed in the openings 18H1, 18H2, and 18H3. Then, the upper first contact 18A, the upper second contact 18B, and the upper third contact 18C are formed.
　続いて、図１７に示したように、層間絶縁層１８上に導電膜１１ｘを成膜したのち、導電膜２１ｘの所定の位置（例えば、パッド部３９Ａ、パッド部３９Ｂおよびパッド部３９Ｃ上）にフォトレジストＰＲを形成する。その後、エッチングおよびフォトレジストＰＲを除去することで、図１８に示した、読み出し電極Ａ、蓄積電極１１Ｂおよび転送電極１１Ｃがパターニングされる。 Subsequently, as shown in FIG. 17, after the conductive film 11x is formed on the interlayer insulating layer 18, the conductive film 21x is placed at predetermined positions (for example, on the pad portion 39A, the pad portion 39B, and the pad portion 39C). A photoresist PR is formed. Thereafter, the read electrode A, the storage electrode 11B, and the transfer electrode 11C shown in FIG. 18 are patterned by etching and removing the photoresist PR.
　次いで、層間絶縁層１８および読み出し電極１１Ａ、蓄積電極１１Ｂおよび上部第３コンタクト１８Ｃ上に絶縁層１２を成膜したのち、読み出し電極１１Ａ上に開口１２Ｈを設ける。この後、層間絶縁層１８上に、第１半導体層１３、第２半導体層１４、光電変換層１５、上部電極１６、保護層１９、遮光膜２１およびカラーフィルタ２２を形成する。最後に、平坦化層等の光学部材およびオンチップレンズ２３を配設する。以上により、図９に示した撮像素子１が完成する。 Next, after the insulating layer 12 is formed on the interlayer insulating layer 18, the readout electrode 11A, the storage electrode 11B, and the upper third contact 18C, an opening 12H is provided on the readout electrode 11A. Thereafter, the first semiconductor layer 13, the second semiconductor layer 14, the photoelectric conversion layer 15, the upper electrode 16, the protective layer 19, the light shielding film 21, and the color filter 22 are formed on the interlayer insulating layer 18. Finally, an optical member such as a planarizing layer and an on-chip lens 23 are disposed. Thus, the image sensor 1 shown in FIG. 9 is completed.
（３－３．撮像素子の制御方法）
（光電変換素子１０による信号の取得）
　本実施の形態の固体撮像装置を構成する撮像素子１では、撮像素子１へ入射した光のうち近赤外領域の光が光電変換素子１０において選択的に検出（吸収）され、光電変換される。 (3-3. Image Sensor Control Method)
(Signal acquisition by the photoelectric conversion element 10)
In the imaging device 1 constituting the solid-state imaging device of the present embodiment, near-infrared light in the light incident on the imaging device 1 is selectively detected (absorbed) by the photoelectric conversion device 10 and subjected to photoelectric conversion. .
　光電変換素子１０は、貫通電極３４を介して、アンプトランジスタＡＭＰのゲートＧａｍｐとフローティングディフュージョンＦＤ１とに接続されている。よって、光電変換素子１０で発生した電子－正孔対のうちの電子（信号電荷）が、下部電極１１側から取り出され、貫通電極３４を介して半導体基板３０の第２面３０Ｂ側へ転送され、フローティングディフュージョンＦＤ１に蓄積される。これと同時に、アンプトランジスタＡＭＰにより、光電変換素子１０で生じた電荷量が電圧に変調される。 The photoelectric conversion element 10 is connected to the gate Gamp of the amplifier transistor AMP and the floating diffusion FD1 through the through electrode 34. Therefore, electrons (signal charges) of the electron-hole pairs generated in the photoelectric conversion element 10 are taken out from the lower electrode 11 side and transferred to the second surface 30B side of the semiconductor substrate 30 through the through electrode 34. Are accumulated in the floating diffusion FD1. At the same time, the charge amount generated in the photoelectric conversion element 10 is modulated into a voltage by the amplifier transistor AMP.
　また、フローティングディフュージョンＦＤ１の隣には、リセットトランジスタＲＳＴのリセットゲートＧｒｓｔが配置されている。これにより、フローティングディフュージョンＦＤ１に蓄積された電荷は、リセットトランジスタＲＳＴによりリセットされる。 Further, a reset gate Grst of the reset transistor RST is disposed next to the floating diffusion FD1. Thereby, the electric charge accumulated in the floating diffusion FD1 is reset by the reset transistor RST.
　本実施の形態では、光電変換素子１０が、貫通電極３４を介して、アンプトランジスタＡＭＰだけでなくフローティングディフュージョンＦＤ１にも接続されているので、フローティングディフュージョンＦＤ１に蓄積された電荷をリセットトランジスタＲＳＴにより容易にリセットすることが可能となる。 In the present embodiment, since the photoelectric conversion element 10 is connected not only to the amplifier transistor AMP but also to the floating diffusion FD1 through the through electrode 34, the charge accumulated in the floating diffusion FD1 can be easily obtained by the reset transistor RST. It becomes possible to reset to.
　これに対して、貫通電極３４とフローティングディフュージョンＦＤ１とが接続されていない場合には、フローティングディフュージョンＦＤ１に蓄積された電荷をリセットすることが困難となり、大きな電圧をかけて上部電極１６側へ引き抜くことになる。そのため、光電変換層１５がダメージを受けるおそれがある。また、短時間でのリセットを可能とする構造は暗時ノイズの増大を招き、トレードオフとなるため、この構造は困難である。 On the other hand, when the through electrode 34 and the floating diffusion FD1 are not connected, it becomes difficult to reset the electric charge accumulated in the floating diffusion FD1, and a large voltage is applied to the upper electrode 16 side. become. For this reason, the photoelectric conversion layer 15 may be damaged. In addition, a structure that can be reset in a short time causes an increase in dark noise, which is a trade-off, so that this structure is difficult.
　図１９は、光電変換素子１０の一動作例を表したものである。（Ａ）は、蓄積電極１１Ｂにおける電位を示し、（Ｂ）は、フローティングディフュージョンＦＤ１（読み出し電極１１Ａ）における電位を示し、（Ｃ）は、リセットトランジスタＴＲ１ｒｓｔのゲート（Ｇｓｅｌ）における電位を示したものである。光電変換素子１０では、読み出し電極１１Ａ、蓄積電極１１Ｂおよび転送電極１１Ｃは、それぞれ個別に電圧が印加されるようになっている。 FIG. 19 illustrates an operation example of the photoelectric conversion element 10. (A) shows the potential at the storage electrode 11B, (B) shows the potential at the floating diffusion FD1 (reading electrode 11A), and (C) shows the potential at the gate (Gsel) of the reset transistor TR1rst. It is. In the photoelectric conversion element 10, voltages are individually applied to the readout electrode 11A, the storage electrode 11B, and the transfer electrode 11C.
　光電変換素子１０では、蓄積期間においては、駆動回路から読み出し電極１１Ａに電位Ｖ１が印加され、蓄積電極１１Ｂに電位Ｖ２が印加される。ここで、電位Ｖ１，Ｖ２は、Ｖ１＞Ｖ２とする。これにより、光電変換によって生じた信号電荷（ここでは、電子）は、蓄積電極１１Ｂに引きつけられ、蓄積電極１１Ｂと対向する第１半導体層１３の領域に蓄積される（蓄積期間）。因みに、蓄積電極１１Ｂと対向する第１半導体層１３の領域の電位は、光電変換の時間経過に伴い、より正側の値となる。なお、正孔は上部電極１６から駆動回路へと送出される。 In the photoelectric conversion element 10, during the accumulation period, the potential V1 is applied from the drive circuit to the readout electrode 11A, and the potential V2 is applied to the storage electrode 11B. Here, the potentials V1 and V2 satisfy V1> V2. Thereby, signal charges (electrons here) generated by the photoelectric conversion are attracted to the storage electrode 11B and stored in the region of the first semiconductor layer 13 facing the storage electrode 11B (storage period). Incidentally, the potential of the region of the first semiconductor layer 13 facing the storage electrode 11B becomes a more positive value as the photoelectric conversion time elapses. The holes are sent from the upper electrode 16 to the drive circuit.
　光電変換素子１０では、蓄積期間の後期においてリセット動作がなされる。具体的には、タイミングｔ１において、走査部は、リセット信号ＲＳＴの電圧を低レベルから高レベルに変化させる。これにより、単位画素Ｐでは、リセットトランジスタＴＲ１ｒｓｔがオン状態になり、その結果、フローティングディフュージョンＦＤ１の電圧が電源電圧ＶＤＤに設定され、フローティングディフュージョンＦＤ１の電圧がリセットされる（リセット期間）。 In the photoelectric conversion element 10, a reset operation is performed in the later stage of the accumulation period. Specifically, at timing t1, the scanning unit changes the voltage of the reset signal RST from a low level to a high level. Thereby, in the unit pixel P, the reset transistor TR1rst is turned on. As a result, the voltage of the floating diffusion FD1 is set to the power supply voltage VDD, and the voltage of the floating diffusion FD1 is reset (reset period).
　リセット動作の完了後、電荷の読み出しが行われる。具体的には、タイミングｔ２において、駆動回路から読み出し電極１１Ａには電位Ｖ３が印加され、蓄積電極１１Ｂには電位Ｖ４が印加され、転送電極１１Ｃには電位Ｖ５が印加される。ここで、電位Ｖ３，Ｖ４，Ｖ５は、Ｖ４＞Ｖ５＞Ｖ６とする。これにより、蓄積電極１１Ｂに対応する領域に蓄積されていた信号電荷は、蓄積電極１１Ｂ上から転送電極１１Ｃおよび読み出し電極１１Ａの順に移動し、読み出し電極１１ＡからフローティングディフュージョンＦＤ１へと読み出される。即ち、第１半導体層１３に蓄積された電荷が制御部に読み出される（転送期間）。 After the reset operation is completed, the charge is read out. Specifically, at timing t2, the potential V3 is applied from the drive circuit to the readout electrode 11A, the potential V4 is applied to the storage electrode 11B, and the potential V5 is applied to the transfer electrode 11C. Here, the potentials V3, V4, and V5 satisfy V4> V5> V6. Thereby, the signal charge accumulated in the region corresponding to the storage electrode 11B moves from the storage electrode 11B to the transfer electrode 11C and the readout electrode 11A in this order, and is read from the readout electrode 11A to the floating diffusion FD1. That is, the charge accumulated in the first semiconductor layer 13 is read out to the control unit (transfer period).
　読み出し動作完了後、再び、駆動回路から読み出し電極１１Ａに電位Ｖ１が印加され、蓄積電極１１Ｂに電位Ｖ２が印加される。これにより、光電変換によって生じた信号電荷は、蓄積電極１１Ｂに引きつけられ、蓄積電極１１Ｂと対向する第１半導体層１３の領域に蓄積される（蓄積期間）。 After the read operation is completed, the potential V1 is again applied from the drive circuit to the read electrode 11A, and the potential V2 is applied to the storage electrode 11B. Thereby, the signal charge generated by the photoelectric conversion is attracted to the storage electrode 11B and stored in the region of the first semiconductor layer 13 facing the storage electrode 11B (storage period).
（固体撮像装置の全体構成）
　図２０は、固体撮像素子１００１を表す機能ブロック図である。この固体撮像素子１００１は、ＣＭＯＳイメージセンサであり、撮像エリアとしての画素部１０１ａを有すると共に、例えば行走査部１３１、水平選択部１３３、列走査部１３４およびシステム制御部１３２からなる回路部１３０を有している。この画素部１ａの周辺領域あるいは画素部１０１ａと積層されて、回路部１３０は、画素部１０１ａの周辺領域に設けられていてもよいし、画素部１０１ａと積層されて（画素部１０１ａに対向する領域に）設けられていてもよい。 (Overall configuration of solid-state imaging device)
FIG. 20 is a functional block diagram illustrating the solid-state image sensor 1001. The solid-state imaging device 1001 is a CMOS image sensor, and includes a pixel unit 101a as an imaging area, and includes a circuit unit 130 including, for example, a row scanning unit 131, a horizontal selection unit 133, a column scanning unit 134, and a system control unit 132. Have. The circuit unit 130 may be provided in the peripheral region of the pixel unit 1a or the pixel unit 101a, and may be provided in the peripheral region of the pixel unit 101a, or may be stacked with the pixel unit 101a (opposite the pixel unit 101a). May be provided).
　画素部１０１ａは、例えば行列状に２次元配置された複数の単位画素Ｐ（例えば、固体撮像素子（１画素分）１０、１０Ａ及び１０Ｂに相当）を有している。この単位画素Ｐには、例えば画素行ごとに画素駆動線Ｌread（具体的には行選択線およびリセット制御線）が配線され、画素列ごとに垂直信号線Ｌsigが配線されている。画素駆動線Ｌreadは、画素からの信号読み出しのための駆動信号を伝送するものである。画素駆動線Ｌreadの一端は、行走査部１３１の各行に対応した出力端に接続されている。 The pixel unit 101a has, for example, a plurality of unit pixels P (for example, corresponding to solid-state imaging devices (for one pixel) 10, 10A, and 10B) that are two-dimensionally arranged in a matrix. In the unit pixel P, for example, a pixel drive line Lread (specifically, a row selection line and a reset control line) is wired for each pixel row, and a vertical signal line Lsig is wired for each pixel column. The pixel drive line Lread transmits a drive signal for reading a signal from the pixel. One end of the pixel drive line Lread is connected to an output end corresponding to each row of the row scanning unit 131.
　行走査部１３１は、シフトレジスタやアドレスデコーダ等によって構成され、画素部１０１ａの各画素Ｐを、例えば行単位で駆動する画素駆動部である。行走査部１３１によって選択走査された画素行の各画素Ｐから出力される信号は、垂直信号線Ｌsigの各々を通して水平選択部１３３に供給される。水平選択部１３３は、垂直信号線Ｌsigごとに設けられたアンプや水平選択スイッチ等によって構成されている。 The row scanning unit 131 includes a shift register, an address decoder, and the like, and is a pixel driving unit that drives each pixel P of the pixel unit 101a, for example, in units of rows. A signal output from each pixel P in the pixel row selected and scanned by the row scanning unit 131 is supplied to the horizontal selection unit 133 through each of the vertical signal lines Lsig. The horizontal selection unit 133 is configured by an amplifier, a horizontal selection switch, and the like provided for each vertical signal line Lsig.
　列走査部１３４は、シフトレジスタやアドレスデコーダ等によって構成され、水平選択部１３３の各水平選択スイッチを走査しつつ順番に駆動するものである。この列走査部１３４による選択走査により、垂直信号線Ｌsigの各々を通して伝送される各画素の信号が順番に水平信号線１３５に伝送され、当該水平信号線１３５を通して外部へ出力される。 The column scanning unit 134 includes a shift register, an address decoder, and the like, and drives the horizontal selection switches in the horizontal selection unit 133 in order while scanning. By the selective scanning by the column scanning unit 134, the signal of each pixel transmitted through each of the vertical signal lines Lsig is sequentially transmitted to the horizontal signal line 135 and output to the outside through the horizontal signal line 135.
　システム制御部１３２は、外部から与えられるクロックや、動作モードを指令するデータなどを受け取り、また、固体撮像素子１０１の内部情報などのデータを出力するものである。システム制御部１３２はさらに、各種のタイミング信号を生成するタイミングジェネレータを有し、当該タイミングジェネレータで生成された各種のタイミング信号を基に行走査部１３１、水平選択部１３３および列走査部１３４などの駆動制御を行う。 The system control unit 132 receives a clock given from the outside, data for instructing an operation mode, and the like, and outputs data such as internal information of the solid-state imaging device 101. The system control unit 132 further includes a timing generator that generates various timing signals. The row scanning unit 131, the horizontal selection unit 133, the column scanning unit 134, and the like are based on the various timing signals generated by the timing generator. Drive control is performed.
＜４．第４の実施形態（電子装置の例）＞
　本技術に係る第４の実施形態の電子装置は、本技術に係る第３の実施形態の少なくとも１つの実施形態の固体撮像装置を備える、電子装置である。本技術に係る第３の実施形態の固体撮像装置は上記のとおりであるので、ここでは説明を省略する。本技術に係る第４の実施形態の電子装置は、優れた画質及び信頼性を有する固体撮像装置を備えるので、画質性能等の向上を図ることができる。 <4. Fourth Embodiment (Example of Electronic Device)>
The electronic device according to the fourth embodiment of the present technology is an electronic device including the solid-state imaging device according to at least one embodiment of the third embodiment according to the present technology. Since the solid-state imaging device according to the third embodiment of the present technology is as described above, the description thereof is omitted here. Since the electronic device according to the fourth embodiment of the present technology includes the solid-state imaging device having excellent image quality and reliability, the image quality performance and the like can be improved.
＜５．本技術を適用した固体撮像装置の使用例＞
　図２１は、イメージセンサとしての本技術に係る第３の実施形態の固体撮像装置の使用例を示す図である。 <5. Example of use of solid-state imaging device to which this technology is applied>
FIG. 21 is a diagram illustrating a usage example of the solid-state imaging device according to the third embodiment of the present technology as an image sensor.
　上述した第３の実施形態の固体撮像装置は、例えば、以下のように、可視光や、赤外光、紫外光、Ｘ線等の光をセンシングするさまざまなケースに使用することができる。すなわち、図２１に示すように、例えば、鑑賞の用に供される画像を撮影する鑑賞の分野、交通の分野、家電の分野、医療・ヘルスケアの分野、セキュリティの分野、美容の分野、スポーツの分野、農業の分野等において用いられる装置（例えば、上述した第４の実施形態の電子装置）に、第３の実施形態の固体撮像装置を使用することができる。 The solid-state imaging device of the third embodiment described above can be used in various cases for sensing light such as visible light, infrared light, ultraviolet light, and X-ray as follows. That is, as shown in FIG. 21, for example, the field of appreciation for taking images for appreciation, the field of transportation, the field of consumer electronics, the field of medical / healthcare, the field of security, the field of beauty, sports The solid-state imaging device of the third embodiment can be used for devices (for example, the electronic device of the fourth embodiment described above) used in the field of agriculture, the field of agriculture, and the like.
　具体的には、鑑賞の分野においては、例えば、デジタルカメラやスマートフォン、カメラ機能付きの携帯電話機等の、鑑賞の用に供される画像を撮影するための装置に、第３の実施形態の固体撮像装置を使用することができる。 Specifically, in the field of viewing, for example, the solid-state display according to the third embodiment is applied to an apparatus for shooting an image provided for viewing, such as a digital camera, a smartphone, or a mobile phone with a camera function. An imaging device can be used.
　交通の分野においては、例えば、自動停止等の安全運転や、運転者の状態の認識等のために、自動車の前方や後方、周囲、車内等を撮影する車載用センサ、走行車両や道路を監視する監視カメラ、車両間等の測距を行う測距センサ等の、交通の用に供される装置に、第３の実施形態の固体撮像装置を使用することができる。 In the field of traffic, for example, in-vehicle sensors that capture images of the front, rear, surroundings, and interior of a vehicle for safe driving such as automatic stop and recognition of the driver's condition, traveling vehicles and roads are monitored. The solid-state imaging device according to the third embodiment can be used as a device used for traffic, such as a monitoring camera that performs distance measurement between vehicles, a distance measurement sensor that performs distance measurement between vehicles, and the like.
　家電の分野においては、例えば、ユーザーのジェスチャを撮影して、そのジェスチャに従った機器操作を行うために、テレビ受像機や冷蔵庫、エアーコンディショナ等の家電に供される装置で、第３の実施形態の固体撮像装置を使用することができる。 In the field of home appliances, for example, a device used for home appliances such as a television receiver, a refrigerator, and an air conditioner to photograph a user's gesture and perform device operations in accordance with the gesture. The solid-state imaging device of the embodiment can be used.
　医療・ヘルスケアの分野においては、例えば、内視鏡や、赤外光の受光による血管撮影を行う装置等の、医療やヘルスケアの用に供される装置に、第３の実施形態の固体撮像装置を使用することができる。 In the field of medical / healthcare, for example, the solid state of the third embodiment is applied to a device used for medical treatment or health care such as an endoscope or a device that performs angiography by receiving infrared light. An imaging device can be used.
　セキュリティの分野においては、例えば、防犯用途の監視カメラや、人物認証用途のカメラ等の、セキュリティの用に供される装置に、第３の実施形態の固体撮像装置を使用することができる。 In the field of security, for example, the solid-state imaging device according to the third embodiment can be used for devices used for security, such as surveillance cameras for crime prevention and cameras for personal authentication.
　美容の分野においては、例えば、肌を撮影する肌測定器や、頭皮を撮影するマイクロスコープ等の、美容の用に供される装置に、第３の実施形態の固体撮像装置を使用することができる。 In the field of beauty, for example, the solid-state imaging device of the third embodiment may be used for a device used for beauty, such as a skin measuring device for photographing the skin or a microscope for photographing the scalp. it can.
　スポーツの分野において、例えば、スポーツ用途等向けのアクションカメラやウェアラブルカメラ等の、スポーツの用に供される装置に、第３の実施形態の固体撮像装置を使用することができる。 In the field of sports, for example, the solid-state imaging device according to the third embodiment can be used in devices used for sports such as action cameras and wearable cameras for sports applications.
　農業の分野においては、例えば、畑や作物の状態を監視するためのカメラ等の、農業の用に供される装置に、第３の実施形態の固体撮像装置を使用することができる。 In the field of agriculture, for example, the solid-state imaging device of the third embodiment can be used for an apparatus used for agriculture, such as a camera for monitoring the state of fields and crops.
　次に、本技術に係る第３の実施形態の固体撮像装置の使用例を具体的に説明する。例えば、上述で説明をした固体撮像装置１００１は、例えばデジタルスチルカメラやビデオカメラ等のカメラシステムや、撮像機能を有する携帯電話など、撮像機能を備えたあらゆるタイプの電子機器に適用することができる。図２２に、その一例として、電子機器１００２（カメラ）の概略構成を示す。この電子機器１００２は、例えば静止画または動画を撮影可能なビデオカメラであり、固体撮像装置３９９と、光学系（光学レンズ）３１０と、シャッタ装置３１１と、固体撮像装置３９９およびシャッタ装置３１１を駆動する駆動部３１３と、信号処理部３１２とを有する。 Next, a usage example of the solid-state imaging device of the third embodiment according to the present technology will be specifically described. For example, the solid-state imaging device 1001 described above can be applied to any type of electronic apparatus having an imaging function, such as a camera system such as a digital still camera or a video camera, or a mobile phone having an imaging function. . FIG. 22 shows a schematic configuration of an electronic device 1002 (camera) as an example. The electronic device 1002 is, for example, a video camera capable of shooting a still image or a moving image, and drives the solid-state imaging device 399, the optical system (optical lens) 310, the shutter device 311, the solid-state imaging device 399, and the shutter device 311. And a signal processing unit 312.
　光学系３１０は、被写体からの像光（入射光）を固体撮像装置３９９の画素部へ導くものである。この光学系３１０は、複数の光学レンズから構成されていてもよい。シャッタ装置３１１は、固体撮像装置３９９への光照射期間および遮光期間を制御するものである。駆動部３１３は、固体撮像装置３９９の転送動作およびシャッタ装置３１１のシャッタ動作を制御するものである。信号処理部３１２は、固体撮像装置３９９から出力された信号に対し、各種の信号処理を行うものである。信号処理後の映像信号Ｄｏｕｔは、メモリなどの記憶媒体に記憶されるか、あるいは、モニタ等に出力される。 The optical system 310 guides image light (incident light) from the subject to the pixel portion of the solid-state imaging device 399. The optical system 310 may be composed of a plurality of optical lenses. The shutter device 311 controls a light irradiation period and a light shielding period for the solid-state imaging device 399. The drive unit 313 controls the transfer operation of the solid-state imaging device 399 and the shutter operation of the shutter device 311. The signal processing unit 312 performs various types of signal processing on the signal output from the solid-state imaging device 399. The video signal Dout after the signal processing is stored in a storage medium such as a memory, or is output to a monitor or the like.
　次に、本技術の実施例について詳細に説明する。実験１では量子ドットを構成する半導体粒子としてＰｂＳを用いた光電変換素子を作製し、その電気特性を評価した。なお、本実施例における光電変換素子の電気特性は、上記第１光電変換素子１０における絶縁層１２を省いた構造で行ったものである。 尚、実験で用いた材料のイオン化ポテンシャルおよび仕事関数は紫外線分光法によって測定を行い、電子親和力は材料の吸収分光特性より得られた光学バンドギャップとイオン化ポテンシャルを用いて求めた。  Next, embodiments of the present technology will be described in detail. In Experiment 1, a photoelectric conversion element using PbS as a semiconductor particle constituting a quantum dot was produced, and its electrical characteristics were evaluated. In addition, the electrical characteristic of the photoelectric conversion element in a present Example is performed by the structure which excluded the insulating layer 12 in the said 1st photoelectric conversion element 10. FIG. Furthermore, the ionization potential and work function of the material used in the experiment were measured by ultraviolet spectroscopy, and the electron affinity was obtained using the optical band gap and ionization potential obtained from the absorption spectral characteristics of the material.
［実験１］
　以下の方法を用いて電気特性評価用サンプルを作製し、その暗電流特性および外部量子効率を評価した。尚、外部量子効率は波長９４０ｎｍ の光を強度１．０×１０－５Ｗ・ｃｍ－２で照射することで測定を行った。 [Experiment 1]
Samples for evaluating electrical characteristics were prepared using the following methods, and the dark current characteristics and external quantum efficiency were evaluated. The external quantum efficiency was measured by irradiating light with a wavelength of 940 nm at an intensity of 1.0 × 10 −5 W · cm −2 .
（実験例１）
　まず、実験例１として、膜厚５０ｎｍのＩＴＯ電極が設けられたガラス基板をＵＶ／オゾン処理にて洗浄したのち、スパッタリンング法を用いてＩＴＯ電極上にＩＧＺＯからなる厚さ１００ｎｍの第１半導体層を成膜した。続いて、この基板を大気中において３５０℃、１ｈｒの熱処理を施すことでＩＧＺＯを空乏化させた。さらに、光電変換層としてオレイン酸がナノ粒子表面に配位したＰｂＳナノ粒子がオクタン溶媒に濃度５０ｍｇ／ｍｌで分散しているインクを用いて、スピンコート法にて２５００ｒｐｍの回転数で第１半導体層上に塗布した。その後、ヨウ素（Ｉ）がメタノール溶媒に濃度1重量％で分散している溶液を滴下し、オレイン酸からＩへのリガンド交換を行った。リガンド交換後はメタノールを滴下してオレイン酸等の余剰な有機物の洗浄を行った。この操作を１０回繰り返すことで厚さ約３００ｎｍの光電変換層を成膜した。成膜後に不活性ガス雰囲気にて１２０℃、５分の熱処理を行い、残留溶媒の除去を行った。次に、光電変換層上に、仕事関数調整層として、真空蒸着法を用いてＨＡＴＣＮ膜を厚さ１０ｎｍで成膜し、さらにスパッタリング法を用いて５０ｎｍのＩＴＯ膜を積層することで上部電極を形成した。以上により、１ｍｍ×１ｍｍの光電変換領域を有する光電変換素子を作製した。 (Experimental example 1)
First, as Experimental Example 1, a glass substrate provided with an ITO electrode having a thickness of 50 nm was cleaned by UV / ozone treatment, and then a first 100 nm thick made of IGZO was formed on the ITO electrode using a sputtering method. A semiconductor layer was formed. Subsequently, the substrate was subjected to heat treatment at 350 ° C. for 1 hour in the atmosphere to deplete IGZO. Further, the first semiconductor at a rotational speed of 2500 rpm by spin coating using an ink in which PbS nanoparticles in which oleic acid is coordinated on the nanoparticle surface is dispersed in an octane solvent at a concentration of 50 mg / ml as a photoelectric conversion layer. Coated on the layer. Thereafter, a solution in which iodine (I) was dispersed in a methanol solvent at a concentration of 1% by weight was added dropwise to perform ligand exchange from oleic acid to I. After ligand exchange, methanol was added dropwise to wash away excess organic materials such as oleic acid. By repeating this operation 10 times, a photoelectric conversion layer having a thickness of about 300 nm was formed. After the film formation, heat treatment was performed at 120 ° C. for 5 minutes in an inert gas atmosphere to remove the residual solvent. Next, a HATCN film having a thickness of 10 nm is formed on the photoelectric conversion layer as a work function adjusting layer by vacuum deposition using a vacuum deposition method, and an ITO film having a thickness of 50 nm is further stacked by sputtering. Formed. Thus, a photoelectric conversion element having a 1 mm × 1 mm photoelectric conversion region was produced.
（実験例２）
　光電変換層を成膜後、熱処理を行った後、２Ｔ－ＮＡＴＡ膜を厚さ１０ｎｍで真空蒸着法により成膜する工程を加えた以外は、実験例１と同様の方法を用いて光電変換素子（実験例２）を作製した。 (Experimental example 2)
Photoelectric conversion element using the same method as in Experimental Example 1, except that after the photoelectric conversion layer was formed, heat treatment was performed, and then a 2T-NATA film was formed by vacuum deposition at a thickness of 10 nm. (Experimental example 2) was produced.
（実験例３）
　仕事関数調整層として、ＨＡＴＣＮ膜の代わりに、ＭｏＯ３膜を厚さ１０ｎｍで真空蒸着法により成膜した以外は 、実験例１と同様の方法を用いて光電変換素子（実験例３）を作製した。 (Experimental example 3)
A photoelectric conversion element (Experimental Example 3) was produced using the same method as in Experimental Example 1 except that a MoO 3 film was formed by a vacuum vapor deposition method with a thickness of 10 nm instead of the HATCN film as a work function adjusting layer. did.
（実験例４）
　光電変換層を成膜後、熱処理を行った後、２Ｔ－ＮＡＴＡ膜を厚さ１０ｎｍで真空蒸着法により成膜する工程を加えた以外は、実験例３と同様の方法を用いて光電変換素子（実験例４）を作製した。 (Experimental example 4)
Photoelectric conversion element using the same method as in Experimental Example 3, except that after the photoelectric conversion layer was formed, heat treatment was performed, and then a 2T-NATA film was formed by vacuum deposition at a thickness of 10 nm. (Experimental example 4) was produced.
（実験例５）
仕事関数調整層のＨＡＴＣＮ膜を成膜する工程を省いた以外は 、実験例１と同様の方法を用いて光電変換素子（実験例５）を作製した。 (Experimental example 5)
A photoelectric conversion element (Experimental Example 5) was produced using the same method as in Experimental Example 1 except that the step of forming the HATCN film of the work function adjusting layer was omitted.
（実験例６）
　光電変換層を成膜後、熱処理を行った後、２Ｔ－ＮＡＴＡ膜を厚さ１０ｎｍで真空蒸着法により成膜する工程を加えた以外は、実験例５と同様の方法を用いて光電変換素子（実験例６）を作製した。 (Experimental example 6)
Photoelectric conversion element using the same method as in Experimental Example 5 except that after the photoelectric conversion layer was formed, heat treatment was performed, and then a 2T-NATA film was formed by vacuum deposition at a thickness of 10 nm. (Experimental example 6) was produced.
（実験例７）
　仕事関数調整層として、ＨＡＴＣＮ膜の代わりに、Ｃ６０フラーレン（Ｃ６０）膜を厚さ１０ｎｍで真空蒸着法により成膜した以外は 、実験例１と同様の方法を用いて光電変換素子（実験例７）を作製した。 (Experimental example 7)
As a work function adjusting layer, a photoelectric conversion element (experiment) was performed using the same method as in Experimental Example 1 except that a C 60 fullerene (C 60 ) film was formed by vacuum deposition at a thickness of 10 nm instead of the HATCN film. Example 7) was prepared.
（実験例８）
　光電変換層を成膜後、熱処理を行った後、[4,4'-ビス(カルバゾール-9-イル)ビフェニル（ＣＢＰ）膜を厚さ１０ｎｍで真空蒸着法により成膜する工程を加えた以外は、実験例１と同様の方法を用いて光電変換素子（実験例８）を作製した。 (Experimental example 8)
After adding a step of forming a [4,4′-bis (carbazol-9-yl) biphenyl (CBP) film with a thickness of 10 nm by vacuum deposition after the photoelectric conversion layer was formed and heat-treated. Produced a photoelectric conversion element (Experimental Example 8) using the same method as in Experimental Example 1.
（実験例９）
　仕事関数調整層として、ＨＡＴＣＮ膜の代わりに、ＭｏＯ３膜を厚さ１０ｎｍで真空蒸着法により成膜した以外は 、実験例８と同様の方法を用いて光電変換素子（実験例９）を作製した。 (Experimental example 9)
A photoelectric conversion element (Experimental Example 9) was produced using the same method as in Experimental Example 8 except that a MoO 3 film was formed by a vacuum deposition method with a thickness of 10 nm instead of the HATCN film as a work function adjusting layer. did.
Figure JPOXMLDOC01-appb-T000007
Figure JPOXMLDOC01-appb-T000007
　表１は、実験例１～実験例９の仕事関数調整層、ｐ型バッファ層、光電変換層、電荷蓄積層および第２電極に用いた材料、仕事関数調整層、ｐ型バッファ層、光電変換層および第２電極の電子親和力、仕事関数およびイオン化ポテンシャルの値、および、実験例１の結果を基準とした実験例２～９における暗電流および量子効率の相対値をまとめたものである。なお、仕事関数およびイオン化ポテンシャルの測定は紫外線分光法を用いて行い、電子親和力については、材料の吸収分光特性より得られた光学バンドギャップおよび紫外線分光法によって得られたイオン化ポテンシャルの値を用いて算出した。 Table 1 shows materials used for the work function adjusting layer, the p-type buffer layer, the photoelectric conversion layer, the charge storage layer, and the second electrode in Experimental Examples 1 to 9, the work function adjusting layer, the p-type buffer layer, and the photoelectric conversion. The values of the electron affinity, work function and ionization potential of the layer and the second electrode, and the relative values of dark current and quantum efficiency in Experimental Examples 2 to 9 based on the results of Experimental Example 1 are summarized. The work function and ionization potential are measured using ultraviolet spectroscopy, and the electron affinity is determined using the optical band gap obtained from the absorption spectral characteristics of the material and the ionization potential obtained by ultraviolet spectroscopy. Calculated.
　表１から明らかなように、光電変換層のイオン化ポテンシャルおよび第２電極の仕事関数よりも大きい電子親和力を有する仕事関数調整層を用いた場合、低い暗電流および高い量子効率を示すことがわかった。また、仕事関数調整層の電子親和力よりも小さいイオン化ポテンシャルを有するＰ型バッファであり、かつ、光電変換層の電子親和力よりも小さい電子親和力を有するＰ型バッファを用いた場合、低い暗電流および高い量子効率を示すことがわかった。 As is clear from Table 1, it was found that when a work function adjusting layer having an ionization potential of the photoelectric conversion layer and an electron affinity larger than the work function of the second electrode was used, low dark current and high quantum efficiency were exhibited. . Further, when a P-type buffer having an ionization potential smaller than the electron affinity of the work function adjusting layer and a P-type buffer having an electron affinity smaller than that of the photoelectric conversion layer is used, low dark current and high It was found to show quantum efficiency.
　さらに表１から明らかなように、光電変換層のイオン化ポテンシャルおよび第２電極の仕事関数よりも大きい仕事関数を有する仕事関数調整層を用いた場合、低い暗電流および高い量子効率を示すことがわかった。また、仕事関数調整層の仕事関数よりも小さいイオン化ポテンシャルを有するＰ型バッファであり、かつ、光電変換層の電子親和力よりも小さい電子親和力を有するＰ型バッファを用いた場合、低い暗電流および高い量子効率を示すことがわかった。 Further, as is apparent from Table 1, it is found that when a work function adjusting layer having a work function larger than the ionization potential of the photoelectric conversion layer and the work function of the second electrode is used, a low dark current and a high quantum efficiency are exhibited. It was. Further, when a P-type buffer having an ionization potential smaller than the work function of the work function adjusting layer and having an electron affinity smaller than the electron affinity of the photoelectric conversion layer is used, a low dark current and a high It was found to show quantum efficiency.
　以上、実施の形態および適用例ならびに実施例を挙げて説明したが、本開示内容は上記実施の形態等に限定されるものではなく、種々変形が可能である。例えば、上記実施の形態では、撮像素子１内に近赤外領域の波長の光を光電変換する光電変換素子１０を単独で用いた例を示したが、例えば可視光等、近赤外領域以外の波長の光を光電変換する他の光電変換素子と組み合わせて用いてもよい。他の光電変換素子としては、例えば、半導体基板３０内に埋め込み形成される、所謂無機光電変換素子や、有機半導体材料を用いて光電変換層を形成した、所謂有機光電変換素子が挙げられる。 The embodiments, application examples, and examples have been described above, but the present disclosure is not limited to the above-described embodiments and the like, and various modifications are possible. For example, in the above-described embodiment, the example in which the photoelectric conversion element 10 that photoelectrically converts light having a wavelength in the near-infrared region is used alone in the imaging element 1 is shown. However, for example, visible light or the like other than the near-infrared region You may use in combination with the other photoelectric conversion element which photoelectrically converts the light of this wavelength. Examples of the other photoelectric conversion element include a so-called inorganic photoelectric conversion element embedded in the semiconductor substrate 30 and a so-called organic photoelectric conversion element in which a photoelectric conversion layer is formed using an organic semiconductor material.
　また、上記実施の形態等では、裏面照射型の撮像素子１の構成を例に挙げて説明したが、表面照射型の撮像素子にも適用可能である。更に、上記のように、他の光電変換素子と組み合わせて用いる場合には、所謂縦方向分光型の撮像素子として構成してもよいし、半導体基板上に、他の波長域の光を光電変換する光電変換素子を２次元配列（例えばベイヤー配列）させたものであってもよい。更にまた、例えば、多層配線側にメモリ素子等の他の機能素子が設けられた基板が積層されていてもよい。 In the above-described embodiment and the like, the configuration of the back-illuminated image sensor 1 is described as an example, but the present invention can also be applied to a front-illuminated image sensor. Furthermore, as described above, when used in combination with other photoelectric conversion elements, it may be configured as a so-called vertical spectral imaging element, or photoelectric conversion of light in other wavelength ranges on a semiconductor substrate. Alternatively, the photoelectric conversion elements may be two-dimensionally arrayed (for example, Bayer array). Furthermore, for example, a substrate on which another functional element such as a memory element is provided on the multilayer wiring side may be laminated.
　また、本技術の光電変換素子１０および撮像素子１ならびに撮像装置１００１では、上記実施の形態等で説明した各構成要素を全て備えている必要はなく、また逆に他の層を備えていてもよい。 In addition, the photoelectric conversion element 10, the imaging element 1, and the imaging apparatus 1001 according to the present technology do not have to include all the components described in the above-described embodiments and the like, and conversely, may include other layers. Good.
　また、本明細書に記載された効果はあくまでも例示であって限定されるものではなく、また他の効果があってもよい。 Further, the effects described in the present specification are merely examples and are not limited, and other effects may be obtained.
　また、本技術は、以下のような構成を取ることもできる。
［１］
　第１電極と、仕事関数調整層と、光電変換層と、電荷蓄積層と、第２電極とをこの順で少なくとも備え、
　該第１電極がアノードであり、
　該第２電極がカソードであり、
　該光電変換層が量子ドット材料を含み、
　該仕事関数調整層が、該第１電極と接して配されて、有機化合物を含み、
　下記の式１を満たす、光電変換素子。
　ＥＡ１≧ＷＦ２・・・・式１
（該式１中のＥＡ１は、該仕事関数調整層の電子親和力を示し、該式１中のＷＦ２は、該第２電極の仕事関数を示す。）
［２］
　前記仕事関数調整層と前記光電変換層が、下記の式２を満たす、［１］に記載の光電変換素子。
　ＥＡ１≧ＩＰ３・・・・式２
（該式２中のＩＰ３は、該光電変換層の該量子ドット材料のイオン化ポテンシャルを示す。）
［３］
　前記仕事関数調整層と前記光電変換層との間に、ｐ型バッファ層を更に備え、
　下記の式３を満たす、［１］に記載の光電変換素子。
　ＥＡ１≧ＩＰ２・・・・式３
（該式３中のＥＡ１は、前記仕事関数調整層の電子親和力を示し、該式３中のＩＰ２は、該ｐ型バッファ層のイオン化ポテンシャルを示す。）
［４］
　更に、下記の式４を満たす、［３］に記載の光電変換素子。
　ＥＡ２≦ＥＡ３・・・・式４
（該式４中のＥＡ２は、前記ｐ型バッファ層の電子親和力を示し、該式４中のＥＡ３は、前記光電変換層の前記量子ドット材料の電子親和力を示す。）
［５］
　前記光電変換層と前記電荷蓄積層との間に、ｎ型バッファ層を更に備える、［１］から［４］のいずれか１つに記載の光電変換素子。
［６］
　前記第２電極と前記電荷蓄積層との間に絶縁層を有し、前記第２電極と絶縁層を介して対抗配置され、かつ、前記絶縁層に設けられた開口を介して前記光電変換層と電気的に接続されている第３電極を更に備える、［１］から［５］のいずれか１つに記載の光電変換素子。
［７］
　第１電極と、仕事関数調整層と、光電変換層と、電荷蓄積層と、第２電極とをこの順で少なくとも備え、
　該第１電極がアノードであり、
　該第２電極がカソードであり、
　該光電変換層が量子ドット材料を含み、
　該仕事関数調整層が、該第１電極と接して配されて、無機化合物を含み、
　下記の式５を満たす、光電変換素子。
　ＷＦ０≧ＷＦ２・・・・式５
（該式５中のＷＦ０は、該仕事関数調整層の仕事関数を示し、該式５中のＷＦ２は、該第２電極の仕事関数を示す。）
［８］
　前記仕事関数調整層と前記光電変換層が、下記の式６を満たす、［７］に記載の光電変換素子。
　ＷＦ０≧ＩＰ３・・・・式６
（該式６中のＩＰ３は、該光電変換層の該量子ドット材料のイオン化ポテンシャルを示す。）
［９］
　前記仕事関数調整層と前記光電変換層との間に、ｐ型バッファ層を更に備え、
　下記の式７を満たす、［７］に記載の光電変換素子。
　ＷＦ０≧ＩＰ２・・・・式７
（該式７中のＷＦ０は、前記仕事関数調整層の仕事関数を示し、該式７中のＩＰ２は、該ｐ型バッファ層のイオン化ポテンシャルを示す。）
［１０］
　更に、下記の式８を満たす、［９］に記載の光電変換素子。
　ＥＡ２≦ＥＡ３・・・・式８
（該式８中のＥＡ２は、前記ｐ型バッファ層の電子親和力を示し、該式８中のＥＡ３は、前記光電変換層の前記量子ドット材料の電子親和力を示す。）
［１１］
　前記光電変換層と前記電荷蓄積層との間に、ｎ型バッファ層を更に備える、［７］から［１０］のいずれか１つに記載の光電変換素子。
［１２］
　前記第２電極と前記電荷蓄積層との間に絶縁層を有し、前記第２電極と絶縁層を介して対抗配置され、かつ、前記絶縁層に設けられた開口を介して前記光電変換層と電気的に接続されている第３電極を更に備える、［７］から［１１］のいずれか１つに記載の光電変換素子。
［１３］
　１次元又は２次元に配列された複数の画素毎に、
　少なくとも、［１］から［６］のいずれか１つに記載の１又は複数の光電変換素子と、半導体基板とが積層された、固体撮像装置。
［１４］
　１又は複数の前記光電変換素子が赤外光の光電変換を行う、［１３］に記載の固体撮像装置。
［１５］
　１次元又は２次元に配列された複数の画素毎に、
　少なくとも、［７］から［１１］のいずれか１つに記載の１又は複数の光電変換素子と、半導体基板とが積層された、固体撮像装置。
［１６］
　１又は複数の前記光電変換素子が赤外光の光電変換を行う、［１５］に記載の固体撮像装置。
［１７］
　［１３］から［１６］のいずれか１つに記載の固体撮像装置を備える、電子装置。 Moreover, this technique can also take the following structures.
[1]
At least a first electrode, a work function adjustment layer, a photoelectric conversion layer, a charge storage layer, and a second electrode in this order;
The first electrode is an anode;
The second electrode is a cathode;
The photoelectric conversion layer includes a quantum dot material;
The work function adjusting layer is disposed in contact with the first electrode and includes an organic compound;
A photoelectric conversion element that satisfies the following formula 1.
E A1 ≧ WF 2 ... Formula 1
(E A1 in the formula 1 represents the electron affinity of the work function adjusting layer, and WF 2 in the formula 1 represents the work function of the second electrode.)
[2]
The photoelectric conversion element according to [1], wherein the work function adjusting layer and the photoelectric conversion layer satisfy the following formula 2.
E A1 ≧ I P3 ... Formula 2
(I P3 in Formula 2 represents the ionization potential of the quantum dot material of the photoelectric conversion layer.)
[3]
A p-type buffer layer is further provided between the work function adjusting layer and the photoelectric conversion layer,
The photoelectric conversion element according to [1], which satisfies the following formula 3.
E A1 ≧ I P2 ... Formula 3
(E A1 in formula 3 represents the electron affinity of the work function adjustment layer, I P2 in formula 3 represents an ionization potential of the p-type buffer layer.)
[4]
Furthermore, the photoelectric conversion element according to [3], which satisfies the following formula 4.
E A2 ≦ E A3 ... Formula 4
(E A2 in the formula 4 represents the electron affinity of the p-type buffer layer, and E A3 in the formula 4 represents the electron affinity of the quantum dot material of the photoelectric conversion layer.)
[5]
The photoelectric conversion element according to any one of [1] to [4], further including an n-type buffer layer between the photoelectric conversion layer and the charge storage layer.
[6]
The photoelectric conversion layer has an insulating layer between the second electrode and the charge storage layer, is opposed to the second electrode and the insulating layer, and is provided through an opening provided in the insulating layer. The photoelectric conversion element according to any one of [1] to [5], further including a third electrode electrically connected to the first electrode.
[7]
At least a first electrode, a work function adjustment layer, a photoelectric conversion layer, a charge storage layer, and a second electrode in this order;
The first electrode is an anode;
The second electrode is a cathode;
The photoelectric conversion layer includes a quantum dot material;
The work function adjusting layer is disposed in contact with the first electrode and includes an inorganic compound;
A photoelectric conversion element that satisfies the following formula 5.
WF 0 ≧ WF 2 ... Formula 5
(WF 0 in Equation 5 represents the work function of the work function adjusting layer, and WF 2 in Equation 5 represents the work function of the second electrode.)
[8]
The photoelectric conversion element according to [7], wherein the work function adjustment layer and the photoelectric conversion layer satisfy the following formula 6.
WF 0 ≧ I P3 ... Formula 6
(I P3 in the equation 6 represents the ionization potential of the quantum dot material of the photoelectric conversion layer.)
[9]
A p-type buffer layer is further provided between the work function adjusting layer and the photoelectric conversion layer,
The photoelectric conversion element according to [7], which satisfies the following formula 7.
WF 0 ≧ I P2 ... Formula 7
(WF 0 in formula 7 indicates the work function of the work function adjusting layer, I P2 in formula 7 indicates the ionization potential of the p-type buffer layer.)
[10]
Furthermore, the photoelectric conversion element as described in [9] which satisfy | fills following formula 8.
E A2 ≦ E A3 ... Formula 8
(E A2 in Formula 8 indicates the electron affinity of the p-type buffer layer, and E A3 in Formula 8 indicates the electron affinity of the quantum dot material of the photoelectric conversion layer.)
[11]
The photoelectric conversion element according to any one of [7] to [10], further including an n-type buffer layer between the photoelectric conversion layer and the charge storage layer.
[12]
The photoelectric conversion layer has an insulating layer between the second electrode and the charge storage layer, is opposed to the second electrode and the insulating layer, and is provided through an opening provided in the insulating layer. The photoelectric conversion element according to any one of [7] to [11], further including a third electrode electrically connected to the.
[13]
For each of a plurality of pixels arranged in one or two dimensions,
A solid-state imaging device in which at least one or a plurality of photoelectric conversion elements according to any one of [1] to [6] and a semiconductor substrate are stacked.
[14]
The solid-state imaging device according to [13], wherein the one or more photoelectric conversion elements perform photoelectric conversion of infrared light.
[15]
For each of a plurality of pixels arranged in one or two dimensions,
A solid-state imaging device in which at least one or a plurality of photoelectric conversion elements according to any one of [7] to [11] and a semiconductor substrate are stacked.
[16]
The solid-state imaging device according to [15], wherein the one or more photoelectric conversion elements perform photoelectric conversion of infrared light.
[17]
[13] An electronic device comprising the solid-state imaging device according to any one of [16].
　１００…光電変換素子、１０１…第１電極（アノード）、１０２…仕事関数調整層、１０３…光電変換層、１０４…電荷蓄積層、１０５…第２電極（カソード）、１０６…第１絶縁層、１０７…第３電極 DESCRIPTION OF SYMBOLS 100 ... Photoelectric conversion element, 101 ... 1st electrode (anode), 102 ... Work function adjustment layer, 103 ... Photoelectric conversion layer, 104 ... Charge storage layer, 105 ... 2nd electrode (cathode), 106 ... 1st insulating layer, 107 ... Third electrode

Claims (18)

  1. 　第１電極と、仕事関数調整層と、光電変換層と、電荷蓄積層と、第２電極とをこの順で少なくとも備え、
    　該第１電極がアノードであり、
    　該第２電極がカソードであり、
    　該光電変換層が量子ドット材料を含み、
    　該仕事関数調整層が、該第１電極と接して配されて、有機化合物を含み、
    　下記の式１を満たす、光電変換素子。
    　ＥＡ１≧ＷＦ２・・・・式１
    （該式１中のＥＡ１は、該仕事関数調整層の電子親和力を示し、該式１中のＷＦ２は、該第２電極の仕事関数を示す。）     At least a first electrode, a work function adjustment layer, a photoelectric conversion layer, a charge storage layer, and a second electrode in this order;
    The first electrode is an anode;
    The second electrode is a cathode;
    The photoelectric conversion layer includes a quantum dot material;
    The work function adjusting layer is disposed in contact with the first electrode and includes an organic compound;
    A photoelectric conversion element that satisfies the following formula 1.
    E A1 ≧ WF 2 ... Formula 1
    (E A1 in the formula 1 represents the electron affinity of the work function adjusting layer, and WF 2 in the formula 1 represents the work function of the second electrode.)
  2. 　前記仕事関数調整層と前記光電変換層が、下記の式２を満たす、請求項１に記載の光電変換素子。
    　ＥＡ１≧ＩＰ３・・・・式２
    （該式２中のＩＰ３は、該光電変換層の該量子ドット材料のイオン化ポテンシャルを示す。）     The photoelectric conversion element according to claim 1, wherein the work function adjusting layer and the photoelectric conversion layer satisfy the following formula 2.
    E A1 ≧ I P3 ... Formula 2
    (I P3 in Formula 2 represents the ionization potential of the quantum dot material of the photoelectric conversion layer.)
  3. 　前記仕事関数調整層と前記光電変換層との間に、ｐ型バッファ層を更に備え、
    　下記の式３を満たす、請求項１に記載の光電変換素子。
    　ＥＡ１≧ＩＰ２・・・・式３
    （該式３中のＥＡ１は、前記仕事関数調整層の電子親和力を示し、該式３中のＩＰ２は、該ｐ型バッファ層のイオン化ポテンシャルを示す。）     A p-type buffer layer is further provided between the work function adjusting layer and the photoelectric conversion layer,
    The photoelectric conversion element of Claim 1 which satisfy | fills following formula 3.
    E A1 ≧ I P2 ... Formula 3
    (E A1 in formula 3 represents the electron affinity of the work function adjustment layer, I P2 in formula 3 represents an ionization potential of the p-type buffer layer.)
  4. 　更に、下記の式４を満たす、請求項３に記載の光電変換素子。
    　ＥＡ２≦ＥＡ３・・・・式４
    （該式４中のＥＡ２は、前記ｐ型バッファ層の電子親和力を示し、該式４中のＥＡ３は、前記光電変換層の前記量子ドット材料の電子親和力を示す。）     Furthermore, the photoelectric conversion element of Claim 3 which satisfy | fills following formula 4.
    E A2 ≦ E A3 ... Formula 4
    (E A2 in the formula 4 represents the electron affinity of the p-type buffer layer, and E A3 in the formula 4 represents the electron affinity of the quantum dot material of the photoelectric conversion layer.)
  5. 　前記光電変換層と前記電荷蓄積層との間に、ｎ型バッファ層を更に備える、請求項１に記載の光電変換素子。 The photoelectric conversion element according to claim 1, further comprising an n-type buffer layer between the photoelectric conversion layer and the charge storage layer.
  6. 　前記第２電極と前記電荷蓄積層との間に絶縁層を有し、前記第２電極と絶縁層を介して対抗配置され、かつ、前記絶縁層に設けられた開口を介して前記光電変換層と電気的に接続されている第３電極を更に備える、請求項１に記載の光電変換素子。 The photoelectric conversion layer has an insulating layer between the second electrode and the charge storage layer, is opposed to the second electrode and the insulating layer, and is provided through an opening provided in the insulating layer. The photoelectric conversion element according to claim 1, further comprising a third electrode electrically connected to the first electrode.
  7. 　第１電極と、仕事関数調整層と、光電変換層と、電荷蓄積層と、第２電極とをこの順で少なくとも備え、
    　該第１電極がアノードであり、
    　該第２電極がカソードであり、
    　該光電変換層が量子ドット材料を含み、
    　該仕事関数調整層が、該第１電極と接して配されて、無機化合物を含み、
    　下記の式５を満たす、光電変換素子。
    　ＷＦ０≧ＷＦ２・・・・式５
    （該式５中のＷＦ０は、該仕事関数調整層の仕事関数を示し、該式５中のＷＦ２は、該第２電極の仕事関数を示す。）     At least a first electrode, a work function adjustment layer, a photoelectric conversion layer, a charge storage layer, and a second electrode in this order;
    The first electrode is an anode;
    The second electrode is a cathode;
    The photoelectric conversion layer includes a quantum dot material;
    The work function adjusting layer is disposed in contact with the first electrode and includes an inorganic compound;
    A photoelectric conversion element that satisfies the following formula 5.
    WF 0 ≧ WF 2 ... Formula 5
    (WF 0 in Equation 5 represents the work function of the work function adjusting layer, and WF 2 in Equation 5 represents the work function of the second electrode.)
  8. 　前記仕事関数調整層と前記光電変換層が、下記の式６を満たす、請求項７に記載の光電変換素子。
    　ＷＦ０≧ＩＰ３・・・・式６
    （該式６中のＩＰ３は、該光電変換層の該量子ドット材料のイオン化ポテンシャルを示す。）     The photoelectric conversion element according to claim 7, wherein the work function adjusting layer and the photoelectric conversion layer satisfy the following formula 6.
    WF 0 ≧ I P3 ... Formula 6
    (I P3 in the equation 6 represents the ionization potential of the quantum dot material of the photoelectric conversion layer.)
  9. 　前記仕事関数調整層と前記光電変換層との間に、ｐ型バッファ層を更に備え、
    　下記の式７を満たす、請求項７に記載の光電変換素子。
    　ＷＦ０≧ＩＰ２・・・・式７
    （該式７中のＷＦ０は、前記仕事関数調整層の仕事関数を示し、該式７中のＩＰ２は、該ｐ型バッファ層のイオン化ポテンシャルを示す。）     A p-type buffer layer is further provided between the work function adjusting layer and the photoelectric conversion layer,
    The photoelectric conversion element of Claim 7 which satisfy | fills following formula 7.
    WF 0 ≧ I P2 ... Formula 7
    (WF 0 in formula 7 indicates the work function of the work function adjustment layer, I P2 in formula 7 indicates the ionization potential of the p-type buffer layer.)
  10. 　更に、下記の式８を満たす、請求項９に記載の光電変換素子。
    　ＥＡ２≦ＥＡ３・・・・式８
    （該式８中のＥＡ２は、前記ｐ型バッファ層の電子親和力を示し、該式８中のＥＡ３は、前記光電変換層の前記量子ドット材料の電子親和力を示す。）     Furthermore, the photoelectric conversion element of Claim 9 which satisfy | fills following formula 8.
    E A2 ≦ E A3 ... Formula 8
    (E A2 in Formula 8 indicates the electron affinity of the p-type buffer layer, and E A3 in Formula 8 indicates the electron affinity of the quantum dot material of the photoelectric conversion layer.)
  11. 　前記光電変換層と前記電荷蓄積層との間に、ｎ型バッファ層を更に備える、請求項７に記載の光電変換素子。 The photoelectric conversion element according to claim 7, further comprising an n-type buffer layer between the photoelectric conversion layer and the charge storage layer.
  12. 　前記第２電極と前記電荷蓄積層との間に絶縁層を有し、前記第２電極と絶縁層を介して対抗配置され、かつ、前記絶縁層に設けられた開口を介して前記光電変換層と電気的に接続されている第３電極を更に備える、請求項７に記載の光電変換素子。 The photoelectric conversion layer has an insulating layer between the second electrode and the charge storage layer, is opposed to the second electrode and the insulating layer, and is provided through an opening provided in the insulating layer. The photoelectric conversion element according to claim 7, further comprising a third electrode electrically connected to the first electrode.
  13. 　１次元又は２次元に配列された複数の画素毎に、
    　少なくとも、請求項１に記載の１又は複数の光電変換素子と、半導体基板とが積層された、固体撮像装置。     For each of a plurality of pixels arranged in one or two dimensions,
    A solid-state imaging device in which at least one or a plurality of photoelectric conversion elements according to claim 1 and a semiconductor substrate are stacked.
  14. 　１又は複数の前記光電変換素子が赤外光の光電変換を行う、請求項１３に記載の固体撮像装置。 The solid-state imaging device according to claim 13, wherein the one or more photoelectric conversion elements perform infrared photoelectric conversion.
  15. 　１次元又は２次元に配列された複数の画素毎に、
    　少なくとも、請求項７に記載の１又は複数の光電変換素子と、半導体基板とが積層された、固体撮像装置。     For each of a plurality of pixels arranged in one or two dimensions,
    A solid-state imaging device in which at least one or a plurality of photoelectric conversion elements according to claim 7 and a semiconductor substrate are stacked.
  16. 　１又は複数の前記光電変換素子が赤外光の光電変換を行う、請求項１５に記載の固体撮像装置。 The solid-state imaging device according to claim 15, wherein the one or more photoelectric conversion elements perform photoelectric conversion of infrared light.
  17. 　請求項１３に記載の固体撮像装置を備える、電子装置。 An electronic device comprising the solid-state imaging device according to claim 13.
  18. 　請求項１５に記載の固体撮像装置を備える、電子装置。 An electronic device comprising the solid-state imaging device according to claim 15.
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