WO2019151022A1

WO2019151022A1 - Semiconductor device and method for manufacturing same

Info

Publication number: WO2019151022A1
Application number: PCT/JP2019/001709
Authority: WO
Inventors: 和雄吉備
Original assignee: 東京エレクトロン株式会社
Priority date: 2018-02-02
Filing date: 2019-01-21
Publication date: 2019-08-08
Also published as: TW201937587A

Abstract

This manufacturing method, in which a pair of semiconductor fins standing upright from a substrate are provided and a fixed potential line conductive material, to which source areas of the semiconductor fins are connected, is provided, in an area between the adjacent semiconductor fins, up to a location higher than any of the apex surfaces of the semiconductor fins, comprises: a first step for preparing an intermediate body in which a protective material is provided on an area outside the area between the semiconductor fins; and a second step for removing the conductive material on the protective material by etching the conductive material up to a location lower than any of the apex surfaces of the semiconductor fins, and leaving the conductive material inside the area between the semiconductor fins.

Description

Semiconductor device and manufacturing method thereof

An exemplary embodiment of the present disclosure relates to a semiconductor device including a fin-type field effect transistor (Fin-FET) and a manufacturing method thereof.

Recent logic standard cells include a plurality of fin-type field effect transistors (hereinafter referred to as FETs), and attempts have been made to reduce the minimum unit height (cell height) of logic circuits. Yes. This is because when the cell height is reduced, the power consumption is reduced and the operation speed of the circuit is increased based on the scaling law.

Patent Document 1 discloses a structure in which a plurality of power rails (power supply lines / ground lines) are embedded in a logic standard cell having fin-type FETs. The dimension between two adjacent power rails is the cell height. Other fin-type FETs are disclosed in Patent Document 5, for example.

Although not a fin-type FET, Patent Document 2 discloses a technique for embedding a bit line of a memory, and Patent Document 3 and Patent Document 4 disclose a capacitor as related technologies.

US Patent Application Publication No. 2017/0062421 JP 2011-1511061 A Japanese Patent Laid-Open No. 10-50951 JP 2001-217407 A JP2015-159284A

However, it is difficult to easily form a power rail (fixed potential line) in a semiconductor device including a fin-type FET.

In a semiconductor device including a fin-type FET, a method for manufacturing a semiconductor device that can easily form a power rail and a semiconductor device that can be formed by such a method are required.

In order to solve the above-described problem, a first semiconductor device manufacturing method according to an aspect includes a first fin group including a pair of semiconductor fins, and a first fin group including a pair of semiconductor fins spaced apart from the first fin group. Two fin groups, and the first fin group includes a first semiconductor fin constituting a fin-type P-type field effect transistor including a source region, a gate region, and a drain region, and the second fin group includes: A semiconductor device comprising: a second semiconductor fin constituting a fin-type N-type field effect transistor including a source region, a gate region, and a drain region, and a fixed potential line to which the source region of the first semiconductor fin is connected In the manufacturing method, the method includes a first step of preparing an intermediate and a second step of leaving a conductive material, and the intermediate in the first step is separated from a substrate. The first semiconductor fins and the third semiconductor fins are provided, and are higher than any of the top surfaces of the first and third semiconductor fins in a region between the adjacent first and third semiconductor fins. A conductive material for the fixed potential line is provided up to a position, a protective material is provided on a region outside the region between the first and third semiconductor fins, and the second step includes the steps of Etching the conductive material to a position lower than any of the top surfaces of the third semiconductor fins, removing the conductive material on the protective material, and in the region between the first and third semiconductor fins, The conductive material is left behind.

According to this manufacturing method, in a semiconductor device including a fin-type FET, since the conductive material embedded between the semiconductor fins is self-aligned by the semiconductor fin, a power rail including a fixed potential line made of a conductive material can be easily formed. Can be formed.

In the second method for manufacturing a semiconductor device, the conductive material includes a first conductive material separated by a first distance d1 from the first semiconductor fin, and a first distance d1 <a second distance d2. A second conductive material separated from the second conductive material by a second distance d2, wherein the first conductive material is an etching barrier film having higher etching resistance than the second conductive material with respect to an etching gas of the second conductive material. It is characterized by being. Since the first conductive material is an etching barrier film, it functions as an etching stopper, and the semiconductor fin is protected by the first conductive material.

In the third method for manufacturing a semiconductor device, the first conductive material is TiN or TaN, and the second conductive material is at least one metal selected from the group consisting of Co, W, and Ru. The etching gas contains CF ₄ or a mixed gas of oxygen and Cl ₂ . In this case, a mixed gas of oxygen (O ₂ ) and Cl ₂ can etch the selected metal such as Ru, but a metal nitride such as TiN (titanium nitride) or TaN (tantalum nitride). Has etching resistance against this mixed gas.

In the fourth method for manufacturing a semiconductor device, the etching gas is a mixed gas of oxygen and Cl ₂ , and Cl with respect to the volume molar concentration C (O ₂ + Cl ₂ ) (mol / L) of the mixed gas in a unit volume. _The ratio of the volume molarity C (Cl ₂ ) (mol / L) of the _two gases has the following inequality: 1% ≦ C (Cl ₂ ) / C (O ₂ + Cl ₂ ) × 100 (%) ≦ 20% It is characterized by satisfying.

In the fifth method of manufacturing a semiconductor device, the etching gas is a mixed gas of oxygen and Cl ₂ , and Cl with respect to the volume molar concentration C (O ₂ + Cl ₂ ) (mol / L) of the mixed gas in a unit volume. _The ratio of the volume molarity C (Cl ₂ ) (mol / L) of the _two gases has the following inequality: 9% ≦ C (Cl ₂ ) / C (O ₂ + Cl ₂ ) × 100 (%) ≦ 11% It is characterized by satisfying.

In a sixth method for manufacturing a semiconductor device, the semiconductor device includes a pair of semiconductor fins erected from a substrate, and the semiconductor semiconductor is located in a region between adjacent semiconductor fins up to a position higher than any of the top surfaces of the semiconductor fins. A first step of preparing an intermediate body provided with a conductive material for a fixed potential line to which a source region of the fin is connected, and provided with a protective material on a region outside the region between the semiconductor fins; A second step of etching the conductive material to a position lower than any of the top surfaces of the substrate, removing the conductive material on the protective material, and leaving the conductive material in a region between the semiconductor fins; It is characterized by providing.

A semiconductor device according to an aspect includes a first fin group including a pair of semiconductor fins, and a second fin group including a pair of semiconductor fins spaced apart from the first fin group, and the first fin group. Includes a first semiconductor fin constituting a fin-type P-type field effect transistor including a source region, a gate region, and a drain region, and the second fin group includes a fin-type including a source region, a gate region, and a drain region. Including a second semiconductor fin constituting an N-type field effect transistor, and including a conductive material embedded in a region between the semiconductor fins of the first fin group to a position lower than any of the top surfaces of the semiconductor fins. And a fixed potential line connected to the source region of the semiconductor fin.

In this semiconductor device, a fixed potential line can be easily formed, and a semiconductor device with a small cell height can be manufactured. Therefore, power consumption can be reduced and an operation speed can be increased.

According to the method for manufacturing a semiconductor device according to the exemplary embodiment, a fixed potential line can be easily formed, and a semiconductor device with a small cell height can be manufactured, so that power consumption can be reduced and an operation speed can be increased. .

FIG. 1 is a circuit diagram of a logic standard cell. FIG. 2 is a truth table of logic standard cells. FIG. 3 is a circuit showing connection of FET groups in the logic standard cell. FIG. 4 is a perspective view of the FET group in the logic standard cell. 5A and 5B are a longitudinal sectional view in the vicinity of the gate of the FET and a longitudinal sectional view in the vicinity of the source / drain of the FET. FIG. 6 is a longitudinal sectional view of an intermediate body of the logic standard cell. FIG. 7 is a plan view of an intermediate body of the logic standard cell. FIG. 8 is a longitudinal sectional view of an intermediate of the logic standard cell. FIG. 9 is a longitudinal sectional view of an intermediate of the logic standard cell. FIG. 10 is a longitudinal sectional view of an intermediate body of the logic standard cell. FIG. 11 is a longitudinal sectional view of an intermediate of the logic standard cell. FIG. 12 is a longitudinal sectional view of an intermediate of the logic standard cell. FIG. 13 is a longitudinal sectional view of an intermediate of the logic standard cell. FIG. 14 is a longitudinal sectional view of an intermediate of the logic standard cell. FIG. 15 is a longitudinal sectional view of an intermediate of the logic standard cell. FIG. 16 is a longitudinal sectional view of an intermediate of the logic standard cell. FIG. 17 is a longitudinal sectional view of an intermediate of the logic standard cell. FIG. 18 is a longitudinal sectional view of an intermediate body of the logic standard cell. FIG. 19 is a plan view of an intermediate of the logic standard cell. FIG. 20 is a longitudinal sectional view of an intermediate of the logic standard cell. FIG. 21 is a longitudinal sectional view of an intermediate body of the logic standard cell. FIG. 22 is a longitudinal sectional view of an intermediate of the logic standard cell. FIG. 23 is a longitudinal sectional view of an intermediate of the logic standard cell. FIG. 24 is a plan view of an intermediate body of the logic standard cell. FIG. 25 is a longitudinal sectional view of an intermediate of the logic standard cell. FIG. 26 is a longitudinal sectional view of an intermediate of the logic standard cell. FIG. 27 is a longitudinal sectional view of an intermediate body of the logic standard cell. FIG. 28 is a longitudinal sectional view of an intermediate body of the logic standard cell. FIG. 29 is a longitudinal sectional view of an intermediate of the logic standard cell. FIG. 30 is a longitudinal sectional view of an intermediate of the logic standard cell. FIG. 31 is a longitudinal sectional view of an intermediate of the logic standard cell. FIG. 32 is a longitudinal sectional view of an intermediate of the logic standard cell. FIG. 33 is a plan view of an intermediate of the logic standard cell. FIG. 34 is a longitudinal sectional view of an intermediate of the logic standard cell. FIG. 35 is a longitudinal sectional view of an intermediate of the logic standard cell. FIG. 36 is a longitudinal sectional view of an intermediate of the logic standard cell. FIG. 37 is a longitudinal sectional view of an intermediate of the logic standard cell. FIG. 38 is a longitudinal sectional view of an intermediate of the logic standard cell. FIG. 39 is a plan view of an intermediate of the logic standard cell. FIG. 40 is a block diagram of the etching apparatus.

Hereinafter, a semiconductor device including a fin-type field effect transistor (Fin-FET) and a manufacturing method thereof will be described. Note that the same reference numerals are used for the same elements, and redundant description is omitted.

Fig. 1 is a circuit diagram of a logic standard cell.

This logic circuit is a NAND circuit with 3 inputs and 1 output. The input signals Vin1, Vin2, and Vin3 are voltage signals, and the output signal Vout is output from the output terminal Tout according to the input values to the input terminals Tin1, Tin2, and Tin3 of the NAND circuit. The NAND circuit includes a first P-type FET (P-FET 1), a second P-type FET (P-FET 2), a third P-type FET (P-FET 3), and a first N-type FET. (N-FET 1), a second N-type FET (N-FET 2), and a third N-type FET (N-FET 3). Although an enhancement type FET is shown in the figure, it may be a depletion type FET. The structure of the FET in the figure is a MOS type, but a junction type FET can also be adopted.

In the NAND circuit, the source S of the P-type FET is electrically connected to the power supply potential V ₊ , and the drain D is electrically connected to the output terminal Tout. In other words, the P-type FET is connected in parallel between terminals (power rails) that supply the power supply potential V ₊ and the ground potential GND. Input terminals Tin1, Tin2, and Tin3 are connected to the gates of the P-type FETs, respectively, and input signals Vin1, Vin2, and Vin3 are applied thereto.

The three N-type FETs are connected in series between the output terminal Tout and the ground potential GND. The source S of the N-type FET located at the bottom in the figure is electrically connected to the ground potential GND. Input terminals Tin1, Tin2, and Tin3 are connected to the gates of the N-type FETs, respectively, and input signals Vin1, Vin2, and Vin3 are applied thereto. This NAND circuit is composed of a complementary logic circuit (CMOS), and power consumption is suppressed as a characteristic of the CMOS logic circuit.

Fig. 2 is a truth table of logic standard cells.

The level of the output signal Vout is determined according to the voltage level (H: high level, L: low level) of the input signals Vin1, Vin2, and Vin3. Since it is a NAND circuit, the output signal Vout is at a low level when all three input signals are at a high level, and the output signal Vout is at a high level in other combinations.

FIG. 3 is a circuit showing the connection of FET groups in the logic standard cell.

Each FET has a source S, a gate G, and a drain D, and a semiconductor region corresponding to each element (electrode) is a source region, a gate region, and a drain region. The source electrode is in contact with the source region, the gate electrode is provided on the gate region via an insulating film, and the drain electrode is in contact with the drain region. The electrical connection is as shown in FIG. 1. However, when a fin circuit is used to form a NAND circuit, the first switch Q1 is interposed between the P-FET 1 and the P-FET 2, and the P-FET 2 Since the second switch Q2 is interposed between the P-FET 3 and a high level is given to these switches (P channel gate), these switches are turned OFF, and between the transistors in the fin for the P-type FET Is prohibited. In the figure, an additional switch QP (P channel gate) is connected to the drain D of the P-FET 3, and this drain D is connected to another potential (eg, reset potential) as necessary. However, there may be no additional switch QP.

On the other hand, a third switch Q3 is interposed between N-FET1 and N-FET2, and a fourth switch Q4 is interposed between N-FET2 and N-FET3, and these switches (N-channel gates) are connected. When a high level is given, these switches are turned OFF, and conduction between transistors in the fin for the N-type FET is permitted. In the figure, an additional switch QN (N channel gate) is connected to the source S of the N-FET 3, and this source S is connected to another potential (eg, reset potential) as necessary. Although there may be no additional switch QN.

FIG. 4 is a perspective view of the FET group in the logic standard cell.

Each FET is opposed to a pair of dummy FETs. That is, for the P-FET1, P-FET2, and P-FET3, the first P-type dummy FET (DP-FET1), the second P-type dummy FET (DP-FET2), Third P-type dummy FETs (DP-FETs 3) face each other. Between these P-type FET pairs, a fixed potential line (power supply potential V ₊ ) is arranged.

Similarly, for N-FET1, N-FET2, and N-FET3, a first N-type dummy FET (DN-FET1) and a second N-type dummy FET (DN-FET2) are used as dummy FETs. The third N-type dummy FETs (DN-FET 3) are opposed to each other. A fixed potential line (ground potential GND) is disposed between these N-type FET pairs.

In the description, an XYZ three-dimensional orthogonal coordinate system is set, the thickness direction of each layer in the laminated structure is set as the Z-axis direction, and two axes orthogonal to the Z-axis are set as the X-axis and the Y-axis. The height direction of each fin is the positive direction of the Z axis, the longitudinal direction is the positive direction of the Y axis, and the width direction is the X axis direction. The cell height CHT is a distance between the center lines of the fixed potential lines (V ₊ / GND) that are adjacently spaced along the X-axis direction. In this example, the cell height CHT is assumed to be 120 nm or less.

FIG. 5- (A) is a longitudinal sectional view near the gate of the FET (Y1 section), and FIG. 5- (B) (Y2 section) near the source / drain of the FET.

5A. In the vicinity of the gate in FIG. 5A, a plurality of semiconductor fins 2 are provided on the semiconductor substrate 1, and conductive materials (7, 8) are embedded between these semiconductor fins 2. FIG. The conductive material 8 constitutes a fixed potential line and is supplied with a power supply potential or a ground potential. A gate electrode 21 is provided on the semiconductor fin 2 via a gate insulating film 18. An oxide film 27 and an interlayer insulating film 29 are deposited on the gate electrode 21, and the gate electrode 21 is interposed via a contact electrode 28. And connected to a specific signal wiring 30.

In the vicinity of the source / drain (Y2 cross section) in FIG. 5B, a plurality of semiconductor fins 2 are provided on the semiconductor substrate 1, and these semiconductor fins 2 are formed of P-type conductive regions 14 and N-type conductive regions 14. A conductive region 15 is formed, one conductive region 14 (source region) is electrically connected to the conductive material 8 via the electrode material ELEC1 (Ru), and the other conductive region 15 (drain region) is connected to another location. The electrode material ELEC1 is electrically connected, and an oxide film 27 and an interlayer insulating film 29 are deposited thereon, and the drain region is connected to another signal wiring 30.

Hereinafter, a method for manufacturing the logic standard cell having the above-described structure will be described.

FIG. 6 is a longitudinal sectional view of the intermediate body of the logic standard cell, and FIG. 7 is a plan view of the intermediate body of the logic standard cell. FIG. 6 is a vertical cross section along the dotted line Y1 in FIG. 7, but the mask MSK1 shown in FIG. 6 is omitted.

First, a semiconductor substrate 1 made of Si is prepared, a striped mask MSK1 is patterned on the surface of the semiconductor substrate 1, and the semiconductor substrate 1 is etched through the mask MSK1. For mask patterning, photolithography using photoresist coating / development is used.

The etching method of the semiconductor substrate (Si) is dry etching, and a capacitively coupled plasma (CCP) type can be adopted as an etching apparatus.

The specific conditions for etching at this time are as follows.

Etching gas: CF ₄
・ Etching temperature: 20 ~ 100 ℃
・ Etching time: 10-60sec

Note that as the etching gas, O ₂ , N _2, or H ₂ can be used instead of CF ₄ , and a mixed gas containing two or more gases selected from an etching gas group consisting of these etchings is used. You can also For this etching, in addition to the CCP type etching apparatus, an electron cyclotron resonance plasma (ECR plasma) type, a helicon wave plasma (HWP) type, an inductively coupled plasma (ICP) type, and a surface wave plasma (SWP) type are adopted. You can also

By this etching, the semiconductor fins 2 remain directly under the mask, and a plurality of semiconductor fins 2 are erected from above the semiconductor substrate 1. The longitudinal direction of the stripe-shaped mask is the Y-axis direction, the distance between the centers of adjacent semiconductor fins 2 in the X-axis direction is 24 nm, and the height of the semiconductor fins 2 in the Z-axis direction is 120 nm. The width of the top surface of the semiconductor fin 2 in the X-axis direction is 8 nm, and the width of the bottom surface between the semiconductor fins 2 is 12 nm. The upper part (part with a height of 50 nm from the top) of the semiconductor fin 2 constitutes a transistor, and the lower part (part with a thickness of 70 nm from the bottom) functions as a side wall adjacent to the fixed potential line. The depth of the semiconductor fin 2 in FIG. 8 in the Y-axis direction is set to 38 nm, for example. Although the dimensions that can significantly reduce power consumption are as described above, the power consumption can be reduced even if each dimension is changed by ± 10%.

FIG. 8 is a longitudinal sectional view of an intermediate of the logic standard cell.

After the plurality of semiconductor fins 2 are formed, the upper mask is removed with an organic solvent such as acetone, and then the semiconductor fins 2 are thinned out. That is, in FIG. 6, the second, fourth, fifth, and seventh semiconductor fins 2 from the left are removed. As a result, the first, third, sixth, and eighth semiconductor fins 2 from the left remain. The removal of the semiconductor fin 2 in FIG. 8 is performed as follows. First, a photoresist is applied on a semiconductor substrate, and only the first, third, sixth, and eighth semiconductor fins 2 from the left are protected, and a mask having an opening in the remaining region is used to pattern the photoresist by photolithography. The semiconductor fin in the opening of the mask is etched. A dry etching method can be used for the etching.

The etching method of the semiconductor fin (Si) is dry etching, and a capacitively coupled plasma (CCP) type can be adopted as an etching apparatus.

The specific conditions for etching at this time are as follows.

As an etching gas, O _2, N ₂ or H ₂ can be used instead of CF ₄ , and a mixed gas containing two or more gases selected from an etching gas group consisting of these etchings is used. You can also For this etching, in addition to the CCP type etching apparatus, an electron cyclotron resonance plasma (ECR plasma) type, a helicon wave plasma (HWP) type, an inductively coupled plasma (ICP) type, and a surface wave plasma (SWP) type are adopted. You can also

A wet etching method can also be used as a method for etching semiconductor fins (Si). As the etchant, HNO ₃ + HF and KOH + IPA (isopropyl alcohol) + H ₂ O ₂ are known for adjusting the etching rate. For example, the etching temperature is set to 20 to 100 ° C. and the etching time is set to 10 to 60 sec. can do.

FIG. 9 is a longitudinal sectional view of an intermediate of the logic standard cell.

Next, the semiconductor fin 2 is heated in an oxygen atmosphere to form an oxide film (SiO ₂ ) on the entire surface of the substrate. The temperature for forming the thermal oxide film is set to 400 ° C. to 1000 ° C., and the thickness of the oxide film 4 covering the semiconductor fin 2 is set to 3 to 6 nm. Further, a protective film 5 (protective material) is formed on the entire surface of the substrate. The material of the protective film 5 is amorphous carbon, and the formation method is CVD / PVD or spin coating. The protective film 5 is filled between the adjacent semiconductor fins 2, and the thickness of the protective film 5 is set so as to cover the top surface of the semiconductor fin 2 and the surface thereof is positioned higher than this.

FIG. 10 is a longitudinal sectional view of an intermediate of the logic standard cell.

Next, a part of the protective film 5 is removed, and a first region between the left pair of semiconductor fins 2 and a second region between the right pair of semiconductor fins 2 are opened. The protection film 5 is removed by etching through a mask. That is, a photoresist is applied on the protective film 5, the first and second regions are opened, and a mask for protecting the remaining regions is formed by patterning the photoresist by photolithography, The protective film 5 is etched. The etching method of the protective film (amorphous carbon) is dry etching, and a capacitively coupled plasma (CCP) type can be adopted as an etching apparatus.

The specific conditions for etching at this time are as follows.

Etching gas: CO
・ Etching temperature: 100-350 ℃
・ Etching time: 20-60sec

As the etching gas, N ₂ or H ₂ can be used instead of CO, and a mixed gas containing two or more gases selected from an etching gas group consisting of these etchings can also be used. For this etching, in addition to the CCP type etching apparatus, an electron cyclotron resonance plasma (ECR plasma) type, a helicon wave plasma (HWP) type, an inductively coupled plasma (ICP) type, and a surface wave plasma (SWP) type are adopted. You can also

Thereby, part of the protective film 5 is etched, and the oxide film 4 located at the bottom between the semiconductor fins 2 is exposed. Note that the oxide film or nitride film in the description is an insulating film.

FIG. 11 is a longitudinal sectional view of an intermediate of the logic standard cell.

Next, the liner film 7 is formed on the substrate surface. The liner film 7 covers the oxide film 4 and the protective film 5 located on the side surface of the semiconductor fin 2.

The formation method of the liner film 7 is a well-known atomic layer deposition (ALD) method, and specific formation conditions are as follows.
-Material of liner film 7: TiN
-Formation temperature: 200-600 ° C
・ Thickness: 0.5nm to 2.0nm
Source gas: TiCl ₄ + N ₂ / N ₂ (Alternate supply on substrate surface)

As the material of the liner film 7, TaN can be used instead of TiN, and a chemical vapor deposition (CVD) method can be used instead of the ALD method.

Thereafter, a conductive material 8 for forming the above-described fixed potential line is formed on the substrate. Ruthenium (Ru) can be used as the conductive material. Ru is a platinum group element and has a characteristic of dissolving in acid. In addition to Ru, tungsten (W) or the like can be used as the conductive material 8. However, when Ru is used, it has an advantage of low resistance over these metals. The conductive material 8 is located not only in the region between the semiconductor fins 2 but also above the uppermost surface of the protective film 5.

The formation method of the conductive material 8 (Ru) is a CVD method, and specific formation conditions are as follows.
-Material of conductive material 8: Ru
-Formation temperature: 200-500 ° C
・ Maximum thickness in the Z-axis direction: 30 to 60 nm
Source gas: Ruthenium carbonyl (Ru ₃ (CO) ₁₂ )
・ Carrier gas: Ar

Note that the conductive material 8 (Ru) can also be formed by a physical vapor deposition (PVD) method such as a sputtering method. Tungsten (W) can be used for the conductive material 8, but in this case, the conductive material 8 (W) can be formed by a CVD method or a sputtering method.
FIG. 12 is a longitudinal sectional view of an intermediate of the logic standard cell.

Next, the conductive material 8 is etched back again to remove a part. By this etch back, the thickness (height) of the conductive material 8 is reduced to 50 nm, and the surface thereof is located below the top surface of the semiconductor fin 2. The liner film 7 (TiN) is an etching barrier film for the etching gas or etching liquid for the conductive material 8.

The etching back method of the conductive material 8 is dry etching, and a capacitively coupled plasma (CCP) type can be adopted as an etching apparatus.

The specific conditions for etch back at this time are as follows.

Etching gas: CF ₄
・ Etching temperature: 20 ~ 100 ℃
・ Etching time: 30sec ~ 240sec

As the etch back gas, a mixed gas of O ₂ and Cl ₂ can be used instead of CF ₄ . For this etching, in addition to the CCP type etching apparatus, an electron cyclotron resonance plasma (ECR plasma) type, a helicon wave plasma (HWP) type, an inductively coupled plasma (ICP) type, and a surface wave plasma (SWP) type are adopted. You can also

Also, a wet etching method can be used as a method for etching the conductive material 8 (Ru).

The liner film 7 (TiN) is etched by wet etching. As an etching solution for Ru, H ₂ O ₂ , FPM (hydrofluoric acid hydrogen peroxide mixed solution) and the like are known. For example, the etching temperature is set to 20 to 100 ° C., and the etching time is set to 30 to 240 sec. Can do. As a TiN etching solution, a mixed solution of H ₂ O ₂ and ammonium hydroxide is also known. The liner film 7 is etched to the same height as the conductive material 8.

FIG. 13 is a longitudinal sectional view of an intermediate of the logic standard cell.

After the liner film 7 is removed by etching to the same height as the conductive material 8, a cap film 101 is formed on the exposed surface of the conductive material 8. The material of the cap film 101 is an antioxidant film of the conductive material 8, and is also a barrier film for protecting the conductive material 8 from etching. Since the cap film 101 is not etched when the material to be etched formed on the cap film 101 is etched, the cap film 101 also functions as an etching stop film. The material of the cap film 101 is Si ₃ N ₄ , but TiN, TaN, AlOx (such as Al ₂ O ₃ ), or the like can be used instead.

FIG. 14 is a longitudinal sectional view of an intermediate of the logic standard cell.

Next, the protective film 5 is removed. Since the protective film 5 is made of amorphous carbon, ashing is used to remove the amorphous carbon. Ashing is a technique for removing a carbon-based compound such as a photoresist. For example, an oxygen (O ₂ ) plasma is generated by a plasma generator, and the amorphous carbon is irradiated with this oxygen plasma. Remove. In addition, photoexcited ashing that irradiates ultraviolet rays in an atmosphere of ozone (O ₃ ) gas is also known.

FIG. 15 is a longitudinal sectional view of an intermediate of the logic standard cell.

Thereafter, an oxide film 9 (SiO ₂ ) is formed on the entire surface of the substrate. The thickness of the oxide film 9 is higher than the height of the semiconductor fin 2. As a method for forming the oxide film 9, an ALD method, a CVD method, a coating method, or the like is applicable. A batch processing apparatus or a single-wafer film forming apparatus can be employed as a mode of transporting and processing the substrate to the processing apparatus, and spin coating can be employed as the film forming apparatus when a coating method is used. it can.

The specific formation condition of the silicon oxide film 9 is a CVD method as follows.
Deposit material: TEOS (tetraethyl orthosilicate), O ₂
・ Deposition time: 10sec ~ 1800sec
-Formation temperature: 400-900 ° C
・ Oxidation time: 1Hour

When the ALD method using tetraethoxysilane is adopted, the formation temperature is 150 to 400 ° C.

FIG. 16 is a longitudinal sectional view of an intermediate of the logic standard cell.

Next, the entire surface of the substrate on which the oxide film 9 is formed is etched again, and the oxide film 4 provided on the semiconductor fin 2 is removed together with the oxide film 9. As a result, the semiconductor portion of the semiconductor fin 2 is exposed, and part of the oxide film 4 and the oxide film 9 remains. The etching method of the oxide film 4 and the oxide film 9 is dry etching, and a capacitively coupled plasma (CCP) type can be adopted as an etching apparatus.

The specific conditions for etching at this time are as follows.

Etching gas: C ₄ F ₈
・ Etching temperature: 20 ~ 100 ℃
・ Etching time: 5-60sec

As the etching gas, CF ₂ , CF ₃ , C ₂ F ₂ , C ₂ F _4, C ₂ F _6, Ar, CHF _3, O _2, or O ₃ may be used instead of C ₄ F _8. It is also possible to use a mixed gas containing two or more gases selected from an etching gas group consisting of these etchings. For this etching, in addition to the CCP type etching apparatus, an electron cyclotron resonance plasma (ECR plasma) type, a helicon wave plasma (HWP) type, an inductively coupled plasma (ICP) type, and a surface wave plasma (SWP) type are adopted. You can also
FIG. 17 is a longitudinal sectional view of an intermediate of the logic standard cell.

Next, a gate oxide film 10 is formed so as to cover the exposed surface of the semiconductor fin 2. The gate oxide film 10 is composed of two layers of oxide films. First, the exposed portion of the semiconductor fin 2 is heated in an oxygen atmosphere to form a thermal oxide film having a thickness of 1.4 nm on the surface. Thereafter, a CVD oxide film having a thickness of 2 nm is formed so as to cover the thermal oxide film. Therefore, oxide film 10 having a thickness of 3.4 nm in total is formed. The thickness of the oxidized semiconductor fin 2 in the X-axis direction is 6.5 nm at the position of the top surface and 8.5 nm at the position of the upper end portion of the oxide film 4.

FIG. 18 is a longitudinal sectional view of an intermediate body of the logic standard cell (near the gate), and FIG. 19 is a plan view of the intermediate body of the logic standard cell. FIG. 18 is a longitudinal section taken along the dotted line Y1 in FIG.

Next, a dummy gate electrode 11 is formed on the semiconductor fin 2 via the oxide film 10. The dummy gate electrode 11 is provided only in a region that functions as a gate region of a transistor or a switch. The method for forming the dummy gate electrode 11 is as follows.

First, a conductive material (polysilicon) for a dummy gate is formed on a substrate by a CVD method using SiH ₄ -based source gas. Next, an inorganic insulator mask 12 is formed on the conductive material layer, in which a stripe-shaped region is protected along the X-axis direction and the remainder is opened.

The inorganic insulator mask 12 is made of an inorganic insulator such as a silicon nitride film. In order to form this inorganic insulator mask, first, an inorganic insulating layer (Si ₃ N ₄ ) is deposited on a conductive material (polysilicon) by CVD, and then a photoresist is applied on the inorganic insulating layer. Then, an organic resin mask having the same pattern as that of the inorganic insulator mask 12 is formed. The organic resin mask is formed by patterning a photoresist by photolithography. The inorganic insulating mask 12 is formed by etching the inorganic insulating layer (Si ₃ N ₄ ) in the opening using the organic resin mask. Sputtering can also be employed as a method for depositing the inorganic insulating layer.

The etching method of the inorganic insulating layer (Si ₃ N ₄ ) is dry etching, and a capacitively coupled plasma (CCP) type can be adopted as an etching apparatus.

The specific conditions for etching at this time are as follows.

Etching gas: CF ₄ and O ₂
・ Etching temperature: 20 ~ 100 ℃
・ Etching time: 5 to 120 sec

As the etching gas, SF ₆ , SF ₅ , SF ₄ , SF ₃ , SF ₂ , Ar, or N ₂ can be used instead of CF ₄ and O _{2. From the} etching gas group consisting of these etchings A mixed gas containing two or more selected gases can also be used. For this etching, in addition to the CCP type etching apparatus, an electron cyclotron resonance plasma (ECR plasma) type, a helicon wave plasma (HWP) type, an inductively coupled plasma (ICP) type, and a surface wave plasma (SWP) type are adopted. You can also

After the inorganic insulator mask 12 is formed, the conductive material (polysilicon) located in the opening of the inorganic insulator mask 12 is etched, so that the conductive material remains only on the gate region, and the dummy gate electrode 11 is formed. It is formed.

Note that the etching method of the conductive material (polysilicon) is dry etching, and a capacitively coupled plasma (CCP) type can be adopted as an etching apparatus.

The specific conditions for etching at this time are as follows.

Etching gas: Cl ₂ and HBr
・ Etching temperature: 20 ~ 120 ℃
・ Etching time: 5 to 300 sec

As the etching gas, Cl ₂ or SF ₆ can be used instead of Cl ₂ and HBr, and a mixed gas containing two or more gases selected from an etching gas group consisting of these etchings is used. You can also. For this etching, in addition to the CCP type etching apparatus, an electron cyclotron resonance plasma (ECR plasma) type, a helicon wave plasma (HWP) type, an inductively coupled plasma (ICP) type, and a surface wave plasma (SWP) type are adopted. You can also

As described above, five dummy gate electrodes 11 extending along the X-axis direction are formed on the substrate (see FIG. 19). In FIG. 19, the upper inorganic insulator mask 12 is not shown.

FIG. 20 is a vertical cross-sectional view (Y2 cross section) of the intermediate body (in the vicinity of the source / drain) of the logic standard cell. In FIG. 19, the source / drain of the transistor is located at the position of the dotted line Y2.

In FIG. 18, the oxide film 10 is formed on the upper portion of the semiconductor fin 2. However, in forming the source region and the drain region, the oxide film 10 shown in FIG. 18 is removed. The oxide film 10 can be removed in the polysilicon etching step when forming the dummy gate electrode 11 shown in FIG.

Next, a sidewall 13 made of SiCN is formed on the surface so as to cover the semiconductor fin 2. The side wall 13 is formed using a PE-CVD (Plasma Enhanced-Chemical Vapor Deposition) method, specifically as follows.
Reaction gas: (SiH ₄ , CH ₄ , H ₂ , N ₂ ) or (N ₂ , (CH ₃ ) ₃ Si—NH—Si (CH ₃ ) ₃ (hexamethyldisilazane (HMDS)))
-Formation temperature: 200-600 ° C
・ Formation time: 10 to 300 sec

The initial sidewall 13 covers the entire upper portion of the semiconductor fin 2 and covers the side surface and top surface of the semiconductor fin 2 and the bottom portion between the fins, but the substrate surface is sputter etched with a rare gas such as argon. The upper side wall of the semiconductor fin 2 and the bottom film between the fins are removed, the upper side is opened, and the side wall 13 is formed.

Next, a protective film PN is formed on the region where the N-FET is to be formed (the region where the semiconductor fin 2 is formed on the right side of the drawing). The material and forming method of the protective film PN are as follows.
・ Material: Resist ・ Formation method: Spin coating

Thereafter, the sidewall 13 in the region where the P-FET is to be formed (the region where the semiconductor fin 2 is formed on the left side of the drawing) is etched. By this etching, the side wall 13 on the left side of the drawing has a desired height. The side wall 13 may be formed by crystal growth of the constituent material.

The side wall 13 (SiCN) etching method is dry etching, and a capacitively coupled plasma (CCP) type can be adopted as an etching apparatus.

Specific conditions for etching at this time are as follows.
Etching gas: CF ₄ and H ₂ O
・ Etching temperature: 20 ~ 100 ℃
・ Etching time: 5 to 300 sec

As the etching gas, COF ₂ , OF ₂ , O ₂ F ₂ can be used instead of CF ₄ and H ₂ O, and two or more gases selected from an etching gas group consisting of these etchings can be used. A mixed gas containing can also be used. For this etching, in addition to the CCP type etching apparatus, an electron cyclotron resonance plasma (ECR plasma) type, a helicon wave plasma (HWP) type, an inductively coupled plasma (ICP) type, and a surface wave plasma (SWP) type are adopted. You can also

Thereafter, the semiconductor fin 2 in the region where the P-FET is to be formed is etched to a position near the upper end of the side wall 13.

The etching method of the semiconductor fin 2 (Si) is dry etching, and the specific conditions of etching at this time are as follows.

As an etching gas, in place of CF _4, O _2, N ₂ or H ₂ can be used, a mixed gas containing two or more gases selected from the etching gas group consisting of etching You can also. For this etching, in addition to the CCP type etching apparatus, an electron cyclotron resonance plasma (ECR plasma) type, a helicon wave plasma (HWP) type, an inductively coupled plasma (ICP) type, and a surface wave plasma (SWP) type are adopted. You can also Other etching gases are also applicable.

Next, the conductive region 14 made of SiGe containing boron at a high concentration is epitaxially grown on the exposed surface of the semiconductor fin 2 for P-FET whose upper portion is etched.

The conductive region 14 (SiGe) functions as a conductive source region or drain region in the P-FET, but a CVD (chemical vapor deposition) method is adopted as a crystal growth method. The specific conditions for crystal growth at this time are as follows.

Source gas: SiH ₄ , GeH ₄
-Impurity gas: B (boron) -containing gas-Growth temperature: 550-700 ° C
・ Growth time: 15-60 min

Boron (B) is a P-type (first conductivity type) impurity in Si, and phosphorus (P) or arsenic (As) is an N-type (second conductivity type) impurity. Further, Si ₂ H ₆ can be used instead of SiH ₄ as a source gas.

Next, the conductive region 15 on the N-FET side is formed.

FIG. 21 is a vertical cross-sectional view (Y2 cross section) of the intermediate body of the logic standard cell (in the vicinity of the source / drain).

First of all. The protective film PN on the region where the N-FET is to be formed (the region where the semiconductor fin 2 is formed on the right side of the drawing) is removed by ashing, and the region where the P-FET is to be formed (the semiconductor fin 2 on the left side of the drawing is formed) The protective film PP on the region) is formed. The material and forming method of the protective film PP are the same as the material and forming method of the protective film PN.

Thereafter, the sidewall 13 in the region where the N-FET is to be formed (the region where the semiconductor fin 2 is formed on the right side of the drawing) is etched. By this etching, the side wall 13 on the right side of the drawing has a desired height. The side wall 13 may be formed by crystal growth of the constituent material.

The etching method for the right side wall 13 (SiCN) is the same as the etching method for the left side wall 13 described above.

Thereafter, the semiconductor fin 2 in the region where the N-FET is to be formed is etched to a position near the upper end of the side wall 13. The etching method for the right semiconductor fin 2 (Si) at this time is the same as the etching method for the left semiconductor fin 2 described above.

Next, a conductive region 15 made of Si containing nitrogen, phosphorus, arsenic or the like at a high concentration is epitaxially grown on the exposed surface of the semiconductor fin 2 for N-FET whose upper portion is etched. Si grows epitaxially with aligned crystal axes.

The conductive region 15 functions as a conductive source region or drain region in the N-FET, but a CVD (chemical vapor deposition) method is adopted as a crystal growth method. The specific conditions for crystal growth at this time are as follows.
・ Source gas: SiH ₄ , C ₂ H ₄
Impurity gas: N ₂
・ Growth temperature: 1300 ~ 1800 ℃
・ Growth time: 60-120 min
Note that as the impurity gas, in addition to N ₂ , a gas containing P, As, Sb, or the like that becomes N-type impurities can be used. Note that when a P-type semiconductor is formed, a P-type impurity such as B or Al is used.

Next, the protective film PP is removed by ashing. Further, as shown in FIG. 22, a nitride film (Si ₃ N ₄ ) 161 and an oxide film 16 (SiO ₂ ) are sequentially formed so as to cover the entire surface of the substrate. As a method for forming the nitride film 161, for example, the same CVD method as that for the insulator 17 can be used.

FIG. 22 is a vertical cross-sectional view (Y2 cross section) of the intermediate body (in the vicinity of the source / drain) of the logic standard cell. The surface position of the oxide film 16 is higher than the height of the conductive region 14 and the conductive region 15. The formation method of the oxide film 16 is film formation or coating, and CVD / PVD or spin coating can be adopted as the forming apparatus.

A specific method for forming the oxide film 16 (SiO ₂ ) is a CVD method as follows. Raw materials: TEOS (tetraethyl orthosilicate), O ₂
-Formation temperature: 400-900 ° C
・ Formation time: 5-12hours
Note that the oxide film 16 can also be formed by using the PVD method or spin coating. The formation temperature of the CVD method can be set to 300 to 1200 ° C., and O ₃ can be used instead of O ₂ . Perhydropolysilazane can be used in a coating method by spin coating.
After the oxide film 16 is formed, the surface of the oxide film 16 is planarized by chemical mechanical polishing (CMP).

FIG. 23 is a longitudinal sectional view (Y1 cross section) of the intermediate body of the logic standard cell (near the gate), and FIG. 24 is a plan view of the intermediate body of the logic standard cell. In FIG. 23, the gate of the transistor is located at the position of the dotted line Y1.

By the above-described CMP, the inorganic insulator mask 12 (protective film) in FIG. 18 is also removed, and the surface of the dummy gate electrode 11 is flattened to expose the surface. Here, a contact hole is formed in a region of the dummy gate electrode 11 immediately above the conductive material 8, and an insulating film 17 (Si ₃ N ₄ ) is formed in the contact hole. The contact hole is formed by forming a mask having this portion opened and etching the dummy gate electrode 11.

The etching method of the dummy gate electrode 11 (polysilicon) is dry etching, and the specific conditions of etching at this time are as follows.

Etching gas: CF ₄
・ Etching temperature: 20 ~ 120 ℃
・ Etching time: 5 to 300 sec

As the etching gas, O _2, N ₂ or H ₂ can be used instead of CF ₄ , and a mixed gas containing two or more gases selected from an etching gas group consisting of these etchings is used. You can also For this etching, in addition to the CCP type etching apparatus, an electron cyclotron resonance plasma (ECR plasma) type, a helicon wave plasma (HWP) type, an inductively coupled plasma (ICP) type, and a surface wave plasma (SWP) type are adopted. You can also

The insulating film 17 (Si ₃ N ₄ ) is formed by vapor phase growth, and a CVD apparatus or a PVD apparatus can be adopted as a forming apparatus. The specific formation conditions of the insulating film 17 are as follows in the case of the CVD method.
Raw materials: SiH ₂ Cl ₂ and NH ₃
-Formation temperature: 300-1200 ° C
-Formation time: 10 sec to 1800 sec

After forming the insulating film 17 on the entire surface of the substrate, the insulating film 17 is CMPed to embed the insulating film 17 (insulator) in the contact hole. As shown in FIG. 24, the insulating film 17 is buried at 10 locations with respect to the five dummy gate electrodes 11. The insulator 17 is used to separate functions between various elements.

FIG. 25 is a longitudinal sectional view (Y1 cross section) of the intermediate body (near the gate) of the logic standard cell.

Subsequently, as shown in FIG. 25, the dummy gate electrode 11 shown in FIG. 23 is removed. The dummy gate electrode 11 is made of polysilicon, and the etching method of the dummy gate electrode 11 at this time is dry etching, and the specific conditions of the etching at this time are as follows.

As the etching gas, O ₂ or H ₂ can be used instead of CF ₄ , and a mixed gas containing two or more gases selected from an etching gas group consisting of these etchings can also be used. . For this etching, in addition to the CCP type etching apparatus, an electron cyclotron resonance plasma (ECR plasma) type, a helicon wave plasma (HWP) type, an inductively coupled plasma (ICP) type, and a surface wave plasma (SWP) type are adopted. You can also

Thereafter, the thin oxide film 10 (SiO ₂ ) shown in FIG. 23 is removed. The etching method of the oxide film 10 is dry etching, and the specific conditions of the etching at this time are as follows.

Etching gas: C ₄ F ₈
・ Etching temperature: 20 ~ 100 ℃
・ Etching time: 5 to 100 sec

As the etching gas, CF ₂ , CF ₃ , C ₂ F ₂ , C ₂ F _4, C ₂ F _6, Ar, CHF _3, O _2, or O ₃ may be used instead of C ₄ F _8. It is also possible to use a mixed gas containing two or more gases selected from an etching gas group consisting of these etchings. For this etching, in addition to the CCP type etching apparatus, an electron cyclotron resonance plasma (ECR plasma) type, a helicon wave plasma (HWP) type, an inductively coupled plasma (ICP) type, and a surface wave plasma (SWP) type are adopted. You can also

Subsequently, a gate electrode is formed.

FIG. 26 is a longitudinal sectional view (Y1 cross section) of the intermediate body (near the gate) of the logic standard cell.

First, the exposed portion of the upper portion of the semiconductor fin 2 is oxidized to form a gate insulating film 18 on the semiconductor fin 2. The gate insulating film 18 is a thermal oxide film of Si, and is formed by heating in an oxygen atmosphere at 800 ° C. to 1100 ° C. The gate insulating film 18 can also be formed at temperatures of about 400 to 900 ° C. (CVD) and 150 to 400 ° C. (ALD). Next, a conductive material 19 made of metal is deposited and formed on the entire surface of the substrate. The deposition method is a sputtering method in which the target metal is decomposed or reacted, and the target metal (specifically, W (tungsten)) is sputtered with plasma-generated argon by a high-frequency plasma sputtering apparatus, and this metal is allowed to reach room temperature. Deposited on the substrate surface. The conductive material 19 becomes the gate electrode of the FET and switch in the P-FET formation region.

FIG. 27 is a longitudinal sectional view (Y1 cross section) of the intermediate body (near the gate) of the logic standard cell.

Next, the conductive material 19 located on the N-FET formation scheduled region (right region) is selectively removed by etching. In the selective removal, a photoresist is applied on the region where the N-FET is to be formed, and this is exposed and developed to form a mask in which only the region where the N-FET is to be formed is opened. When the conductive material 19 is etched and the oxide film 9 is exposed, the etching is stopped.

The etching method of the conductive material 19 (W) is dry etching, and the specific conditions of the etching at this time are as follows.
Etching gas: CF ₄ , O ₂
・ Etching temperature: 100-350 ℃
・ Etching time: 20-60sec

As an etching gas, a mixed gas of O ₂ gas, CF ₄ gas and HBr can be used instead of CF ₄ and O ₂ , and two or more kinds selected from an etching gas group consisting of these etchings can be used. A mixed gas containing a gas can also be used. For this etching, in addition to the CCP type etching apparatus, an electron cyclotron resonance plasma (ECR plasma) type, a helicon wave plasma (HWP) type, an inductively coupled plasma (ICP) type, and a surface wave plasma (SWP) type are adopted. You can also Note that wet etching is also possible.

Further, another conductive material 20 is deposited and formed in the space in the N-FET formation scheduled region (right region) from which the conductive material 19 has been removed. The deposition method is a sputtering method in which a target metal is decomposed or reacted, and a target metal (W) is sputtered with argon converted into plasma by a high-frequency plasma sputtering apparatus, and this metal is deposited on the substrate surface at room temperature. The conductive material 20 becomes the gate electrode of the FET and switch in the N-FET formation region. Thereafter, the surface of the conductive material 20 is planarized by CMP.

The P-side gate electrode (conductive material 19) and the N-side gate electrode (conductive material 20) are in physical contact and are electrically connected to function as an integrated gate electrode 21. The conductive material 19 and the conductive material 20 may be changed to different metals when the work function is controlled.

FIG. 28 is a longitudinal sectional view (Y1 cross section) of the intermediate body (near the gate) of the logic standard cell.

As shown in the figure, after forming the integrated gate electrode 21, a protective nitride film 22 (SiNx) is formed on the gate electrode 21. As a forming method, the nitride film 22 is formed on the gate electrode 21 by a CVD method using SiH ₂ Cl ₂ and NH ₃ as source gases. The forming temperature is set to room temperature, and the thickness is set to 20 nm, for example.

Further, as shown in FIG. 29 (Y2 cross section), the oxide film 16 on the source region (P-type conductive region 14) and the drain region (N-type conductive region 15) is anisotropically etched as shown. ,Remove. A mask pattern is formed on the oxide film 16 before etching, and only the portions adjacent to the source region and the drain region in the X-axis direction remain.
The etching method of the oxide film 16 is dry etching, and the specific conditions of the etching at this time are as follows.

Next, as shown in FIG. 30, a protective film CA as an insulating layer is formed on the entire surface of the substrate. The material of the protective film CA is amorphous carbon, and the formation method is CVD / PECVD or spin coating. The protective film CA is filled between the adjacent semiconductor fins 2. The thickness of the protective film CA is higher than the top surface of the semiconductor fin 2, and the surface of the protective film CA is higher than the source region 14 and the drain region 15. Set to be located.

Further, as shown in FIG. 31, a hard mask HM is formed on the protective film CA. As a formation method, a CVD method at room temperature, a PVD method, or an ALD method can be used. As a material of the hard mask HM, a nitride film, a titanium-based film, a silicon-based film, a silicon oxide film, or the like is used. Can do. In this example, a silicon nitride film (Si ₃ N ₄ ) is used.

Next, as shown in FIG. 32 (Y2 cross section), the hard mask HM is patterned by etching using photolithography, and focusing on one Y2 cross section, the central region in the X direction and the fixing of the N-FET A pattern is formed in which the region immediately above the potential line 8 is opened (see FIG. 33).

Next, as shown in FIG. 34 (Y2 cross section), using the hard mask HM as a mask, the protective film CA in the region immediately below the opening is removed. As a removal method, dry etching methods such as CCP, ECR, HWP, ICP, SWP can be used.

Thereafter, as shown in FIG. 35 (Y2 cross section), an oxide film OX (SiO ₂ ) is formed in the region where the protective film CA has been removed, and then the oxide film OX is subjected to CMP to planarize the surface. To do. CMP is stopped on the surface of the hard mask HM.

Next, as shown in FIG. 36 (Y2 cross section), the protective film CA is removed, and the first contact hole CH10 in which the fixed potential line 8, the nitride film 161 on the surface of the source region 14 and the drain region 15 are exposed, Two contact holes CH20 and a third contact hole CH30 are formed simultaneously. As a removing method, dry etching is used. The first contact hole CH10 is formed in a region where the protective film CA (insulating layer) is present in the oxide film OX (insulating layer), and extends toward the source region 14 and the fixed potential line 8 to form the second contact. The hole CH20 and the third contact hole CH30 are formed in a region where the protective film CA (insulating layer) exists in the oxide film OX (insulating layer), and extend to the two drain regions 15 respectively.

For the P-FET, the shape of the contact hole reaching the drain region is the same as the shape of the contact hole reaching the drain region of the N-FET shown in the Y2 cross section. The shape of the contact hole reaching the source region is the same as that of the contact hole reaching the source region of the P-FET in the N-FET 3 (see FIG. 3), and in other N-FETs The shape of the contact hole reaching the drain region of the N-FET in the Y2 cross section is the same (see FIG. 33).

More specifically, in the contact hole forming process, with respect to the P-FET, the plurality of contact holes include the first contact hole CH10 and the second and third contact holes, and the first contact hole CH10 is a source region. 14 and the fixed potential line 8, and the second contact hole and the third contact hole extend toward two drain regions in the same XZ section of the P-FET, respectively, and the first contact hole The second contact hole and the third contact hole are opened simultaneously.

On the other hand, with regard to the N-FET, the plurality of contact holes are the first contact hole extending toward the source region of the N-FET 3 (see FIG. 3), the second contact hole CH20 and the third contact hole in the Y2 cross section being CH30. The second contact hole CH20 and the third contact hole CH30 extend toward the drain regions 15 located at two positions on the Y2 cross section, and the first contact hole of the N-FET 3 The first contact hole, the second contact hole, and the third contact hole are opened simultaneously, extending toward the source region and the fixed potential line 8 (GND). In N-FETs other than N-FET 3, the first contact hole only needs to extend toward the source region, and does not need to extend to the fixed potential line 8.

39, when the switch Q4 in FIG. 39 is turned on, the second contact hole CH20 and the third contact hole CH30 reaching the drain region in the Y2 cross section of FIG. When connecting adjacent N-FETs using these, these contact holes are required.

The etching method of the hard mask HM and the protective film CA at this time is reactive ion etching (RIE: reactive ion etching) of dry etching, and the hard mask HM (Si ₃ N ₄ ) and the protective film CA (amorphous carbon). ) Can be continuously processed by changing the gas and conditions for supplying the gas. It is also possible to process both etchings continuously in the same etching vessel. As the etching apparatus, a capacitively coupled plasma (CCP) type can be adopted.

Specific conditions for dry etching of the hard mask HM at this time are as follows.
Etching gas: CF ₄
・ Etching temperature: 20 ~ 100 ℃
・ Etching time: 5 to 120 sec

As an etching gas, O ₂ , O ₃ , SF ₆ , SF ₅ , SF ₄ , SF ₃ , SF ₂ , Ar, or N ₂ can be used instead of CF _4. Etching made of these etchings A mixed gas containing two or more gases selected from a gas group can also be used. For this etching, in addition to the CCP type etching apparatus, an electron cyclotron resonance plasma (ECR plasma) type, a helicon wave plasma (HWP) type, an inductively coupled plasma (ICP) type, and a surface wave plasma (SWP) type are adopted. You can also

Specific conditions for dry etching of the protective film CA are as follows.
Etching gas: CO
・ Etching temperature: 100-350 ℃
・ Etching time: 20-60sec

As the etching gas, N ₂ or H ₂ can be used instead of CO, and a mixed gas containing two or more gases selected from an etching gas group consisting of these etchings can also be used. In addition to the CCP type etching apparatus, this etching is performed by using electron cyclotron resonance plasma (ECR plasma) type, helicon wave plasma (HWP) type, inductively coupled plasma (ICP) type, and surface wave plasma. (SWP) type can be adopted, and continuous etching is possible only by changing the etching gas and conditions in the same chamber as the etching chamber (container) of the hard mask HM. Productivity is improved if processing is possible in the same chamber. However, when the processing time becomes long, it is possible to perform processing in different chambers connected in a vacuum environment in consideration of throughput. Further, when the protective film CA is etched by RIE, the side walls below the source region and the drain region become the oxide film 16. In this ALE, the etching selectivity between the protective film CA and the oxide film 16 is sufficient. The protective film CA is selectively removed.

Further, as shown in FIG. 37, a part of the nitride film 161 as an insulating layer formed in advance is removed by etching to expose the source region 14 and the drain region 15, and in the Y2 cross section, P The portion of the nitride film 101 on the conductive material 8 that is a fixed potential line on the FET side is also removed simultaneously with the nitride film 161. The etching method of the nitride film 161 and the nitride film 101 (Si ₃ N ₄ ) is ALE (Atomic Layer Etching), and a capacitively coupled plasma (CCP) type can be adopted as an etching apparatus. As a result, the surface of the conductive material 8 as the fixed potential line is exposed and can be connected thereto. Note that not only the source region of the P-FET but also the N-NET source region (see FIG. 3) is connected to the fixed potential line, a structure obtained by horizontally inverting FIG. 37 may be employed.

The specific conditions of ALE at this time are as follows, and the first gas and the second gas are alternately supplied onto the substrate surface.
Etching gas: first gas is C ₅ F ₈ , second gas is CF ₄
・ Etching temperature: -20 ~ 100 ℃
・ Etching time: 30 to 120 sec

Note that C ₅ HF ₉ , C ₄ HF ₇ , and C ₃ HF ₅ can be used as the first etching gas instead of C ₅ F ₈ , and CF ₄ is used as the second etching gas. Instead, C ₂ F ₆ , C ₃ F ₈ , CH ₃ F, CH ₂ F ₂ , and CHF ₃ can be used. For this etching, in addition to the CCP type etching apparatus, an electron cyclotron resonance plasma (ECR plasma) type, a helicon wave plasma (HWP) type, an inductively coupled plasma (ICP) type, and a surface wave plasma (SWP) type are adopted. You can also The

nitride films

161 and 101 can be etched in the same chamber (container) in which the hard mask HM and the protective film CA are etched. Alternatively, it is possible to perform processing in different chambers connected in a vacuum environment in consideration of throughput.

Further, wet etching can be adopted as the etching of the nitride film, and a batch type can be adopted as the etching apparatus. Specific conditions for etching at this time are as follows.
Etching solution: H ₃ PO ₄
・ Etching temperature: 80-200 ℃
・ Etching time: 5-60 min

In the etching, a mask having the pattern opened is formed by photolithography using a photoresist, and a desired region is etched using the mask.

Note that other plasma etching may be employed as an etching method for the nitride film 161 and the nitride film 101 (Si ₃ N ₄ ). For example, plasma etching using the following gas species in a CCP type plasma etching apparatus.

Etching gas: CF ₄
・ Etching temperature: 20 ~ 100 ℃
・ Etching time: 5 to 120 sec

Thus, the surface of the left conductive material 8 that is a fixed potential line is exposed in the Y2 cross section. Further, although the upper surfaces of the source region 14 and the drain region 15 are exposed, the ground potential conductive material 8 which is a fixed potential line on the N-FET side is not exposed.

As described above, the insulating layer that is opened when the contact hole is formed includes a plurality of insulating layers including the hard mask HM (nitride film), the protective layer CA (amorphous carbon layer), and the nitride films (161, 101). Consists of layers. The insulating layer includes at least a first nitride film (hard mask HM), a protective film CA (amorphous carbon layer), and second nitride films (nitride films 161 and 101).

Further, the step of opening the contact hole includes a step of etching the first nitride film (hard mask HM) and the protective film CA (amorphous carbon layer) and a part of the second nitride film (nitride films 161 and 101). And a process of performing. Further, the step of etching the first nitride film (hard mask HM) and the protective film CA (amorphous carbon layer) can be carried out continuously by reactive ion etching (RIE) to increase productivity. Moreover, the damage to the source and drain can be minimized by executing the second nitride film by atomic layer etching. In addition, the step of etching the first nitride film (hard mask HM) and the protective film CA (amorphous carbon layer) and the step of etching the part of the second nitride film are performed continuously in the same chamber (container). You can also This enables processing with high productivity and less damage.

Next, as shown in FIG. 38, after a liner film LF2 (TiN or TaN) is formed on the entire surface of the substrate, an electrode material ELEC1 is formed on the substrate surface so as to cover the entire surface. As this formation method, a CVD method, a PVD method, a plating method, or a coating method can be used, but a sputtering method can also be used. The liner film LF2 is located at the boundary between the electrode material ELEC1 and the substrate.

When the liner film LF2 made of TiN is formed by the sputtering method, the specific formation conditions are as follows.
-Material of liner film LF2: TiN
-Formation temperature: 200-600 ° C
・ Thickness: 0.5nm to 2.0nm

As the material for the liner film LF2, TaN can be used instead of TiN.

As the electrode material ELEC1, Ru, Co, or W can be used.

38, in the first contact hole CH10, the second contact hole CH20, and the third contact hole CH30 in FIG. 37, the first contact electrode (electrode material ELEC1) and the second contact electrode (electrode material), respectively. ELEC1) and a third contact electrode (electrode material ELEC1) are formed.

The source region 14 and the drain region 15 are electrically connected to the electrode ELEC1 well by annealing at about 450 ° C. Thereafter, the exposed surface of the electrode material ELEC1 (Ru) filled in the contact hole on the substrate surface is etched back by dry etching or wet etching to remove excess ruthenium metal R and planarize the surface. . If necessary, the substrate surface may be subjected to CMP treatment.

Reference is now made to FIG. As shown in FIG. 5, an oxide film 27 (SiO ₂ ) is formed on the planarized substrate surface. That is, in the Y2 cross section, the oxide film 27 is formed on the electrode material ELEC1 and the oxide film OX. The method for forming the oxide film 27 is vapor phase growth, and an ALD apparatus or a CVD apparatus can be employed as the forming apparatus.

When the CVD method is used, specific conditions for forming the oxide film 27 are as follows.
Raw materials: TEOS (tetraethyl orthosilicate), O ₂
-Formation temperature: 400-900 ° C
・ Formation time: 5 to 1800 sec

Note that the oxide film 16 can also be formed by using an ALD method, a PVD method, or spin coating. The formation temperature of the CVD method can be set to 300 to 1200 ° C., and O ₃ can be used instead of O ₂ . Perhydropolysilazane can be used in a coating method by spin coating.

Next, a contact hole is formed in the oxide film 27, and a contact electrode 28 is formed in the contact hole. The contact hole is formed by forming a mask on the oxide film 27 and etching through the mask. In this mask, a photoresist is applied on the exposed surface of the oxide film 27, and this is exposed and developed to open only the source region and drain region in the N-FET formation scheduled region and the region on the gate electrode 21. To form. The oxide film 27 is etched through this mask, and the etching is stopped when the electrode material is exposed. The etching method for the oxide film 27 (SiO ₂ ) at this time may be dry etching similar to the oxide film 16 and the oxide film 9 described above. As an etching apparatus, in addition to a CCP type etching apparatus, an electron cyclotron resonance is used. A plasma (ECR plasma) type, a helicon wave plasma (HWP) type, an inductively coupled plasma (ICP) type, and a surface wave plasma (SWP) type can also be adopted.

The material of the contact electrode 28 is made of ruthenium, Co or W, and can be formed by CVD or PVD. The forming temperature is 200 to 600 ° C. When the contact hole is filled with this material, Finish the deposition. Thereafter, the surface of the oxide film 27 is CMPed to remove excess electrode material.

Next, SiOC, which is a low-k (low dielectric constant material), is formed on the oxide film 27 as an interlayer insulating film 29, and a line-shaped recess extending in the Y-axis direction is formed on the SiOC. Then, the signal wiring 30 is formed. When an interlayer insulating film material having a low dielectric constant is used, the inter-wiring capacitance can be reduced. SiO ₂ is known as the material for the interlayer insulating film, but the relative dielectric constant is about 4.2 to 4.0, and the relative dielectric constant is preferably 3.0 or less. As the Low-k film, a carbon-enhanced silicon oxide film (SiOC film) of PE-CVD (Plasma Enhanced-Chemical Vapor Deposition) having a relative dielectric constant k = 2.9 is known.

The formation method of the interlayer insulating film 29 is a PE-CVD method, and a PE-CVD apparatus can be adopted as the formation apparatus.

Specific conditions for forming the interlayer insulating film 29 (SiOC film) are as follows.
・ Raw material: (CH ₃ ) ₃ Si—NH—Si (CH ₃ ) ₃ (hexamethyldisilazane (HMDS)), O ₂
-Formation temperature: 400-1200 ° C
・ Formation time: 5-60 min

The etching method of SiOC constituting the interlayer insulating film is dry etching, and a capacitively coupled plasma (CCP) type can be adopted as an etching apparatus. The specific conditions for etching are as follows.

Etching gas: C ₄ F ₈
・ Etching temperature: 20 ~ 100 ℃
・ Etching time: 5 to 300 sec

Note that the etching gas is CF ₂ , CF ₃ , C ₂ F ₂ , C ₂ instead of C ₄ F _8.
F _4, C ₂ F _6, Ar, N _2, O _2, or O ₃ can be used, and a mixed gas containing two or more gases selected from an etching gas group consisting of these etchings can also be used. . For this etching, in addition to the CCP type etching apparatus, an electron cyclotron resonance plasma (ECR plasma) type, a helicon wave plasma (HWP) type, an inductively coupled plasma (ICP) type, and a surface wave plasma (SWP) type are adopted. You can also

The material of the signal wiring 30 is made of Cu, the forming method is plating, the forming temperature is room temperature, and the deposition of the material is finished when the signal wiring is filled with this material. Thereafter, the surface of the interlayer insulating film 29 is CMPed to remove excess material.

Thereby, the electrode material ELEC1 (Ru) formed on the drain region and the source region on the N-FET side is connected to the signal wiring 30 via the contact electrode 28, and the gate electrode 21 is connected via the contact electrode 28. It is connected to another signal wiring 30. The number of signal wirings 30 is plural, and can be connected to various elements as necessary. Note that, in the Y2 cross section, the source region in the P-FET and the drain region in the N-FET are shown, but this cross sectional structure is the same in the XZ cross section passing through the source region in the P-FET. Further, except for the N-FET 3, the XZ cross section passing through the drain region of the P-FET and the source region of the N-FET is the same as the cross section passing through the drain region of the N-FET forming region of the Y2 cross section. Further, the XZ cross section passing through the source region of the N-FET 3 is a cross section obtained by inverting the left and right of the Y2 cross section, and the source region of the N-FET 3 is connected to a fixed potential line (GND) made of the conductive material 8. .

As described above, as shown in FIGS. 3 and 4, a plurality of P-type fin-type transistors P-FET1, P-FET2, and P-FET3, and a P-type fin-type dummy FET, DP-FET1, DP-FET2, and DP-FET3 are formed, and a plurality of N-type fin-type transistors N-FET1, N-FET2, and N-FET3, and an N-type fin-type dummy FET, DN- FET1, DN-FET2, and DN-FET3 are formed.

In FIG. 39, input signals Vin1, Vin2, Vin3 and a high-level control signal (High) are input to the signal wiring 30 in FIG. 39, and the output signals Vout are P-FET1, P-FET2, P Although it is taken out from the signal wiring 30 connected to the drain region of the FET 3, the drain region of the N-FET 1 is electrically connected to the signal wiring 30 of the output signal Vout. Since different signal wirings 30 are connected to the gate electrode of the transistor and the gate electrodes of the switches Q1 to Q4, different signals or biases can be given to them.

As described above, in the etching in FIGS. 36 to 38, the control device in the plasma processing apparatus has a semiconductor fin including a source region and a drain region constituting a field effect transistor, and a fixed potential line provided along with the semiconductor fin. (Conductive material 8), a first step of preparing an intermediate body in which an insulating layer CA is provided over a source region, a drain region, and a fixed potential line, and an insulating layer The CA includes a second step of simultaneously opening a plurality of contact holes respectively extending to the source region, the drain region, and the fixed potential line. This method further includes a step of forming a plurality of contact electrodes (electrode material ELEC1 (FIG. 38)) in the plurality of contact holes, respectively.

In addition, it is possible to manufacture a product even if all the manufacturing conditions described above are changed by ± 15%.

FIG. 40 is a block diagram of an etching apparatus using plasma.

Controller CONT controls power source BV to generate plasma from plasma generation source PG. The generated plasma is an etching gas plasma supplied from the gas supply source 100 into the processing container 102, and the amount of the etching gas is controlled by the controller CONT. The plasma gas moves toward the substrate W (wafer) and etches various materials on the substrate W. The substrate W is fixed by an electrostatic chuck CK, and the temperature of the substrate W is adjusted by the heater 105. The electrostatic chuck CK is connected to the ground in the controller CONT via the matching unit MG, and the heater 105 is connected to the controller CONT via the heater power source 104. An exhaust pipe 111 is connected to the processing container 102 and is connected to an exhaust device 110 (vacuum pump) via a pressure control valve PCV.

The apparatus shown in the figure includes a CCP type etching apparatus, an electron cyclotron resonance plasma (ECR plasma) type, a helicon wave plasma (HWP) type, and an inductively coupled plasma (ICP) depending on the form of the plasma generation source PG. It functions as a type, surface wave plasma (SWP) type plasma processing apparatus, and can perform the etching described above.

As described above, in the etching in FIG. 12, the control device in the plasma processing apparatus includes the first semiconductor fin (for P-FET) and the third semiconductor fin (for P-FET) erected from the substrate. A conductive material 8 for a fixed potential line is provided in a region between the adjacent first and third semiconductor fins up to a position higher than any of the top surfaces of the first and third semiconductor fins. A first step of preparing an intermediate provided with a protective material (protective film 5) on a region outside the region between the semiconductor fins, to a position lower than any of the top surfaces of the first and third semiconductor fins; Etching the conductive material 8 to remove the conductive material on the protective material (protective film 5), and to perform the second step of leaving the conductive material 8 in the region between the first and third semiconductor fins. Control to The control method of this embodiment is executed by such a control device.

In the control of the etching of the conductive material, as an etching gas for plasma treatment, oxygen _{(O 2),} and the case of using a mixed gas of Cl _2, the proportion of Cl _2, i.e. _{_{Cl 2 / (O 2 + Cl}} 2 ) × 100 value (%) is controlled to be 1% to 20%. It is preferably controlled to be 7% to 15%. More preferably, it is controlled to be 9% to 11%.

In other words, when the second conductive material forming the fixed potential line is at least one metal selected from the group consisting of Co, W, and Ru, the etching gas for the second conductive material is oxygen (O ₂ ) is a mixed gas of Cl ₂ and the flow rate ratio of the Cl ₂ gas to the total gas, that is, to the molar concentration C (O ₂ + Cl ₂ ) (mol / L) of the mixed gas in a unit volume in the processing vessel. It is preferable that the ratio of the volume molar concentration C (Cl ₂ ) (mol / L) of the Cl ₂ gas satisfies the following inequality.
1% ≦ C (Cl ₂ ) / C (O ₂ + Cl ₂ ) × 100 (%) ≦ 20%, more preferably
9% ≦ C (Cl ₂ ) / C (O ₂ + Cl ₂ ) × 100 (%) ≦ 11%.

In these cases, if the lower limit is not reached, the etching rate tends to be inferior. If the upper limit is exceeded, it is considered that the selectivity tends to be impaired. Since the etching rate and the selectivity can be obtained at the same time, there is an effect that these problems are unlikely to occur.

According to this control method, the power rail can be easily formed in the semiconductor device including the fin-type FET for the reason of self-alignment.

In FIG. 12, the conductive material includes the first conductive material (liner film 7) separated from the first semiconductor fin 2 by the first distance d <b> 1 and the first semiconductor fin 2, where the first distance d <b> 1 is equal to the second distance d <b> 2. And a second conductive material (conductive material 8) separated by a second distance d2, and the first conductive material has an etching resistance higher than that of the second conductive material against the etching gas of the second conductive material. It is. Since the first conductive material is an etching barrier film, it functions as an etching stopper, and the semiconductor fin 2 is protected by the first conductive material (liner film 7).

The first conductive material 7 is TiN or TaN, the second conductive material 8 is at least one metal selected from the group consisting of Co, W, and Ru, and the etch-back gas of the second conductive material 8 is , (1) CF ₄ , or (2) a mixed gas of oxygen and Cl ₂ . In this case, a mixed gas of oxygen (O ₂ ) and Cl ₂ can etch the selected metal such as Ru, but a metal nitride such as TiN (titanium nitride) or TaN (tantalum nitride). Has etching resistance against this mixed gas. In the case of these metals, both the etching stopper function and the electrical conductivity required for the fixed power supply line can be achieved. In particular, when Ru is used as the conductive material, there is an effect of low resistance.

Further, the above manufacturing method includes a pair of semiconductor fins 2 erected from the substrate, and the semiconductor fins 2 are located in a region between the adjacent semiconductor fins 2 to a position higher than any of the top surfaces of the semiconductor fins 2. A first step of preparing an intermediate body in which a conductive material 8 for a fixed potential line to which a source region is connected is provided and a protective material is provided on a region outside the region between the semiconductor fins 2; The conductive material 8 is etched to a position lower than any of the top surfaces, the conductive material on the protective material is removed, and a second step of leaving the conductive material in the region between the semiconductor fins is provided. .

In the semiconductor device (logic standard cell) described above, the first fin group (P-FET) composed of a pair of semiconductor fins 2 and the second fin composed of a pair of semiconductor fins separated from the first fin group. A fin group (N-FET), and the first fin group (P-FET) includes a first semiconductor fin constituting a fin-type P-type field effect transistor including a source region, a gate region, and a drain region. The second fin group (N-FET) includes a second semiconductor fin constituting a fin-type N-type field effect transistor including a source region, a gate region, and a drain region, and includes a first fin group (P-FET). The region between the semiconductor fins 2 includes a conductive material 8 embedded up to a position lower than any of the top surfaces of the semiconductor fins, and is fixed to the source region of the semiconductor fins 2. It has a potential line 8.

2 ... Semiconductor fin, 7 ... Liner film, 8 ... Conductive material, 9 ... Oxide film, 11 ... Gate electrode, 13 ... Side wall, CH10 ... First contact hole, CH20 ... Second contact hole, CH30 ... Third contact hole , CA ... protective film (amorphous carbon layer: insulating layer), HM ... hard mask (first nitride film: insulating layer), 161 ... nitride film (second nitride film: insulating layer), 29 ... interlayer insulating film, 30 ... Signal wiring.

Claims

A first fin group comprising a pair of semiconductor fins;
A second fin group spaced apart from the first fin group and comprising a pair of semiconductor fins;
With
The first fin group includes a first semiconductor fin constituting a fin-type P-type field effect transistor including a source region, a gate region, and a drain region,
The second fin group includes a second semiconductor fin constituting a fin-type N-type field effect transistor including a source region, a gate region, and a drain region,
A fixed potential line to which the source region of the first semiconductor fin is connected;
In a method for manufacturing a semiconductor device comprising:
A first step of preparing an intermediate;
A second step of leaving the conductive material;
With
The intermediate in the first step is
The first semiconductor fin standing from the substrate;
A third semiconductor fin;
With
In the region between the adjacent first and third semiconductor fins, a conductive material for the fixed potential line is provided up to a position higher than any of the top surfaces of the first and third semiconductor fins,
A protective material is provided on a region outside the region between the first and third semiconductor fins, and the second step includes
Etching the conductive material to a position lower than any of the top surfaces of the first and third semiconductor fins, removing the conductive material on the protective material, and a region between the first and third semiconductor fins In which the conductive material remains,
A method for manufacturing a semiconductor device.
The conductive material is
As the first distance d1 <the second distance d2,
A first conductive material spaced a first distance d1 from the first semiconductor fin;
A second conductive material spaced a second distance d2 from the first semiconductor fin;
With
The first conductive material is an etching barrier film having higher etching resistance than the second conductive material with respect to the etching gas of the second conductive material.
The method of manufacturing a semiconductor device according to claim 1.
The first conductive material is TiN or TaN,
The second conductive material is at least one metal selected from the group consisting of Co, W and Ru;
The etching gas is
CF 4 or
A mixed gas of oxygen and Cl 2 ;
The method of manufacturing a semiconductor device according to claim 2, comprising:
The etching gas is a mixed gas of oxygen and Cl 2 ,
The volume ratio of the molar concentration C of the mixed gas per unit volume (O 2 + Cl 2) ( mol / L) molarity of Cl 2 gas to the C (Cl 2) (mol / L) is the following inequality:
1% ≦ C (Cl 2 ) / C (O 2 + Cl 2 ) × 100 (%) ≦ 20%,
The method of manufacturing a semiconductor device according to claim 2, wherein:
The etching gas is a mixed gas of oxygen and Cl 2 ,
The volume ratio of the molar concentration C of the mixed gas per unit volume (O 2 + Cl 2) ( mol / L) molarity of Cl 2 gas to the C (Cl 2) (mol / L) is the following inequality:
9% ≦ C (Cl 2 ) / C (O 2 + Cl 2 ) × 100 (%) ≦ 11%
The method of manufacturing a semiconductor device according to claim 2, wherein:
A fixed potential line including a pair of semiconductor fins erected from a substrate and connected to a source region of the semiconductor fin up to a position higher than any of the top surfaces of the semiconductor fins in a region between adjacent semiconductor fins A first step of preparing an intermediate in which a conductive material is provided and a protective material is provided on a region outside the region between the semiconductor fins;
Etching the conductive material to a position lower than any of the top surfaces of the semiconductor fins to remove the conductive material on the protective material and to leave the conductive material in a region between the semiconductor fins. Two steps,
A method for manufacturing a semiconductor device, comprising:
A first fin group comprising a pair of semiconductor fins;
A second fin group spaced apart from the first fin group and comprising a pair of semiconductor fins;
With
The first fin group includes a first semiconductor fin constituting a fin-type P-type field effect transistor including a source region, a gate region, and a drain region,
The second fin group includes a second semiconductor fin constituting a fin-type N-type field effect transistor including a source region, a gate region, and a drain region,
A fixed potential line connected to a source region of the semiconductor fin, including a conductive material embedded in a region between the semiconductor fins of the first fin group to a position lower than any top surface of the semiconductor fin; ,
A semiconductor device comprising: