WO2019148793A1 - Low latency instruction scheduler containing automatic management function and method for filtering speculative access - Google Patents

Low latency instruction scheduler containing automatic management function and method for filtering speculative access Download PDF

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WO2019148793A1
WO2019148793A1 PCT/CN2018/099740 CN2018099740W WO2019148793A1 WO 2019148793 A1 WO2019148793 A1 WO 2019148793A1 CN 2018099740 W CN2018099740 W CN 2018099740W WO 2019148793 A1 WO2019148793 A1 WO 2019148793A1
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access
automatic management
guessing
instruction scheduler
address
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PCT/CN2018/099740
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French (fr)
Chinese (zh)
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洪振洲
李庭育
黄中柱
陈育鸣
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江苏华存电子科技有限公司
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Publication of WO2019148793A1 publication Critical patent/WO2019148793A1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802—Instruction prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system

Definitions

  • the present invention relates to an instruction scheduler.
  • One of the objects of the present invention is to provide a low latency instruction scheduler with automatic management functionality that is capable of filtering speculative repetitive access.
  • Another object of the present invention is to provide a filtering guess access method for a low-latency instruction scheduler, which effectively filters speculative repeated access.
  • a low-latency instruction scheduler having an automatic management function is connected to a microprocessor through a local memory bus, the low-delay instruction scheduler includes an automatic management module, and further includes a guessing access filter, wherein
  • the guessing access filter filters out speculative repetitive access from the microprocessor and sends it to the auto management module upon receiving a valid access from the microprocessor.
  • the guessing access filter records the address to be accessed next time, and if the next command data write address is the same as the last time, the guessing access The filter filters out the access; if the next command data write address is the same as the address to be accessed next time, the access is valid.
  • the method further includes an instruction memory and an instruction number register connected to the automatic management module.
  • the guessing access filter records the address to be accessed next time, if the next time The command data write address is the same as the last time, and the guessing access filter filters out the access; if the next command data write address is the same as the record to be accessed next time, the guess The sexual access filter sends the access to the automatic management module.
  • the invention has the beneficial effects that the invention compares each access by adding a guessing access filter, and if the content is not in accordance with expectations, the filtering discards the access, and if it meets the expectation, the instruction is sent. To the automatic management module, this ensures that the correct operation of the system is not affected by guessing access.
  • 1 is a structural state diagram of a low latency instruction scheduler of the present invention when receiving a speculative repeated access
  • FIG. 2 is a structural state diagram of a prior art low latency instruction scheduler receiving a speculative repetitive access.
  • a low-delay instruction scheduler with automatic management function is connected to a microprocessor through a local memory bus.
  • the low-delay instruction scheduler includes an automatic management module 1 and a guessing access filter 2.
  • the automatic management module 1 is an automatic pointer management module.
  • the guessing access filter 2 filters out the speculative repetitive access from the microprocessor and sends it to the automatic management module 1 upon receiving an effective access from the microprocessor, and the automatic management module 1 operates. Specifically, each time the command data is written, the guessing access filter 2 records the address to be accessed next time, and if the next command data write address is the same as the last time, the guessing access filter 2 It is determined to be a duplicate access and the access is filtered out. If the next command data write address is the same as the address to be accessed next time, indicating that the access is valid, the guess access filter 2 sends the access command to the automatic management module 1. This allows the instruction dispatcher connected to a particular local memory bus to function properly without being affected by guessing access.
  • the low latency instruction scheduler further includes an instruction memory and an instruction number register connected to the automatic management module 1.
  • FIG. 2 it is a structural diagram of a prior art low-delay instruction scheduler. There is no filtering function. When a speculative repeated access occurs, the instruction number register is incremented by one. In Figure 1, the guessing repeated access filtering is performed, and the instruction number register is unchanged.
  • the filtering guessing access method based on the low-latency instruction scheduler described above, each time the command data is written, the guessing access filter 2 records the address to be accessed next time, if the next command is The data write address is the same as the last time, and the guessing access filter 2 filters out the access; if the next command data write address is the same as the address to be accessed next time, the guessing access filter The device 2 sends the access to the automatic management module 1.

Abstract

Disclosed is a low latency instruction scheduler comprising an automatic management function, wherein a microprocessor is connected by means of a local memory bus; the low latency instruction scheduler comprises an automatic management module, and further comprises a speculative access filter, the speculative access filter filtering out speculative repeated access from the microprocessor and transmitting valid access received from the microprocessor to the automatic management module. Further disclosed is a method for filtering speculative access of a low latency instruction scheduler. The present invention is capable of effectively filtering the speculative repeated access.

Description

含自动管理功能的低延迟指令调度器及过滤猜测访问方法Low-delay instruction scheduler with automatic management function and filtering guess access method 技术领域Technical field
本发明涉及指令调度器。The present invention relates to an instruction scheduler.
背景技术Background technique
现有的芯片架构中，有自动指针管理模块的指令调度器若透过局部内存总线与某些特定微处理器相连时，会产生一些多余重复的存取，使自动管理模块产生误动作，进而导致系统芯片运作错误。如何有效防止这一问题的产生，是本领域技术人员需要解决的问题。In the existing chip architecture, if the instruction dispatcher of the automatic pointer management module is connected to some specific microprocessors through the local memory bus, some redundant and repeated accesses are generated, causing the automatic management module to malfunction. Caused the system chip to operate incorrectly. How to effectively prevent this problem from occurring is a problem that a person skilled in the art needs to solve.
发明内容Summary of the invention
本发明的目的之一在于提供具有自动管理功能的低延迟指令调度器，能够过滤猜测性重复存取。One of the objects of the present invention is to provide a low latency instruction scheduler with automatic management functionality that is capable of filtering speculative repetitive access.
本发明的目的之二在于提供低延迟指令调度器的过滤猜测访问方法，有效过滤猜测性重复存取。Another object of the present invention is to provide a filtering guess access method for a low-latency instruction scheduler, which effectively filters speculative repeated access.
实现上述目的的技术方案是：The technical solution to achieve the above objectives is:
一种具有自动管理功能的低延迟指令调度器，通过局部内存总线连接微处理器，所述低延迟指令调度器包括自动管理模块，还包括猜测性存取过滤器，其中，A low-latency instruction scheduler having an automatic management function, is connected to a microprocessor through a local memory bus, the low-delay instruction scheduler includes an automatic management module, and further includes a guessing access filter, wherein
所述猜测性存取过滤器过滤掉来自微处理器的猜测性重复存取，并在接收到来自微处理器的有效存取后将其发送给所述自动管理模块。The guessing access filter filters out speculative repetitive access from the microprocessor and sends it to the auto management module upon receiving a valid access from the microprocessor.
优选的，在每次写入命令数据时，所述猜测性存取过滤器记录下次即将被存取的地址，若下次的命令数据写入地址与上次相同，所述猜测性存取过滤器过滤掉该次存取；若下次的命令数据写入地址与记录的下次即将被存取的地址相同，表示该次存取有效。Preferably, each time the command data is written, the guessing access filter records the address to be accessed next time, and if the next command data write address is the same as the last time, the guessing access The filter filters out the access; if the next command data write address is the same as the address to be accessed next time, the access is valid.
优选的，还包括连接所述自动管理模块的指令内存和指令数寄存器。Preferably, the method further includes an instruction memory and an instruction number register connected to the automatic management module.
本发明之二的基于上述的低延迟指令调度器的过滤猜测访问方法，在每次写入 命令数据时，所述猜测性存取过滤器记录下次即将被存取的地址，若下次的命令数据写入地址与上次相同，所述猜测性存取过滤器过滤掉该次存取；若下次的命令数据写入地址与记录的下次即将被存取的地址相同，所述猜测性存取过滤器将该次存取发送给所述自动管理模块。According to the second aspect of the present invention, in the filtering guessing access method of the low-delay instruction scheduler described above, each time the command data is written, the guessing access filter records the address to be accessed next time, if the next time The command data write address is the same as the last time, and the guessing access filter filters out the access; if the next command data write address is the same as the record to be accessed next time, the guess The sexual access filter sends the access to the automatic management module.
本发明的有益效果是：本发明通过增设猜测性存取过滤器，对每次存取加以比对，如不符合预期，将过滤丢弃此次存取，如符合预期，则收下此指令送往自动管理模块，如此保证系统运作的正确性不受猜测性存取影响。The invention has the beneficial effects that the invention compares each access by adding a guessing access filter, and if the content is not in accordance with expectations, the filtering discards the access, and if it meets the expectation, the instruction is sent. To the automatic management module, this ensures that the correct operation of the system is not affected by guessing access.
附图说明DRAWINGS
图1是本发明的低延迟指令调度器接收猜测性重复存取时的结构状态图；1 is a structural state diagram of a low latency instruction scheduler of the present invention when receiving a speculative repeated access;
图2是现有技术的低延迟指令调度器接收猜测性重复存取时的结构状态图。2 is a structural state diagram of a prior art low latency instruction scheduler receiving a speculative repetitive access.
具体实施方式Detailed ways
下面将结合附图对本发明作进一步说明。The invention will now be further described with reference to the accompanying drawings.
请参阅图1，本发明之一的具有自动管理功能的低延迟指令调度器，通过局部内存总线连接微处理器，低延迟指令调度器包括自动管理模块1和猜测性存取过滤器2。自动管理模块1即是自动指针管理模块。Referring to FIG. 1, a low-delay instruction scheduler with automatic management function is connected to a microprocessor through a local memory bus. The low-delay instruction scheduler includes an automatic management module 1 and a guessing access filter 2. The automatic management module 1 is an automatic pointer management module.
猜测性存取过滤器2过滤掉来自微处理器的猜测性重复存取，并在接收到来自微处理器的有效存取后将其发送给自动管理模块1，自动管理模块1进行动作。具体地，在每次写入命令数据时，猜测性存取过滤器2记录下次即将被存取的地址，若下次的命令数据写入地址与上次相同，猜测性存取过滤器2判定为重复存取，并过滤掉该次存取。若下次的命令数据写入地址与记录的下次即将被存取的地址相同，表示该次存取有效，猜测性存取过滤器2将该次存取的指令发送给自动管理模块1。如此使连接于特定局部内存总线的指令调度器正常运作，不受猜测性存取影响。The guessing access filter 2 filters out the speculative repetitive access from the microprocessor and sends it to the automatic management module 1 upon receiving an effective access from the microprocessor, and the automatic management module 1 operates. Specifically, each time the command data is written, the guessing access filter 2 records the address to be accessed next time, and if the next command data write address is the same as the last time, the guessing access filter 2 It is determined to be a duplicate access and the access is filtered out. If the next command data write address is the same as the address to be accessed next time, indicating that the access is valid, the guess access filter 2 sends the access command to the automatic management module 1. This allows the instruction dispatcher connected to a particular local memory bus to function properly without being affected by guessing access.
另外，低延迟指令调度器还包括连接自动管理模块1的指令内存和指令数寄存器。图2中，为现有技术的低延迟指令调度器的结构图，没有过滤功能，在发生猜测性重复存取时，指令数寄存器加1。图1中，将猜测性重复存取过滤，指令数寄存器不变。In addition, the low latency instruction scheduler further includes an instruction memory and an instruction number register connected to the automatic management module 1. In FIG. 2, it is a structural diagram of a prior art low-delay instruction scheduler. There is no filtering function. When a speculative repeated access occurs, the instruction number register is incremented by one. In Figure 1, the guessing repeated access filtering is performed, and the instruction number register is unchanged.
本发明之二的基于上述的低延迟指令调度器的过滤猜测访问方法，在每次写入命令数据时，猜测性存取过滤器2记录下次即将被存取的地址，若下次的命令数据写入地址与上次相同，猜测性存取过滤器2过滤掉该次存取；若下次的命令数据写入地址与记录的下次即将被存取的地址相同，猜测性存取过滤器2将该次存取发送给自动管理模块1。According to the second aspect of the present invention, the filtering guessing access method based on the low-latency instruction scheduler described above, each time the command data is written, the guessing access filter 2 records the address to be accessed next time, if the next command is The data write address is the same as the last time, and the guessing access filter 2 filters out the access; if the next command data write address is the same as the address to be accessed next time, the guessing access filter The device 2 sends the access to the automatic management module 1.
以上实施例仅供说明本发明之用，而非对本发明的限制，有关技术领域的技术人员，在不脱离本发明的精神和范围的情况下，还可以作出各种变换或变型，因此所有等同的技术方案也应该属于本发明的范畴，应由各权利要求所限定。The above embodiments are merely illustrative of the invention, and are not intended to limit the invention, and various modifications and changes can be made without departing from the spirit and scope of the invention. The technical solution should also fall within the scope of the invention and should be defined by the claims.

Claims (4)

  1. 一种具有自动管理功能的低延迟指令调度器，通过局部内存总线连接微处理器，所述低延迟指令调度器包括自动管理模块，其特征在于，还包括猜测性存取过滤器，其中，A low-latency instruction scheduler having an automatic management function, is connected to a microprocessor through a local memory bus, and the low-delay instruction scheduler includes an automatic management module, and further includes a guessing access filter, wherein
    所述猜测性存取过滤器过滤掉来自微处理器的猜测性重复存取，并在接收到来自微处理器的有效存取后将其发送给所述自动管理模块。The guessing access filter filters out speculative repetitive access from the microprocessor and sends it to the auto management module upon receiving a valid access from the microprocessor.
  2. 根据权利要求1所述的具有自动管理功能的低延迟指令调度器，其特征在于，在每次写入命令数据时，所述猜测性存取过滤器记录下次即将被存取的地址，若下次的命令数据写入地址与上次相同，所述猜测性存取过滤器过滤掉该次存取；若下次的命令数据写入地址与记录的下次即将被存取的地址相同，表示该次存取有效。The low latency instruction scheduler with automatic management function according to claim 1, wherein each time the command data is written, the guessing access filter records an address to be accessed next time, if The next command data write address is the same as the last time, and the guessing access filter filters out the access; if the next command data write address is the same as the address to be accessed next time, Indicates that the access is valid.
  3. 根据权利要求1所述的具有自动管理功能的低延迟指令调度器，其特征在于，还包括连接所述自动管理模块的指令内存和指令数寄存器。The low latency instruction scheduler with automatic management function according to claim 1, further comprising an instruction memory and an instruction number register connected to said automatic management module.
  4. 一种基于权利要求1所述的低延迟指令调度器的过滤猜测访问方法，其特征在于，在每次写入命令数据时，所述猜测性存取过滤器记录下次即将被存取的地址，若下次的命令数据写入地址与上次相同，所述猜测性存取过滤器过滤掉该次存取；若下次的命令数据写入地址与记录的下次即将被存取的地址相同，所述猜测性存取过滤器将该次存取发送给所述自动管理模块。A filtering guess access method based on the low latency instruction scheduler of claim 1, wherein the guessing access filter records an address to be accessed next time each time the command data is written If the next command data write address is the same as the last time, the guessing access filter filters out the access; if the next command data is written to the address and the next address to be accessed is recorded. Similarly, the guessing access filter sends the access to the automatic management module.
PCT/CN2018/099740 2018-01-30 2018-08-09 Low latency instruction scheduler containing automatic management function and method for filtering speculative access WO2019148793A1 (en)

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