WO2019145807A1 - Dispositif à semi-conducteur et procédé de fabrication de dispositif à semi-conducteur - Google Patents

Dispositif à semi-conducteur et procédé de fabrication de dispositif à semi-conducteur Download PDF

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Publication number
WO2019145807A1
WO2019145807A1 PCT/IB2019/050205 IB2019050205W WO2019145807A1 WO 2019145807 A1 WO2019145807 A1 WO 2019145807A1 IB 2019050205 W IB2019050205 W IB 2019050205W WO 2019145807 A1 WO2019145807 A1 WO 2019145807A1
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Prior art keywords
insulator
oxide
conductor
transistor
film
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PCT/IB2019/050205
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English (en)
Japanese (ja)
Inventor
山崎舜平
藤井照幸
石塚章広
平石鈴之介
高橋俊輔
永松翔
八塚昇大
山出直人
栃林克明
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株式会社半導体エネルギー研究所
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Priority to JP2019567411A priority Critical patent/JPWO2019145807A1/ja
Priority to CN201980008975.XA priority patent/CN111615743A/zh
Publication of WO2019145807A1 publication Critical patent/WO2019145807A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/70—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components

Definitions

  • One embodiment of the present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.
  • one embodiment of the present invention relates to a semiconductor wafer, a module, and an electronic device.
  • a semiconductor device refers to any device that can function by utilizing semiconductor characteristics.
  • a semiconductor circuit such as a transistor, a semiconductor circuit, an arithmetic device, and a memory device are one embodiment of a semiconductor device.
  • Display devices liquid crystal display devices, light emitting display devices, etc.
  • projection devices lighting devices
  • electro-optical devices power storage devices
  • storage devices semiconductor circuits
  • imaging devices electronic devices, and the like may have semiconductor devices in some cases. .
  • one embodiment of the present invention is not limited to the above technical field.
  • One aspect of the invention disclosed in the present specification and the like relates to a product, a method, or a manufacturing method.
  • one aspect of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter).
  • Oxide semiconductor materials are widely known as semiconductor thin films applicable to transistors, but oxide semiconductors are attracting attention as other materials.
  • oxide semiconductor for example, not only single-component metal oxides such as indium oxide and zinc oxide but also multi-component metal oxides are known.
  • oxides of multi-element metals in particular, research on In-Ga-Zn oxide (hereinafter also referred to as IGZO) has been actively conducted.
  • Non-Patent Documents 1 to 3 a c-axis aligned crystalline (CAAC) structure and an nc (nanocrystalline) structure which are neither single crystal nor amorphous are found in an oxide semiconductor (see Non-Patent Documents 1 to 3) ).
  • Non-Patent Document 1 and Non-Patent Document 2 also disclose a technique for manufacturing a transistor using an oxide semiconductor having a CAAC structure.
  • non-patent documents 4 and 5 show that even oxide semiconductors that are less crystalline than the CAAC structure and the nc structure have minute crystals.
  • Non-Patent Document 6 a transistor using IGZO as an active layer has an extremely low off current (see Non-Patent Document 6), and LSIs and displays utilizing the characteristics have been reported (see Non-Patent Document 7 and Non-Patent Document 8) .
  • An object of one embodiment of the present invention is to provide a semiconductor device with a large on current. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device having high frequency characteristics. Alternatively, an object of one embodiment of the present invention is to provide a highly reliable semiconductor device. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device which can be miniaturized or highly integrated. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device having favorable electrical characteristics. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device with high productivity.
  • An object of one embodiment of the present invention is to provide a semiconductor device capable of holding data for a long time.
  • An object of one embodiment of the present invention is to provide a semiconductor device with high data writing speed.
  • An object of one embodiment of the present invention is to provide a semiconductor device with high design freedom.
  • An object of one embodiment of the present invention is to provide a semiconductor device capable of suppressing power consumption.
  • An object of one embodiment of the present invention is to provide a novel semiconductor device.
  • One embodiment of the present invention is a first insulator, a second insulator on the first insulator, a first conductor, a third insulator on the second insulator, A fourth insulator on the first conductor, the second insulator, and the third insulator, a fifth insulator on the fourth insulator, and a fifth insulator on the fifth insulator A second oxide on the first oxide, a second conductor and a third conductor on the second oxide, and a sixth on the second conductor Insulator, seventh insulator on third conductor, third oxide on second oxide, eighth insulator on third oxide, and eighth insulator A fourth conductor located on the body and overlapping the second oxide, a ninth insulator covering the eighth insulator and the fourth conductor, and a tenth insulator on the ninth insulator And the second insulator is in contact with the side surface of the first conductor, Insulator is in contact with the fourth insulator, a semiconductor device.
  • a first insulator, a second insulator over the first insulator, a first conductor, and a third insulator over the second insulator The fourth insulator on the first conductor, the second insulator, and the third insulator, the fifth insulator on the fourth insulator, and the fifth insulator A second oxide on the first oxide, a second conductor and a third conductor on the second oxide, and a second on the second conductor
  • the sixth insulator, the seventh insulator on the third conductor, the third oxide on the second oxide, the eighth insulator on the third oxide, and the eighth insulator A fourth conductor located on the insulator and overlapping the second oxide, a ninth insulator covering the eighth insulator and the fourth conductor, and a ninth insulator And a tenth insulator, the second insulator being in contact with the side surface of the first conductor Insulator 10, the second insulator, and a fourth insulator and in contact with
  • the second insulator and the tenth insulator be less likely to transmit one or both of oxygen and hydrogen than the fifth insulator, respectively.
  • the second insulator and the tenth insulator be less likely to transmit one or both of oxygen and hydrogen than the eighth insulator, respectively.
  • the second insulator and the tenth insulator each have silicon and nitrogen.
  • the resistivity of each of the second insulator and the tenth insulator is preferably 1 ⁇ 10 10 ⁇ cm or more and 1 ⁇ 10 15 ⁇ cm or less.
  • the fourth insulator and the ninth insulator are preferably oxides each containing one or both of aluminum and hafnium.
  • each of the fourth insulator and the ninth insulator is preferably aluminum oxide.
  • the first to third oxides preferably include In, an element M (M is Al, Ga, Y, or Sn), and Zn.
  • a semiconductor device with large on-state current can be provided.
  • a semiconductor device having high frequency characteristics can be provided.
  • a semiconductor device with high reliability can be provided.
  • a semiconductor device which can be miniaturized or highly integrated can be provided.
  • a semiconductor device having favorable electrical characteristics can be provided.
  • a semiconductor device with high productivity can be provided.
  • a semiconductor device capable of holding data for a long time can be provided.
  • a semiconductor device with high data writing speed can be provided.
  • a semiconductor device with a high degree of freedom in design can be provided.
  • a semiconductor device capable of suppressing power consumption can be provided.
  • a novel semiconductor device can be provided.
  • 7A and 7B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention.
  • 7A and 7B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention.
  • FIG. 18 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention.
  • 7A to 7C are a top view and a cross-sectional view illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 7A to 7C are a top view and a cross-sectional view illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 7A to 7C are a top view and a cross-sectional view illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 7A to 7C are a top view and a cross-sectional view illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 7A to 7C are a top view and a cross-sectional view illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 7A to 7C are a top view and a cross-sectional view illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 7A to 7C are a top view and a cross-sectional view illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 7A to 7C are a top view and a cross-sectional view illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 7A to 7C are a top view and a cross-sectional view illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 7A to 7C are a top view and a cross-sectional view illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 7A to 7C are a top view and a cross-sectional view illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 7A to 7C are a top view and a cross-sectional view illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 7A to 7C are a top view and a cross-sectional view illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 7A to 7C are a top view and a cross-sectional view illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 7A to 7C are a top view and a cross-sectional view illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 7A to 7C are a top view and a cross-sectional view illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 7A to 7C are a top view and a cross-sectional view illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • FIG. 18 is a cross-sectional view illustrating a structure of a memory device of one embodiment of the present invention.
  • FIG. 18 is a cross-sectional view illustrating a structure of a memory device of one embodiment of the present invention.
  • FIG. 18 is a cross-sectional view illustrating a structure of a memory device of one embodiment of the present invention.
  • FIG. 18 is a block diagram illustrating a configuration example of a memory device according to one embodiment of the present invention.
  • FIG. 18 is a circuit diagram illustrating a configuration example of a memory device according to one embodiment of the present invention.
  • FIG. 10 is a schematic view of a semiconductor device according to one embodiment of the present invention.
  • FIG. 10 is a schematic view of a memory device according to one embodiment of the present invention.
  • FIG. 7 illustrates an electronic device according to one embodiment of the present invention. The photograph which shows the cross section of the semiconductor device of an example.
  • the size, layer thicknesses, or areas may be exaggerated for clarity. Therefore, it is not necessarily limited to the scale.
  • the drawings schematically show ideal examples, and are not limited to the shapes or values shown in the drawings.
  • a layer, a resist mask, and the like may be unintentionally reduced by a process such as etching, but may not be reflected in the drawings for ease of understanding.
  • the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and repeated description may be omitted.
  • the hatch pattern may be the same and no reference numeral may be given.
  • the description of some components may be omitted particularly in a top view (also referred to as a “plan view”) or a perspective view.
  • the description of some hidden lines may be omitted.
  • the ordinal numbers given as the first, second and the like are used for convenience and do not indicate the order of steps or the order of layers. Therefore, for example, “first” can be appropriately replaced with “second” or “third” and the like.
  • the ordinal numbers described in this specification and the like may not match the ordinal numbers used to specify one embodiment of the present invention.
  • the present invention is not limited to a predetermined connection relationship, for example, the connection relationship shown in the figure or the sentence, and anything other than the connection relationship shown in the figure or the sentence is also disclosed in the figure or the sentence.
  • X and Y each denote an object (eg, a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, a layer, or the like).
  • the functions of the source and the drain may be switched when adopting transistors of different polarities or when the direction of current changes in circuit operation. Therefore, in the present specification and the like, the terms “source” and “drain” may be used interchangeably.
  • the channel width in the region where the channel is actually formed (hereinafter also referred to as “effective channel width”) and the channel width shown in the top view of the transistor ( Hereinafter, it may be different from “apparent channel width”).
  • the effective channel width may be larger than the apparent channel width, and the effect may not be negligible.
  • the ratio of the channel formation region formed on the side surface of the semiconductor may be large. In that case, the effective channel width is larger than the apparent channel width.
  • channel width may refer to an apparent channel width.
  • channel width may refer to an effective channel width. Note that the channel length, channel width, effective channel width, apparent channel width and the like can be determined by analyzing a cross-sectional TEM image or the like.
  • the impurity of a semiconductor means, for example, elements other than the main components of the semiconductor.
  • an element having a concentration of less than 0.1 atomic% can be said to be an impurity.
  • the inclusion of impurities may cause, for example, an increase in the DOS (Density of States) of the semiconductor, or a decrease in crystallinity.
  • the semiconductor is an oxide semiconductor
  • examples of the impurity that changes the characteristics of the semiconductor include a group 1 element, a group 2 element, a group 13 element, a group 14 element, a group 15 element, and an oxide semiconductor.
  • transition metals other than the main components thereof such as hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen and the like.
  • water may also function as an impurity.
  • oxygen vacancies may be formed, for example, by the addition of impurities.
  • the impurity that changes the characteristics of the semiconductor include oxygen, a group 1 element excluding hydrogen, a group 2 element, a group 13 element, and a group 15 element.
  • silicon oxynitride has a higher content of oxygen than nitrogen as its composition.
  • silicon nitride oxide has a nitrogen content higher than that of oxygen as its composition.
  • the term “insulator” can be reworded as an insulating film or an insulating layer. Further, the term “conductor” can be rephrased as a conductive film or a conductive layer. Further, the term “semiconductor” can be reworded as a semiconductor film or a semiconductor layer.
  • parallel means the state in which two straight lines are arrange
  • substantially parallel refers to a state in which two straight lines are arranged at an angle of ⁇ 30 degrees or more and 30 degrees or less.
  • vertical means a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, the case of 85 degrees or more and 95 degrees or less is also included.
  • substantially perpendicular refers to a state in which two straight lines are disposed at an angle of 60 degrees or more and 120 degrees or less.
  • a barrier film is a film having a function of suppressing permeation of impurities such as water and hydrogen and oxygen, and in the case where the barrier film has conductivity, a conductive barrier film and I sometimes call.
  • the metal oxide is a metal oxide in a broad sense.
  • Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductor or simply OS), and the like.
  • oxide semiconductors also referred to as oxide semiconductor or simply OS
  • the metal oxide may be referred to as an oxide semiconductor. That is, in the case of describing an OS FET or an OS transistor, it can be said to be a transistor having an oxide or an oxide semiconductor.
  • normally-off means that the current per 1 ⁇ m of the channel width flowing in the transistor is 1 ⁇ 10 ⁇ 20 at room temperature when no potential is applied to the gate or the ground potential is applied to the gate. A or less, 1 ⁇ 10 ⁇ 18 A or less at 85 ° C., or 1 ⁇ 10 ⁇ 16 A or less at 125 ° C.
  • Embodiment 1 Hereinafter, an example of a semiconductor device including the transistor 200 according to one embodiment of the present invention will be described.
  • 1A, 1B, and 1C are a top view and a cross-sectional view of a transistor 200 and a periphery of the transistor 200 according to one embodiment of the present invention.
  • FIG. 1A is a top view of a semiconductor device including the transistor 200.
  • FIG. 1B and 1C are cross-sectional views of the semiconductor device.
  • FIG. 1B is a cross-sectional view of a portion indicated by an alternate long and short dash line A1-A2 in FIG. 1A, and is also a cross-sectional view in the channel length direction of the transistor 200.
  • 1C is a cross-sectional view of a portion indicated by an alternate long and short dash line A3-A4 in FIG. 1A, and is also a cross-sectional view in the channel width direction of the transistor 200. Note that in the top view of FIG. 1A, some elements are omitted for clarity of the drawing.
  • the semiconductor device of one embodiment of the present invention includes an insulator 214, a transistor 200 disposed over the insulator 214, an insulator 280 disposed over the transistor 200, and an insulator 282 disposed over the insulator 280. And an insulator 281 disposed on the insulator 282.
  • the insulator 214, the insulator 280, the insulator 281, and the insulator 282 function as interlayer films.
  • the transistor 200 includes the conductor 240 (the conductor 240 a and the conductor 240 b) which is electrically connected to the transistor 200 and functions as a plug.
  • an insulator 241 (insulator 241 a and insulator 241 b) is provided in contact with the side surface of the conductor 240 functioning as a plug. Further, over the insulator 281 and the conductor 240, a conductor 246 (a conductor 246a and a conductor 246b) which is electrically connected to the conductor 240 and functions as a wiring is provided.
  • An insulator 241a is provided in contact with the inner wall of the opening of the insulator 273a, the oxide 230c, the insulator 250, the insulator 254, the insulator 274, the insulator 280, the insulator 282, and the insulator 281, and the side surface thereof.
  • the first conductor of the conductor 240a is provided in contact with the second conductor of the conductor 240a.
  • An insulator 241b is provided in contact with the inner wall of the opening of the insulator 273b, the oxide 230c, the insulator 250, the insulator 254, the insulator 274, the insulator 280, the insulator 282, and the insulator 281, and the side surface thereof.
  • the first conductor of the conductor 240b is provided in contact with the second conductor of the conductor 240b.
  • the height of the top surface of the conductor 240 and the height of the top surface of the insulator 281 can be approximately the same.
  • the transistor 200 illustrates a structure in which the first conductor of the conductor 240 and the second conductor of the conductor 240 are stacked, the present invention is not limited to this.
  • the conductor 240 may be provided as a single layer or a stacked structure of three or more layers. In the case where the structure has a stacked structure, ordinal numbers may be assigned in order of formation to be distinguished.
  • the transistor 200 includes a conductor 205 (a conductor 205 a and a conductor 205 b) on an insulator 214 and a side surface of the conductor 205, which are disposed on a substrate (not shown). And an insulator 215 in contact with part of the top surface of the insulator 214, an insulator 216 over the insulator 215, and an insulator 222 disposed over the insulator 216, over the insulator 215, and over the conductor 205.
  • the oxide 230c side surface, the insulator 250 side surface, and the insulator 254 side surface are substantially flush with each other in one and the other of the channel length directions of the transistor 200, as illustrated in FIGS. It is disposed on the insulator 222. Further, in one side in the channel width direction, the oxide 230 c side surface, the insulator 250 side surface, and the insulator 254 side surface are substantially flush and are disposed on the insulator 222.
  • the transistor 200 is disposed over the insulator 214 and the conductor 205 over the insulator 214, an insulator 222 over the insulator 215 and over the conductor 205, and over the insulator 222.
  • an insulator 250 disposed on the conductor 242b, a conductor 260 located on the insulator 250 and overlapping the oxide 230b, and an insulator 274 covering the insulator 250 and the conductor 260.
  • the insulator 215 is in contact with the side surface of the conductor 205
  • the insulator 274 is in contact with part of the top surface of the insulator 222.
  • the insulator 222, the insulator 254, and the insulator 274 preferably have a function of suppressing diffusion of hydrogen (eg, at least one of a hydrogen atom, a hydrogen molecule, and the like).
  • the insulator 222, the insulator 254, and the insulator 274 preferably have a function of suppressing diffusion of oxygen (eg, at least one of oxygen atom, oxygen molecule, and the like).
  • the insulator 222, the insulator 254, and the insulator 274 preferably each have lower permeability to one or both of oxygen and hydrogen than the insulator 224, respectively.
  • the insulator 222, the insulator 254, and the insulator 274 preferably each have lower permeability to one or both of oxygen and hydrogen than the insulator 250, respectively.
  • the insulator 222, the insulator 254, and the insulator 274 preferably each have lower permeability to one or both of oxygen and hydrogen than the insulator 280.
  • the oxide 230 is disposed on the oxide 230a disposed on the insulator 224, the oxide 230b disposed on the oxide 230a, and the oxide 230b, and at least a part of the oxide 230 is disposed. And an oxide 230c in contact with the top surface of 230b.
  • the transistor 200 a structure in which three layers of an oxide 230a, an oxide 230b, and an oxide 230c are stacked in a region where a channel is formed (hereinafter also referred to as a channel formation region) and in the vicinity thereof is shown.
  • the present invention is not limited to this.
  • a single layer of the oxide 230b, a two-layer structure of the oxide 230b and the oxide 230a, a two-layer structure of the oxide 230b and the oxide 230c, or a stacked structure of four or more layers may be provided.
  • the conductor 260 is illustrated as a stacked-layer structure of two layers, but the present invention is not limited to this.
  • the conductor 260 may have a single-layer structure or a stacked structure of three or more layers.
  • the transistor 200 uses a metal oxide (hereinafter, also referred to as an oxide semiconductor) which functions as an oxide semiconductor for the oxide 230 (the oxide 230a, the oxide 230b, and the oxide 230c) including a channel formation region. Is preferred.
  • a metal oxide hereinafter, also referred to as an oxide semiconductor
  • oxide semiconductor which functions as an oxide semiconductor for the oxide 230 (the oxide 230a, the oxide 230b, and the oxide 230c) including a channel formation region. Is preferred.
  • the transistor 200 in which an oxide semiconductor is used for a channel formation region has extremely low leak current (off current) in a non-conduction state; thus, a semiconductor device with low power consumption can be provided. Further, an oxide semiconductor can be formed by a sputtering method or the like, and thus can be used for the transistor 200 included in a highly integrated semiconductor device.
  • In-M-Zn oxide as the oxide 230 (the element M is aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium It is preferable to use a metal oxide such as one or more selected from neodymium, hafnium, tantalum, tungsten, or magnesium.
  • a metal oxide such as one or more selected from neodymium, hafnium, tantalum, tungsten, or magnesium.
  • aluminum, gallium, yttrium or tin may be used as the oxide 230.
  • an In-Ga oxide, an In-Zn oxide, a Ga-Zn oxide, and a Ga oxide may be used as the oxide 230.
  • the transistor including an oxide semiconductor when impurities and oxygen vacancies are present in a region of the oxide semiconductor in which a channel is formed, the electric characteristics are easily changed and reliability may be deteriorated.
  • oxygen vacancies when oxygen vacancies are included in the region in the oxide semiconductor in which a channel is formed, the transistor is likely to be normally on. Therefore, it is preferable that oxygen deficiency in the region where the channel is formed be reduced as much as possible.
  • oxygen may be supplied to the oxide 230 through the insulator 250 or the like to compensate for oxygen vacancies. Accordingly, it is possible to provide a transistor in which the variation in the electrical characteristics is suppressed, the stable electrical characteristics are provided, and the reliability is improved.
  • the conductor 260 functions as a first gate electrode of the transistor 200.
  • the conductor 242 (the conductor 242 a and the conductor 242 b) functions as a source electrode or a drain electrode of the transistor 200.
  • the oxide semiconductor layer 230 is included in the conductor 242 (the conductor 242 a and the conductor 242 b) which is provided on and in contact with the oxide 230 and functions as a source electrode or a drain electrode of the transistor 200.
  • a low-resistance region may be partially formed between the oxide 230 and the conductor 242 or in the vicinity of the surface of the oxide 230. It functions as a source region or drain region of 200.
  • an impurity such as hydrogen, nitrogen, or a metal element
  • the carrier density may increase.
  • a region which does not overlap with the conductor 242 a and the conductor 242 b in the oxide 230 includes a region functioning as a channel formation region of the transistor 200.
  • the region preferably has a lower carrier density than the low resistance region, and has a reduced V o H.
  • the insulator 254 is preferably in contact with the top surface of the insulator 250, the side surface of the conductor 260, and the top surface of the conductor 260.
  • the insulator 274 is preferably in contact with the top surface of the insulator 254, the side surface of the insulator 254, the side surface of the insulator 250, the side surface of the oxide 230c, and part of the top surface of the insulator 222.
  • the insulator 280 is separated from the conductor 260, the insulator 224, the insulator 250, and the oxide 230 by the insulator 254 and the insulator 274.
  • the transistor 200 With such a structure, entry of impurities such as hydrogen and water contained in the insulator 280 or impurities such as hydrogen from the outside of the transistor 200 into the transistor 200 can be suppressed; thus, the transistor 200 is favorable. It can provide electrical characteristics and reliability.
  • the insulators 273a and 273b have a function of suppressing permeation of impurities such as hydrogen and water and oxygen.
  • the insulator 273a is on the conductor 242a, and can prevent diffusion of impurities such as hydrogen and water and oxygen from above the conductor 242a.
  • the insulator 273 b is on the conductor 242 b and can prevent diffusion of oxygen from above the conductor 242 b.
  • As the insulators 273a and 273b for example, aluminum oxide, hafnium oxide, or silicon nitride can be used.
  • FIG. 3 is a cross-sectional view of a portion indicated by an alternate long and short dash line A7-A8 in FIG. 1A and is also a cross-sectional view in the channel width direction of the conductor 240b electrically connected to the transistor 200 and functioning as a plug. .
  • the insulator 241b is disposed on the side surface of the conductor 240b, diffusion of impurities such as hydrogen and water from the insulator 280 and oxygen to the conductor 240b is suppressed. Can. The same effect is obtained for the conductor 240a.
  • a side surface of the conductor 242b, a side surface of the oxide 230a, and a side surface of the oxide 230b are covered with the oxide 230c, the insulator 250, and the insulator 254, and the insulator 254 is covered with the insulator 274. It has become.
  • the top surface of the conductor 242b is covered with the oxide 230c, the insulator 250, and the insulator 254, and the insulator 254 is covered with the insulator 274. Since diffusion of impurities such as hydrogen and water from the upper surface direction of the body 242b can be suppressed, oxidation of the conductor 242b can be suppressed. The same effect is obtained for the conductor 242a.
  • the side surface of the oxide 230a and the side direction of the oxide 230b for example, impurities such as hydrogen and water from the insulator 280 can be suppressed from diffusing into the oxide 230a and the oxide 230b. .
  • the height of the bottom surface of the conductor 260 in the region where the oxide 230a and the oxide 230b and the conductor 260 do not overlap with each other is oxide It is preferable to arrange
  • the conductor 260 functioning as a gate electrode covers the side surface and the top surface of the oxide 230 b in the channel formation region with the oxide 230 c and the insulator 250 interposed therebetween. It is easy to act on the entire oxide 230 b in the formation region. Thus, the on-state current of the transistor 200 can be increased and the frequency characteristics can be improved.
  • a semiconductor device having a transistor with a large on current can be provided.
  • a semiconductor device having a transistor with high frequency characteristics can be provided.
  • a semiconductor device can be provided which has stable electrical characteristics and suppressed reliability while suppressing fluctuations in the electrical characteristics.
  • a semiconductor device having a transistor with low off current can be provided.
  • the conductor 205 is disposed to overlap with the oxide 230 a, the oxide 230 b, and the conductor 260. In addition, it is preferable to arrange so as to overlap with the entire oxide 230 a, the entire oxide 230 b, and the entire conductor 260.
  • the conductor 260 may function as a first gate (also referred to as a top gate) electrode.
  • the conductor 205 may function as a second gate (also referred to as a bottom gate) electrode.
  • the Vth of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260 without interlocking.
  • Vth of the transistor 200 can be larger than 0 V and off current can be reduced. Therefore, when a negative potential is applied to the conductor 205, the drain current when the potential applied to the conductor 260 is 0 V can be smaller than when no potential is applied.
  • the conductor 205 may be larger than a size of a region which does not overlap with the conductor 242 a and the conductor 242 b of the oxide 230 as illustrated in FIG.
  • the conductor 205 preferably extends also in a region outside the end portion of the oxide 230 which intersects the channel width direction. That is, it is preferable that the conductor 205 and the conductor 260 overlap with each other through an insulator outside the side surface of the oxide 230 in the channel width direction.
  • local charging referred to as charge up
  • the conductor 205 may overlap with at least the oxide 230 located between the conductor 242 a and the conductor 242 b.
  • the channel formation region is electrically driven by the electric field of the conductor 260 having a function as a first gate electrode and the electric field of the conductor 205 having a function as a second gate electrode. It can be surrounded.
  • a structure of a transistor which electrically surrounds a channel formation region by an electric field of the first gate electrode and the second gate electrode is referred to as a surrounded channel (S-channel) structure.
  • the conductor 205a is preferably a conductor that suppresses permeation of impurities such as water or hydrogen and oxygen.
  • impurities such as water or hydrogen and oxygen.
  • titanium, titanium nitride, tantalum or tantalum nitride can be used.
  • the conductor 205 b is preferably formed using a conductive material containing tungsten, copper, or aluminum as a main component.
  • the conductor 205 is illustrated as having two layers, it may have a multilayer structure of three or more layers.
  • the oxide semiconductor, the insulator or the conductor located under the oxide semiconductor, and the insulator or the conductor located over the oxide semiconductor are different films without being exposed to the air. It is preferable to deposit a species continuously because a substantially high-purity intrinsic oxide semiconductor film can be deposited, in which the concentration of impurities (in particular, hydrogen and water) is reduced.
  • the insulator 222, the insulating film to be the insulator 224, and the oxide 230a are provided over the insulator 216, the insulator 215, and the conductor 205 using a deposition apparatus having six treatment chambers.
  • An oxide film, an oxide film to be the oxide 230 b, a conductive film to be the conductor 242, and an insulating film to be the insulator 273 may be successively formed in this order.
  • the insulator 215, the insulator 274, and the insulator 281 preferably function as a barrier insulating film which suppresses impurities such as water or hydrogen from entering the transistor 200 from the substrate side or from above. Therefore, the insulator 215, the insulator 274, and the insulator 281 each include a hydrogen atom, a hydrogen molecule, a water molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (N 2 O, NO, NO 2 or the like), a copper atom, or the like. It is preferable to use an insulating material having a function of suppressing the diffusion of impurities (the above-mentioned impurities are difficult to transmit). Alternatively, it is preferable to use an insulating material having a function of suppressing diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, and the like) (the above-described oxygen is difficult to permeate).
  • oxygen for example, at least one of oxygen atom
  • silicon nitride or the like is preferably used as the insulator 215, the insulator 274, and the insulator 281. Accordingly, diffusion of an impurity such as water or hydrogen from the substrate side to the transistor 200 side with respect to the insulator 215 can be suppressed. Alternatively, oxygen contained in the insulator 224 or the like can be suppressed from diffusing to the substrate side more than the insulator 215. Further, diffusion of an impurity such as water or hydrogen from the insulator 280 and / or the conductor 246 or the like which is higher than the insulator 274 can be suppressed.
  • the resistivity of the insulator 215, the insulator 274, and the insulator 281 is preferably a 1 ⁇ 10 15 ⁇ cm or less 1 ⁇ 10 10 ⁇ cm or more.
  • an insulator 215 is in contact with a side surface of the conductor 205.
  • an insulator 222 is disposed in contact with the top surface of the conductor 205.
  • the bottom surface of the conductor 205 is disposed in contact with the top surface of the insulator 214. That is, the conductor 205 is covered with an insulator which suppresses the permeation of impurities such as water or hydrogen and oxygen.
  • impurities such as water or hydrogen and oxygen can be prevented from being absorbed by the conductor 205, and excess oxygen can be efficiently added to the oxide 230.
  • diffusion of impurities such as water or hydrogen in the conductor 205 can be suppressed.
  • the insulator 214 may have a stacked structure.
  • a stacked structure of an aluminum oxide film and a silicon nitride film is preferably used for the insulator 214.
  • the aluminum oxide film can supply oxygen below the insulator 214. Further, diffusion of impurities such as hydrogen and water which are diffused from the substrate side to the transistor 200 side can be suppressed by the silicon nitride film.
  • the insulator 216 and the insulator 280 preferably have a lower dielectric constant than the insulator 214.
  • a material having a low dielectric constant as an interlayer film, parasitic capacitance generated between wirings can be reduced.
  • silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, or A silicon oxide or the like having a void may be used as appropriate.
  • the insulator 222 and the insulator 224 have a function as a gate insulator.
  • silicon oxide, silicon oxynitride, or the like may be used as appropriate.
  • the insulator 224 in contact with the oxide 230 preferably releases oxygen by heating.
  • oxygen released by heating may be referred to as excess oxygen.
  • the insulator 224 silicon oxide, silicon oxynitride, or the like may be used as appropriate.
  • an oxide material from which part of oxygen is released by heating is preferably used as the insulator 224.
  • the oxide from which oxygen is released by heating means that the amount of released oxygen in terms of molecular oxygen is 1.0 ⁇ 10 18 molecules / cm 3 or more, preferably 1 or more, in Thermal Desorption Spectroscopy (TDS) analysis. It is an oxide film having a molecular weight of not less than 0 ⁇ 10 19 molecules / cm 3 , more preferably not less than 2.0 ⁇ 10 19 molecules / cm 3 , or not less than 3.0 ⁇ 10 20 molecules / cm 3 .
  • the surface temperature of the film at the time of TDS analysis is preferably in the range of 100 ° C. to 700 ° C., or 100 ° C. to 400 ° C.
  • the insulator 222 preferably functions as a barrier insulating film which suppresses impurities such as water or hydrogen from entering the transistor 200 from the substrate side.
  • the insulator 222 preferably has lower hydrogen permeability than the insulator 224.
  • the insulator 222 preferably has a function of suppressing the diffusion of oxygen (eg, at least one of oxygen atom, oxygen molecule, and the like) (the oxygen is difficult to transmit).
  • the insulator 222 preferably has lower oxygen permeability than the insulator 224. Since the insulator 222 has a function of suppressing diffusion of oxygen and impurities, oxygen contained in the oxide 230 can be suppressed from diffusing to the insulator 220 side, which is preferable.
  • the conductor 205 can be inhibited from reacting with the insulator 224 and oxygen in the oxide 230.
  • the insulator 222 may be an insulator including an oxide of one or both of aluminum and hafnium which are insulating materials.
  • an insulator containing one or both oxides of aluminum and hafnium it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like.
  • the insulator 222 suppresses the release of oxygen from the oxide 230 and the entry of impurities such as hydrogen from the peripheral portion of the transistor 200 to the oxide 230. Act as a layer.
  • aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators.
  • these insulators may be nitrided.
  • silicon oxide, silicon oxynitride, or silicon nitride may be stacked over the above insulator.
  • the insulator 222 is made of, for example, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO 3 ) or (Ba, Sr) TiO 3 (BST).
  • An insulator containing a so-called high-k material may be used in a single layer or a stack. As the miniaturization and higher integration of transistors progress, problems such as leakage current may occur due to thinning of the gate insulator. By using a high-k material for the insulator functioning as a gate insulator, it is possible to reduce the gate potential at the time of transistor operation while maintaining the physical thickness.
  • the insulator 222 and the insulator 224 may have a stacked structure of two or more layers.
  • the invention is not limited to the laminated structure made of the same material, but may be a laminated structure made of different materials.
  • the oxide 230 includes an oxide 230a, an oxide 230b over the oxide 230a, and an oxide 230c over the oxide 230b.
  • the oxide 230a under the oxide 230b, diffusion of impurities from the structure formed below the oxide 230a to the oxide 230b can be suppressed.
  • the oxide 230c over the oxide 230b, diffusion of impurities from the structure formed above the oxide 230c to the oxide 230b can be suppressed.
  • the oxide 230 preferably has a stacked-layer structure of oxides having different atomic ratios of metal atoms.
  • the atomic ratio of the element M in the constituent elements is larger than the atomic ratio of the element M in the constituent elements of the metal oxide used for the oxide 230b.
  • the atomic ratio of the element M to In is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 230b.
  • the atomic ratio of In to the element M is preferably larger than the atomic ratio of In to the element M in the metal oxide used for the oxide 230a.
  • the oxide 230c a metal oxide which can be used for the oxide 230a or the oxide 230b can be used.
  • the oxide 230 b preferably has crystallinity.
  • a CAAC-OS c-axis aligned crystalline oxide semiconductor
  • An oxide having crystallinity such as CAAC-OS has a dense structure with high crystallinity, with few impurities and defects (such as oxygen deficiency). Accordingly, extraction of oxygen from the oxide 230 b by the source electrode or the drain electrode can be suppressed. Thus, even when heat treatment is performed, extraction of oxygen from the oxide 230 b can be reduced, so that the transistor 200 is stable against a high temperature (so-called thermal budget) in the manufacturing process.
  • the energy at the lower end of the conduction band of the oxide 230a and the oxide 230c be higher than the energy at the lower end of the conduction band of the oxide 230b.
  • the electron affinity of the oxide 230a and the oxide 230c be smaller than the electron affinity of the oxide 230b.
  • the energy level at the lower end of the conduction band changes gently.
  • the energy level at the bottom of the conduction band at the junction of the oxide 230a, the oxide 230b, and the oxide 230c can be said to be continuously changed or connected continuously.
  • the density of defect states in the mixed layer formed at the interface between the oxide 230 a and the oxide 230 b and at the interface between the oxide 230 b and the oxide 230 c may be lowered.
  • the oxide 230c has a stacked structure
  • In: Ga: Zn 4: 2: 3 [atom And a stacked structure of gallium oxide and the like.
  • the main route of the carrier is the oxide 230b.
  • the oxide 230 a and the oxide 230 c described above the density of defect states in the interface between the oxide 230 a and the oxide 230 b and the interface between the oxide 230 b and the oxide 230 c can be reduced. Therefore, the influence of interface scattering on carrier conduction is reduced, and the transistor 200 can obtain high on current and high frequency characteristics.
  • the constituent element of the oxide 230c is on the insulator 250 side.
  • the oxide 230c has a stacked structure and an oxide which does not contain In is positioned above the stacked structure, it is possible to suppress In which can diffuse to the insulator 250 side. Since the insulator 250 functions as a gate insulator, when In is diffused, the characteristics of the transistor become defective. Therefore, by forming the oxide layer 230c in a stacked structure, a highly reliable semiconductor device can be provided.
  • a metal oxide which functions as an oxide semiconductor is preferably used.
  • a metal oxide to be a channel formation region one having a band gap of 2 eV or more, preferably 2.5 eV or more is preferably used.
  • a metal oxide with a large band gap the off-state current of the transistor can be reduced.
  • a semiconductor device with low power consumption can be provided.
  • a conductor 242 (a conductor 242 a and a conductor 242 b) functioning as a source electrode and a drain electrode is provided over the oxide 230 b.
  • the thickness of the conductor 242 may be, for example, 1 nm to 50 nm, preferably 2 nm to 25 nm.
  • the conductor 242 aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, It is preferable to use a metal element selected from lanthanum or an alloy containing the above-described metal element as a component, or an alloy in which the above-described metal element is combined.
  • tantalum nitride, titanium nitride, tungsten, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. are used. Is preferred.
  • tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel are difficult to oxidize. It is preferable because it is a conductive material or a material which maintains conductivity even by absorbing oxygen.
  • the insulator 250 functions as a gate insulator.
  • the insulator 250 is preferably placed in contact with the top surface of the oxide 230c.
  • silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, silicon oxide having holes are used. be able to. In particular, silicon oxide and silicon oxynitride are preferable because they are stable to heat.
  • the insulator 250 is preferably formed using an insulator from which oxygen is released by heating.
  • an insulator from which oxygen is released by heating in contact with the top surface of the oxide 230c as the insulator 250, oxygen can be effectively supplied to the channel formation region in the oxide 230b.
  • the concentration of impurities such as water or hydrogen in the insulator 250 is preferably reduced.
  • the thickness of the insulator 250 is preferably 1 nm or more and 20 nm or less.
  • the oxide 252 may be provided between the insulator 250 and the conductor 260.
  • the oxide 252 preferably suppresses oxygen diffusion from the insulator 250 to the conductor 260.
  • the oxide which suppresses the diffusion of oxygen By providing the oxide which suppresses the diffusion of oxygen, the diffusion of oxygen from the insulator 250 to the conductor 260 is suppressed. That is, a reduction in the amount of oxygen supplied to the oxide 230 can be suppressed.
  • oxidation of the conductor 260 by oxygen in the insulator 250 can be suppressed.
  • the oxide 252 may have a function as part of a gate insulator. Therefore, in the case of using silicon oxide, silicon oxynitride, or the like for the insulator 250, the oxide 252 is preferably an oxide which is a high-k material having a high dielectric constant.
  • the gate insulator has a stacked structure of the insulator 250 and the oxide 252, a stacked structure which is stable to heat and has a high relative dielectric constant can be obtained. Therefore, while maintaining the physical thickness of the gate insulator, it is possible to reduce the gate potential applied at the time of transistor operation. In addition, it is possible to reduce the equivalent oxide thickness (EOT) of the insulator that functions as a gate insulator.
  • EOT equivalent oxide thickness
  • a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, or magnesium it can.
  • aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like, which is an insulator containing one or both oxides of aluminum and hafnium is preferably used.
  • the conductor 260 is illustrated as a two-layer structure in FIG. 1, but may be a single-layer structure or a stacked structure of three or more layers.
  • the conductor 260a has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N 2 O, NO, NO 2 etc.), copper atoms, etc. It is preferable to use a material. Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (eg, at least one of oxygen atom, oxygen molecule, and the like).
  • the conductor 260a has a function of suppressing the diffusion of oxygen
  • the oxygen contained in the insulator 250 can suppress the oxidation of the conductor 260b and the decrease in conductivity.
  • a conductive material having a function of suppressing oxygen diffusion for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like is preferably used.
  • the conductor 260 b is preferably formed using a conductive material containing tungsten, copper, or aluminum as a main component.
  • a conductor with high conductivity is preferably used.
  • a conductive material containing tungsten, copper, or aluminum as a main component can be used.
  • the conductor 260b may have a stacked structure, for example, a stacked structure of titanium and titanium nitride and the above conductive material.
  • the insulator 280 may be, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, or silicon oxide with holes. It is preferable to have. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, a material such as silicon oxide, silicon oxynitride, or silicon oxide having holes is preferable because a region containing oxygen which is released by heating can be easily formed.
  • the concentration of impurities such as water or hydrogen in the insulator 280 be reduced.
  • the top surface of the insulator 280 may be planarized.
  • the insulator 282 preferably functions as a barrier insulating film which suppresses impurities such as water or hydrogen from entering the insulator 280 from above.
  • an insulator that can be used for the insulator 254 or the like may be used.
  • Conductor 240a and conductor 240b are arranged.
  • the conductor 240 a and the conductor 240 b are provided opposite to each other with the conductor 260 interposed therebetween. Note that the heights of the top surfaces of the conductor 240 a and the conductor 240 b may be on the same plane as the top surface of the insulator 281.
  • An insulator 241 a is provided in contact with the inner wall of the opening of the insulator 281, the insulator 282, the insulator 280, the insulator 274, the insulator 254, the insulator 250, the oxide 230 c, and the insulator 273.
  • a first conductor of the conductor 240a is formed in contact with the side surface.
  • the conductor 242a is positioned at least at a part of the bottom of the opening, and the conductor 240a is in contact with the conductor 242a.
  • an insulator 241 b is provided in contact with the inner wall of the insulator 281, the insulator 282, the insulator 280, the insulator 274, the insulator 254, the insulator 250, the oxide 230 c, and the insulator 273.
  • the first conductor of the conductor 240 b is formed in contact with
  • the conductor 242 b is positioned at least at a part of the bottom of the opening, and the conductor 240 b is in contact with the conductor 242 b.
  • the conductor 240a and the conductor 240 b may have a stacked structure.
  • the conductor in contact with the insulator 281, the insulator 282, the insulator 280, the insulator 274, the insulator 254, the insulator 250, the insulator 250, the oxide 230c, and the insulator 273 is used.
  • a conductive material having a function of suppressing permeation of an impurity such as water or hydrogen is preferably used.
  • tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide or the like is preferably used.
  • a conductive material having a function of suppressing permeation of impurities such as water or hydrogen may be used in a single layer or a stack.
  • oxygen added to the insulator 280 can be prevented from being absorbed by the conductor 240 a and the conductor 240 b.
  • impurities such as water or hydrogen can be suppressed from being mixed into the oxide 230 through the conductor 240 a and the conductor 240 b from the upper layer of the insulator 281.
  • an insulator such as aluminum oxide, silicon nitride, or silicon nitride oxide may be used, for example. Since the insulator 241a and the insulator 241b are provided in contact with the insulator 254 and the insulator 274, an impurity such as water or hydrogen is mixed in the oxide 230 from the insulator 280 or the like through the conductor 240a and the conductor 240b. Can be suppressed. Further, oxygen contained in the insulator 280 can be prevented from being absorbed by the conductor 240 a and the conductor 240 b.
  • a conductor 246 (a conductor 246a and a conductor 246b) functioning as a wiring may be provided in contact with the top surface of the conductor 240a and the top surface of the conductor 240b.
  • the conductor 246 preferably uses a conductive material whose main component is tungsten, copper, or aluminum.
  • the conductor may have a stacked structure, for example, a stack of titanium and titanium nitride and the above conductive material. Note that the conductor may be formed so as to be embedded in an opening provided in an insulator.
  • 2A, 2B, and 2C are a top view and a cross-sectional view of the transistor 201 and a periphery of the transistor 201 according to one embodiment of the present invention.
  • FIG. 2A is a top view of a semiconductor device including the transistor 201.
  • FIG. 2B and 2C are cross-sectional views of the semiconductor device.
  • FIG. 2B is a cross-sectional view of a portion indicated by an alternate long and short dash line A1-A2 in FIG. 2A and also a cross-sectional view of the transistor 201 in the channel length direction.
  • 2C is a cross-sectional view of a portion indicated by an alternate long and short dash line A3-A4 in FIG. 2A, and is also a cross-sectional view in the channel width direction of the transistor 201. Note that in the top view of FIG. 2A, some elements are omitted for clarity of the drawing.
  • the transistor 201 includes an insulator 214 disposed on a substrate (not shown), a conductor 205 (conductor 205 a and conductor 205 b) on the insulator 214, and a conductor An insulator 215 in contact with the side surface of the insulator 205 and part of the top surface of the insulator 214, an insulator 216 over the insulator 215, and an insulator disposed over the insulator 216, the insulator 215, and the conductor 205 Body 222, an insulator 224 disposed on the insulator 222, an oxide 230a disposed on the insulator 224, an oxide 230b disposed on the oxide 230a, and an upper surface of the oxide 230b
  • the conductor 242a and the conductor 242b in contact with each other, part of the top surface of the insulator 222, the side surface of the insulator 224, the side surface of the oxide 230a, the
  • an insulator similar to the insulator 273a and the insulator 273b can be used as the insulator 273, an insulator similar to the insulator 273a and the insulator 273b can be used. For example, aluminum oxide, hafnium oxide or silicon nitride can be used.
  • the other structures and effects can be referred to the structure of the semiconductor device including the transistor 200.
  • an insulator substrate, a semiconductor substrate, or a conductor substrate may be used, for example.
  • the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as a yttria stabilized zirconia substrate), and a resin substrate.
  • the semiconductor substrate may be, for example, a semiconductor substrate of silicon, germanium or the like, or a compound semiconductor substrate of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide or gallium oxide.
  • the conductive substrate there is a semiconductor substrate having an insulator region inside the aforementioned semiconductor substrate, for example, an SOI (Silicon On Insulator) substrate.
  • the conductive substrate there are a graphite substrate, a metal substrate, an alloy substrate, a conductive resin substrate and the like.
  • a substrate provided with a conductor or a semiconductor on an insulator substrate a substrate provided with a conductor or an insulator on a semiconductor substrate, a substrate provided with a semiconductor or an insulator on the conductor substrate, and the like.
  • those provided with elements on these substrates may be used.
  • the elements provided on the substrate include a capacitor, a resistor, a switch, a light-emitting element, a memory element, and the like.
  • the insulator includes, for example, an insulating oxide, a nitride, an oxynitride, a nitride oxide, a metal oxide, a metal oxynitride, a metal nitride oxide, and the like.
  • the thinning of the gate insulator may cause problems such as leakage current.
  • a high-k material for the insulator that functions as a gate insulator voltage reduction during transistor operation can be achieved while maintaining the physical thickness.
  • a material having a low relative dielectric constant for an insulator functioning as an interlayer film parasitic capacitance generated between wirings can be reduced. Therefore, depending on the function of the insulator, the material may be selected.
  • oxides of gallium oxide, hafnium oxide, zirconium oxide, aluminum and hafnium, oxynitrides of aluminum and hafnium, oxides of silicon and hafnium, silicon and hafnium can be used. And the like, or nitrides having silicon and hafnium.
  • the transistor including an oxide semiconductor is surrounded by an insulator (such as the insulator 214, the insulator 222, the insulator 254, and the insulator 274) having a function of suppressing permeation of impurities such as hydrogen and oxygen.
  • an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium
  • An insulator containing lanthanum, neodymium, hafnium, or tantalum may be used in a single layer or a stack.
  • metal oxides such as tantalum oxide, metal nitrides such as aluminum nitride, aluminum titanium nitride, titanium nitride, silicon nitride oxide, or silicon nitride can be used.
  • the insulator functioning as a gate insulator is preferably an insulator having a region containing oxygen which is desorbed by heating.
  • the structure in which silicon oxide or silicon oxynitride having a region containing oxygen released by heating is in contact with the oxide 230, oxygen vacancies in the oxide 230 can be compensated.
  • ⁇ Conductor> aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, iridium, strontium, lanthanum It is preferable to use a metal element selected from the like, or an alloy containing the above-described metal element as a component, or an alloy in which the above-described metal element is combined.
  • tantalum nitride, titanium nitride, tungsten, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. are used. Is preferred.
  • tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel are difficult to oxidize.
  • a semiconductor with high electrical conductivity typically a polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.
  • a plurality of conductive layers formed of the above materials may be stacked.
  • a stacked structure in which a material containing a metal element described above and a conductive material containing oxygen are combined may be used.
  • a stacked structure in which the material containing the metal element described above and the conductive material containing nitrogen are combined may be used.
  • a stacked structure in which the above-described material containing a metal element, the conductive material containing oxygen, and the conductive material containing nitrogen are combined may be used.
  • a stacked structure in which a material containing the above-described metal element and a conductive material containing oxygen are combined is used for a conductor functioning as a gate electrode.
  • a conductive material containing oxygen may be provided on the channel formation region side.
  • a conductor functioning as a gate electrode a conductive material containing oxygen and a metal element contained in a metal oxide in which a channel is formed is preferably used.
  • a conductive material containing the above-described metal element and nitrogen may be used.
  • a conductive material containing nitrogen such as titanium nitride or tantalum nitride may be used.
  • indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, silicon were added.
  • Indium tin oxide may be used.
  • indium gallium zinc oxide containing nitrogen may be used.
  • Metal oxide As the oxide 230, a metal oxide which functions as an oxide semiconductor is preferably used. Hereinafter, metal oxides applicable to the oxide 230 according to the present invention will be described.
  • the metal oxide preferably contains at least indium or zinc. In particular, it is preferable to contain indium and zinc. In addition to them, aluminum, gallium, yttrium or tin is preferably contained. In addition, one or more selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium may be included.
  • the metal oxide is an In-M-Zn oxide having indium, an element M and zinc.
  • the element M is aluminum, gallium, yttrium, tin, or the like.
  • Other elements applicable to the element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium and the like.
  • the element M a plurality of the aforementioned elements may be combined in some cases.
  • metal oxides having nitrogen may also be collectively referred to as metal oxides.
  • a metal oxide having nitrogen may be referred to as metal oxynitride.
  • Oxide semiconductors can be divided into single crystal oxide semiconductors and other non-single crystal oxide semiconductors.
  • the non-single crystal oxide semiconductor for example, CAAC-OS, polycrystalline oxide semiconductor, nc-OS (nanocrystalline oxide semiconductor), pseudo amorphous oxide semiconductor (a-like OS: a-like OS: a-like OS), And amorphous oxide semiconductors.
  • the CAAC-OS has c-axis orientation, and a plurality of nanocrystals are connected in the a-b plane direction to form a strained crystal structure.
  • distortion refers to a portion where the orientation of the lattice arrangement changes between the region in which the lattice arrangement is aligned and the region in which another lattice arrangement is aligned in the region where the plurality of nanocrystals are connected.
  • the nanocrystals are based on hexagons, but may not be regular hexagons and may be non-hexagonal. Moreover, distortion may have a lattice arrangement such as pentagon and heptagon.
  • the CAAC-OS it is difficult to confirm clear crystal grain boundaries (also referred to as grain boundaries) even in the vicinity of strain. That is, it is understood that the formation of crystal grain boundaries is suppressed by the distortion of the lattice arrangement. This is because the CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms is not dense in the a-b plane direction, or that the bonding distance between atoms is changed due to metal element substitution. It is for.
  • a CAAC-OS is a layered crystal in which a layer containing indium and oxygen (hereinafter referred to as In layer) and a layer containing element M, zinc and oxygen (hereinafter referred to as (M, Zn) layer) are stacked. It tends to have a structure (also referred to as a layered structure).
  • In layer a layer containing indium and oxygen
  • M, Zn zinc and oxygen
  • indium and the element M can be substituted with each other, and when the element M in the (M, Zn) layer is replaced with indium, it can also be expressed as a (In, M, Zn) layer.
  • indium in the In layer is substituted with the element M, it can also be represented as an (In, M) layer.
  • CAAC-OS is a highly crystalline metal oxide. On the other hand, it is difficult to confirm clear crystal grain boundaries in CAAC-OS, so it can be said that the decrease in electron mobility due to crystal grain boundaries does not easily occur. In addition, since the crystallinity of metal oxides may be lowered due to the incorporation of impurities or the formation of defects, CAAC-OS is a metal oxide with few impurities or defects (also referred to as oxygen vacancy (V 2 O )). It can be said that it is a thing. Therefore, the metal oxide having a CAAC-OS has stable physical properties. Therefore, a metal oxide having a CAAC-OS is resistant to heat and has high reliability.
  • the nc-OS has periodicity in atomic arrangement in a minute region (eg, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm).
  • nc-OS has no regularity in crystal orientation among different nanocrystals. Therefore, no orientation can be seen in the entire film. Therefore, the nc-OS may not be distinguished from the a-like OS or the amorphous oxide semiconductor depending on the analysis method.
  • IGZO indium-gallium-zinc oxide
  • IGZO indium-gallium-zinc oxide
  • IGZO may have a stable structure by using the above-mentioned nanocrystals.
  • IGZO tends to be difficult to grow crystals in the atmosphere, so smaller crystals (for example, the above-mentioned nanocrystals) than large crystals (here, crystals of a few mm or crystals of a few cm) But may be structurally stable.
  • the a-like OS is a metal oxide having a structure between nc-OS and an amorphous oxide semiconductor.
  • the a-like OS has a wrinkle or low density region. That is, a-like OS has lower crystallinity than nc-OS and CAAC-OS.
  • Oxide semiconductors have various structures, and each has different characteristics.
  • the oxide semiconductor of one embodiment of the present invention may have two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS.
  • the concentration of alkali metal or alkaline earth metal in the metal oxide obtained by SIMS is 1 ⁇ 10 18 atoms. / cm 3 or less, preferably below 2 ⁇ 10 16 atoms / cm 3 .
  • hydrogen contained in the metal oxide reacts with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy.
  • oxygen vacancies When hydrogen enters the oxygen vacancies, electrons that are carriers may be generated.
  • a part of hydrogen may be bonded to oxygen which is bonded to a metal atom to generate an electron which is a carrier. Therefore, a transistor using a metal oxide which contains hydrogen is likely to be normally on.
  • the hydrogen concentration obtained by SIMS is less than 1 ⁇ 10 20 atoms / cm 3 , preferably less than 1 ⁇ 10 19 atoms / cm 3 , more preferably 5 ⁇ 10 18 atoms / cm. It is less than 3 and more preferably less than 1 ⁇ 10 18 atoms / cm 3 .
  • a thin film with high crystallinity As the metal oxide used for the semiconductor of the transistor, the stability or the reliability of the transistor can be improved.
  • the thin film include thin films of single crystal metal oxides or thin films of polycrystalline metal oxides.
  • a high temperature or laser heating step is required to form a thin film of monocrystalline metal oxide or a thin film of polycrystalline metal oxide on a substrate. Therefore, the cost of the manufacturing process increases, and the throughput also decreases.
  • Non-Patent Document 1 and Non-Patent Document 2 In-Ga-Zn oxide having a CAAC structure (referred to as CAAC-IGZO) was discovered in 2009.
  • CAAC-IGZO has c-axis orientation, can not be clearly identified in grain boundaries, and can be formed on a substrate at a low temperature.
  • a transistor using CAAC-IGZO is reported to have excellent electrical characteristics and reliability.
  • nc-IGZO In-Ga-Zn oxide having an nc structure was discovered (see Non-Patent Document 3).
  • nc-IGZO has periodicity in atomic arrangement in a minute area (for example, an area of 1 nm or more and 3 nm or less) and regularity in crystal orientation is not observed between different areas. There is.
  • Non-Patent Document 4 and Non-Patent Document 5 show the transition of the average crystal size by the irradiation of an electron beam to the thin films of the above-described CAAC-IGZO, nc-IGZO, and IGZO with low crystallinity.
  • a low crystalline IGZO thin film crystalline IGZO of about 1 nm has been observed even before electron beam irradiation. Therefore, it is reported here that in IGZO, the presence of a completely amorphous structure could not be confirmed.
  • the thin film of CAAC-IGZO and the thin film of nc-IGZO have high stability to electron beam irradiation as compared with the thin film of IGZO having low crystallinity. Therefore, it is preferable to use a thin film of CAAC-IGZO or a thin film of nc-IGZO as a semiconductor of the transistor.
  • a transistor using a metal oxide has extremely low leakage current in the non-conductive state, specifically, the off-state current per ⁇ m channel width of the transistor is on the order of yA / ⁇ m (10 -24 A / ⁇ m).
  • Non-Patent Document 6 For example, a low power consumption CPU or the like to which a characteristic that a leak current of a transistor using a metal oxide is low is disclosed (see Non-Patent Document 7).
  • Non-Patent Document 8 application to a display device of a transistor using a characteristic that the leakage current of a transistor using a metal oxide is low has been reported (see Non-Patent Document 8).
  • the displayed image is switched several tens of times per second.
  • the number of times of switching images per second is called a refresh rate.
  • the refresh rate may be referred to as a drive frequency.
  • Such fast screen switching which is difficult for human eyes to perceive, is considered as the cause of eye fatigue. Therefore, it has been proposed to reduce the number of image rewrites by reducing the refresh rate of the display device.
  • power consumption of the display device can be reduced by driving with a lower refresh rate.
  • Such a driving method is called idling stop (IDS) driving.
  • IDS idling stop
  • the discovery of the CAAC structure and the nc structure contributes to the improvement of the electrical characteristics and reliability of a transistor using a metal oxide having a CAAC structure or an nc structure, as well as to the cost reduction and the throughput improvement of the manufacturing process.
  • researches on application of the transistor to a display device and an LSI using the characteristic that the leakage current of the transistor is low have been advanced.
  • FIG. 4 to FIG. 15 shows a top view.
  • (B) in each drawing is a cross-sectional view corresponding to a portion indicated by an alternate long and short dash line A1-A2 illustrated in (A), and is also a cross-sectional view in the channel length direction of the transistor 200.
  • (C) in each drawing is a cross-sectional view corresponding to a portion indicated by dashed dotted line A3-A4 in (A), and is also a cross-sectional view in the channel width direction of the transistor 200.
  • one part element is abbreviate
  • a substrate (not shown) is prepared, and an insulator 214 is formed over the substrate.
  • the film formation of the insulator 214 can be performed by sputtering, chemical vapor deposition (CVD), molecular beam epitaxy (MBE), pulsed laser deposition (PLD), or ALD. This can be performed using an atomic layer deposition (Atomic Layer Deposition) method or the like.
  • the CVD method can be classified into a plasma enhanced CVD (PECVD) method using plasma, a thermal CVD (TCVD: thermal CVD) method using heat, a photo CVD method using light, etc. . Furthermore, it can be divided into metal CVD (MCVD: Metal CVD) and metal organic CVD (MOCVD: Metal Organic CVD) depending on the source gas used.
  • PECVD plasma enhanced CVD
  • TCVD thermal CVD
  • MCVD Metal CVD
  • MOCVD Metal Organic CVD
  • the plasma CVD method provides high quality films at relatively low temperatures.
  • the thermal CVD method is a film formation method capable of reducing plasma damage to an object to be processed because plasma is not used.
  • a wiring, an electrode, an element (such as a transistor or a capacitor), or the like included in a semiconductor device may be charged up by receiving charge from plasma. At this time, wirings, electrodes, elements, and the like included in the semiconductor device may be broken by the stored charge.
  • a thermal CVD method which does not use plasma, such plasma damage does not occur, so that the yield of the semiconductor device can be increased.
  • the thermal CVD method since plasma damage does not occur during film formation, a film with few defects can be obtained.
  • the ALD method can deposit atoms one by one by utilizing the self-controllability which is the property of atoms, it is possible to form an extremely thin film, to form a film with a high aspect ratio, pin Film formation with few defects such as holes is possible, film formation with excellent coverage is possible, and film formation at low temperature is possible.
  • the ALD method also includes a film formation method PEALD (Plasma Enhanced ALD) method using plasma. The use of plasma may make film formation at a lower temperature possible, which may be preferable.
  • Some precursors used in the ALD method include impurities such as carbon.
  • the film provided by the ALD method may contain a large amount of impurities such as carbon, as compared with a film provided by another film formation method.
  • quantification of impurities can be performed using X-ray photoelectron spectroscopy (XPS).
  • the CVD method and the ALD method are film forming methods in which a film is formed by a reaction on the surface of an object to be processed unlike a film forming method in which particles released from a target or the like are deposited. Therefore, the film forming method is less susceptible to the shape of the object to be processed, and has good step coverage.
  • the ALD method since the ALD method has excellent step coverage and uniformity of thickness, it is suitable for coating the surface of an opening with a high aspect ratio.
  • the ALD method may be preferably used in combination with another deposition method such as a CVD method having a high deposition rate.
  • the CVD method and the ALD method can control the composition of the obtained film by the flow rate ratio of the source gas.
  • a film having any composition can be formed depending on the flow rate ratio of the source gas.
  • a film whose composition is continuously changed can be formed by changing the flow ratio of the source gas while forming the film.
  • aluminum oxide is deposited as the insulator 214 by a sputtering method.
  • diffusion of impurities such as water and hydrogen and oxygen into a layer higher than the insulator 214 can be suppressed.
  • a conductive film to be the conductor 205 is formed over the insulator 214.
  • the conductive film to be the conductor 205 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the conductive film to be the conductor 205 can be a multilayer film.
  • tantalum nitride is formed as a conductive film to be the conductor 205a by a sputtering method.
  • tungsten is deposited by a sputtering method as a conductive film to be the conductor 205b.
  • a conductive film to be the conductor 205 is processed using a lithography method to form the conductor 205.
  • the resist is exposed through a mask.
  • the exposed area is removed or left using a developer to form a resist mask.
  • the conductor, the semiconductor, the insulator, or the like can be processed into a desired shape by etching through the resist mask.
  • the resist mask may be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like.
  • a liquid immersion technique may be used in which a liquid (for example, water) is filled and exposed between the substrate and the projection lens.
  • an electron beam or an ion beam may be used instead of the light described above.
  • the mask is unnecessary. Note that for the removal of the resist mask, dry etching such as ashing can be performed, wet etching can be performed, wet etching can be performed after the dry etching, or dry etching can be performed after the wet etching.
  • a hard mask made of an insulator or a conductor may be used instead of the resist mask.
  • an insulating film or a conductive film serving as a hard mask material is formed over the conductive film to be the conductor 205, a resist mask is formed over the conductive film, and the hard mask material is etched.
  • a hard mask can be formed. The etching of the conductive film to be the conductor 205 may be performed after the resist mask is removed, or may be performed with the resist mask left. In the latter case, the resist mask may disappear during etching. The hard mask may be removed by etching after the conductive film to be the conductor 205 is etched. On the other hand, when the material of the hard mask does not affect the post-process or can be used in the post-process, it is not necessary to remove the hard mask.
  • a capacitively coupled plasma (CCP) etching apparatus having a parallel plate electrode can be used as a dry etching apparatus.
  • the capacitive coupling type plasma etching apparatus having a parallel plate type electrode may be configured to apply a high frequency power to one of the parallel plate type electrodes.
  • a plurality of different high frequency power supplies may be applied to one of the parallel plate electrodes.
  • a high frequency power supply of the same frequency may be applied to each of the parallel plate electrodes.
  • high-frequency power supplies having different frequencies may be applied to the parallel plate electrodes.
  • a dry etching apparatus having a high density plasma source can be used.
  • an inductively coupled plasma (ICP) etching apparatus can be used as a dry etching apparatus having a high density plasma source.
  • the insulating film 215A is formed over the conductor 214 and the insulator 214.
  • the insulating film 215A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • silicon nitride is formed as the insulating film 215A by a CVD method.
  • the insulating film 216A is formed.
  • the insulating film 216A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • silicon oxide is formed as the insulating film 216A by a CVD method (see FIG. 4).
  • the thickness of the insulating film 216A is preferably greater than or equal to the thickness of the conductor 205.
  • the thickness of the conductor 205 is 1, the thickness of the insulating film 216A is 1 or more and 3 or less.
  • the film thickness of the conductor 205 is 150 nm, and the film thickness of the insulating film 216A is 350 nm.
  • CMP chemical Mechanical Polishing
  • the insulator 222 is formed over the insulator 216, the insulator 215, and the conductor 205.
  • an insulator containing an oxide of one or both of aluminum and hafnium may be deposited. Note that aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used as the insulator containing one or both of the oxides of aluminum and hafnium.
  • An insulator containing one or both oxides of aluminum and hafnium has barrier properties against oxygen, hydrogen, and water.
  • the insulator 222 has a barrier property to hydrogen and water, diffusion of hydrogen and water contained in a structure provided in the periphery of the transistor 200 to the inside of the transistor 200 through the insulator 222 is suppressed. , And the formation of oxygen vacancies in the oxide 230 can be suppressed.
  • the insulator 222 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the insulating film 224A is formed over the insulator 222.
  • the insulating film 224A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • heat treatment is preferably performed.
  • the heat treatment may be performed at 250 ° C. to 650 ° C., preferably 300 ° C. to 500 ° C., more preferably 320 ° C. to 450 ° C.
  • the heat treatment is performed in a nitrogen or inert gas atmosphere or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. Further, the heat treatment may be performed under reduced pressure.
  • the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in order to compensate for desorbed oxygen. Good.
  • the heat treatment after the formation of the insulating film 224A, treatment in a nitrogen atmosphere at a temperature of 400 ° C. for one hour is performed, and further treatment in an oxygen atmosphere at a temperature of 400 ° C. I do.
  • impurities such as hydrogen and water contained in the insulating film 224A can be removed and the like.
  • the heat treatment can also be performed at each timing after the insulator 220 is formed and after the insulator 222 is formed.
  • one or more methods selected from an ion implantation method, an ion doping method, a plasma treatment, and a plasma immersion ion implantation method in order to form a region containing oxygen which is desorbed by heating in the insulating film 224A.
  • Oxygen may be supplied to the insulating film 224A using At this time, oxygen can be supplied to the insulating film 224A with good control by using an ion implantation method in which ionized source gas is separated by mass and added, which is preferable.
  • plasma treatment including oxygen may be performed under reduced pressure.
  • plasma treatment containing oxygen for example, it is preferable to use a device having a power supply for generating high density plasma using microwaves.
  • the substrate side may have a power supply for applying an RF (Radio Frequency).
  • RF Radio Frequency
  • high density plasma high density oxygen radicals can be generated, and by applying RF to the substrate side, oxygen radicals generated by high density plasma can be efficiently introduced into the insulating film 224A. it can.
  • plasma treatment including oxygen may be performed to compensate for the released oxygen.
  • impurities such as hydrogen and water contained in the insulating film 224A can be removed by appropriately selecting the conditions of the plasma treatment. In that case, the heat treatment may not be performed.
  • an oxide film 230A to be the oxide 230a and an oxide film 230B to be the oxide 230b are sequentially formed over the insulating film 224A (see FIG. 6).
  • the oxide film is preferably formed continuously without being exposed to the air environment. By forming the film without opening to the atmosphere, impurities or moisture from the air environment can be prevented from adhering to the oxide film 230A and the oxide film 230B, and the vicinity of the interface between the oxide film 230A and the oxide film 230B can be It can be kept clean.
  • the oxide film 230A and the oxide film 230B can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • Sputtering is preferably used to form the oxide film 230A and the oxide film 230B, and oxygen or a mixed gas of oxygen and a rare gas is used as a sputtering gas.
  • oxygen in the oxide film to be formed can be increased, and the crystallinity of the oxide film can be improved. Further, by performing film formation while heating the substrate, crystallinity of the oxide film can be improved.
  • the above metal oxide target can be used.
  • a metal oxide film is formed by a sputtering apparatus, a film having an atomic ratio different from that of the target is formed.
  • the [Zn] of the film may be smaller than the [Zn] of the target.
  • an oxygen gas or a rare gas which is used as a sputtering gas is a gas which is highly purified to a dew point of ⁇ 60 ° C. or less, preferably ⁇ 100 ° C. or less.
  • the oxide film 230A and the oxide film 230B are formed by sputtering, it is preferable to remove moisture in the film formation chamber of the sputtering apparatus as much as possible.
  • the proportion of oxygen contained in the sputtering gas of the oxide film 230A may be 70% or more, preferably 80% or more, and more preferably 100%.
  • the oxide film 230B may be formed into the above-described CAAC-OS film when the ratio of oxygen contained in the sputtering gas is 10% or more, preferably 30% or more. it can.
  • each oxide film may be formed in accordance with the characteristics to be obtained for the oxide 230 by appropriately selecting deposition conditions and an atomic ratio.
  • heat treatment may be performed.
  • the above-described heat treatment conditions can be used.
  • impurities such as hydrogen and water in the oxide film 230A and the oxide film 230B can be removed.
  • treatment for one hour at a temperature of 400 ° C. in an oxygen atmosphere is performed.
  • the conductive film 242A is formed over the oxide film 230B.
  • the conductive film 242A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the insulating film 273A is formed over the conductive film 242A.
  • the insulating film 273A is preferably formed using an insulating film containing an oxide of one or both of aluminum and hafnium.
  • aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used as the insulating film containing one or both of the oxides of aluminum and hafnium.
  • An insulating film containing an oxide of one or both of aluminum and hafnium has a barrier property to oxygen, hydrogen, and water.
  • the insulating film 273A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the conductive film 243A is formed over the insulating film 273A (see FIG. 6).
  • the conductive film 243A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the above-described insulator 222, the insulating film 224A, the oxide film 230A, the oxide film 230B, the conductive film 242A, the insulating film 273A, and the conductive film 243A may be successively formed in this order.
  • the insulator 222 By sequentially forming the insulator 222, the insulating film 224A, the oxide film 230A, the oxide film 230B, the conductive film 242A, the insulating film 273A, and the conductive film 243A sequentially without exposure to the air, surface adsorption water, etc. It is possible to prevent the surface of the oxide film and the conductive film from being adsorbed. Therefore, each interface of the laminated film is not exposed to the air, so the impurity concentration is reduced. In addition, entry of impurities such as water or hydrogen into the insulating film, the oxide film, the conductive film, and the like can be suppressed.
  • the insulator 222 In order to successively form the insulator 222, the insulating film 224A, the oxide film 230A, the oxide film 230B, the conductive film 242A, the insulating film 273A, and the conductive film 243A sequentially without exposing them to the air, different film types are continuously formed. It is preferred to use a multi-chamber apparatus having a plurality of possible treatment chambers.
  • the conductive film 243A is processed by a lithography method to form a conductor layer 243B (see FIG. 7).
  • the cross-sectional shape preferably has a tapered shape.
  • the taper angle is 30 degrees or more and less than 75 degrees, preferably 30 degrees or more and less than 70 degrees with respect to a plane parallel to the bottom surface of the substrate. By having such a taper angle, the coverage of the film in the subsequent film forming process is improved. Further, it is preferable to use a dry etching method for the processing.
  • the processing by the dry etching method is suitable for micro processing and processing of the above-mentioned taper shape.
  • a resist 244 is formed by lithography (see FIG. 8).
  • the conductor layer 243B, the insulating film 273A, and the conductive film 242A are etched using the resist 244 as an etching mask to form the conductor 243a, the conductor 243b, the insulator layer 273B, and the conductor layer 242B, and then , And remove the resist 244 (see FIG. 9).
  • the oxide film 230A and the oxide film 230B are etched using the exposed portion of the surface of the conductor 243a, the conductor 243b, and the insulator layer 273B as an etching mask to form an oxide 230a and an oxide 230b.
  • the insulator layer 273B in the region sandwiched between the conductor 243a and the conductor 243b on the conductor layer 242B is etched to form an insulator 273a and an insulator 273b (FIG. 10). reference).
  • the etching rates of the oxide film 230A and the oxide film 230B are faster than the etching rates of the conductor 243a, the conductor 243b, and the conductor layer 242B.
  • the etching rate of the conductor 243a, the conductor 243b, and the conductor layer 242B is 1, the etching rate of the oxide film 230A and the oxide film 230B is 3 or more and 50 or less, preferably 5 or more and 30 or less.
  • the exposed portions of the surfaces of the conductor 243a, the conductor 243b, and the conductor layer 242B are etched to form the conductor 242a and the conductor 242b.
  • the insulating film 224A is etched until the surface of the insulator 222 is exposed to form the insulator 224 (see FIG. 11).
  • the oxide 230 a, the oxide 230 b, the conductor 242 a, and the conductor 242 b are formed so that at least part thereof overlaps with the conductor 205.
  • the side surfaces of the oxide 230 a, the side surfaces of the oxide 230 b, the side surfaces of the conductor 242 a, and the side surfaces of the conductor 242 b are preferably substantially perpendicular to the top surface of the insulator 222.
  • the area can be reduced and the density can be increased by being substantially perpendicular.
  • the top surface of the insulator 222 may have a low angle with each of the side surface of the oxide 230a, the side surface of the oxide 230b, the side surface of the conductor 242a, and the side surface of the conductor 242b.
  • an angle formed by the top surface of the insulator 222 with the side surface of the oxide 230a, the side surface of the oxide 230b, the side surface of the conductor 242a, and the side surface of the conductor 242b is preferably 60 ° to 70 °.
  • oxide film and the conductive film may be processed by a lithography method.
  • dry etching or wet etching can be used for the processing. Machining by dry etching is suitable for micromachining.
  • an impurity due to an etching gas or the like may be attached or diffused to the surface or the inside of the oxide 230a, the oxide 230b, or the like.
  • the impurities include, for example, fluorine or chlorine.
  • the cleaning method may be wet cleaning using a cleaning solution or the like, plasma treatment using plasma, cleaning by heat treatment, or the like, and the above cleaning may be performed in combination as appropriate.
  • cleaning treatment may be performed using an aqueous solution prepared by diluting oxalic acid, phosphoric acid, hydrofluoric acid, or the like with carbonated water or pure water.
  • ultrasonic cleaning may be performed using pure water or carbonated water.
  • heat treatment may be performed.
  • the heat treatment may be performed under reduced pressure and the oxide film 230C which is to be the oxide 230c may be formed successively without being exposed to the air.
  • the temperature of the heat treatment is preferably 100 ° C. or more and 400 ° C. or less. In this embodiment, the temperature of heat treatment is set to 200.degree.
  • the oxide film 230C can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the oxide film 230C may be formed by a film formation method similar to that of the oxide film 230A or the oxide film 230B in accordance with the characteristics desired for the oxide film to be the oxide 230c.
  • the oxide film 230C may be stacked.
  • Film formation may be performed using a target having a numerical ratio].
  • the proportion of oxygen contained in the sputtering gas of the oxide film 230C may be 70% or more, preferably 80% or more, and more preferably 100%.
  • heat treatment may be performed.
  • the heat treatment may be performed under reduced pressure and the insulating film 250A which is to be the insulator 250 continuously may be formed without exposure to the air.
  • the water and hydrogen adsorbed on the surface of the oxide film 230C and the like are removed, and the water concentration and the hydrogen concentration in the oxide 230a, the oxide 230b and the oxide film 230C are further reduced.
  • the temperature of the heat treatment is preferably 100 ° C. or more and 400 ° C. or less.
  • the insulating film 250A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • silicon oxynitride is preferably deposited by a CVD method.
  • the film formation temperature at the time of forming the insulating film 250A is preferably 350 ° C. or more and less than 450 ° C., particularly about 400 ° C.
  • an oxide film to be the oxide 252 may be formed over the insulating film 250A.
  • the oxide film to be the oxide 252 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • an oxide film to be the oxide 252 an oxide film similar to the oxide film 230C can be used.
  • a conductive film to be the conductor 260a and a conductive film to be the conductor 260b are formed.
  • the conductive film to be the conductor 260a and the conductive film to be the conductor 260b can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • titanium nitride is formed by a sputtering method as a conductive film to be the conductor 260a
  • tungsten is formed by a sputtering method as a conductive film to be the conductor 260b.
  • an insulating film 250A, an oxide film to be the oxide 252, a conductive film to be the conductor 260a, and a conductive film to be the conductor 260b for example, oxide films 230C
  • the insulating film 250A, the oxide film to be the oxide 252, the conductive film to be the conductor 260a, and the conductive film to be the conductor 260b may be successively formed using a multi-chamber apparatus.
  • the conductive film to be the conductor 260a, the conductive film to be the conductor 260b, and the oxide film to be the oxide 252 are sequentially processed by a lithography method to obtain the conductor 260a, the conductor 260b, and the oxide 252.
  • the conductor 260a and the conductor 260b are processed by using a dry etching method, and the oxide 252 is processed by using a wet etching method (see FIG. 12).
  • the side surfaces of the conductor 260a, the side surfaces of the conductor 260b, and the side surfaces of the oxide 252 preferably substantially match.
  • heat treatment may be performed.
  • the heat treatment is preferably performed at 300 ° C. to 450 ° C. in a nitrogen atmosphere.
  • treatment is performed at a temperature of 400 ° C. for one hour in a nitrogen atmosphere.
  • an insulating film to be the insulator 254 is formed to cover the insulating film 250A, the oxide 252, and the conductor 260.
  • heat treatment may be performed before formation of the insulating film to be the insulator 254.
  • the heat treatment may be performed under reduced pressure and an insulating film to be the insulator 254 may be formed without being exposed to the air.
  • the insulating film to be the insulator 254 is preferably an insulator having a function of suppressing permeation of impurities such as water and hydrogen and oxygen.
  • the insulating film to be the insulator 254 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • aluminum oxide is deposited by sputtering after heat treatment is performed under reduced pressure using a sputtering apparatus.
  • the insulating film to be the insulator 254, the insulating film 250A, and the oxide film 230C are sequentially processed by a lithography method to form the insulator 254, the insulator 250, and the oxide 230c. It is preferable that the side surface of the insulator 254, the side surface of the insulator 250, and the side surface of the oxide 230c substantially coincide with each other on one side and the other side of the transistor 200 in the channel length direction of the transistor 200. Further, in one channel width direction of the transistor 200, the side surface of the insulator 254, the side surface of the insulator 250, and the side surface of the oxide 230c preferably substantially coincide with each other and are preferably provided over the insulator 222.
  • the insulator 274 is formed over the insulator 222 and the insulator 254.
  • the insulator 274 is preferably an insulator having a function of suppressing permeation of impurities such as water and hydrogen and oxygen.
  • silicon nitride, silicon nitride oxide, aluminum oxide, or the like can be used.
  • the insulator 274 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment mode, silicon nitride is deposited by a CVD method (see FIG. 13).
  • an insulating film to be the insulator 280 is formed over the insulator 274.
  • the insulating film to be the insulator 280 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • CMP treatment is performed on the insulating film to be the insulator 280 to form the insulator 280 having a flat top surface.
  • heat treatment may be performed.
  • treatment is performed at a temperature of 400 ° C. for one hour in a nitrogen atmosphere.
  • the heat treatment the water concentration and the hydrogen concentration in the insulator 250 and the insulator 280 can be reduced.
  • an insulating film to be the insulator 282 may be formed over the insulator 280.
  • the insulating film to be the insulator 282 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • an insulating film to be the insulator 282 for example, an aluminum oxide film is preferably formed by a sputtering method. By depositing aluminum oxide by sputtering, diffusion of hydrogen contained in the insulator 280 can be suppressed in some cases to the insulator 250 and the oxide 230 in some cases.
  • heat treatment may be performed.
  • treatment is performed at a temperature of 400 ° C. for one hour in a nitrogen atmosphere.
  • oxygen added as a film of the insulator 282 can be injected into the insulator 250 and the insulator 280.
  • an insulating film to be the insulator 281 may be formed over the insulator 282.
  • the insulating film to be the insulator 281 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • silicon nitride is deposited by a CVD method (see FIG. 14).
  • an opening which reaches the conductor 242a is formed in the insulator 273a, the oxide 230c, the insulator 250, the insulator 254, the insulator 274, the insulator 280, the insulator 282, and the insulator 281.
  • an opening reaching the conductor 242 b is formed in the insulator 273 b, the oxide 230 c, the insulator 250, the insulator 254, the insulator 274, the insulator 280, the insulator 282, and the insulator 281.
  • the formation of the opening may be performed using a lithography method.
  • an insulating film to be the insulator 241 is formed, and the insulating film is anisotropically etched to form the insulator 241.
  • the insulating film to be the insulator 241 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • an insulating film having a function of suppressing permeation of oxygen is preferably used.
  • aluminum oxide is preferably deposited by an ALD method.
  • a silicon nitride film may be used.
  • anisotropic etching may be performed by, for example, dry etching.
  • the conductive film to be the conductor 240 a and the conductor 240 b preferably has a stacked structure including a conductor having a function of suppressing permeation of impurities such as water and hydrogen.
  • a stack of tantalum nitride, titanium nitride, or the like, tungsten, molybdenum, copper, or the like can be used.
  • the conductive film to be the conductor 240 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • CMP treatment is performed to remove part of the conductive film to be the conductor 240 a and the conductor 240 b and expose the insulator 281.
  • the conductor 240a and the conductor 240b having a flat top surface can be formed (see FIG. 15). Note that part of the insulator 281 may be removed by the CMP treatment.
  • the conductive film to be the conductor 246 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • a conductive film to be the conductor 246 is processed by a lithography method to form a conductor 246a in contact with the top surface of the conductor 240a and a conductor 246b in contact with the top surface of the conductor 240b (see FIG. 1).
  • a semiconductor device including the transistor 200 illustrated in FIG. 1 can be manufactured.
  • the transistor 200 can be manufactured by using the method for manufacturing a semiconductor device described in this embodiment.
  • FIG. 16 to FIG. 16 is a cross-sectional view corresponding to a portion indicated by an alternate long and short dash line A1-A2 in (A), and is also a cross-sectional view in the channel length direction of the transistor 200.
  • (C) in each drawing is a cross-sectional view corresponding to a portion indicated by dashed dotted line A3-A4 in (A), and is also a cross-sectional view in the channel width direction of the transistor 200.
  • one part element is abbreviate
  • the method for manufacturing the semiconductor device including the transistor 201 illustrated in FIG. 2 is the same as the method for manufacturing the semiconductor device including the transistor 200 illustrated in FIG. 1 up to the formation of the conductive film 242A (see FIG. 16).
  • the conductive film 242A, the oxide film 230B, the oxide film 230A, and the insulating film 224A are sequentially processed by a lithography method to form a conductor layer 242B, an oxide 230b, an oxide 230a, and an insulator 224 (see FIG. 17).
  • an insulating film 273A is formed to cover the insulator 222, the conductor layer 242B, the oxide 230b, the oxide 230a, and the insulator 224.
  • the insulating film 273A is preferably formed using an insulator having a function of suppressing permeation of impurities such as water and hydrogen and oxygen.
  • the insulating film 273A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, silicon nitride is deposited (see FIG. 18).
  • the insulator film 273B, the conductor 242a, and the conductor 242b are formed by processing the insulating film 273A and the conductor layer 242B by lithography, and a part of the top surface of the insulator 222 and the oxide 230b are formed. A reaching opening 255 is formed (see FIG. 19).
  • the oxide 230 a, the oxide 230 b, the conductor 242 a, and the conductor 242 b are formed so that at least part thereof overlaps with the conductor 205.
  • the side surfaces of the oxide 230 a, the side surfaces of the oxide 230 b, the side surfaces of the conductor 242 a, and the side surfaces of the conductor 242 b are preferably substantially perpendicular to the top surface of the insulator 222.
  • the area can be reduced and the density can be increased by being substantially perpendicular.
  • the top surface of the insulator 222 may have a low angle with each of the side surface of the oxide 230a, the side surface of the oxide 230b, the side surface of the conductor 242a, and the side surface of the conductor 242b.
  • an angle formed by the top surface of the insulator 222 with the side surface of the oxide 230a, the side surface of the oxide 230b, the side surface of the conductor 242a, and the side surface of the conductor 242b is preferably 60 ° to 70 °.
  • oxide film and the conductive film may be processed by a lithography method.
  • dry etching or wet etching can be used for the processing. Machining by dry etching is suitable for micromachining.
  • an impurity due to an etching gas or the like may be attached or diffused to the surface or the inside of the oxide 230a, the oxide 230b, or the like.
  • the impurities include, for example, fluorine or chlorine.
  • the cleaning method may be wet cleaning using a cleaning solution or the like, plasma treatment using plasma, cleaning by heat treatment, or the like, and the above cleaning may be performed in combination as appropriate.
  • cleaning treatment may be performed using an aqueous solution prepared by diluting oxalic acid, phosphoric acid, hydrofluoric acid, or the like with carbonated water or pure water.
  • ultrasonic cleaning may be performed using pure water or carbonated water.
  • heat treatment may be performed.
  • the heat treatment may be performed under reduced pressure and the oxide film 230C which is to be the oxide 230c may be formed successively without being exposed to the air.
  • the temperature of the heat treatment is preferably 100 ° C. or more and 400 ° C. or less. In this embodiment, the temperature of heat treatment is set to 200.degree.
  • the oxide film 230C can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the oxide film 230C may be formed by a film formation method similar to that of the oxide film 230A or the oxide film 230B in accordance with the characteristics desired for the oxide film to be the oxide 230c.
  • the oxide film 230C may be stacked.
  • Film formation may be performed using a target having a numerical ratio].
  • the proportion of oxygen contained in the sputtering gas of the oxide film 230C may be 70% or more, preferably 80% or more, and more preferably 100%.
  • heat treatment may be performed.
  • the heat treatment may be performed under reduced pressure and the insulating film 250A which is to be the insulator 250 continuously may be formed without exposure to the air.
  • the water and hydrogen adsorbed on the surface of the oxide film 230C and the like are removed, and the water concentration and the hydrogen concentration in the oxide 230a, the oxide 230b and the oxide film 230C are further reduced.
  • the temperature of the heat treatment is preferably 100 ° C. or more and 400 ° C. or less.
  • the insulating film 250A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • silicon oxynitride is preferably deposited by a CVD method.
  • the film formation temperature at the time of forming the insulating film 250A is preferably 350 ° C. or more and less than 450 ° C., particularly about 400 ° C.
  • an oxide film to be the oxide 252 may be formed over the insulating film 250A.
  • the oxide film to be the oxide 252 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • an oxide film to be the oxide 252 an oxide film similar to the oxide film 230C can be used.
  • a conductive film to be the conductor 260a and a conductive film to be the conductor 260b are formed.
  • the conductive film to be the conductor 260a and the conductive film to be the conductor 260b can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • titanium nitride is formed by a sputtering method as a conductive film to be the conductor 260a
  • tungsten is formed by a sputtering method as a conductive film to be the conductor 260b.
  • an insulating film 250A, an oxide film to be the oxide 252, a conductive film to be the conductor 260a, and a conductive film to be the conductor 260b for example, oxide films 230C
  • the insulating film 250A, the oxide film to be the oxide 252, the conductive film to be the conductor 260a, and the conductive film to be the conductor 260b may be successively formed using a multi-chamber apparatus.
  • the conductive film to be the conductor 260a, the conductive film to be the conductor 260b, and the oxide film to be the oxide 252 are sequentially processed by a lithography method to obtain the conductor 260a, the conductor 260b, and the oxide 252.
  • the conductor 260a and the conductor 260b are processed using a dry etching method, and the oxide 252 is processed using a wet etching method (see FIG. 20).
  • the side surfaces of the conductor 260a, the side surfaces of the conductor 260b, and the side surfaces of the oxide 252 preferably substantially match.
  • heat treatment may be performed.
  • the heat treatment is preferably performed at 300 ° C. to 450 ° C. in a nitrogen atmosphere.
  • treatment is performed at a temperature of 400 ° C. for one hour in a nitrogen atmosphere.
  • an insulating film to be the insulator 254 is formed to cover the insulating film 250A, the oxide 252, and the conductor 260.
  • heat treatment may be performed before formation of the insulating film to be the insulator 254.
  • the heat treatment may be performed under reduced pressure and an insulating film to be the insulator 254 may be formed without being exposed to the air.
  • the insulating film to be the insulator 254 is preferably an insulator having a function of suppressing permeation of impurities such as water and hydrogen and oxygen.
  • the insulating film to be the insulator 254 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • aluminum oxide is deposited by sputtering after heat treatment is performed under reduced pressure using a sputtering apparatus.
  • the insulating film to be the insulator 254, the insulating film 250A, the oxide film 230C, and the insulator layer 273B are sequentially processed by a lithography method to obtain the insulator 254, the insulator 250, the oxide 230c, and the insulator 273.
  • the side surface of the insulator 254, the side surface of the insulator 250, the side surface of the oxide 230c, and the side surface of the insulator 273 substantially coincide with each other and are arranged over the insulator 222. preferable.
  • the side surface of the insulator 254, the side surface of the insulator 250, and the side surface of the oxide 230c substantially coincide with each other and are preferably provided over the insulator 222 (FIG. 21). reference).
  • the insulator 274 is formed over the insulator 222 and the insulator 254.
  • the insulator 274 is preferably an insulator having a function of suppressing permeation of impurities such as water and hydrogen and oxygen.
  • silicon nitride, silicon nitride oxide, aluminum oxide, or the like can be used.
  • the insulator 274 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment mode, silicon nitride is deposited by a CVD method (see FIG. 21).
  • an insulating film to be the insulator 280 is formed over the insulator 274.
  • the insulating film to be the insulator 280 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • CMP treatment is performed on the insulating film to be the insulator 280 to form the insulator 280 having a flat top surface.
  • heat treatment may be performed.
  • treatment is performed at a temperature of 400 ° C. for one hour in a nitrogen atmosphere.
  • the heat treatment the water concentration and the hydrogen concentration in the insulator 250 and the insulator 280 can be reduced.
  • an insulating film to be the insulator 282 may be formed over the insulator 280.
  • the insulating film to be the insulator 282 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • an insulating film to be the insulator 282 for example, an aluminum oxide film is preferably formed by a sputtering method. By depositing aluminum oxide by sputtering, diffusion of hydrogen contained in the insulator 280 can be suppressed in some cases to the insulator 250 and the oxide 230 in some cases.
  • heat treatment may be performed.
  • treatment is performed at a temperature of 400 ° C. for one hour in a nitrogen atmosphere.
  • oxygen added as a film of the insulator 282 can be injected into the insulator 250 and the insulator 280.
  • an insulator to be the insulator 281 may be formed over the insulator 282.
  • the insulating film to be the insulator 281 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • silicon nitride is deposited by a CVD method (see FIG. 22).
  • an opening which reaches the conductor 242 a is formed in the insulator 273, the oxide 230 c, the insulator 250, the insulator 254, the insulator 274, the insulator 280, the insulator 282, and the insulator 281.
  • an opening reaching the conductor 242 b is formed in the insulator 273, the oxide 230 c, the insulator 250, the insulator 254, the insulator 274, the insulator 280, the insulator 282, and the insulator 281.
  • the formation of the opening may be performed using a lithography method.
  • an insulating film to be the insulator 241 is formed, and the insulating film is anisotropically etched to form the insulator 241.
  • the insulating film to be the insulator 241 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • an insulating film having a function of suppressing permeation of oxygen is preferably used.
  • aluminum oxide is preferably deposited by an ALD method.
  • a silicon nitride film may be used.
  • anisotropic etching may be performed by, for example, dry etching.
  • the conductive film to be the conductor 240 a and the conductor 240 b preferably has a stacked structure including a conductor having a function of suppressing permeation of impurities such as water and hydrogen.
  • a stack of tantalum nitride, titanium nitride, or the like, tungsten, molybdenum, copper, or the like can be used.
  • the conductive film to be the conductor 240 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • CMP treatment is performed to remove part of the conductive film to be the conductor 240 a and the conductor 240 b and expose the insulator 281.
  • the conductor 240 a and the conductor 240 b whose top surface is flat can be formed.
  • part of the insulator 281 may be removed by the CMP treatment.
  • the conductive film to be the conductor 246 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • a conductive film to be the conductor 246 is processed by a lithography method to form a conductor 246a in contact with the top surface of the conductor 240a and a conductor 246b in contact with the top surface of the conductor 240b (see FIG. 2).
  • a semiconductor device including the transistor 201 illustrated in FIG. 2 can be manufactured.
  • the transistor 201 can be manufactured by using the method for manufacturing a semiconductor device described in this embodiment.
  • a semiconductor device with large on-state current can be provided.
  • a semiconductor device having high frequency characteristics can be provided.
  • a semiconductor device with high reliability can be provided.
  • a semiconductor device which can be miniaturized or highly integrated can be provided.
  • a semiconductor device having favorable electrical characteristics can be provided.
  • a semiconductor device with low off current can be provided.
  • a semiconductor device with reduced power consumption can be provided.
  • a semiconductor device with high productivity can be provided.
  • FIG. 1 An example of a semiconductor device (memory device) using a capacitor which is one embodiment of the present invention is illustrated in FIG.
  • the transistor 200 is provided above the transistor 300
  • the capacitor 100 is provided above the transistor 300 and the transistor 200. Note that the transistor 200 described in the above embodiment can be used as the transistor 200.
  • the transistor 200 is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor. Since the transistor 200 has low off-state current, stored data can be held for a long time by using the transistor for the memory device. That is, since the refresh operation is not required or the frequency of the refresh operation is extremely low, power consumption of the memory device can be sufficiently reduced.
  • the wiring 1001 is electrically connected to the source of the transistor 300, and the wiring 1002 is electrically connected to the drain of the transistor 300.
  • the wiring 1003 is electrically connected to one of the source and the drain of the transistor 200, the wiring 1004 is electrically connected to the first gate of the transistor 200, and the wiring 1006 is electrically connected to the second gate of the transistor 200. It is connected to the.
  • the gate of the transistor 300 and the other of the source and the drain of the transistor 200 are electrically connected to one of the electrodes of the capacitor 100, and the wiring 1005 is electrically connected to the other of the electrodes of the capacitor 100. .
  • the memory device illustrated in FIG. 23 can form a memory cell array by being arranged in a matrix.
  • the transistor 300 is provided over the substrate 311 and functions as a conductor 316 functioning as a gate electrode, an insulator 315 functioning as a gate insulator, a semiconductor region 313 formed of part of the substrate 311, and a source region or a drain region. It has low resistance region 314a and low resistance region 314b.
  • the transistor 300 may be either p-channel or n-channel.
  • the semiconductor region 313 (a part of the substrate 311) in which a channel is formed has a convex shape.
  • the conductor 316 is provided to cover the side surface and the top surface of the semiconductor region 313 with the insulator 315 interposed therebetween.
  • the conductor 316 may use a material for adjusting a work function.
  • Such a transistor 300 is also referred to as a FIN type transistor because it uses the convex portion of the semiconductor substrate.
  • an insulator which functions as a mask for forming the convex portion may be provided in contact with the upper portion of the convex portion.
  • a semiconductor film having a convex shape may be formed by processing the SOI substrate.
  • transistor 300 illustrated in FIG. 23 is an example, and is not limited to the structure, and an appropriate transistor may be used depending on the circuit configuration and the driving method.
  • the capacitive element 100 is provided above the transistor 200.
  • the capacitor 100 includes the conductor 110 functioning as a first electrode, the conductor 120 functioning as a second electrode, and the insulator 130 functioning as a dielectric.
  • the conductor 112 provided over the conductor 246 and the conductor 110 can be formed at the same time.
  • the conductor 112 has a function as a plug electrically connected to the capacitor 100, the transistor 200, or the transistor 300, or a wiring.
  • the conductor 112 and the conductor 110 each have a single-layer structure in FIG. 23, the present invention is not limited to this structure, and a stacked structure of two or more layers may be employed. For example, between a conductor having a barrier property and a conductor having high conductivity, a conductor having high adhesion to a conductor having a barrier property and a conductor having high conductivity may be formed.
  • the insulator 130 may be, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxide nitride, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium oxynitride, hafnium nitride Or the like may be used, and they can be provided in a stack or a single layer.
  • the capacitive element 100 can secure a sufficient capacity by having an insulator with a high dielectric constant (high-k), and by having an insulator with a large dielectric strength, the dielectric strength can be improved, and the capacitance can be increased.
  • the electrostatic breakdown of the element 100 can be suppressed.
  • an insulator of a high dielectric constant (high-k) material (a material with a high relative dielectric constant), an oxide having gallium oxide, hafnium oxide, zirconium oxide, aluminum and hafnium, an oxynitride having aluminum and hafnium And oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, or nitrides containing silicon and hafnium.
  • silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon is added, carbon and nitrogen are materials having high dielectric strength (materials having low dielectric constant). There is silicon oxide added, silicon oxide having pores, or a resin.
  • a wiring layer provided with an interlayer film, a wiring, a plug and the like may be provided between the respective structures. Also, a plurality of wiring layers can be provided depending on the design.
  • a conductor having a function as a plug or a wiring may be provided with the same reference numeral collectively as a plurality of structures.
  • the wiring and the plug electrically connected to the wiring may be an integral body. That is, a part of the conductor may function as a wiring, and a part of the conductor may function as a plug.
  • an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are sequentially stacked as an interlayer film.
  • the conductor 328 electrically connected to the capacitor 100 or the transistor 200, the conductor 330, and the like are embedded. Note that the conductor 328 and the conductor 330 function as a plug or a wiring.
  • the insulator functioning as an interlayer film may function as a planarization film covering the uneven shape below it.
  • the top surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to enhance the planarity.
  • CMP chemical mechanical polishing
  • a wiring layer may be provided over the insulator 326 and the conductor 330.
  • the insulator 350, the insulator 352, and the insulator 354 are sequentially stacked and provided.
  • a conductor 356 is formed on the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or a wire.
  • the conductor 218, a conductor (conductor 205) included in the transistor 200, and the like are embedded.
  • the conductor 218 has a function as a plug electrically connected to the capacitor 100 or the transistor 300, or a wiring.
  • an insulator 150 is provided over the conductor 120 and the insulator 130.
  • an insulator which can be used as an interlayer film, an insulating oxide, a nitride, an oxynitride, a nitride oxide, a metal oxide, a metal oxynitride, a metal nitride oxide, or the like can be given.
  • the material may be selected depending on the function of the insulator.
  • the insulator 216, the insulator 212, the insulator 352, the insulator 354, and the like are preferably insulators with low dielectric constants.
  • the insulator includes silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and silicon oxide having voids. It is preferable to have a resin or the like.
  • the insulator may be silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, or silicon oxide having voids. It is preferable to have a laminated structure of and a resin. Silicon oxide and silicon oxynitride are thermally stable, and thus, when combined with a resin, a stacked structure with a thermally stable and low dielectric constant can be obtained. Examples of the resin include polyester, polyolefin, polyamide (such as nylon and aramid), polyimide, polycarbonate or acrylic.
  • the transistor including an oxide semiconductor electrical characteristics of the transistor can be stabilized by being surrounded by an insulator having a function of suppressing transmission of impurities such as hydrogen and oxygen. Therefore, for the insulator 210, the insulator 350, and the like, an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen can be used.
  • an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium
  • An insulator containing lanthanum, neodymium, hafnium or tantalum may be used in a single layer or a stack.
  • a metal oxide such as tantalum oxide, silicon nitride oxide, silicon nitride, or the like can be used.
  • Conductors that can be used for wiring and plugs include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium
  • a material containing one or more metal elements selected from ruthenium and the like can be used.
  • a semiconductor with high electrical conductivity typically a polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.
  • the conductive materials of the above can be used in a single layer or a stack. It is preferable to use a high melting point material such as tungsten or molybdenum which achieves both heat resistance and conductivity, and it is preferable to use tungsten. Alternatively, it is preferably formed of a low resistance conductive material such as aluminum or copper. Wiring resistance can be lowered by using a low resistance conductive material.
  • an insulator having an excess oxygen region may be provided in the vicinity of the oxide semiconductor.
  • the insulator having a barrier property is preferably provided between the insulator having the excess oxygen region and the conductor provided in the insulator having the excess oxygen region.
  • the insulator 224 and the transistor 200 can be sealed by the insulator 222 having a barrier property, the insulator 254, and the insulator 274.
  • the insulator 241c is in contact with the conductor 240c and part of the insulator 280, and suppresses diffusion of impurities such as water or hydrogen and oxygen contained in the insulator 280 into the conductor 240c. Can.
  • the insulator 241c by providing the insulator 241c, absorption of excess oxygen of the insulator 280 by the conductor 240c can be suppressed. Further, with the insulator 241c, diffusion of hydrogen, which is an impurity, to the transistor 200 through the conductor 240c can be suppressed.
  • an insulating material having a function of suppressing diffusion of impurities such as water or hydrogen and oxygen can be used as the insulator 241c.
  • an insulating material having a function of suppressing diffusion of impurities such as water or hydrogen and oxygen can be used.
  • aluminum oxide or hafnium oxide is preferably used.
  • metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide or tantalum oxide, silicon nitride oxide, silicon nitride, or the like can be used.
  • FIG. 24 An example of a memory device using the semiconductor device of one embodiment of the present invention is illustrated in FIG.
  • the memory device illustrated in FIG. 24 includes a transistor 400 in addition to the semiconductor device including the transistor 200, the transistor 300, and the capacitor 100 illustrated in FIG.
  • the transistor 400 can control the second gate voltage of the transistor 200.
  • the first gate and the second gate of the transistor 400 are diode-connected to the source, and the source of the transistor 400 is connected to the second gate of the transistor 200.
  • the negative potential of the second gate of the transistor 200 is held in this configuration, the voltage between the first gate and the source of the transistor 400 and the voltage between the second gate and the source become 0 V.
  • the power of the transistor 200 and the transistor 400 need not be supplied to the second gate of the transistor 200. Negative potential can be maintained for a long time. Accordingly, the memory device including the transistor 200 and the transistor 400 can hold stored data for a long time.
  • the wiring 1001 is electrically connected to the source of the transistor 300, and the wiring 1002 is electrically connected to the drain of the transistor 300.
  • the wiring 1003 is electrically connected to one of the source and the drain of the transistor 200, the wiring 1004 is electrically connected to the gate of the transistor 200, and the wiring 1006 is electrically connected to the back gate of the transistor 200.
  • the gate of the transistor 300 and the other of the source and the drain of the transistor 200 are electrically connected to one of the electrodes of the capacitor 100, and the wiring 1005 is electrically connected to the other of the electrodes of the capacitor 100. .
  • the wiring 1007 is electrically connected to the source of the transistor 400, the wiring 1008 is electrically connected to the gate of the transistor 400, the wiring 1009 is electrically connected to the back gate of the transistor 400, and the wiring 1010 is a drain of the transistor 400 And are electrically connected.
  • the wiring 1006, the wiring 1007, the wiring 1008, and the wiring 1009 are electrically connected.
  • the memory device shown in FIG. 24 can form a memory cell array by being arranged in a matrix as in the memory device shown in FIG. Note that one transistor 400 can control the second gate voltage of the plurality of transistors 200. Therefore, the number of transistors 400 may be smaller than that of the transistors 200.
  • the transistor 400 is formed in the same layer as the transistor 200 and can be manufactured in parallel.
  • the transistor 400 includes a conductor 460 (conductor 460a and a conductor 460b) functioning as a first gate electrode, a conductor 405 functioning as a second gate electrode, an insulator 222 functioning as a gate insulating layer, An insulator 224 and an insulator 450, an oxide 452 provided over the insulator 450, an oxide 430c having a region where a channel is formed, a conductor 442a functioning as one of a source and a drain, an oxide And 432 b, an oxide 432 a, a conductor 442 b functioning as the other of the source and the drain, an oxide 431 b, and an oxide 431 a, and a conductor 440 (the conductor 440 a and the conductor 440 b).
  • the conductor 405 is in the same layer as the conductor 205.
  • the oxide 431a and the oxide 432a are in the same layer as the oxide 230a, and the oxide 431b and the oxide 432b are in the same layer as the oxide 230b.
  • the conductor 442 is the same layer as the conductor 242.
  • the oxide 430c is the same layer as the oxide 230c.
  • the insulator 450 is the same layer as the insulator 250.
  • the oxide 452 is the same layer as the oxide 252.
  • the conductor 460 is the same layer as the conductor 260.
  • the oxide 430c can be formed by processing an oxide film to be the oxide 230c.
  • the threshold voltage of the transistor 400 can be greater than 0 V, the off-state current can be reduced, and the drain current can be extremely reduced when the second gate voltage and the first gate voltage are 0 V.
  • dicing lines (sometimes referred to as scribe lines, dividing lines, or cutting lines) provided when a plurality of semiconductor devices are taken out in chip form by dividing a large-area substrate into semiconductor elements will be described.
  • a dividing method for example, after a groove (dicing line) for dividing a semiconductor element is first formed in a substrate, it may be cut at a dicing line to divide (divide) into a plurality of semiconductor devices.
  • a region where the insulator 274 and the insulator 215 are in contact with each other is preferably designed to be a dicing line. That is, the insulator 274 may be formed after an opening is provided in the insulator 222 and the insulator 216 in the vicinity of the memory cell including the plurality of transistors 200 and a region serving as a dicing line provided on the outer edge of the transistor 400. .
  • the insulator 215 is in contact with the insulator 274.
  • the insulator 215 and the insulator 274 may be formed using the same material and the same method. Adhesion can be improved by providing the insulator 215 and the insulator 274 using the same material and the same method.
  • the insulator 215 and the insulator 274 for example, silicon nitride is preferably used.
  • the insulator 224, the transistor 200, and the transistor 400 can be surrounded by the insulator 215 and the insulator 274. Since the insulator 215 and the insulator 274 have a function of suppressing diffusion of oxygen, hydrogen, and water, the substrate is divided in each of the circuit regions in which the semiconductor element described in this embodiment is formed. Accordingly, even when processed into a plurality of chips, impurities such as hydrogen or water can be prevented from being mixed from the side direction of the divided substrate and diffused into the transistor 200 and the transistor 400.
  • excess oxygen in the insulator 224 can be prevented from diffusing to the insulator 274 and the insulator 215. Accordingly, excess oxygen in the insulator 224 is efficiently supplied to the transistor 200 or the oxide in which the channel in the transistor 400 is formed.
  • the oxygen can reduce oxygen vacancies in the oxide in which a channel in the transistor 200 or the transistor 400 is formed. Accordingly, the oxide in which the channel in the transistor 200 or the transistor 400 is formed can be an oxide semiconductor with low density of defect states and stable characteristics. That is, variation in the electrical characteristics of the transistor 200 or the transistor 400 can be suppressed, and the reliability can be improved.
  • a transistor using an oxide as a semiconductor (hereinafter sometimes referred to as an OS transistor) and a capacitor according to one embodiment of the present invention are applied using FIGS. 25 and 26.
  • the storage device (hereinafter sometimes referred to as an OS memory device) will be described.
  • the OS memory device is a storage device including at least a capacitor and an OS transistor which controls charge and discharge of the capacitor. Since the off-state current of the OS transistor is extremely small, the OS memory device has excellent retention characteristics and can function as a non-volatile memory.
  • FIG. 25A shows an example of the configuration of the OS memory device.
  • the memory device 1400 includes a peripheral circuit 1411 and a memory cell array 1470.
  • the peripheral circuit 1411 includes a row circuit 1420, a column circuit 1430, an output circuit 1440, and a control logic circuit 1460.
  • the column circuit 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, and a write circuit.
  • the precharge circuit has a function of precharging the wiring.
  • the sense amplifier has a function of amplifying a data signal read from the memory cell.
  • the wiring is a wiring connected to a memory cell included in the memory cell array 1470, which will be described in detail later.
  • the amplified data signal is output as the data signal RDATA to the outside of the storage device 1400 through the output circuit 1440.
  • the row circuit 1420 includes, for example, a row decoder, a word line driver circuit, and the like, and can select a row to be accessed.
  • the storage device 1400 is externally supplied with a low power supply voltage (VSS), a high power supply voltage (VDD) for the peripheral circuit 1411, and a high power supply voltage (VIL) for the memory cell array 1470 as a power supply voltage. Further, control signals (CE, WE, RE), an address signal ADDR, and a data signal WDATA are input to the storage device 1400 from the outside.
  • the address signal ADDR is input to the row decoder and the column decoder, and WDATA is input to the write circuit.
  • the control logic circuit 1460 processes external input signals (CE, WE, RE) to generate control signals for row decoders and column decoders.
  • CE is a chip enable signal
  • WE is a write enable signal
  • RE is a read enable signal.
  • the signal processed by the control logic circuit 1460 is not limited to this, and another control signal may be input as necessary.
  • Memory cell array 1470 has a plurality of memory cells MC arranged in a matrix and a plurality of wirings.
  • the number of wirings connecting the memory cell array 1470 and the row circuit 1420 is determined by the configuration of the memory cells MC, the number of memory cells MC provided in one column, and the like.
  • the number of wirings connecting the memory cell array 1470 and the column circuit 1430 is determined by the configuration of the memory cells MC, the number of memory cells MC in one row, and the like.
  • FIG. 25A shows an example in which the peripheral circuit 1411 and the memory cell array 1470 are formed on the same plane
  • the present embodiment is not limited to this.
  • the memory cell array 1470 may be provided so as to overlap with part of the peripheral circuit 1411.
  • a sense amplifier may be provided so as to overlap below the memory cell array 1470.
  • [DOSRAM] 26A to 26C show an example of the circuit configuration of a memory cell of a DRAM.
  • a DRAM using a memory cell of a 1OS transistor single capacitive element type may be referred to as a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory).
  • a memory cell 1471 illustrated in FIG. 26A includes a transistor M1 and a capacitor CA.
  • the transistor M1 has a gate (sometimes referred to as a front gate) and a back gate.
  • the first terminal of the transistor M1 is connected to the first terminal of the capacitive element CA, the second terminal of the transistor M1 is connected to the wiring BIL, the gate of the transistor M1 is connected to the wiring WOL, and the back gate of the transistor M1 Is connected to the wiring BGL.
  • the second terminal of the capacitive element CA is connected to the wiring CAL.
  • the wiring BIL functions as a bit line
  • the wiring WOL functions as a word line.
  • the wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitive element CA. It is preferable to apply a low level potential to the wiring CAL at the time of data writing and reading.
  • the wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M1. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M1 can be increased or decreased.
  • the memory cell MC is not limited to the memory cell 1471 and can change the circuit configuration.
  • the memory cell MC may have a configuration in which the back gate of the transistor M1 is connected to the wiring WOL instead of the wiring BGL.
  • the memory cell MC may be a memory cell including a single gate transistor, that is, a transistor M1 having no back gate.
  • the transistor 200 can be used as the transistor M1 and the capacitor 100 can be used as the capacitor CA.
  • the leak current of the transistor M1 can be made very low. That is, since the written data can be held for a long time by the transistor M1, the frequency of refresh of the memory cell can be reduced. In addition, the refresh operation of the memory cell can be made unnecessary. In addition, since the leakage current is extremely low, multi-value data or analog data of the memory cell 1471, the memory cell 1472, and the memory cell 1473 can be held.
  • the bit line when the sense amplifier is provided so as to overlap below the memory cell array 1470, the bit line can be shortened.
  • the bit line capacitance can be reduced, and the storage capacitance of the memory cell can be reduced.
  • [NOSRAM] 26D to 26H show examples of the circuit configuration of a gain cell type memory cell of two transistors and one capacitance element.
  • the memory cell 1474 illustrated in FIG. 26D includes a transistor M2, a transistor M3, and a capacitor CB.
  • the transistor M2 has a front gate (sometimes simply referred to as a gate) and a back gate.
  • NOSRAM Nonvolatile Oxide Semiconductor RAM
  • the first terminal of the transistor M2 is connected to the first terminal of the capacitive element CB, the second terminal of the transistor M2 is connected to the wiring WBL, the gate of the transistor M2 is connected to the wiring WOL, and the back gate of the transistor M2 Is connected to the wiring BGL.
  • the second terminal of the capacitive element CB is connected to the wiring CAL.
  • the first terminal of the transistor M3 is connected to the wiring RBL, the second terminal of the transistor M3 is connected to the wiring SL, and the gate of the transistor M3 is connected to the first terminal of the capacitive element CB.
  • the wiring WBL functions as a write bit line
  • the wiring RBL functions as a read bit line
  • the wiring WOL functions as a word line.
  • the wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitive element CB. When writing data, holding data, and reading data, it is preferable to apply a low level potential to the wiring CAL.
  • the wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M2. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M2 can be increased or decreased.
  • the memory cell MC is not limited to the memory cell 1474, and the configuration of the circuit can be changed as appropriate.
  • the memory cell MC may have a configuration in which the back gate of the transistor M2 is connected to the wiring WOL instead of the wiring BGL.
  • the memory cell MC may be a memory cell including a single gate transistor, that is, a transistor M2 having no back gate as illustrated in a memory cell 1476 illustrated in FIG. 26F.
  • the memory cell MC may have a configuration in which the wiring WBL and the wiring RBL are combined into one wiring BIL.
  • the transistor 200 can be used as the transistor M2, the transistor 300 can be used as the transistor M3, and the capacitor 100 can be used as the capacitor CB.
  • the leakage current of the transistor M2 can be made very low.
  • the frequency of refresh of the memory cell can be reduced.
  • the refresh operation of the memory cell can be made unnecessary.
  • the memory cell 1474 can hold multilevel data or analog data. The same applies to memory cells 1475 to 1477.
  • the transistor M3 may be a transistor having silicon in a channel formation region (hereinafter, may be referred to as a Si transistor).
  • the conductivity type of the Si transistor may be n-channel or p-channel.
  • the Si transistor may have higher field effect mobility than the OS transistor. Therefore, a Si transistor may be used as the transistor M3 functioning as a read out transistor. Further, by using a Si transistor for the transistor M3, the transistor M2 can be provided by being stacked on the transistor M3, so that the area occupied by the memory cell can be reduced and high integration of the memory device can be achieved.
  • the transistor M3 may be an OS transistor.
  • OS transistors are used for the transistors M2 and M3, the memory cell array 1470 can be configured using only n-type transistors.
  • FIG. 26H shows an example of a gain cell type memory cell of three transistors and one capacitance element.
  • a memory cell 1478 illustrated in FIG. 26H includes transistors M4 to M6 and a capacitor CC.
  • the capacitive element CC is appropriately provided.
  • the memory cell 1478 is electrically connected to the wirings BIL, RWL, WWL, BGL, and GNDL.
  • the wiring GNDL is a wiring for applying a low level potential. Note that the memory cell 1478 may be electrically connected to the wirings RBL and WBL instead of the wiring BIL.
  • the transistor M4 is an OS transistor having a back gate, and the back gate is electrically connected to the wiring BGL. Note that the back gate and the gate of the transistor M4 may be electrically connected to each other. Alternatively, the transistor M4 may not have a back gate.
  • the transistors M5 and M6 may be n-channel Si transistors or p-channel Si transistors, respectively.
  • the transistors M4 to M6 may be OS transistors.
  • the memory cell array 1470 can be configured using only n-type transistors.
  • the transistor 200 can be used as the transistor M4, the transistor 300 can be used as the transistors M5 and M6, and the capacitive element 100 can be used as the capacitive element CC.
  • the leak current of the transistor M4 can be made very low.
  • peripheral circuit 1411 the memory cell array 1470, and the like described in this embodiment are not limited to the above. Arrangements or functions of these circuits and wirings, circuit elements, and the like connected to the circuits may be changed, deleted, or added as needed.
  • Embodiment 4 an example of a chip 1200 on which the semiconductor device of the present invention is mounted is described with reference to FIG.
  • a plurality of circuits (systems) are mounted on the chip 1200.
  • SoC system on chip
  • the chip 1200 includes a central processing unit (CPU) 1211, a graphics processing unit (GPU) 1212, one or more analog operation units 1213, one or more memory controllers 1214, one or more Interface 1215, one or more network circuits 1216, and the like.
  • CPU central processing unit
  • GPU graphics processing unit
  • analog operation units 1213 one or more analog operation units 1213
  • memory controllers 1214 one or more memory controllers 1214
  • Interface 1215 one or more network circuits 1216, and the like.
  • Bumps (not shown) are provided on the chip 1200 and are connected to the first surface of a printed circuit board (PCB) 1201 as shown in FIG. 27B. Further, a plurality of bumps 1202 are provided on the back surface of the first surface of the PCB 1201 and are connected to the motherboard 1203.
  • PCB printed circuit board
  • the motherboard 1203 may be provided with a storage device such as a DRAM 1221 and a flash memory 1222.
  • a storage device such as a DRAM 1221 and a flash memory 1222.
  • the DOS RAM described in the above embodiment can be used for the DRAM 1221.
  • the NOSRAM described in the above embodiment can be used for the flash memory 1222.
  • the CPU 1211 preferably has a plurality of CPU cores.
  • the GPU 1212 preferably has a plurality of GPU cores.
  • the CPU 1211 and the GPU 1212 may each have a memory for temporarily storing data.
  • a memory common to the CPU 1211 and the GPU 1212 may be provided in the chip 1200.
  • the memory the aforementioned NOSRAM or DOSRAM can be used.
  • the GPU 1212 is suitable for parallel calculation of a large number of data, and can be used for image processing and product-sum operation. By providing the image processing circuit and the product-sum operation circuit using the oxide semiconductor of the present invention in the GPU 1212, image processing and product-sum operation can be performed with low power consumption.
  • the wiring between the CPU 1211 and the GPU 1212 can be shortened, and data transfer from the CPU 1211 to the GPU 1212, data transfer between memories of the CPU 1211 and the GPU 1212, And, after the calculation by the GPU 1212, transfer of the calculation result from the GPU 1212 to the CPU 1211 can be performed at high speed.
  • the analog operation unit 1213 includes one or both of an A / D (analog / digital) conversion circuit and a D / A (digital / analog) conversion circuit. Further, the product-sum operation circuit may be provided in the analog operation unit 1213.
  • the memory controller 1214 has a circuit functioning as a controller of the DRAM 1221 and a circuit functioning as an interface of the flash memory 1222.
  • the interface 1215 includes an interface circuit with an external connection device such as a display device, a speaker, a microphone, a camera, and a controller.
  • the controller includes a mouse, a keyboard, a game controller, and the like.
  • USB Universal Serial Bus
  • HDMI registered trademark
  • High-Definition Multimedia Interface or the like can be used.
  • the network circuit 1216 includes a network circuit such as a LAN (Local Area Network). It may also have circuitry for network security.
  • LAN Local Area Network
  • the circuits can be formed in the same manufacturing process. Therefore, even if the number of circuits required for the chip 1200 increases, there is no need to increase the number of manufacturing processes, and the chip 1200 can be manufactured at low cost.
  • the PCB 1201 provided with the chip 1200 having the GPU 1212, the DRAM 1221, and the motherboard 1203 provided with the flash memory 1222 can be referred to as a GPU module 1204.
  • the GPU module 1204 has a chip 1200 using SoC technology, so its size can be reduced. Moreover, since it is excellent in image processing, it is suitable to use for portable electronic devices, such as a smart phone, a tablet terminal, a laptop PC, and a portable (portable) game machine.
  • a deep neural network DNN
  • CNN convolutional neural network
  • RNN recursive neural network
  • DBM deep layer Boltzmann machine
  • the chip 1200 can be used as an AI chip, or the GPU module 1204 can be used as an AI system module because operations such as DBN can be performed.
  • the semiconductor device described in the above embodiment is, for example, a storage device of various electronic devices (for example, an information terminal, a computer, a smartphone, an electronic book terminal, a digital camera (including a video camera), a recording and reproducing device, a navigation system, etc.)
  • the computer includes a tablet computer, a notebook computer, a desktop computer, and a large computer such as a server system.
  • the semiconductor device described in the above embodiment is applied to various removable storage devices such as a memory card (for example, an SD card), a USB memory, and an SSD (solid state drive).
  • FIG. 28 schematically shows several configuration examples of the removable storage device.
  • the semiconductor device described in the above embodiment is processed into a packaged memory chip and used for various storage devices and removable memories.
  • FIG. 28A is a schematic view of a USB memory.
  • the USB memory 1100 includes a housing 1101, a cap 1102, a USB connector 1103, and a substrate 1104.
  • the substrate 1104 is housed in a housing 1101.
  • the memory chip 1105 and the controller chip 1106 are attached to the substrate 1104.
  • the semiconductor device described in the above embodiment can be incorporated in the memory chip 1105 or the like of the substrate 1104.
  • FIG. 28 (B) is a schematic view of the appearance of the SD card
  • FIG. 28 (C) is a schematic view of the internal structure of the SD card.
  • the SD card 1110 has a housing 1111, a connector 1112 and a substrate 1113.
  • the substrate 1113 is housed in a housing 1111.
  • the memory chip 1114 and the controller chip 1115 are attached to the substrate 1113.
  • the capacity of the SD card 1110 can be increased.
  • a wireless chip provided with a wireless communication function may be provided over the substrate 1113.
  • data can be read and written from the memory chip 1114 by wireless communication between the host device and the SD card 1110.
  • the semiconductor device described in the above embodiment can be incorporated in the memory chip 1114 or the like of the substrate 1113.
  • FIG. 28 (D) is a schematic view of the appearance of the SSD
  • FIG. 28 (E) is a schematic view of the internal structure of the SSD.
  • the SSD 1150 includes a housing 1151, a connector 1152, and a substrate 1153.
  • the substrate 1153 is housed in a housing 1151.
  • the memory chip 1154, the memory chip 1155, and the controller chip 1156 are attached to the substrate 1153.
  • the memory chip 1155 is a work memory of the controller chip 1156, and for example, a DOSRAM chip may be used.
  • the capacity of the SSD 1150 can be increased.
  • the semiconductor device described in the above embodiment can be incorporated in the memory chip 1154 or the like of the substrate 1153.
  • FIG. 29 illustrates a specific example of an electronic device provided with a processor such as a CPU or a GPU, or a chip according to one embodiment of the present invention.
  • the GPU or the chip according to one embodiment of the present invention can be mounted on various electronic devices.
  • the electronic devices include, for example, television devices, desktop or notebook personal computers, monitors for computers, etc., large-sized game machines such as digital signage (Digital Signage), pachinko machines, etc.
  • digital signage Digital Signage
  • pachinko machines large-sized game machines
  • electronic devices equipped with screens, digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, portable information terminals, sound reproduction devices, etc. may be mentioned.
  • artificial intelligence can be mounted on an electronic device by providing the integrated circuit or the chip according to one embodiment of the present invention to the electronic device.
  • the electronic device of one embodiment of the present invention may have an antenna. By receiving the signal with the antenna, display of images, information, and the like can be performed on the display portion.
  • the antenna may be used for contactless power transmission.
  • the electronic device of one embodiment of the present invention includes a sensor (force, displacement, position, velocity, acceleration, angular velocity, rotation number, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, It may have a function of measuring voltage, power, radiation, flow, humidity, inclination, vibration, odor or infrared.
  • the electronic device of one embodiment of the present invention can have various functions. For example, a function of displaying various information (still images, moving images, text images, etc.) on the display unit, a touch panel function, a calendar, a function of displaying date or time, etc., a function of executing various software (programs), wireless communication A function, a function of reading a program or data recorded in a recording medium, or the like can be provided.
  • FIG. 29 shows an example of the electronic device.
  • FIG. 29A shows a mobile phone (smart phone) which is a type of information terminal.
  • the information terminal 5500 includes a housing 5510 and a display portion 5511.
  • a touch panel is provided in the display portion 5511 as an input interface, and a button is provided in the housing 5510.
  • the information terminal 5500 can execute an application using artificial intelligence by applying the chip of one embodiment of the present invention.
  • an application using artificial intelligence for example, an application that recognizes a conversation and displays the content of the conversation on the display unit 5511, recognizes characters, figures, and the like input by the user with respect to a touch panel included in the display unit 5511; An application displayed on the display portion 5511, an application for performing biometric authentication such as fingerprint or voiceprint, and the like can be given.
  • a desktop information terminal 5300 is illustrated in FIG.
  • the desktop information terminal 5300 includes a main body 5301 of the information terminal, a display 5302, and a keyboard 5303.
  • the desktop information terminal 5300 can execute an application using artificial intelligence by applying the chip of one embodiment of the present invention.
  • applications using artificial intelligence include design support software, text correction software, and menu automatic generation software.
  • new artificial intelligence can be developed.
  • FIGS. 29A and 29B are illustrated in FIGS. 29A and 29B as examples of the electronic device, an information terminal other than the smartphone and the desktop information terminal may be applied. it can.
  • an information terminal other than a smart phone and a desktop information terminal for example, a PDA (Personal Digital Assistant), a notebook information terminal, a work station, etc. may be mentioned.
  • PDA Personal Digital Assistant
  • FIG. 29C illustrates an electric refrigerator-freezer 5800 which is an example of an electric appliance.
  • the electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator door 5802, a freezer door 5803 and the like.
  • an electric refrigerator-freezer 5800 having artificial intelligence can be realized.
  • the electric refrigerator-freezer 5800 is automatically stored in the electric refrigerator-freezer 5800, which automatically generates a menu based on the food stored in the electric refrigerator-freezer 5800, the expiration date of the food, etc. It can have a function of automatically adjusting to the temperature according to the food.
  • the electric refrigerator-freezer has been described as an electric appliance, but other electric appliances include, for example, a vacuum cleaner, a microwave oven, an electronic oven, a rice cooker, a water heater, an IH cooker, a water server, and an air conditioner. Appliances, washing machines, dryers, audiovisual equipment etc. may be mentioned.
  • FIG. 29D illustrates a portable game console 5200 which is an example of the game console.
  • the portable game machine includes a housing 5201, a display portion 5202, a button 5203, and the like.
  • a low-power consumption portable game device 5200 can be realized. Further, since low power consumption can reduce heat generation from the circuit, it is possible to reduce the influence of heat generation on the circuit itself, peripheral circuits, and modules.
  • a portable game device 5200 having artificial intelligence can be realized.
  • the expressions such as the progress of the game, the behavior and behavior of creatures appearing on the game, and the phenomena occurring on the game are determined by the program possessed by the game.
  • the expression which is not limited to the program of the game becomes possible. For example, it is possible to express that the contents asked by the player, the progress of the game, the time, and the behavior of the person appearing on the game change.
  • FIG. 29D illustrates a portable game machine as an example of a game machine
  • a game machine to which a GPU or a chip of one embodiment of the present invention is applied is not limited to this.
  • a game machine to which the GPU or chip of one embodiment of the present invention is applied for example, a home-use stationary game machine, an arcade game machine installed in an entertainment facility (game center, amusement park, etc.), a sports facility Pitching machines for batting practice.
  • the GPU or chip of one embodiment of the present invention can be applied to an automobile that is a mobile body and the driver seat area of the automobile.
  • FIG. 29 (E1) shows a car 5700 which is an example of a moving body
  • FIG. 29 (E2) shows a periphery of a windshield in a room of the car.
  • the display panel 5702 in addition to the display panel 5702, and the display panel 5703, the display panel 5704 attached to a pillar is illustrated.
  • the display panel 5701 to the display panel 5703 can provide various information by displaying a speedometer, a tachometer, a travel distance, a fuel gauge, a gear state, an air conditioning setting, and the like.
  • display items, layouts, and the like displayed on the display panel can be appropriately changed in accordance with the user's preference, and design can be enhanced.
  • the display panels 5701 to 5703 can also be used as lighting devices.
  • the display panel 5704 By projecting an image from an imaging device (not shown) provided in the automobile 5700 on the display panel 5704, it is possible to complement the view (dead angle) blocked by the pillar. That is, by displaying an image from an imaging device provided outside the automobile 5700, a blind spot can be compensated to enhance safety. In addition, by displaying an image that complements the invisible part, it is possible to check the safety more naturally and without discomfort.
  • the display panel 5704 can also be used as a lighting device.
  • the GPU or chip of one embodiment of the present invention can be applied as a component of artificial intelligence, for example, the chip can be used for an autonomous driving system of a car 5700. Moreover, the said chip
  • a mobile body is not limited to a motor vehicle.
  • a moving object a train, a monorail, a ship, a flying object (a helicopter, a drone, a plane, a rocket) and the like can also be mentioned, and the chip of one embodiment of the present invention is applied to these moving objects.
  • a system using artificial intelligence can be provided.
  • the GPU or chip of one embodiment of the present invention can be applied to a broadcast system.
  • FIG. 29F schematically shows data transmission in the broadcast system. Specifically, FIG. 29F shows a path until the radio wave (broadcast signal) transmitted from the broadcast station 5680 reaches the television receiver (TV) 5600 of each home.
  • the TV 5600 includes a receiver (not shown), and the broadcast signal received by the antenna 5650 is transmitted to the TV 5600 through the receiver.
  • the antenna 5650 is a UHF (Ultra High Frequency) antenna.
  • a BS ⁇ 110 ° CS antenna, a CS antenna, or the like can be used as the antenna 5650.
  • the radio wave 5675A and the radio wave 5675B are broadcast signals for ground wave broadcasting, and the radio wave tower 5670 amplifies the received radio wave 5675A and transmits the radio wave 5675B.
  • Each household can view terrestrial TV broadcast on the TV 5600 by receiving the radio wave 5675 B by the antenna 5650.
  • the broadcast system is not limited to the terrestrial broadcast shown in FIG. 29F, and may be satellite broadcast using an artificial satellite, data broadcast by an optical line, or the like.
  • the above-described broadcast system may be a broadcast system using artificial intelligence by applying the chip of one embodiment of the present invention.
  • compression of the broadcast data is performed by the encoder, and when the antenna 5650 receives the broadcast data, the decoder of the receiving apparatus included in the TV 5600 Restoration is performed.
  • artificial intelligence for example, in motion compensation prediction which is one of compression methods of an encoder, it is possible to recognize a display pattern included in a display image.
  • intra-frame prediction using artificial intelligence can also be performed.
  • image interpolation processing such as up conversion can be performed in restoration of broadcast data by the decoder.
  • the above-described broadcast system using artificial intelligence is suitable for ultra high definition television (UHDTV: 4K, 8K) broadcast where the amount of broadcast data is increased.
  • the TV 5600 may be provided with a recording device having artificial intelligence.
  • a recording device having artificial intelligence it is possible to automatically record a program according to the user's preference by making the recording device learn the user's preference to the artificial intelligence.
  • the electronic device described in this embodiment the function of the electronic device, the application example of artificial intelligence, the effect thereof, and the like can be combined with the description of other electronic devices as appropriate.
  • a sample in which the conductor 205 functioning as the second gate electrode of the transistor 200 illustrated in FIG. 1, the insulator 215 in contact with the side surface of the conductor 205, and the insulator 216 are formed is manufactured, and cross-sectional observation of the sample is performed. It was carried out using a scanning transmission electron microscope (HD-2300 manufactured by Hitachi High-Technologies Corporation). The manufactured samples were a sample A in which a silicon nitride film was formed by sputtering as the insulator 215, and a sample B in which a silicon nitride film was formed by CVD as the insulator 215.
  • a silicon wafer was thermally oxidized to form a silicon oxide film.
  • an aluminum oxide film was formed to a thickness of 40 nm as the insulator 214 by a sputtering method over the silicon oxide film.
  • a conductive film to be the conductor 205 As a conductive film to be the conductor 205, a tungsten film was formed to a thickness of 100 nm by a sputtering method. A film to be a hard mask was formed over the conductive film to be the conductor 205, and a hard mask was formed by a lithography method. Next, using the hard mask as an etching mask, a conductive film to be the conductor 205 was processed to form the conductor 205.
  • an insulating film to be the insulator 215 was formed by depositing a silicon nitride film to a thickness of 20 nm by a sputtering method.
  • a silicon nitride film was formed to a thickness of 20 nm by a CVD method as an insulating film to be the insulator 215.
  • a silicon oxynitride film was formed to a thickness of 300 nm as the insulating film to be the insulator 216 by a CVD method.
  • FIG. 30 (A) shows a cross-sectional image of the sample A
  • FIG. 30 (B) shows a cross-sectional image of the sample B.
  • Insulating both the sample A using a silicon nitride film formed by sputtering as the insulator 215 and the sample B using a silicon nitride film formed by CVD as the insulator 215 in contact with the side surface of the conductor 205 It was confirmed that the body 215 was formed without failure and the insulator 216 was also formed without failure. In addition, it was confirmed that the respective heights of the top surface of the conductor 205, the top surface of the insulator 215, and the top surface of the insulator 216 were approximately equal and flat.
  • This embodiment can be implemented by appropriately combining at least a part of the other embodiments described in the present specification.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Thin Film Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

L'invention concerne un dispositif à semi-conducteur ayant un courant élevé à l'état passant et une excellente fiabilité. Le dispositif à semi-conducteur comprend : un premier isolant ; un premier conducteur et un second isolant sur le premier isolant ; un troisième isolant sur le second isolant ; un quatrième isolant sur le premier conducteur, sur le second isolant et sur le troisième isolant ; un cinquième isolant sur le quatrième isolant ; un premier oxyde sur le cinquième isolant ; un second oxyde sur le premier oxyde ; un second conducteur et un troisième conducteur sur le second oxyde ; un sixième isolant sur le second conducteur ; un septième isolant sur le troisième conducteur ; un troisième oxyde sur le second oxyde ; un huitième isolant sur le troisième oxyde ; un quatrième conducteur positionné sur le huitième isolant et chevauchant le second oxyde ; un neuvième isolant recouvrant le huitième isolant et le quatrième conducteur ; et un dixième isolant sur le neuvième isolant. Le second isolant est en contact avec la surface latérale du premier conducteur, et le dixième isolant est en contact avec le quatrième isolant.
PCT/IB2019/050205 2018-01-25 2019-01-11 Dispositif à semi-conducteur et procédé de fabrication de dispositif à semi-conducteur WO2019145807A1 (fr)

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JP2019567411A JPWO2019145807A1 (ja) 2018-01-25 2019-01-11 半導体装置、および半導体装置の作製方法
CN201980008975.XA CN111615743A (zh) 2018-01-25 2019-01-11 半导体装置及半导体装置的制造方法

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Cited By (1)

* Cited by examiner, † Cited by third party
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WO2021090115A1 (fr) * 2019-11-08 2021-05-14 株式会社半導体エネルギー研究所 Dispositif à semi-conducteur

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US20170317111A1 (en) * 2016-04-28 2017-11-02 Semiconductor Energy Laboratory Co., Ltd. Transistor, semiconductor device, and electronic device
US20170373194A1 (en) * 2016-06-27 2017-12-28 Semiconductor Energy Laboratory Co., Ltd. Transistor
US20170373195A1 (en) * 2016-06-27 2017-12-28 Semiconductor Energy Laboratory Co., Ltd. Transistor and semiconductor device
US20170373192A1 (en) * 2016-06-27 2017-12-28 Semiconductor Energy Laboratory Co., Ltd. Transistor and semiconductor device

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US20170317111A1 (en) * 2016-04-28 2017-11-02 Semiconductor Energy Laboratory Co., Ltd. Transistor, semiconductor device, and electronic device
US20170373194A1 (en) * 2016-06-27 2017-12-28 Semiconductor Energy Laboratory Co., Ltd. Transistor
US20170373195A1 (en) * 2016-06-27 2017-12-28 Semiconductor Energy Laboratory Co., Ltd. Transistor and semiconductor device
US20170373192A1 (en) * 2016-06-27 2017-12-28 Semiconductor Energy Laboratory Co., Ltd. Transistor and semiconductor device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2021090115A1 (fr) * 2019-11-08 2021-05-14 株式会社半導体エネルギー研究所 Dispositif à semi-conducteur

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