WO2019139617A1

WO2019139617A1 - Heterojunction bipolar transistors having lateral growth structures

Info

Publication number: WO2019139617A1
Application number: PCT/US2018/013575
Authority: WO
Inventors: Sansaptak DASGUPTA; Han Wui Then; Marko Radosavljevic
Original assignee: Intel Corporation
Priority date: 2018-01-12
Filing date: 2018-01-12
Publication date: 2019-07-18

Abstract

Heterojunction bipolar transistors having lateral growth structures are disclosed. A disclosed heterojunction bipolar transistor includes a substrate, a dielectric above the substrate, the dielectric having a trench extending therethrough, a collector extending through the trench and above the dielectric, a base laterally extending from the collector, and an emitter laterally extending from the base.

Description

HETEROJUNCTION BIPOLAR TRANSISTORS HAVING LATERAL GROWTH STRUCTURES

FIELD OF THE DISCLOSURE

[0001] This disclosure relates generally to semiconductor fabrication and, more particularly, to heterojunction bipolar transistors having lateral growth structures.

BACKGROUND

[0002] Semiconductor devices such as microprocessors (e.g., processors) have become smaller and more compact, while their die transistor counts have increased dramatically due to increasing computational needs (e.g., transistor counts in the billions). With this increased compactness, heterojunction bipolar transistors (HBTs) have been fabricated onto semiconductor wafers. These transistors are implemented to handle high frequency signals, such as those present in radio frequency (RF) systems requiring high power efficiency, such as mobile devices.

BRIEF DESCRIPTION OF THE DRAWINGS

[0003] FIG. 1 is a cross-sectional view of a known heterojunction bipolar transistor.

[0004] FIG. 2 is a cross-sectional view of an example heterojunction bipolar transistor in accordance with teachings of this disclosure.

[0005] FIG. 3 is a cross-sectional view of an alternative example heterojunction bipolar transistor in accordance with teachings of this disclosure.

[0006] FIGS. 4A-4D are cross-sectional views of example fabrication steps to produce an example heterojunction bipolar transistor device in accordance with teachings of this disclosure.

[0007] FIG. 4E is an overhead view of an example heterojunction bipolar transistor. [0008] FIGS. 5A-5C depict example fabrication steps that may be implemented with the examples disclosed herein.

[0009] FIG. 6 is a flowchart representative of an example method of manufacturing the examples disclosed herein.

[0010] FIG. 7 is a top view of an example wafer and example dies that may include a heterojunction bipolar transistor, such as the example heterojunction bipolar transistors of FIGS. 2 and 3, in accordance with any of the examples disclosed herein.

[0011] FIG. 8 is a cross-sectional side view of an example integrated circuit (IC) device that may include a heterojunction bipolar transistor, such as the example heterojunction bipolar transistors of FIGS. 2 and 3, in accordance with any of the examples disclosed herein.

[0012] FIG. 9 is a cross-sectional side view of an example IC package that may include a heterojunction bipolar transistor, such as the example heterojunction bipolar transistors of FIGS. 2 and 3, in accordance with any of the examples disclosed herein.

[0013] FIG. 10 is a cross-sectional side view of an example IC device assembly that may include a heterojunction bipolar transistor, such as the example heterojunction bipolar transistors of FIGS. 2 and 3, in accordance with any of the examples disclosed herein.

[0014] FIG. 11 is a block diagram of an example electrical device that may include a heterojunction bipolar transistor, such as the example heterojunction bipolar transistors of FIGS. 2 and 3, in accordance with any of the examples disclosed herein.

[0015] The figures are not to scale. Instead, the thickness of the layers or regions may be enlarged in the drawings. In general, the same reference numbers will be used throughout the drawing(s) and accompanying written description to refer to the same or like parts. As used in this patent, stating that any part (e.g., a layer, film, area, region, or plate) is in any way on (e.g., positioned on, located on, disposed on, or formed on, etc.) another part, indicates that the referenced part is either in contact with the other part, or that the referenced part is above the other part with one or more intermediate part(s) located therebetween. Stating that any part is in contact with another part means that there is no intermediate part between the two parts. Although the figures show layers and regions with clean lines and boundaries, some or all of these lines and/or boundaries may be idealized. In reality, the boundaries and/or lines may be unobservable, blended, and/or irregular.

DETAILED DESCRIPTION

[0016] Heterojunction bipolar transistors having lateral growth structures are disclosed. Heterojunction bipolar transistors are sometimes implemented to handle high frequency signals, such as those present in radio frequency (RF) systems requiring high power efficiency (e.g., mobile devices). Known heterojunction bipolar transistors can sometimes be subject to leakage and voltage breakdown during high frequency operation.

[0017] Examples disclosed herein enable heterojunction bipolar transistors with relatively high frequency operation and breakdown voltages, both of which enable forward looking RF applications. Examples disclosed herein utilize a horizontal arrangement of a subcollector, which is formed in a trench of a dielectric, with a base and an emitter laterally extending from the subcollector. In particular, the emitter laterally extends from the base.

According to some of the examples disclosed herein, the subcollector, the base and emitter are at least partially grown and/or re-grown along a lateral direction.

[0018] In some examples, the subcollector, the base and/or the emitter have a generally trapezoidal profile. In some examples, the emitter is n- doped (e.g., an n- doped emitter at least partially composed of gallium nitride). In some examples, the collector and/or a subcollector associated with the collector include aluminum gallium nitride. Additionally or alternatively, the base includes p- doped gallium nitride and/or indium gallium nitride.

[0019] As used herein, the term“above” is used with reference to a bulk region of a base semiconductor substrate (e.g., a semiconductor wafer) on which components of an integrated circuit are formed. Specifically, as used herein, a first component of an integrated circuit is“above” a second component when the first component is farther away from the bulk region of the semiconductor substrate. Likewise, as used herein, a first component is “below” another component when the first component is closer to the bulk region of the semiconductor substrate. As noted above, one component can be above or below another with other components therebetween or while being in direct contact with one another. As used herein, the terms“lateral,”

“laterally,”“laterally grown” or“lateral growth” are also used with reference to a bulk region of a base semiconductor substrate and refer to a direction with which the bulk region generally extends.

[0020] FIG. 1 is a cross-sectional view of a known heterojunction bipolar transistor 100. The heterojunction bipolar transistor 100 includes an n+ emitter 102, a base 104, which is composed of gallium nitride and disposed below the emitter 102, and an n- subcollector 106 that is disposed below the base 104. The heterojunction bipolar transistor 100 also includes a subcollector 108, which is composed of n+ gallium nitride and disposed above a sapphire substrate 110.

[0021] In FIG. 1, a tri-etching process is typically applied to define a trench 112 with a corresponding sidewall 114. As a result of a presence of the sidewall 114, the base 104 is prone to damage, such as dislocations that can cause leakage and voltage breakdown. Accordingly, a signal (e.g., a voltage signal) frequency of the heterojunction bipolar transistor 100 is limited by a relatively low frequency threshold. In contrast, examples disclosed herein mitigate these adverse effects by, instead, implementing a horizontal structural arrangement that can be produced by lateral growth (e.g., epitaxial lateral growth).

[0022] FIG. 2 is a cross-sectional view of an example heterojunction bipolar transistor 200 in accordance with the teachings of this disclosure. The heterojunction bipolar transistor 200 of the illustrated example includes a substrate 202, a dielectric (e.g., a shallow trench isolation) 204, a collector 205 that includes a first subcollector (e.g., first subcollector layer) 206 and a second subcollector (e.g., a second subcollector layer) 208. The example heterojunction bipolar transistor 200 also includes a base 210 and an emitter 212. Further, an arrow 220 generally indicates an orientation of a +c plane while an arrow 222 generally indicates an orientation of an m plane.

[0023] According to the illustrated example, the substrate 202 includes silicon while the dielectric 204 includes an oxide. The first subcollector 206 includes n- gallium nitride in this example. Further, the example second subcollector 208 includes aluminum gallium nitride, while the base 210 includes p- doped gallium nitride or indium gallium nitride. In this example, the emitter 212 includes either aluminum gallium nitride or n- doped gallium nitride. However, the example materials described above are only examples and any appropriate material and/or doping can be used in conjunction with examples disclosed herein.

[0024] To define a structure or arrangement of the example heterojunction bipolar transistor 200, the second subcollector 208, the base 210 and emitter 212 are all at least partially laterally grown (horizontally in the view of FIG. 2) using an epitaxial growth process. In some examples, at least a portion of the second subcollector 208 grows laterally as the portion extends above the dielectric 204. In other words, the second collector 208 can exhibit epitaxial growth in both horizontal and vertical directions (as viewed in FIG. 2) to define the horizontal arrangement shown in FIG. 2, which is distinct from the vertical arrangement of the heterojunction bipolar transistor 100 of FIG. 1.

[0025] To prevent breakdown (e.g., voltage breakdown) and/or leakage of the heterojunction bipolar transistor 200, the second subcollector 208 of the illustrated example is bordered/flanked (e.g., surrounded) at its lateral edge 226 by the base 210. Further, a lateral edge 228 of the base 210 is bordered by the emitter 212. This example horizontal arrangement of the second subcollector 208 with the base 210 and the emitter 212 reduces sidewall exposure that is encountered with the known heterojunction bipolar transistor 100 described above in connection with FIG. 1. Accordingly, this arrangement of the heterojunction bipolar transistor 200 in conjunction with the example materials significantly reduces (e.g., prevents) voltage breakdown and/or leakage. Further, this arrangement also enables relatively higher p- doping of the base 210 and, thus, reduces contact resistance. As a result, the example heterojunction bipolar transistor 200 can function at relatively high frequencies and can also have a higher breakdown voltage.

[0026] FIG. 3 is a cross-sectional view of an alternative example heterojunction bipolar transistor 300 in accordance with teachings of this disclosure. The example heterojunction bipolar transistor 300 is similar to the example heterojunction bipolar transistor 200, but instead includes a generally trapezoidal structure and/or ramped features.

[0027] According to the illustrated example of FIG. 3, the

heterojunction bipolar transistor 300 includes a substrate 302, which includes silicon. The example heterojunction bipolar transistor 300 also includes a dielectric 304, which may be an oxide. The example heterojunction bipolar transistor 300 also includes a collector 305 that includes both a first subcollector 306 and a second subcollector 308, which is disposed above the first subcollector 306. In this example, the first subcollector 306 includes n- gallium nitride while the second subcollector 308 includes aluminum gallium nitride. Further, the heterojunction bipolar transistor 300 includes a base 310 and an emitter 312. The base 310 of the illustrated example includes p- doped gallium nitride or indium gallium nitride, while the example emitter 312 includes aluminum gallium nitride or gallium nitride.

[0028] According to the illustrated example, an upper portion 311 of the second subcollector 308 exhibits a generally trapezoidal overall shape. In particular, the upper portion 311 defines a ramped or inclined lateral surface or edge 315. As a result, the base 310 exhibits a generally trapezoidal overall shape with inclined lateral surfaces in this example because the base 310 is epitaxially grown in a lateral direction from the upper portion 311. Likewise, the emitter 312 exhibits a generally trapezoidal overall shape with inclined lateral surfaces because the emitter 312 is epitaxially grown in a lateral direction from the inclined lateral surfaces of the base 310.

[0029] In this example, a dimension 316 represents a relatively smaller width dimension of the second subcollector 308 that extends into the dielectric

304 while a dimension 318 represents a larger width dimension of the subcollector 308 that is proximate the base 310. In some examples, the dimension 316 is approximately 100 nanometers (nm) to 10 microns in width. According to the illustrated example, the dielectric 304 is approximately 100- 300 nanometers (nm) thick (vertically in the view of FIG. 3). The example subcollector 308 is approximately 0.5-1 micron thick. Further, the base 310 is approximately 200- 500 nm thick. The dimensions disclosed herein are only examples and any appropriate dimensions may be implemented based on application need (e.g., desired breakdown voltage, desired frequency range, etc.). In this example, an arrow 320 represents an orientation of a c+ plane while an arrow 322 represents an orientation of a semipolar plane.

[0030] FIGS. 4A-4D are cross-sectional views of example fabrication steps to produce an example heterojunction bipolar transistor device in accordance with teachings of this disclosure. Turning to FIG. 4A, a substrate layer 402 is formed/deposited and a dielectric 404 is applied above the substrate layer 402. According to the illustrated example, a trench 406 is etched (e.g., chemically-etched, photo-etched, mechanically-etched, etc.) and/or cut into the dielectric 404.

[0031] A first subcollector 408, which includes n+ gallium nitride in this example, is applied and/or deposited into the trench 406. In this example, the first subcollector 408 is epitaxially grown. Further, a second subcollector 410 of the illustrated example is epitaxially grown from the first subcollector 408 within the trench 406. In this example, a portion 412 of the second subcollector 410 extends beyond the trench 406 and grows laterally (to the left and right sides of the view of FIG. 4A) based on epitaxial growth.

[0032] Turning to FIG. 4B, a mask (e.g., a hard mask) 414 is applied and/or deposited above the subcollector 410, for example. In this example, a growth and/or re-growth of the subcollector 410 forms and/or defines inclined surfaces 416, thereby defining a generally trapezoidal shape of the

subcollector 410. However, in some examples, the subcollector 410 is etched to define or alter inclined surfaces 416.

[0033] FIG. 4C depicts a base 418 laterally grown from the inclined surfaces 416. Further, an emitter 420 of the illustrated example is laterally grown from the base 418. Accordingly, both the base 418 and the emitter 420 also exhibit a generally trapezoidal profile based on lateral growth relative to the subcollector 410.

[0034] Turning to FIG. 4D, an emitter contact (e.g., a metal emitter contact) 430 is defined above and/or on the emitter 420. According to the illustrated example, at least one collector contact 432 is defined above the subcollector 410. Further, a dielectric 434 of the illustrated example is also applied and/or deposited above the subcollector 410, the base 418 and the emitter 420. According to the illustrated example, a contact 436 is provided. In particular, the example contact 436 extends through the subcollector 410 between the collector contact 432 and the subcollector 408.

[0035] FIG. 4E is an overhead view of the example shown in FIG. 4D. As can be seen in the illustrated example of FIG. 4E, the base 418 has a generally c-shaped structure with base contact arms 440 (not extending through the cross-section shown in FIG. 4D) that extend along a top surface (e.g., a top edge) of the dielectric 434. Further, the base contact arms 440 extend between the collector contacts 432 and the emitter contacts 430, as viewed in FIG. 4E.

[0036] FIGS. 5A-5C depict example fabrication steps that may be implemented for examples disclosed herein. Turning to FIG. 5A, a cross- sectional view of an example mid-process structure 500 is shown. The example structure 500 includes a silicon substrate 502, a dielectric 504, a first subcollector 506, a second subcollector 508, a base 510, a first hard mask 512 and a second hard mask 514.

[0037] FIG. 5B is an overhead view of the example structure 500. According to the illustrated example of FIG. 5B, the first hard mask 512 and the second hard mask 514 have different lengths. In particular, the first hard mask 512 has a longer length than the second hard mask 514.

[0038] FIG. 5C is a cross-sectional view depicting a further fabrication step to produce an alternative heterojunction bipolar transistor with improved contact properties. In this example, the second hard mask 514 of FIG. 5 A is etched and an emitter 520 is provided via an epitaxial growth process. In this example, the emitter 520 borders, surrounds and/or contacts both a lateral surface 522 and an upper surface 524 of the base 510. As a result, electrical contact between the emitter 520 and the base 510 is significantly improved.

[0039] FIG. 6 is a flowchart representative of an example method 600 to manufacture the example heterojunction bipolar transistor 200 of FIG. 2 and described in connection with the process(es) illustrated in FIGS. 4A-5C. While the example method is described in connection with the heterojunction bipolar transistor 200, the example method 600 may be implemented to produce any of the examples disclosed herein. The example method 600 begins as a wafer (e.g., the substrate 202) is being processed to fabricate the example heterojunction bipolar transistor 200.

[0040] The dielectric 204 is etched to define a trench (block 602). In particular, the example dielectric 204 is etched via a photo-etching process or chemical etching process to remove a full depth of the dielectric 204, thereby extending the trench to the substrate 202. In other examples, at least a portion of the substrate 202 is also etched.

[0041] According to the illustrated example, the collector 205 is formed in the trench (block 604). In particular, the collector 205 includes the first subcollector 206 disposed in the trench with the second subcollector 208 disposed above the first subcollector 206.

[0042] In some examples, the second subcollector 208 of the collector 205 is etched (block 606). In particular, lateral surfaces (e.g., edges, sidewalls, etc.) of a portion (e.g., an upper portion) of the second subcollector is etched to facilitate lateral growth of the base 210 and/or the emitter 212.

[0043] In some examples, the first hard mask 512 is formed and/or deposited above the second subcollector 208 (block 608).

[0044] According to the illustrated example, the base 210 that extends laterally from the subcollector 208 is formed (block 610). In particular, the example base 210 is grown laterally (e.g., sideways) from the subcollector 208 via an epitaxial growth process. [0045] In some examples, the second hard mask 514 is formed and/or deposited to laterally extend from the base 210 (block 612). In some examples, the second hard mask 214 laterally extends from a lateral edge of the base 210.

[0046] In examples that implement the second hard mask 514, the second hard mask 514 is etched (block 614).

[0047] In this example, the emitter 212 is formed to laterally extend from the base 210 and, thus, laterally extend from (e.g., surround, border) the subcollector 208 (block 616). In particular, the example emitter 212 is epitaxially grown in a lateral direction from the base 210. As a result, the emitter 212 and the base 210 are placed on the same layer and/or aligned in a vertical direction (e.g., a distance from a plane defined by a substrate layer) in this example. In some examples, the emitter 212 is also grown vertically to overgrow a top surface of the base 210.

[0048] In this example, the first hard mask 512 is etched (block 618). Accordingly, the collector 205 is exposed so that the collector contact 432 can be formed thereon.

[0049] According to the illustrated example, the collector contact 432 and the emitter contacts 430 are formed (block 620) and the example method 600 ends.

[0050] Although the example method 600 is described with reference to the flowchart illustrated in FIG. 6, many other methods of manufacturing the example heterojunction bipolar transistors 200, 300 of FIGS. 2 and 3 may alternatively be used. For example, the order of execution of the blocks may be changed, and/or some of the blocks described may be changed, eliminated, or combined. Similarly, additional operations may be included in the manufacturing process before, in between, or after the blocks shown in FIG. 6.

[0051] The example heterojunction bipolar transistors 200, 300 disclosed herein may be included in any suitable electronic component. FIGS. 7-11 illustrate various example apparatus that may include any of the example FETs disclosed herein.

[0052] FIG. 7 is a top view of an example wafer 700 and example dies 602 that may include one or more of the example heterojunction bipolar transistors 200, 300 or may be included in an integrated circuit (IC) package whose substrate includes one or more example heterojunction bipolar transistor(s) 200, 300 (e.g., as discussed below with reference to FIG. 8) in accordance with any of the examples disclosed herein. The wafer 700 may be composed of semiconductor material and may include one or more dies 702 having IC structures formed on a surface of the wafer 700. Each of the dies 702 may be a repeating unit of a semiconductor product that includes any suitable IC. After the fabrication of the semiconductor product is complete, the wafer 700 may undergo a singulation process in which the dies 702 are separated from one another to provide discrete "chips" of the semiconductor product. The die 702 may include one or more of the example heterojunction bipolar transistor(s) 200, 300 (e.g., as discussed below with reference to FIG. 8), one or more transistors (e.g., some of the transistors 840 of FIG. 8, discussed below) and/or supporting circuitry to route electrical signals to the transistors, as well as any other IC components. In some examples, the wafer 700 or the die 702 may include a memory device (e.g., a random access memory (RAM) device, such as a static RAM (SRAM) device, a magnetic RAM (MRAM) device, a resistive RAM (RRAM) device, a conductive- bridging RAM (CBRAM) device, etc.), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuit element. Multiple ones of these devices may be combined on a single die 702. For example, a memory array formed by multiple memory devices may be formed on a same die 702 as a processing device (e.g., the processing device 1102 of FIG. 11) or other logic that is configured to store information in the memory devices or execute instructions stored in the memory array.

[0053] FIG. 8 is a cross-sectional side view of an IC device 800 that may include one or more of the example heterojunction bipolar transistor(s) 200, 300 or may be included in an IC package whose substrate includes one or more of the example heterojunction bipolar transistor(s) 200, 300 (e.g., as discussed below with reference to FIG. 9), in accordance with any of the examples disclosed herein. One or more of the IC devices 800 may be included in one or more dies 702 (FIG. 7). The IC device 800 may be formed on a substrate 802 (e.g., the wafer 700 of FIG. 7) and may be included in a die (e.g., the die 702 of FIG. 7). The substrate 802 may be a semiconductor substrate composed of semiconductor material systems including, for example, n-type or p-type materials systems (or a combination of both). The substrate 802 may include, for example, a crystalline substrate formed using a bulk silicon or a silicon-on-insulator (SOI) substructure. In some examples, the substrate 802 may be formed using alternative materials, which may or may not be combined with silicon, that include, but are not limited to, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Further materials classified as group II- VI, III-V, or IV may also be used to form the substrate 802. Although a few examples of materials from which the substrate 802 may be formed are described here, any material that may serve as a foundation for an IC device 800 may be used. The substrate 802 may be part of a singulated die (e.g., the dies 702 of FIG. 7) or a wafer (e.g., the wafer 700 of FIG. 7).

[0054] The IC device 800 may include one or more device layers 804 disposed on the substrate 802. The device layer 804 may include features of one or more transistors 840 (e.g., metal oxide semiconductor field-effect transistors (MOSFETs)) formed on the substrate 802. The device layer 804 may include, for example, one or more source and/or drain (S/D) regions 820, a gate 822 to control current flow in the transistors 840 between the S/D regions 820, and one or more S/D contacts 824 to route electrical signals to/from the S/D regions 820. The transistors 840 may include additional features not depicted for the sake of clarity, such as device isolation regions, gate contacts, and the like. The transistors 840 are not limited to the type and configuration depicted in FIG. 8 and may include a wide variety of other types and configurations such as, for example, planar transistors, non-planar transistors, or a combination of both. Non-planar transistors may include FinFET transistors, such as double-gate transistors or tri-gate transistors, and wrap-around or all-around gate transistors, such as nanoribbon and nanowire transistors. [0055] Each transistor 840 may include a gate 822 formed of at least two layers, a gate dielectric and a gate electrode. The gate dielectric may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide, silicon carbide, and/or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some examples, an annealing process may be carried out on the gate dielectric to improve its quality when a high-k material is used.

[0056] The gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or n-type work function metal, depending on whether the transistor 840 is to be a p-type metal oxide semiconductor (PMOS) or an n-type metal oxide semiconductor (NMOS) transistor. In some implementations, the gate electrode may include a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer. For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides (e.g., ruthenium oxide), and any of the metals discussed below with reference to an NMOS transistor (e.g., for work function tuning). For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to a PMOS transistor (e.g., for work function tuning).

[0057] In some examples, when viewed as a cross-section of the transistor 840 along the source-channel-drain direction, the gate electrode may include a U-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In other examples, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In other examples, the gate electrode may include a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may include one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.

[0058] In some examples, a pair of sidewall spacers may be formed on opposing sides of the gate stack to bracket the gate stack. The sidewall spacers may be formed from materials such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching. In some examples, a plurality of spacer pairs may be used; for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.

[0059] The S/D regions 820 may be formed within the substrate 802 adjacent to the gate 822 of each transistor 840. The S/D regions 820 may be formed using an implantation/diffusion process or an etching/deposition process, for example. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate 802 to form the S/D regions 820. An annealing process that activates the dopants and causes them to diffuse farther into the substrate 802 may follow the ion-implantation process. In the latter process, the substrate 802 may first be etched to form recesses at the locations of the S/D regions 820.

An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the S/D regions 820. In some implementations, the S/D regions 820 may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some examples, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In some examples, the S/D regions 820 may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. In further examples, one or more layers of metal and/or metal alloys may be used to form the S/D regions 820.

[0060] In some examples, the device layer 804 and/or the substrate 802 may include one or more of the example heterojunction bipolar transistor(s) 200, 300 in addition to or instead of transistors 840. For example, a single heterojunction bipolar transistor 200, 300 may be implemented in the device layer 804, but any number and structure of the example heterojunction bipolar transistor(s) 200, 300 may be included in a device layer 804. The heterojunction bipolar transistor(s) 200, 300 included in a device layer 804 may be referred to as a "front end" device. In some examples, the IC device 800 may not include any front end heterojunction bipolar transistor(s) 200,

300. One or more of the example heterojunction bipolar transistor(s) 200, 300 in the device layer 804 may be coupled to any suitable other ones of the devices in the device layer 804, to any devices in the metallization stack 819 (discussed below), and/or to one or more of the conductive contacts 836 (discussed below).

[0061] Electrical signals, such as power and/or input/output (I/O) signals, may be routed to and/or from the devices (e.g., transistors 840 and/or the example heterojunction bipolar transistor(s) 200, 300) of the device layer 604 through one or more interconnect layers disposed on the device layer 804 (illustrated in FIG. 8 as interconnect layers 806-810). For example, electrically conductive features of the device layer 804 (e.g., the gate 822 and the S/D contacts 824) may be electrically coupled with the interconnect structures 828 of the interconnect layers 806-810. The one or more interconnect layers 806-810 may form a metallization stack (also referred to as an "ILD stack") 819 of the IC device 800. In some examples, one or more of the example heterojunction bipolar transistor(s) 200, 300 may be disposed in one or more of the interconnect layers 806-810, in accordance with any of the techniques disclosed herein. For example, a single example heterojunction bipolar transistor 200, 300 may be implemented in the interconnect layer 808 for illustration purposes, but any number and structure of the example heterojunction bipolar transistor 200, 300 may be included in any one or more of the layers in a metallization stack 819. An example heterojunction bipolar transistor 200, 300 included in the metallization stack 819 may be referred to as a "back-end" device. In some examples, the IC device 800 may not include any back-end heterojunction bipolar transistor 200, 300; in some examples, the IC device 800 may include both front- and back-end heterojunction bipolar transistor 200, 300. One or more of the example FET(s) 200 in the metallization stack 819 may be coupled to any suitable ones of the devices in the device layer 804, and/or to one or more of the conductive contacts 836 (discussed below).

[0062] The interconnect structures 828 may be arranged within the interconnect layers 806-810 to route electrical signals according to a wide variety of designs (in particular, the arrangement is not limited to the particular configuration of interconnect structures 828 depicted in FIG. 8). Although a particular number of interconnect layers 806-810 is depicted in FIG. 8, examples of the present disclosure include IC devices having more or fewer interconnect layers than depicted.

[0063] In some examples, the interconnect structures 828 may include lines 828a and/or vias 828b filled with an electrically conductive material such as a metal. The lines 828a may be arranged to route electrical signals in a direction of a plane that is substantially parallel with a surface of the substrate 802 upon which the device layer 804 is formed. For example, the lines 828a may route electrical signals in a direction in and out of the page from the perspective of FIG. 8. The vias 828b may be arranged to route electrical signals in a direction of a plane that is substantially perpendicular to the surface of the substrate 802 upon which the device layer 804 is formed. In some examples, the vias 828b may electrically couple lines 828 a of different interconnect layers 806-810 together.

[0064] The interconnect layers 806-810 may include a dielectric material 826 disposed between the interconnect structures 828, as shown in FIG. 8. In some examples, the dielectric material 826 disposed between the interconnect structures 828 in different ones of the interconnect layers 806-810 may have different compositions; in other examples, the composition of the dielectric material 826 between different interconnect layers 806-810 may be the same.

[0065] A first interconnect layer 806 (referred to as Metal 1 or "Ml ") may be formed directly on the device layer 804. In some examples, the first interconnect layer 806 may include lines 828a and/or vias 828b, as shown.

The lines 828 a of the first interconnect layer 806 may be coupled with contacts (e.g., the S/D contacts 824) of the device layer 804.

[0066] A second interconnect layer 808 (referred to as Metal 2 or "M2") may be formed directly on the first interconnect layer 806. In some examples, the second interconnect layer 808 may include vias 828b to couple the lines 828a of the second interconnect layer 808 with the lines 828a of the first interconnect layer 806. Although the lines 828a and the vias 828b are structurally delineated with a line within each interconnect layer (e.g., within the second interconnect layer 808) for the sake of clarity, the lines 828a and the vias 828b may be structurally and/or materially contiguous (e.g., simultaneously filled during a dual-damascene process) in some examples.

[0067] A third interconnect layer 810 (referred to as Metal 3 or "M3") (and additional interconnect layers, as desired) may be formed in succession on the second interconnect layer 808 according to similar techniques and configurations described in connection with the second interconnect layer 808 or the first interconnect layer 806. In some examples, the interconnect layers that are "higher up" in the metallization stack 819 in the IC device 800 (i.e., further away from the device layer 804) may be thicker.

[0068] The IC device 800 may include a solder resist material 834

(e.g., polyimide or similar material) and one or more conductive contacts 836 formed on the interconnect layers 806-810. In FIG. 8, the conductive contacts 836 are illustrated as taking the form of bond pads. The conductive contacts 836 may be electrically coupled with the interconnect structures 828 and configured to route the electrical signals of the transistor(s) 840 to other external devices. For example, solder bonds may be formed on the one or more conductive contacts 836 to mechanically and/or electrically couple a chip including the IC device 800 with another component (e.g., a circuit board). The IC device 800 may include additional or alternate structures to route the electrical signals from the interconnect layers 806-810; for example, the conductive contacts 836 may include other analogous features (e.g., posts) that route the electrical signals to external components.

[0069] FIG. 9 is a cross-sectional view of an example IC package 950 that may include one or more of the example heterojunction bipolar transistor(s) 200, 300. The package substrate 952 may be formed of a dielectric material, and may have conductive pathways extending through the dielectric material between the face 972 and the face 974, or between different locations on the face 972, and/or between different locations on the face 974. These conductive pathways may take the form of any of the interconnects 828 discussed above with reference to FIG. 8. In some examples, a single heterojunction bipolar transistor 200, 300 may be implemented in the package substrate 952, but this number and location of the example heterojunction bipolar transistor(s) 200, 300 in the IC package 950 is simply illustrative, and any number of the example heterojunction bipolar transistor(s) 200, 300 (with any suitable structure) may be included in a package substrate 952. In some examples, no heterojunction bipolar transistor 200, 300 may be included in the package substrate 952.

[0070] The IC package 950 may include a die 956 coupled to the package substrate 952 via conductive contacts 954 of the die 956, first-level interconnects 958, and conductive contacts 960 of the package substrate 952. The conductive contacts 960 may be coupled to conductive pathways 962 through the package substrate 952, allowing circuitry within the die 956 to electrically couple to various ones of the conductive contacts 964 or to the example heterojunction bipolar transistor(s) 200, 300 (or to other devices included in the package substrate 952, not shown). The first-level interconnects 958 illustrated in FIG. 9 are solder bumps, but any suitable first- level interconnects 958 may be used. As used herein, a "conductive contact" may refer to a portion of conductive material (e.g., metal) serving as an electrical interface between different components; conductive contacts may be recessed in, flush with, or extending away from a surface of a component, and may take any suitable form (e.g., a conductive pad or socket).

[0071] In some examples, an underfill material 966 may be disposed between the die 956 and the package substrate 952 around the first-level interconnects 958, and a mold compound 968 may be disposed around the die 956 and in contact with the package substrate 952. In some examples, the underfill material 966 may be the same as the mold compound 968. Example materials that may be used for the underfill material 966 and the mold compound 968 are epoxy mold materials, as suitable. Second-level interconnects 970 may be coupled to the conductive contacts 964. The second-level interconnects 970 illustrated in FIG. 9 are solder balls (e.g., for a ball grid array arrangement), but any suitable second-level interconnects 970 may be used (e.g., pins in a pin grid array arrangement or lands in a land grid array arrangement). The second-level interconnects 970 may be used to couple the IC package 950 to another component, such as a circuit board (e.g., a motherboard), an interposer, or another IC package, as known in the art and as discussed below with reference to FIG. 10.

[0072] In FIG. 9, the IC package 950 is a flip chip package, and includes the example heterojunction bipolar transistor 200, 300 in the package substrate 952. The number and location of the example heterojunction bipolar transistor (s) 200, 300 in the package substrate 952 of the IC package 950 is simply illustrative, and any number of the example heterojunction bipolar transistor (s) 200, 300 (with any suitable structure) may be included in a package substrate 952. In some examples, no heterojunction bipolar transistor 200, 300 may be included in the package substrate 952. The die 956 may take the form of any of the examples of the die 702 discussed herein (e.g., may include any of the examples of the IC device 700). In some examples, the die 956 may include one or more of the example heterojunction bipolar transistor (s) 200, 300 (e.g., as discussed above with reference to FIG. 7 and FIG. 8); in other examples, the die 956 may not include any heterojunction bipolar transistor 200, 300.

[0073] Although the IC package 950 illustrated in FIG. 9 is a flip chip package, other package architectures may be used. For example, the IC package 950 may be a ball grid array (BGA) package, such as an embedded wafer-level ball grid array (eWLB) package. In another example, the IC package 950 may be a wafer-level chip scale package (WLCSP) or a panel fanout (FO) package. Although a single die 956 is illustrated in the IC package 950 of FIG. 9, an IC package 950 may include multiple dies 956 (e.g., with one or more of the multiple dies 956 coupled to the example

heterojunction bipolar transistor 200, 300 included in the package substrate 952). An IC package 950 may include additional passive components, such as surface-mount resistors, capacitors, and inductors disposed on the first face 972 or the second face 974 of the package substrate 952. More generally, an IC package 950 may include any other active or passive components known in the art.

[0074] FIG. 10 is a block diagram of an example electrical device that may include a heterojunction bipolar transistor, such as the example heterojunction bipolar transistors of FIGS. 2 and 3, in accordance with any of the examples disclosed herein.

[0075] FIG. 10 is a cross-sectional side view of an IC device assembly 1000 that may include one or more IC packages or other electronic components (e.g., a die) including one or more of the example heterojunction bipolar transistor(s) 200, 300, in accordance with any of the examples disclosed herein. The IC device assembly 1000 includes a number of components disposed on a circuit board 1002 (which may be, e.g., a motherboard). The IC device assembly 1000 includes components disposed on a first face 1040 of the circuit board 1002 and an opposing second face

1042 of the circuit board 1002; generally, components may be disposed on one or both faces 1040 and 1042. Any of the IC packages discussed below with reference to the IC device assembly 1000 may take the form of any of the examples of the IC package 850 discussed above with reference to FIG. 8 (e.g., may include one or more of the example heterojunction bipolar transistor (s) 200, 300 in a package substrate 852 or in a die).

[0076] In some examples, the circuit board 1002 may be a printed circuit board (PCB) including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (alone or in conjunction with other metal layers) between the components coupled to the circuit board 1002. In other examples, the circuit board 1002 may be a non-PCB substrate.

[0077] The IC device assembly 1000 illustrated in FIG. 10 includes a package-on-interposer structure 1036 coupled to the first face 1040 of the circuit board 1002 by coupling components 1016. The coupling components 1016 may electrically and mechanically couple the package-on-interposer structure 1036 to the circuit board 1002, and may include solder balls (as shown in FIG. 10), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure.

[0078] The package-on-interposer structure 1036 may include an IC package 1020 coupled to an interposer 1004 by coupling components 1018. The coupling components 1018 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 1016. Although a single IC package 1020 is shown in FIG. 10, multiple IC packages may be coupled to the interposer 1004; indeed, additional interposers may be coupled to the interposer 1004. The interposer 1004 may provide an intervening substrate used to bridge the circuit board 1002 and the IC package 1020. The IC package 1020 may be or include, for example, a die (the die 702 of FIG. 7), an IC device (e.g., the IC device 800 of FIG. 8), or any other suitable component. Generally, the interposer 1004 may spread a connection to a wider pitch or reroute a connection to a different connection. For example, the interposer 1004 may couple the IC package 1020 (e.g., a die) to a set of BGA conductive contacts of the coupling components 816 for coupling to the circuit board 802. In the examples illustrated in FIG. 10, the IC package 1020 and the circuit board 1002 are attached to opposing sides of the interposer 1004; in other examples, the IC package 1020 and the circuit board 1002 may be attached to a same side of the interposer 1004. In some examples, three or more components may be interconnected by way of the interposer 1004.

[0079] The interposer 1004 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, an epoxy resin with inorganic fillers, a ceramic material, or a polymer material such as polyimide. In some examples, the interposer 1004 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The interposer 1004 may include metal vias 1008 and interconnects 1010, including but not limited to through-silicon vias (TSVs) 806. The interposer 804 may further include embedded devices 1014, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer 1004. The package-on-interposer structure 1036 may take the form of any of the package-on-interposer structures known in the art. In some examples, the interposer 1004 may include one or more of the example FET 200

[0080] The IC device assembly 1000 may include an IC package 1024 coupled to the first face 1040 of the circuit board 1002 by coupling components 1022. The coupling components 1022 may take the form of any of the examples discussed above with reference to the coupling components 1016, and the IC package 1024 may take the form of any of the examples discussed above with reference to the IC package 1020.

[0081] The IC device assembly 1000 illustrated in FIG. 10 includes a package-on-package structure 1034 coupled to the second face 1042 of the circuit board 1002 by coupling components 1028. The package-on-package structure 1034 may include an IC package 1026 and an IC package 1032 coupled together by coupling components 1030 such that the IC package 1026 is disposed between the circuit board 1002 and the IC package 1032. The coupling components 1028 and 1030 may take the form of any of the examples of the coupling components 1016 discussed above, and the IC packages 1026 and 1032 may take the form of any of the examples of the IC package 1020 discussed above. The package-on-package structure 1034 may be configured in accordance with any of the package-on-package structures known in the art.

[0082] From the foregoing, it will be appreciated that example methods, apparatus and articles of manufacture have been disclosed that enable HBT devices that can handle high frequencies, as well as higher breakdown voltages. Further, the examples disclosed herein enable more reliable HBT structures that can reduce leakage, poor base resistance and/or poor contact to p-GAN.

[0083] FIG. 11 is a block diagram of an example electrical device 1100 that may include one or more the example heterojunction bipolar transistor(s) 200, 300, in accordance with any of the examples disclosed herein. For example, any suitable ones of the components of the electrical device 1100 may include one or more of the IC packages 950, IC devices 1000, or dies 702 disclosed herein. A number of components are illustrated in FIG. 11 as included in the electrical device 1100, but any one or more of these components may be omitted or duplicated, as suitable for the application. In some examples, some or all of the components included in the electrical device 1100 may be attached to one or more motherboards. In some examples, some or all of these components are fabricated onto a single system-on-a-chip (SoC) die. [0084] Additionally, in various examples, the electrical device 1100 may not include one or more of the components illustrated in FIG. 11, but the electrical device 1100 may include interface circuitry for coupling to the one or more components. For example, the electrical device 1100 may not include a display device 1106, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a display device 1106 may be coupled. In another set of examples, the electrical device 1100 may not include an audio input device 1124 or an audio output device 1108, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device 1124 or audio output device 1108 may be coupled.

[0085] The electrical device 1100 may include a processing device 1102 (e.g., one or more processing devices). As used herein, the term

"processing device" or "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The processing device 1102 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices. The electrical device 1100 may include a memory 1104, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM)), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid state memory, and/or a hard drive. In some examples, the memory 1104 may include memory that shares a die with the processing device 1102. This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM). One or more of the heterojunction bipolar transistor(s) 200, 300 may be located in one or more of the components of FIG. 11. [0086] In some examples, the electrical device 1100 may include a communication chip 1112 (e.g., one or more communication chips). For example, the communication chip 1112 may be configured for managing wireless communications for the transfer of data to and from the electrical device 1100. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some examples they might not.

[0087] The communication chip 1112 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultra mobile broadband (UMB) project (also referred to as "3GPP2"), etc.). IEEE 802.16 compatible

Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 802.16 standards. The communication chip 912 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 912 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 1112 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT),

Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication chip 1112 may operate in accordance with other wireless protocols in other examples. The electrical device 1100 may include an antenna 1122 to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions).

[0088] In some examples, the communication chip 1112 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the

communication chip 1112 may include multiple communication chips. For instance, a first communication chip 1112 may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication chip 1112 may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some examples, a first communication chip 1112 may be dedicated to wireless communications, and a second communication chip 1112 may be dedicated to wired

communications.

[0089] The electrical device 1100 may include battery/power circuitry 1114. The battery/power circuitry 1114 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the electrical device 1100 to an energy source separate from the electrical device 1100 (e.g., AC line power).

[0090] The electrical device 1100 may include a display device 1106 (or corresponding interface circuitry, as discussed above). The display device 1106 may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.

[0091] The electrical device 1100 may include an audio output device 1108 (or corresponding interface circuitry, as discussed above). The audio output device 1108 may include any device that generates an audible indicator, such as speakers, headsets, or earbuds. [0092] The electrical device 1100 may include an audio input device 1124 (or corresponding interface circuitry, as discussed above). The audio input device 1124 may include any device that generates a signal

representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).

[0093] The electrical device 1100 may include a GPS device 1118 (or corresponding interface circuitry, as discussed above). The GPS device 1118 may be in communication with a satellite-based system and may receive a location of the electrical device 1100, as known in the art.

[0094] The electrical device 1100 may include another output device 1110 (or corresponding interface circuitry, as discussed above). Examples of the other output device 1110 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

[0095] The electrical device 1100 may include another input device 1120 (or corresponding interface circuitry, as discussed above). Examples of the other input device 1120 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0096] The electrical device 1100 may have any desired form factor, such as a hand-held or mobile electrical device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra mobile personal computer, etc.), a desktop electrical device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable electrical device. In some examples, the electrical device 1100 may be any other electronic device that processes data. [0097] Example 1 includes a heterojunction bipolar transistor including a substrate, a dielectric above the substrate, the dielectric having a trench extending therethrough, a collector extending through the trench and above the dielectric, a base laterally extending from the collector, and an emitter laterally extending from the base.

[0098] Example 2 includes the subject matter of Example 1, where the includes a first subcollector beneath a second subcollector.

[0099] Example 3 includes the subject matter of Example 2, where the first subcollector includes aluminum, gallium, nitride, and an n- dopant.

[00100] Example 4 includes the subject matter of any one of Examples 2 or 3, where a portion of the second subcollector includes a generally trapezoidal profile.

[00101] Example 5 includes the subject matter of any one of Examples 2 to 4, where the second subcollector has a first width in the trench and a second width above the trench, wherein the second width is greater than the first width.

[00102] Example 6 includes the subject matter of any one of Examples 1 to 5, wherein the emitter includes an n- dopant.

[00103] Example 7 includes the subject matter of any one of Examples 1 to 6, wherein the emitter includes aluminum, gallium and a nitride.

[00104] Example 8 includes the subject matter of any one of Examples 1 to 7, wherein the emitter further extends from a top edge of the base.

[00105] Example 9 includes the subject matter of any one of Examples 1 to 8, where at least one of the collector, the base or the emitter is laterally grown.

[00106] Example 10 includes a method of producing a heterojunction bipolar transistor, the method including etching a dielectric to form a trench therein, forming a collector in the trench, wherein the collector extends past a top surface of the dielectric, forming a base to laterally extend from the collector, and forming an emitter to laterally extend from the base.

[00107] Example 11 includes the subject matter of Example 10, where the collector includes a first subcollector beneath a second subcollector. [00108] Example 12 includes the subject matter of Example 11, and further includes including forming a first hard mask above the second sub collector.

[00109] Example 13 includes the subject matter of Example 12, and further includes forming a second hard mask that laterally extends from the base.

[00110] Example 14 includes the subject matter of Example 13, and further includes etching the second hard mask, wherein the emitter further extends from a top surface of the base.

[00111] Example 15 includes the subject matter of Example 13, where the first hard mask has a first length and the second hard mask has a second length, the first length being larger than the second length.

[00112] Example 16 includes the subject matter of any one of Examples 11 to 15, where the forming of the collector includes epitaxially growing the second subcollector in horizontal and vertical directions.

[00113] Example 17 includes the subject matter of any one of Examples 10 to 16, and further includes forming emitter and collector contacts.

[00114] Example 18 includes a system with a processing device having a communications chip, and a heterojunction bipolar transistor. The heterojunction bipolar transistor includes a substrate, a dielectric above the substrate, where the dielectric has a trench extending therethrough, a collector extending through the trench and above the dielectric, a base laterally extending from the collector, and an emitter laterally extending from the base.

[00115] Example 19 includes the subject matter of Example 18, where the collector includes a first subcollector beneath a second subcollector.

[00116] Example 20 includes the subject matter of Example 19, where the second subcollector has a first width in the trench and a second width proximate the base, wherein the second width is greater than the first width.

[00117] Example 21 includes the subject matter of any one of Examples 19 to 20, where the first subcollector includes aluminum, gallium, nitride and an n- dopant. [00118] Example 22 includes the subject matter of any one of

Examples 19 to 21, lateral surfaces of the second subcollector include inclined lateral surfaces.

[00119] Example 23 includes the subject matter of any one of

Examples 18 to 22, where the emitter includes an n- dopant.

[00120] Example 24 includes the subject matter of any one of

Examples 18 to 23, where the emitter includes, aluminum, gallium and nitride.

[00121] Example 25 includes the subject matter of any one of

Examples 18 to 24, where the emitter further extends from a top surface of the base.

[00122] Example 26 includes the subject matter of any one of

Examples 18 to 25, where wherein at least one of the collector, the base or the emitter is laterally grown.

[00123] From the foregoing, it will be appreciated that example heterojunction bipolar transistors, electric devices including one or more such heterojunction bipolar transistors, example systems including one or more such heterojunction bipolar transistors, and methods of fabricating such heterojunction bipolar transistors have been disclosed. Example

heterojunction bipolar transistors disclosed herein have reduced leakage and higher frequency of operation. Example heterojunction bipolar transistors also enable high breakdown voltages. As such, example heterojunction bipolar transistors achieve higher performance and higher yield efficiency than known heterojunction bipolar transistors.

[00124] Although certain example methods, apparatus and articles of manufacture have been disclosed herein, the scope of coverage of this patent is not limited thereto. On the contrary, this patent covers all methods, apparatus and articles of manufacture fairly falling within the scope of the claims of this patent.

Claims

What Is Claimed Is:

1. A heterojunction bipolar transistor comprising:

a substrate;

a dielectric above the substrate, the dielectric having a trench extending therethrough;

a collector extending through the trench and above the dielectric;

a base laterally extending from the collector; and an emitter laterally extending from the base.

2. The heterojunction bipolar transistor as defined in claim 1, wherein the collector includes a first subcollector beneath a second sub collector.

3. The heterojunction bipolar transistor as defined in claim 2, wherein the first subcollector includes aluminum, gallium, nitride, and an n- dopant.

4. The heterojunction bipolar transistor as defined in any one of claims 2 or 3, wherein a portion of the second subcollector includes a generally trapezoidal profile.

5. The heterojunction bipolar transistor as defined in any one of claims 2 to 4, wherein the second subcollector has a first width in the trench and a second width above the trench, wherein the second width is greater than the first width.

6. The heterojunction bipolar transistor as defined in any one of claims 1 to 5, wherein the emitter includes an n- dopant.

7. The heterojunction bipolar transistor as defined in any one of claims 1 to 6, wherein the emitter includes aluminum, gallium and a nitride.

8. The heterojunction bipolar transistor as defined in any one of claims 1 to 7, wherein the emitter further extends from a top edge of the base.

9. The heterojunction bipolar transistor as defined in any one of claims 1 to 8, wherein at least one of the collector, the base or the emitter is laterally grown.

10. A method of producing a heterojunction bipolar transistor, the method comprising:

etching a dielectric to form a trench therein;

forming a collector in the trench, wherein the collector extends past a top surface of the dielectric;

forming a base to laterally extend from the collector; and forming an emitter to laterally extend from the base.

11. The method as defined in claim 10, wherein the collector includes a first subcollector beneath a second subcollector

12. The method as defined in claim 11, further including forming a first hard mask above the second subcollector.

13. The method as defined in claim 12, further including forming a second hard mask that laterally extends from the base.

14. The method as defined in claim 13, further including etching the second hard mask, wherein the emitter further extends from a top surface of the base.

15. The method as defined in claim 13, wherein the first hard mask has a first length and the second hard mask has a second length, the first length being larger than the second length.

16. The method as defined in any one of claims 11 to 15, wherein the forming of the collector includes epitaxially growing the second subcollector in horizontal and vertical directions.

17. The method as defined in any one of claims 10 to 16, further including forming emitter and collector contacts.

18. A system comprising:

a processing device including:

a communications chip; and

a heterojunction bipolar transistor including:

a substrate,

a dielectric above the substrate, the dielectric having a trench extending therethrough,

a collector extending through the trench and above the dielectric,

a base laterally extending from the collector, and an emitter laterally extending from the base.

19. The system as defined in claim 18, wherein the collector includes a first subcollector beneath a second subcollector.

20. The system as defined in claim 19, wherein the second subcollector has a first width in the trench and a second width proximate the base, wherein the second width is greater than the first width.

21. The system as defined in any one of claims 19 or 20, wherein the first subcollector includes aluminum, gallium, nitride and an n- dopant.

22. The system as defined in any one of claims 19 to 21, wherein lateral surfaces of the second subcollector include inclined lateral surfaces.

23. The system as defined in any one of claims 18 to 22, wherein the emitter includes an n- dopant.

24. The system as defined in any one of claims 18 to 23, wherein the emitter includes, aluminum, gallium and nitride.

25. The system as defined in any one of claims 18 to 24, wherein the emitter further extends from a top surface of the base.

26. The system as defined in any one of claims 18 to 25, wherein at least one of the collector, the base or the emitter is laterally grown.