WO2019139598A1

WO2019139598A1 - Ferroelectric neurons and synapses with dual gate ferroelectric transistors

Info

Publication number: WO2019139598A1
Application number: PCT/US2018/013404
Authority: WO
Inventors: Dmitri E. Nikonov; Seiyon Kim; Sasikanth Manipatruni; Ian A. Young
Original assignee: Intel Corporation
Priority date: 2018-01-11
Filing date: 2018-01-11
Publication date: 2019-07-18

Abstract

Described is an apparatus which comprises: a first gate including: a first structure comprising a first ferroelectric material; and a second structure adjacent to the first structure, wherein the second structure comprises a first gate electrode; a source adjacent to the first gate; a second gate including: a third structure comprising a second ferroelectric material; and a fourth structure adjacent to the third structure, wherein the fourth structure comprises a second gate electrode; a drain adjacent to the second gate; and a semiconductor body adjacent to the first and second gates, and between the source and the drain.

Description

FERROELECTRIC NEURONS AND SYNAPSES WITH DUAL GATE

FERROELECTRIC TRANSISTORS

BACKGROUND

[0001] A neural network is a computing system that performs inferences and leams patterns in the data by processing continuous signals with configurable circuit parameters and generally without task-specific programming. For example, a neural network may learn to identify a certain object from a picture/image. A neural network comprises a collection of processing units, called“neurons,” that communicate with other neurons via connections, generally referred to as“synapses”. A neural network generally has a few thousand to a few million units and millions of connections. Presently, most neural network algorithms are implemented in digital logic, which is inefficient and slow. Analog neuron circuits are inherently more efficient. However, forming a neural network using analog techniques and circuits requires numerous transistors to implement a neuron function. Conversely, spin/nanomagnets based neurons implement a neural network with many fewer elements. However, existing implementations are slow and power hungry.

BRIEF DESCRIPTION OF THE DRAWINGS

[0002] The embodiments of the disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure, which, however, should not be taken to limit the disclosure to the specific embodiments, but are for explanation and understanding only.

[0003] Fig. 1 illustrates a model of a neural gate comprising multiple input synapses and a neuron.

[0004] Fig. 2 illustrates a schematic of a neuron implemented with complementary metal oxide semiconductor (CMOS) transistors.

[0005] Fig. 3 illustrates a schematic of a synapse implemented with CMOS transistors.

[0006] Fig. 4 illustrates a ferroelectric double gate transistor that behaves as a synapse in a neural network, in accordance with some embodiments.

[0007] Fig. 5A illustrates a plot showing ferroelectric material hysteresis for different ferroelectric crystals.

[0008] Fig. 5B illustrates a plot showing ferroelectric capacitor hysteresis charge versus voltage. [0009] Fig. 6 illustrates a schematic of a ferroelectric neural gate, in accordance with some embodiments.

[0010] Fig. 7 A illustrates a cross-section of a material stack used for forming a ferroelectric layer of the ferroelectric double gate transistor, according to some embodiments.

[0011] Fig. 7B illustrates a cross-section of a super-lattice material stack used for forming a ferroelectric layer of the ferroelectric double gate transistor, according to some embodiments.

[0012] Fig. 8 illustrates a super-lattice of PbTiCF (PTO) with SrTiCb (STO) according to some embodiments of the disclosure.

[0013] Figs. 9A-B illustrate a layout of a device structure comprising ferroelectric neural gates, and a corresponding cross-section of a neural gate, respectively, in accordance with some embodiments.

[0014] Figs. 10A-R illustrate cross-sections showing formation of a ferroelectric neural gate, in accordance with some embodiments.

[0015] Fig. 11 illustrates a cross-section a double-gate ferroelectric transistor with threshold adjusting implant, according to some embodiments of the disclosure.

[0016] Fig. 12 illustrates a smart device or a computer system or a SoC (System-on-

Chip) having neural network formed of dual-gate ferroelectric transistors, according to some embodiments.

DETAILED DESCRIPTION

[0017] Some embodiments describe a neural gate circuit comprising double ferroelectric gate transistors as synapses and a ferroelectric capacitor as a neuron. In some embodiments, an input to the double ferroelectric gate transistor is encoded as a voltage pulse. For example, inputs are encoded as voltage pulses applied to one of the gates of the ferroelectric transistor synapse. In some embodiments, weights are encoded as a conductance of a segment of the transistor channel set by voltages applied to the other gate. In some embodiments, the output of the synapse (e.g., an output of the double gate transistor that receives an input voltage pulse and an encoded weight) is a product of the input voltage pulse and the weight. In some embodiments, the output current pulses from the double gate ferroelectric transistors are summed as a charge in a conventional capacitor. In some embodiments, this charge is enforced on a ferroelectric capacitor which provides the output voltage being a non-linear threshold function of the charge. In some embodiments, the output voltage is used as input to subsequent states of the neural network. In some embodiments, the ferroelectric gates of the double ferroelectric gate transistor comprises a super-lattice which is formed with PTO/STO (e.g., repeated 2 to 100 times). In some embodiments, the super-lattice comprises of materials with improper ferroelectricity (e.g., STO/PTO,

LuFe03/LuFe20₄) .

[0018] There are many technical effects of various embodiments. For example, the neural network formed by the double ferroelectric gate transistors use 20 times fewer number of regular transistors (e.g., complementary metal oxide semiconductor (CMOS) transistors) and thus much smaller area than analog or digital transistor based solutions. The operation energy of the neural network formed by the double ferroelectric gate transistors is much smaller than that of a neural network formed by CMOS transistors. The operation delay of the neural network formed by the double ferroelectric gate transistors is much smaller than that of the neural network formed by CMOS transistors. In some embodiments, the ferroelectric polarization in the double ferroelectric gate transistor of some embodiments holds weights as non-volatile memory. As such, weight voltages may persist even if the power to a processor is shut off or if a processor is put to a sleep state.

[0019] The neural network formed by the double ferroelectric gate transistors is also better in performance than spintronic neural networks. The double ferroelectric gate transistor of some embodiments has lower operation energy compared to spintronic neural network gate. For instance, the operation energy for a double ferroelectric gate transistor of some embodiments is less than 1 fj (femto Joule) instead of approximately 30 fJ per spintronic gate. The double ferroelectric gate transistor of some embodiments has lower operation delay compared to spintronic neural network gate. For example, the operation delay of a double ferroelectric gate transistor of some embodiments is approximately 300 picoseconds (ps) instead of approximately 10 nanoseconds (ns) per spintronic neural network gate. In some embodiments, the signal in neural network formed by the double ferroelectric gate transistors is carried by charge currents, and as such the distance from the input to the output nodes is not limited as in spin-based interconnects where spins degrade over a very short interconnect distance. Other technical effects will be evident from the various embodiments and figures.

[0020] In the following description, numerous details are discussed to provide a more thorough explanation of the embodiments of the present disclosure. It will be apparent, however, to one skilled in the art, that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring embodiments of the present disclosure.

[0021] Note that in the corresponding drawings of the embodiments, signals are represented with lines. Some lines may be thicker, to indicate more constituent signal paths, and/or have arrows at one or more ends, to indicate primary information flow direction. Such indications are not intended to be limiting. Rather, the lines are used in connection with one or more exemplary embodiments to facilitate easier understanding of a circuit or a logical unit. Any represented signal, as dictated by design needs or preferences, may actually comprise one or more signals that may travel in either direction and may be implemented with any suitable type of signal scheme.

[0022] Throughout the specification, and in the claims, the term "connected" means a direct connection, such as electrical, mechanical, or magnetic connection between the things that are connected, without any intermediary devices. The term "coupled" means a direct or indirect connection, such as a direct electrical, mechanical, or magnetic connection between the things that are connected or an indirect connection, through one or more passive or active intermediary devices. The term "circuit" or“module” may refer to one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. The term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data/clock signal. The meaning of "a," "an," and "the" include plural references. The meaning of "in" includes "in" and "on."

[0023] The terms“substantially,”“close,”“approximately,”“near,” and“about,” generally refer to being within +/- 10% of a target value (unless specifically specified).

Unless otherwise specified the use of the ordinal adjectives“first,”“second,” and“third,” etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.

[0024] For the purposes of the present disclosure, phrases“A and/or B” and“A or B” mean (A), (B), or (A and B). For the purposes of the present disclosure, the phrase“A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C). The terms “left,”“right,”“front,”“back,”“top,”“bottom,”“over,”“under,” and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions.

[0025] Fig. 1 illustrates a model 100 of a neural gate comprising multiple input synapses and a neuron. A neural gate circuit is a building block of neural networks. It produces an output T which is a non-linear function of an array of inputs x with n elements “x” and an array of stored weights“wi”, where T is an integer index. Model 100 expresses a neural gate function:

fix) = dil w + b . . . (1)

where g( ) is a step-like threshold function, and b is an offset that can be added to the sum. Here, the synapses perform the product of input‘x’ with its corresponding weights‘w’.

These synapses are elements of the neural gate executing analog multiplication. The neuron is the element performing summation of the synapse inputs and applying the non-linear threshold function. Figs. 2-3 illustrate complex CMOS implementations of neurons that use multiple transistors for a single synapse and single neuron.

[0026] Fig. 2 illustrates a schematic of a neuron 200 implemented with CMOS transistors. It comprises an input differential pair integrator (DPI) circuit used as a low-pass filter (MLI-3), a spike-event generating amplifier with current-based positive feedback (MAI- ₆), a spike reset circuit with refractory period functionality (MRI-₆) and a spike-frequency adaptation mechanism implemented by an additional DPI low-pass filter (MGI_-6).

[0027] The DPI block MLI-3 models the neuron’s leak conductance; it produces exponential sub-threshold dynamics in response to constant input currents. The neuron’s membrane capacitance is represented by the capacitor C_mem while Sodium channel activation and inactivation dynamics are modeled by the positive-feedback circuits in the spike- generation amplifier MAI-6. The spike-generation amplifier M,\ I -6. implements current-based positive feedback (modeling both sodium activation and inactivation conductances) and produces address-events at extremely low-power operation.

[0028] The reset MRI_-6 block models the Potassium conductance and refractory period functionality. The reset block (MRI-6) resets the neuron and keeps it in a resting state for a refractory period, set by the Vref bias voltage. The spike-frequency adaptation block MGI_-6 models the neuron’ s Calcium conductance that produces the after-hyper-polarizing current I_ahp, which is proportional to the neuron’ s mean firing rate. The spike-frequency adaptation block is a low-pass filter (MGI_-6) which integrates the spikes and produces a slow after hyper- polarizing current I_ahp responsible for spike-frequency adaptation.

[0029] Fig. 3 illustrates a schematic of a synapse 300 implemented with CMOS transistors. Synapse 300 is a DPI synapse circuit, including short term plasticity, and conductance-based functional blocks. The short-term depression block is implemented by MOSFETs M_SI-3; the basic DPI dynamics are implemented by the block Mni-e; the voltage gated channels are implemented by MNI-2, and conductance based voltage dependence is achieved with MGI-2.

[0030] However, when neuron 200 and synapse 300 are used in a neural network that includes millions of neuron 200 and synapse 300, the area and power of the integrated circuit becomes prohibitive.

[0031] The neural network of some embodiments formed by double ferroelectric gate transistors use 20 times fewer the number of regular transistors than those of neuron 200 and synapse 300 and thus a much smaller area and power. The operation energy of the neural network formed by the double ferroelectric gate transistors is much smaller per transistor than neuron 200 and synapse 300. For example, the operation energy for a neuron or synapse implemented by double ferroelectric gate transistor of some embodiments is less than 1 femto-Joules (fj) instead of 1 pico-Joules (pj) per CMOS neuron 200 or synapse 300. The operation delay of the neural network formed by the double ferroelectric gate transistors is much smaller than a CMOS neuron 200 and synapse 300. For example, the operation delay of a double ferroelectric gate neuron or synapse of some embodiments is approximately 300 picoseconds (ps) instead of approximately 10 nanoseconds (ns) per CMOS neuron 200 or synapse 300.

[0032] Fig. 4 illustrates a cross-section of ferroelectric double gate transistor 400 that behaves as a synapse in a neural network, in accordance with some embodiments. In some embodiments, transistor 400 is a five terminal device which comprises substrate 401, source region (or source) 402, drain region (or drain) 403, first gate including ferroelectric material 404a and contact 405a, and second gate including ferroelectric material 404b and contact 405b, and dielectric gate layer 406 (e.g., Si0₂, low-k dielectric, or high-k dielectric). The five terminals are the source terminal, drain terminal, first gate terminal, second gate terminal, and bulk/substrate/body terminal.

[0033] The first and second gates are positioned between the source region and the drain region. In some embodiments, the two gates are separated by oxide, and are independently controllable. In some embodiments, there is some overlap between the first gate and source 402, and some overlap between the second gate and drain 403. In some embodiments, a semiconductor body (e.g., having a channel region) is formed under the two gates electrically connecting the source and drain when applied voltages on Vgl and Vg2. Here, source voltage Vs is applied to the source terminal, drain voltage Vd is applied to the drain terminal, first gate voltage Vgl is applied to the first gate terminal, and Vg2 is applied to the second gate terminal. [0034] While ferroelectric double gate transistor 400 is shown as a high level double gate transistor, a person skilled in the art can adjust doping of the substrate, drain, and source regions to make the ferroelectric double gate transistor a p-type or n-type transistor.

According to the conductivity type of the ferroelectric double gate transistor, the polarity of the bias voltages Vgl and Vg2 can be adjusted to properly turn on the ferroelectric double gate transistor. In some embodiments, the thickness of ferroelectric material 404a is such that it does not exhibit the hysteresis.

[0035] For example, the polarization Pgl of ferroelectric material 404a and the corresponding charge in the semiconductor body (e.g., channel) under it is a function only of the value of Vgl. In some embodiments, the thickness of ferroelectric material 404b is such that it has hysteresis. For example, polarization Pg2 of ferroelectric material 404b can be partially switched between values Ps and -Ps along a vertical direction. In this case, polarization Pg2 is determined by the history of value and duration of pulses of voltage Vg2.

[0036] In some embodiments, a constant voltage Vs is applied to source 402 to create source-to-drain current while drain 403 serves as a current output. Below the threshold of the transistor, the current is approximately given by:

where Vds is the source-to-drain voltage, K , k' are constants determined by the transistor parameters, k_BT is the thermal energy. In some embodiments, the inputs are encoded as

( k-'R

and the weights are encoded as w_t = exp « 2 Thus, the output current

V ^kB^T

is proportional to / oc x w . In some embodiments, the input voltage is encoded to be in a range of -1 Volt (V) to 1 V. In some embodiments, the voltage of Vgl is below or at the threshold of ferroelectric material 404a or the threshold of the ferroelectric double gate transistor 400. In some embodiments, Vgl is applied to the first gate as a short pulse to pass sufficient charge through the transistor channel.

[0037] In some embodiments, a pulse of voltage Vg2 is applied to contact 404b to set channel conductance representing weight w; of equation (1). In some embodiments, the weight Wi sets a value of conductance of a segment under the second gate. In some embodiments, the voltage Vg2 is generated by another voltage source, and the voltage of weight Wi (e.g., voltage of Vg2) is below or near the threshold of the ferroelectric material 404b. In some embodiments, most of the voltage drop occurs under this segment of the channel formed between source 402 and drain 403. In some embodiments, the conductance of the channel under the second gate can be varied over a wide range by Vg2. In some embodiments, ferroelectric material 404b holds the charge associated with the weight w; as a non-volatile memory. As such, in some embodiments, additional circuitry and memory devices may not be required to maintain the voltage associated with weight w;.

[0038] In some embodiments, a capacitive device is charged by the drain current from transistor 400. In some embodiments, the drain current represents the product of the applied voltages x; and w;. As such, the complexity of circuit 300 of Fig. 3 is reduced to a single double gate ferroelectric transistor in accordance with various embodiments. While the embodiments are described with reference to double gate ferroelectric transistor, other non- ferroelectric double gate transistors can also be used to generate a drain current that represents the product of the applied voltages Xi and Wi. For example, the ferroelectric material 404a/b can be replaced with a non-ferroelectric high-K dielectric.

[0039] In some embodiments, the first gate is directly coupled or adjacent to dielectric layer 406. In one such embodiment there is no ferroelectric material 404a under first gate contact 405 a. For example, a regular high-k dielectric can be used instead of ferroelectric material 404a. All other connections and applications of voltages to the terminals remain the same as discussed above with reference to Fig. 4.

[0040] Fig. 5A illustrates plot 500 showing ferroelectric material (e.g., material

404a/b) hysteresis for different ferroelectric crystals— 100, 103, 118, and 001. A ferroelectric material exhibits ferroelectricity which is a property by which a spontaneous electric polarization can be revered by an electric field (e.g., applied voltage). When dielectric materials are polarized, the induced polarization‘P’ is almost exactly proportional to the applied external electric field E. In such materials, the polarization is a linear function of the applied electric field or voltage. Ferroelectric materials, on the other hand, demonstrate a spontaneous non-zero polarization even when the applied electric field E is zero. As such, the spontaneous polarization can be reversed by an applied electric field in the opposite direction. This results in a hysteresis loop because the polarization of a ferroelectric material is dependent not only on the present electric field but also on its history. The thresholding function of the neuron as described with reference to Fig. 1 (and equation 1) is similar to one of the branches of curve 100 in plot 500 which makes the ferroelectric material a great candidate for mimicking the threshold function of the neural gate function of equation 1.

[0041] Fig. 5B illustrates plot 520 showing ferroelectric capacitor hysteresis charge versus voltage. Plot 520 shows that there is a non-linear behavior or function of voltage versus charge for a ferroelectric capacitor. In some embodiments, one branch of the ferroelectric material hysteresis curve is used for thresholding function of a neuron without the need for polarization reversal.

[0042] Fig. 6 illustrates a schematic of a ferroelectric neural gate 600, in accordance with some embodiments. In some embodiments, a plurality of double gate transistors 601 i-_n, where‘n’ is an integer, are organized to receive a plurality of input voltages x; and weights Wi. For example, double gate transistor 601₁ receives xi and wi in electrodes marked Vgl and Vg2, respectively, double gate transistor 6OI₂ receives x₂ and w₂ in electrodes marked Vgl and Vg2, respectively, and double gate transistor 60l_n receives x_n and w_n in electrodes marked Vgl and Vg2, respectively. In some embodiments, Vs for all double gate transistors of the plurality is provided as a constant voltage to generate a source-to-drain current. The output drain current from each double gate transistor is summed as charge by capacitor 602, in accordance with some embodiments. For example, drain current II from double gate transistor 601₁, drain current 12 from double gate transistor 601₂, and drain current In from double gate transistor 60l_n are summed at capacitor 603. In some embodiments, capacitor 602 is any state of the art or conventional capacitor. Here, a first terminal of capacitor 602 is coupled to drains of each double gate transistor, and a second terminal of capacitor 602 is coupled to a second capacitor 603.

[0043] In some embodiments, the multiplication of input voltage x; and weight w; occurs below the threshold of the double gate transistor, and the drain current from the double gate transistor represents the product of input voltage x; and weight Wi. In some

embodiments, the non-linear function of the neural gate function of equation 1 is achieved by ferroelectric capacitor 603. In some embodiments, ferroelectric capacitor 603 comprises metal contact 603a (e.g., any suitable conducting material), ferroelectric material 603c (e.g., same as ferroelectric material 404a/b), and metal contact 603b. In some embodiments, by choosing the capacitance of ferroelectric capacitor 603 and different voltage biases for Vgl and Vg2 of the double gate transistors, a variety of non-linear functions can be realized.

[0044] In some embodiments, the output voltage Vo encoding the output value“xo” is used as input to subsequent states of the neural network. For example, the output“xo” is provided as input to a plurality of double gate transistors 604 i-_m, where‘m’ is an integer. In some embodiments, double gate transistors 604 belong to different neural gates, or in other words, connected to different neuron elements. As such, a cascaded network of neurons and synapses can be realized in accordance with some embodiments. In various embodiments, the voltage Vo is provided to the first gate electrodes of transistors 604. [0045] In some embodiments, ferroelectric capacitor 603 is formed in the backend of the die. Here, the term“backend” generally refers to a section of a die which is opposite of a “frontend” and where an IC package couples to IC die bumps. For example, high level metal layers (e.g., metal layer 6 and above in a ten metal stack die) and corresponding vias that are closer to a die package are considered part of the backend of the die. Conversely, the term “frontend” generally refers to a section of the die that includes the active region (e.g., where transistors are fabricated) and low level metal layers and corresponding vias that are closer to the active region (e.g., metal layer 5 and below in the ten metal stack die example). In some embodiments, ferroelectric capacitor 603 is formed in the frontend of the die.

[0046] Fig. 7A illustrates a cross-section of a material stack 700 used for forming a ferroelectric layer of the ferroelectric double gate transistor 400 and/or ferroelectric capacitor 604, according to some embodiments. In some embodiments, material stack 700 comprises a first conductive layer 70la, a layer 70lb comprising perovskite, a second conductive layer 70lc, and a conductive seed layer 70ld. In some embodiments, first and second conductive layers 70la/c are conductive oxides that include one of the following elements: Sr, Ru, La,

Sr, Mn, Nb, Cr, or O. In some embodiments, first and second conductive layers 70la c are conductive oxides which comprise: SrRuCL, (La,Sr)Co0₃ [LSCO], Lao_.s Sro_.s M n i _ _< N i _< O, Cu- doped SrFeo.9Nbo.1O3 , (La,Sr)Cr03.

[0047] In some embodiments, layer 702b comprising perovskite is sandwiched between first and second conductive layers 70la c such that layer 702b is adjacent to first and second conductive layers 70la/c. In some embodiments, layer 702b comprises a low leakage perovskite. Perovskites have cubic structure with a general formula of ABO3, where‘A’ includes one of an alkaline earth or rare earth element (e.g., Sr, Bi, Ba, etc.) while Έ’ is one of a 3d, 4d, or 5d transition metal element (e.g., Ti, Fe, etc.). In some embodiments, layer 702b includes one of SrTiCb, BiFeCb, BiTiCb, or BaTiCL.

[0048] In some embodiments, a seed layer (or starting layer) 70ld is deposited first and then layers 70lc, 70lb, 70la are deposited. In some embodiments, the seed layer 70ld is used to template the conductive layer 70 lc. In some embodiments, a seed layer 70 le is deposited in addition to or instead of 70ld. In some embodiment seed layer 70ld/e includes one of: Ti, Al, Nb, La, or STO (SrTiCL). In some embodiments, seed layer 70ld/e includes one of: TiAl, Nb doped STO, or La doped STO.

[0049] Fig. 7B illustrates a cross-section of a super-lattice material stack 720 used for forming a ferroelectric layer of the ferroelectric double gate transistor 400 and/or ferroelectric capacitor 604, according to some embodiments. The capacitor of Fig. 7B is similar to the capacitor of Fig. 7A except that perovskite layer 70lb is replaced by super lattice 70lb. In some embodiments, super lattice 80lb includes alternating layers of materials. For example, layer 802 comprises PbTiCF, layer 803 comprises SrTiCF, layer 804 comprises PbTiCF, and layer 806 comprises SrTiCF, and so on (e.g., 2 to 100 times). In some embodiments, one layer can be a non-polar oxide of the type (A^B^Cb) such as SrZrCb, and another layer can be a polar oxide of the type (A⁺¹B⁺⁵0₃ or A⁺³B⁺³0₃) such as LaAlCb and LaGaC , where‘A’ can comprise one of: La, Sr, Pb, Pr, Nd, Sm, Gd, Y, Tb, Dy, Ho, Er, Tm, Lu, Ce, Li, Na, K, Rb, or Ag, and Έ’ can comprise Ga, Al, Sc, In, Ta, Ti, or Zr.

[0050] As more alternating layers of PbTi03 and SrTi03 are added, the capacitor can store more charge. In some embodiments, the two or more layers of super lattice 70 lb has a thickness that extends from the first metal layer 70la to the second metal layer 70lc. In some embodiments the thickness is in a range of 2 nm (nanometers) to 100 nm. In some embodiments, the two or more layers of super lattice 70 lb have a width which is

perpendicular to the thickness, and wherein the width is in a range of 5 nm to 100 nm. In some embodiments, the super lattice is formed with PTO/STO (e.g., repeated 2 to 100 times) for capacitance enhancement. In some embodiments, the super lattice comprises of materials with improper ferroelectricity (e.g., STO/PTO, LuFe0₃/LuFe₂0₄).

[0051] Fig. 8 illustrates a super lattice 800 (e.g., 720) of PbTi0₃ (PTO) with SrTi0₃

(STO) according to some embodiments of the disclosure. Three super lattices are shown in Fig. 8. The first supper lattice (a) is FEz(T3- mode) giving rise to a polarization P_z. The second super lattice (b) is AFD_zo (M₄- mode) with oxygen rotation angle fzo. The third super lattice is AFD_{Zi (}IVL+ mode) with oxygen rotation angle f_z,. Charge is stored in rotational degree of freedom of oxygen atoms indicated by the rotational arrows in super lattice (a) and (c).

[0052] Figs. 9A-B illustrate a layout 900 of a device structure comprising ferroelectric neural gates, and a corresponding cross-section 920 of a neural gate, respectively, in accordance with some embodiments. Layout 900 shows at least two double gate ferroelectric FETs. Here, the first gate is shown in simplified form as 901 extending along the y direction, the second gate is shown in simplified form as 902 extending along the y direction, and fins 902 are shown extending along the x direction. While various embodiments are shown using FinFET technology as the base transistor technology, other types of transistor technologies can also be used for fabricating double-gate ferroelectric FETs. For example, planar transistors can be used for fabricating double-gate ferroelectric FETs. A cut AA’ along fin 903 for one portion 904 of a double-gate ferroelectric FET is illustrated by cross-section 920 of Fig. 9B.

[0053] Cross-section 920 illustrates a first ferroelectric gate region 921 and a second ferroelectric gate region 922, where both gate regions comprise substrate 923 (same as 401). In some embodiments, substrate 923 is a bulk silicon substrate. In some embodiments, substrate 923 is silicon-on-insulator. Substrate 923 may comprise other materials which may or may not be combined with silicon, such as: germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. While several examples of materials from which substrate 923 may be formed are described here, any material that may serve as a foundation upon which a semiconductor device may be built falls within the spirit and scope of the various embodiments.

[0054] In some embodiments, dielectric layer 406 is formed over substrate 923 such that the gates of the double-gate ferroelectric FET are adjacent to dielectric layer 406.

Dielectric layer 406 may comprise materials such as: SiCk, low-k dielectric, or high-k dielectric materials. In some embodiments, dielectric layer 406 comprises a material that has a dielectric constant that is greater than the dielectric constant of silicon dioxide. For example, dielectric layer 406 may have a dielectric constant that is at least about twice that of silicon dioxide (e.g., a dielectric constant that is greater than about 8).

[0055] When serving as the gate dielectric for the double-gate ferroelectric FET, in some embodiments, dielectric layer 406 is a high-k gate dielectric. Some of the materials that may be used to make high-k gate dielectrics include: hafnium oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. Although a few examples of materials that may be used to form dielectric layer 406 are described here, layer 406 may be made from other materials that serve to reduce gate leakage from the level present in devices that include silicon dioxide gate dielectrics.

[0056] In various embodiments, dielectric layer 406 may be formed on substrate 923 using a conventional deposition method, e.g., a conventional atomic layer chemical vapor deposition (“CVD”), low pressure CVD, or physical vapor deposition (“PVD”) process. In one such process, a metal oxide precursor (e.g., a metal chloride) and steam may be fed at selected flow rates into a CVD reactor, which is then operated at a selected temperature and pressure to generate an atomically smooth interface between substrate 923 and dielectric layer 406. The CVD reactor may be operated long enough to form a layer with a desired thickness. In some applications, dielectric layer 406 may be less than about 100 angstroms thick (e.g., between about 5 angstroms and about 60 angstroms thick).

[0057] As deposited, dielectric layer 406 may include undesirable impurities, e.g., hydrogen and/or unreacted metal, which render that layer incompatible with polysilicon. In some embodiments, an insulating layer (not shown) is formed on dielectric layer 406. In some embodiments, insulating layer is compatible with dielectric layer 406 and the two gate electrodes to be formed on the insulating layer. Insulating layer may comprise a single layer or multiple layers. In some embodiments, the insulating layer may be made from silicon nitride. Such a silicon nitride layer may be formed on dielectric layer 406 using conventional silicon nitride deposition techniques, e.g., conventional CVD, PVD or remote plasma processes. In some embodiments, such a process is used to form a silicon nitride layer that is between about 3 angstroms and about 25 angstroms thick. Such a silicon nitride insulating layer may comprise of a single silicon nitride layer, or alternatively comprise of a plurality of monolayers of silicon nitride.

[0058] It is understood that other materials that are compatible with both dielectric layer 406 and polysilicon, and that prevent polysilicon from interacting with dielectric layer 406, may be used instead— without departing from the spirit and scope of the various embodiments. In some embodiments, after insulating layer is formed on dielectric layer 406, the gate electrodes may be formed on the insulating layer. In some embodiments, the two gate electrodes are formed on dielectric layer 406 in the absence of the insulating layer.

[0059] Here, source and drain regions 924 (same as 401) and 925 (same as 402), respectively, are doped n-type or doped p-type materials depending on the conductivity type of the double-gate ferroelectric FET. Any suitable dopants may be used for forming source and drain regions 924 and 925. In some embodiments, there is some overlap between the first gate and source 924, and some overlap between the second gate and drain 925.

[0060] In some embodiments, in forming a p-type double-gate ferroelectric transistor, the source and drain regions 924/925, respectively, may be formed by selectively depositing epitaxial boron (B) doped silicon or SiGe with germanium concentrations up to 30%, as an example. For example, under the processing conditions of lOOsccm of dichlorosilane (DCS), 20slm ¾, 750-800°C, 20Torr, l50-200sccm HC1, a diborane (B2¾) flow of l50-200sccm and a GeH₄ flow of l50-200sccm, a highly doped SiGe film with a deposition rate of 20 nm/min, B concentration of 1E20 cm ³ and a germanium concentration of 20% is achieved.

A low resistivity of 0.7-0.9 mOhm-cm resulting from the high B concentration in the film provides the benefit of high conductivity in the tip source/drain regions and thereby reduced Rextemai. SiGe in the source/drain regions may exert compressive strain on the channel, which in turn results in enhanced mobility and improved transistor performance.

[0061] In some embodiments, in forming an n-type double-gate ferroelectric transistor, the source/drain regions 924/925 are formed, for instance, using in-situ

phosphorous doped silicon deposited selectively under processing conditions of 100 seem of DCS, 25-50 seem HC1, 200-300 seem of 1% P¾ with a carrier ¾ gas flow of 20 slm at 750°C and 20Torr. A phosphorous concentration of 2E20 cm ³ with a resistivity of 0.4-0.6 mOhm-cm is achieved in the deposited film.

[0062] In some embodiments, the first and second gates are formed above the dielectric layer 406 and by etching into an oxide region 926. The oxide region may comprise a low-k or dielectric material or a sacrificial dielectric layer such as Si02. Other inter- layer dielectric(s) (ILD) may also be used for region 926. Region 926 typically has the mechanical strength to withstand a planarization process such as chemical mechanical polishing (CMP).

[0063] In various embodiments, a pair of spacers 927 may be formed on either sides of the two gates in any well-known manner to isolate the source/drain regions 924/925 from the ferroelectric gates. In some embodiments, a layer of germanide (not shown) may be formed on top of the source/drain regions 924/925 if the source/drain regions 924/925 comprise Ge. Ordinary, well-known, anisotropic etching may be used to fabricate the spacers 927. In some embodiments, a carbon-doped nitride, doped with 5-13% carbon concentration is used for spacers 927.

[0064] Here, layers 928 (same as 404a) and 930 (same as 404b) comprise a ferroelectric material (also referred to as FE material 928). In some embodiments, ferroelectric materials 928/930 comprise a super-lattice which is formed with PTO/STO (e.g., repeated 2 to 100 times). In some embodiments, the super-lattice comprises of materials with improper ferroelectricity (e.g., STO/PTO, LuFe0₃/LuFe₂0₄) as described with reference to Figs. 7-8. For example, ferroelectric material 928 comprises a first conductive layer, a layer comprising perovskite, a second conductive layer, and a conductive seed layer. In some embodiments, the first and second conductive layers are conductive oxides that include one of the following elements: Sr, Ru, La, Sr, Mn, Nb, Cr, or O. In some embodiments, the first and second conductive layers are conductive oxides which comprise: SrRu0₃, (La,Sr)Co0₃ [LSCO], LaiLsSnLsMrii- NhO, Cu-doped SrFeo.9Nbo.1O3 , (La,Sr)Cr03. In some

embodiments, the layer comprising perovskite is sandwiched between the first and second conductive layers such that the layer is adjacent to the first and second conductive layers. In some embodiments, the layer comprises a low leakage perovskite. In some embodiments, the layer includes one of SrTiCb, BiFeCb, BiTiCF, or BaTi0₃. In some embodiments, a seed layer (or starting layer) is deposited first and then the other layers are deposited. In some embodiments, the seed layer is used to template the conductive layer. In some embodiment the seed layer includes one of: Ti, Al, Nb, La, or STO (SrTiCb). In some embodiments, the seed layer includes one of: TiAl, Nb doped STO, or La doped STO.

[0065] In some embodiments, ferroelectric materials 928/930 comprise: Barium titanate, Bismuth titanate, Germanium telluride, Lead titanate, Lead zirconate titanate, Lithium niobate, Potassium niobate, or Bismuth iron oxide, or super lattices of these materials. For example, super lattice of Barium titanate, Bismuth titanate, Germanium telluride, Lead titanate, Lead zirconate titanate, Lithium niobate, Potassium niobate, or Bismuth iron oxide. In some embodiments, ferroelectric materials 928/930 can be uniform materials (or any of the above materials) instead of super lattices.

[0066] In some embodiments, work-function metal 929 is deposited over the FE material 928 such that it is adjacent to the FE material 928 and the gate electrode 901. In some embodiments, work-function metal 931 is deposited over the FE material 930 such that it is adjacent to the FE material 930 and the gate electrode 902. In some embodiments, gate electrode layers 901/902 may be formed by blanket deposition of a suitable gate electrode material. In some embodiments, a gate electrode material for gate electrode layers 901/902 (same as 404a/b) may comprise a metal film such as tungsten, tantalum, titanium and/or nitrides and alloys thereof. For the n-channel transistors, metals with work function in the range of 3.9 to 4.6 eV may be used, such as Ag, Mo, Pb, Ti, V, Al, Bi, Cr, Zn, Nb, Ta, Zr.

For the p-channel transistors, metals with a work function of 4.6 to 5.2 eV may be used, such as Au, Be, Co, Cu, Ru, Ni, W, Fe, Ir, Pt. The difference of work function of the metals 929 and 931 is dependent on the choice of materials, contact potentials relative to them, and their coercive voltage (at which switching of polarization occurs).

[0067] Figs. 10A-R illustrate cross-sections 1000, 1020, 1030, 1040, 1050, 1060,

1070, 1080, 1090, 1100, 1110, 1120, 1130, 1140, 1150, 1160, 1170, and 1180, respectively, showing formation of a ferroelectric neural gate, in accordance with some embodiments. The processes described here are just one example of fabricating the dual-gate or double-gate ferroelectric transistor. Other ways are also possible for achieving the same or similar structure of the device.

[0068] Cross-section 1000 shows a possible starting point for fabricating the dual gate or double-gate ferroelectric transistor. Here, the process starts after deposition of dielectric layer 406 and after formation of source and drain regions 924/925 in substrate 923. In some embodiments, the process begins after poly dummy or extra gates are fabricated (e.g., one gate one for FE-FET 1 921 and another gate for FE-FET 2 922). Cross-section 1020 illustrates an ILD deposition of low-k material 926 over dielectric 406.

[0069] Cross-section 1030 illustrates etching of low-k dielectric 926 for gate regions

1031 and 1032. Cross-section 1040 illustrates deposition of spacer material 927 along the side walls of the etched region. Cross-section 1050 illustrates etching of spacer material along the x-surface of dielectric 406. In some embodiments, cross-section 1050 is achieved by removing poly plugs from dummy poly gates which leaves spacers 927 behind on the sidewalls of the removed ploy plugs.

[0070] Cross-section 1060 illustrates deposition of ferroelectric material 928 for first gate region and deposition of a protective plug (e.g., a photoresist) 1061 for the second gate region. Any known suitable material can be used for protective plug 1061. In some embodiments, protective plug 1061 is not deposited and ferroelectric material 928 is deposited for both gate regions and later etched such that the ferroelectric material 928 forms another sidewall adjacent to spacers 927 as shown by cross-section 1070. In some embodiments, ferroelectric material 928 is deposited as a thin layer adjacent to spacers 927 as shown by cross-section 1070 without the process of etching to make opening 1031.

[0071] Cross-section 1080 shows deposition of first work function metal (or metal 1)

929 for first gate region such that the work function metal 928 forms another sidewall adjacent to ferroelectric material 928. In some embodiments, first work function metal (or metal 1) 929 is deposited in opening 1031 and later etched to form sidewall as shown in cross-section 1080.

[0072] Cross-section 1090 illustrates etching or removal of protective plug 1061.

Cross-section 1100 shows deposition of protective plug 1101 (e.g., a photoresist) to fabricate the second gate region. Cross-section 1110 shows deposition of a second ferroelectric material 930 which is deposited such that it is adjacent to sidewalls of spacers 927. In some embodiments, second ferroelectric material 930 is different from first ferroelectric material 928. In some embodiments, second ferroelectric material 930 is same as first ferroelectric material 928 but with different thickness. For example, second ferroelectric material 930 is thicker (in the z direction) than the first ferroelectric material 928. In some embodiments, when the first and second ferroelectric materials are the same and of the same thicknesses, then protective plug 1101 may not be used. Cross-section 1120 shows deposition of second work function metal 931. In some embodiments, second work function metal 931 is different from first work function metal 929. In some embodiments, second work function metal 931 is same as first work function metal 929.

[0073] Cross-section 1130 illustrates deposition of another protection plug 1131 (e.g., a photoresist) to prepare for recessing of the gate regions. Cross-section 1140 illustrates the device after protection plug 1131 is recessed. Cross-section 1150 illustrates the device after the device is recessed further to expose metals 929 and 930, and protective plug 1101 is removed. Cross-section 1160 illustrates deposition of gate metal/fill 901/902. Cross-section 1170 shows the device after the gate metal fill is polished. Cross-section 1180 illustrates formation of contacts 1181 and 1182 to couple to source and drain regions 925 and 925, respectively. In some embodiments, contacts 1181 and 1181 may include one or more of: Ti, W, Al, Cu, Ag, Au, or Graphene.

[0074] Fig. 11 illustrates a cross-section 1190 a double-gate ferroelectric transistor with threshold adjusting implant, according to some embodiments of the disclosure. Fig. 11 is similar to Fig. 10R but for an implant region under the second gate region such that the implant region is adjacent to the drain 925 and extends laterally under the second gate region 1032 but not under the first gate region 1031. The function of the implant (e.g., BF₂ and other such implants) is to adjust the threshold of the second gate without affecting the threshold of the first gate.

[0075] Fig. 12 illustrates a smart device or a computer system or a SoC (System-on-

Chip) having neural network formed of dual-gate ferroelectric transistors, according to some embodiments. It is pointed out that those elements of Fig. 12 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. The supercapacitor of some

embodiments can be used to charge any or all blocks of SoC 2100, in accordance with some embodiments.

[0076] For purposes of the embodiments, the transistors in various circuits and logic blocks described here are metal oxide semiconductor (MOS) transistors or their derivatives, where the MOS transistors include drain, source, gate, and bulk terminals. The transistors and/or the MOS transistor derivatives also include Tri-Gate and FinFET transistors, Gate All Around Cylindrical Transistors, Tunneling FET (TFET), Square Wire, or Rectangular Ribbon Transistors, ferroelectric FET (FeFETs), or other devices implementing transistor functionality like carbon nanotubes or spintronic devices. MOSFET symmetrical source and drain terminals i.e., are identical terminals and are interchangeably used here. A TFET device, on the other hand, has asymmetric Source and Drain terminals. Those skilled in the art will appreciate that other transistors, for example, Bi-polar junction transistors (BJT PNP/NPN), BiCMOS, CMOS, etc., may be used without departing from the scope of the disclosure.

[0077] Fig. 12 illustrates a block diagram of an embodiment of a mobile device in which flat surface interface connectors could be used. In some embodiments, computing device 1600 represents a mobile computing device, such as a computing tablet, a mobile phone or smart-phone, a wireless-enabled e-reader, or other wireless mobile device. It will be understood that certain components are shown generally, and not all components of such a device are shown in computing device 1600.

[0078] In some embodiments, computing device 1600 includes first processor 1610 and network interface within 1670 such as a wireless interface so that a system embodiment may be incorporated into a wireless device, for example, cell phone or personal digital assistant. Any of the various blocks of computing device 1600 can have or use the super capacitor of various embodiments.

[0079] In some embodiments, processor 1610 can include one or more physical devices, such as microprocessors, application processors, microcontrollers, programmable logic devices, or other processing means. In some embodiments, processor 1610 includes neural network formed of double-gate ferroelectric transistors. In some embodiments, other blocks of SoC 1600 can also include neural network formed of double-gate ferroelectric transistors. The processing operations performed by processor 1610 include the execution of an operating platform or operating system on which applications and/or device functions are executed. The processing operations include operations related to I/O (input/output) with a human user or with other devices, operations related to power management, and/or operations related to connecting the computing device 1600 to another device. The processing operations may also include operations related to audio I/O and/or display I/O.

[0080] In some embodiments, computing device 1600 includes audio subsystem

1620, which represents hardware (e.g., audio hardware and audio circuits) and software (e.g., drivers, codecs) components associated with providing audio functions to the computing device. Audio functions can include speaker and/or headphone output, as well as microphone input. Devices for such functions can be integrated into computing device 1600, or connected to the computing device 1600. In one embodiment, a user interacts with the computing device 1600 by providing audio commands that are received and processed by processor 1610. [0081] In some embodiments, computing device 1600 comprises display subsystem

1630. Display subsystem 1630 represents hardware (e.g., display devices) and software (e.g., drivers) components that provide a visual and/or tactile display for a user to interact with the computing device 1600. Display subsystem 1630 includes display interface 1632, which includes the particular screen or hardware device used to provide a display to a user. In one embodiment, display interface 1632 includes logic separate from processor 1610 to perform at least some processing related to the display. In one embodiment, display subsystem 1630 includes a touch screen (or touch pad) device that provides both output and input to a user.

[0082] In some embodiments, computing device 1600 comprises I/O controller 1640.

I/O controller 1640 represents hardware devices and software components related to interaction with a user. I/O controller 1640 is operable to manage hardware that is part of audio subsystem 1620 and/or display subsystem 1630. Additionally, I/O controller 1640 illustrates a connection point for additional devices that connect to computing device 1600 through which a user might interact with the system. For example, devices that can be attached to the computing device 1600 might include microphone devices, speaker or stereo systems, video systems or other display devices, keyboard or keypad devices, or other FO devices for use with specific applications such as card readers or other devices.

[0083] As mentioned above, I/O controller 1640 can interact with audio subsystem

1620 and/or display subsystem 1630. For example, input through a microphone or other audio device can provide input or commands for one or more applications or functions of the computing device 1600. Additionally, audio output can be provided instead of, or in addition to display output. In another example, if display subsystem 1630 includes a touch screen, the display device also acts as an input device, which can be at least partially managed by I/O controller 1640. There can also be additional buttons or switches on the computing device 1600 to provide I/O functions managed by I/O controller 1640.

[0084] In some embodiments, I/O controller 1640 manages devices such as accelerometers, cameras, light sensors or other environmental sensors, or other hardware that can be included in the computing device 1600. The input can be part of direct user interaction, as well as providing environmental input to the system to influence its operations (such as filtering for noise, adjusting displays for brightness detection, applying a flash for a camera, or other features).

[0085] In some embodiments, computing device 1600 includes power management

1650 that manages battery power usage, charging of the battery, and features related to power saving operation. Memory subsystem 1660 includes memory devices for storing information in computing device 1600. Memory can include nonvolatile (state does not change if power to the memory device is interrupted) and/or volatile (state is indeterminate if power to the memory device is interrupted) memory devices. Memory subsystem 1660 can store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of the applications and functions of the computing device 1600. In some embodiments, Memory subsystem 1660 includes the scheme of analog in-memory pattern matching with the use of resistive memory elements.

[0086] Elements of embodiments are also provided as a machine-readable medium

(e.g., memory 1660) for storing the computer-executable instructions (e.g., instructions to implement any other processes discussed herein). The machine-readable medium (e.g., memory 1660) may include, but is not limited to, flash memory, optical disks, CD-ROMs, DVD ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, phase change memory (PCM), or other types of machine-readable media suitable for storing electronic or computer- executable instructions. For example, embodiments of the disclosure may be downloaded as a computer program (e.g., BIOS) which may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of data signals via a communication link (e.g., a modem or network connection).

[0087] In some embodiments, computing device 1600 comprises connectivity 1670.

Connectivity 1670 includes hardware devices (e.g., wireless and/or wired connectors and communication hardware) and software components (e.g., drivers, protocol stacks) to enable the computing device 1600 to communicate with external devices. The computing device 1600 could be separate devices, such as other computing devices, wireless access points or base stations, as well as peripherals such as headsets, printers, or other devices.

[0088] Connectivity 1670 can include multiple different types of connectivity. To generalize, the computing device 1600 is illustrated with cellular connectivity 1672 and wireless connectivity 1674. Cellular connectivity 1672 refers generally to cellular network connectivity provided by wireless carriers, such as provided via GSM (global system for mobile communications) or variations or derivatives, CDMA (code division multiple access) or variations or derivatives, TDM (time division multiplexing) or variations or derivatives, or other cellular service standards. Wireless connectivity (or wireless interface) 1674 refers to wireless connectivity that is not cellular, and can include personal area networks (such as Bluetooth, Near Field, etc.), local area networks (such as Wi-Fi), and/or wide area networks (such as WiMax), or other wireless communication. [0089] In some embodiments, computing device 1600 comprises peripheral connections 1680. Peripheral connections 1680 include hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) to make peripheral connections. It will be understood that the computing device 1600 could both be a peripheral device ("to" 1682) to other computing devices, as well as have peripheral devices ("from" 1684) connected to it. The computing device 1600 commonly has a "docking" connector to connect to other computing devices for purposes such as managing (e.g., downloading and/or uploading, changing, synchronizing) content on computing device 1600. Additionally, a docking connector can allow computing device 1600 to connect to certain peripherals that allow the computing device 1600 to control content output, for example, to audiovisual or other systems.

[0090] In addition to a proprietary docking connector or other proprietary connection hardware, the computing device 1600 can make peripheral connections 1680 via common or standards-based connectors. Common types can include a Universal Serial Bus (USB) connector (which can include any of a number of different hardware interfaces), DisplayPort including MiniDisplayPort (MDP), High Definition Multimedia Interface (HDMI), Firewire, or other types.

[0091] Reference in the specification to "an embodiment," "one embodiment," "some embodiments," or "other embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments. The various appearances of "an embodiment," "one embodiment," or "some embodiments" are not necessarily all referring to the same embodiments. If the specification states a component, feature, structure, or characteristic "may," "might," or "could" be included, that particular component, feature, structure, or characteristic is not required to be included. If the specification or claim refers to "a" or "an" element, that does not mean there is only one of the elements. If the specification or claims refer to "an additional" element, that does not preclude there being more than one of the additional element.

[0092] Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment anywhere the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive. [0093] While the disclosure has been described in conjunction with specific embodiments thereof, many alternatives, modifications and variations of such embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. The embodiments of the disclosure are intended to embrace all such alternatives, modifications, and variations as to fall within the broad scope of the appended claims.

[0094] In addition, well known power/ground connections to integrated circuit (IC) chips and other components may or may not be shown within the presented figures, for simplicity of illustration and discussion, and so as not to obscure the disclosure. Further, arrangements may be shown in block diagram form in order to avoid obscuring the disclosure, and also in view of the fact that specifics with respect to implementation of such block diagram arrangements are highly dependent upon the platform within which the present disclosure is to be implemented (i.e., such specifics should be well within purview of one skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the disclosure, it should be apparent to one skilled in the art that the disclosure can be practiced without, or with variation of, these specific details. The description is thus to be regarded as illustrative instead of limiting.

[0095] The following examples pertain to further embodiments. Specifics in the examples may be used anywhere in one or more embodiments. All optional features of the apparatus described herein may also be implemented with respect to a method or process.

[0096] Example 1. An apparatus comprising: a first gate including: a first structure comprising a first ferroelectric material; a second structure adjacent to the first structure, wherein the second structure comprises a metal having a first work function; and a third structure adjacent to the second structure, wherein the third structure comprises a gate electrode, wherein the first gate is adjacent to one of a source or drain; and a second gate including: a fourth structure comprising a second ferroelectric material; a fifth structure adjacent to the fourth structure, wherein the fifth structure comprises a metal having a second work function; and a sixth structure adjacent to the fifth structure, wherein the sixth structure comprises a second gate electrode, wherein the second gate is adjacent to one of the source or drain; and a semiconductor body adjacent to the first and second gates, and between the source and the drain.

[0097] Example 2. The apparatus of example 1, wherein the first or second ferroelectric materials include: a seventh structure comprising metal; an eighth structure comprising metal; and two or more structures coupled between the seventh and eighth structures, wherein the two or more structures include: a ninth structure comprising a conductive oxide, a tenth structure comprising a conductive oxide, and an eleventh structure comprising a perovskite, wherein the eleventh structure is adjacent to the ninth and tenth structures.

[0098] Example 3. The apparatus of example 2, wherein the two or more structures comprise a twelfth structure adjacent to one of the ninth or tenth structures, wherein the twelfth structure comprises a conductive seed structure.

[0099] Example 4. The apparatus of example 3, wherein the twelfth structure includes one of: Ti, Al, Nb, La, Sr, or O.

[00100] Example 5. The apparatus according to any of examples 1 to 4, wherein the seventh and eighth structures include one of: Sr, Ru, La, Sr, Mn, Nb, Cr, Ni, Cu, Fe, or O.

[00101] Example 6. The apparatus according to any of examples 1 to 4, wherein the eleventh structure includes one of: Sr, Ti, O, Bi, Fe, or Ba.

[00102] Example 7. The apparatus of example 3, wherein the eleventh structure includes a super lattice comprising: a first structure including Pb, Ti, and O; and a second structure comprising Sr, Ti, and O.

[00103] Example 8. The apparatus of example 7, wherein the first and second structures of the super lattice and are repeated in a range of 2 to 100 times.

[00104] Example 9. The apparatus according to any of the preceding examples, wherein the first and/or second ferroelectric materials include: Barium titanate, Bismuth titanate, Germanium telluride, Lead titanate, Lead zirconate titanate, Lithium niobate, Potassium niobate, or Bismuth iron oxide.

[00105] Example 10. The apparatus according to any of the preceding examples, wherein the first and/or second ferroelectric materials include: Ba, Ti, O, Bi, Ge, Te, Pb, Zr, Li, Nb, K, or Fe.

[00106] Example 11. The apparatus according to any one of the preceding examples, wherein the source and drain comprise n-doped material.

[00107] Example 12. The apparatus of example 1 comprises an implant adjacent to the second gate and the drain.

[00108] Example 13. The apparatus of example 1, wherein the first work function is same as the second work function.

[00109] Example 14. The apparatus of example 1, wherein the first work function is different from the second work function.

[00110] Example 15. The apparatus of example 1, wherein the metal of the second structure and/or fifth structure comprises: Ag, Mo, Pb, Ti, V, Al, Bi, Cr, Zn, Nb, Ta, or Zr. [00111] Example 16. The apparatus of example 1, wherein the metal of the second structure and/or fifth structure comprises: Au, Be, Co, Cu, Ru, Ni, W, Fe, Ir, or Pt.

[00112] Example 17. The apparatus of example 1, wherein the first and second gate electrodes includes one or more of: tungsten, tantalum, titanium or nitrogen.

[00113] Example 18. An apparatus comprising: a plurality of double gate transistors wherein each double gate transistor is to receive a first voltage and a second voltage on its respective first and second gates; and a capacitor having a first terminal and a second terminal, wherein the first terminal is coupled to one of source or drain terminals of each double gate transistor of the plurality of double gate transistors, wherein: the first gate comprises: a first structure comprising a first ferroelectric material; a second structure adjacent to the first structure, wherein the second structure comprises a metal having a first work function; and a third structure adjacent to the second structure, wherein the third structure comprises a gate electrode, wherein the first gate is adjacent to a source; and the second gate comprises: a fourth structure comprising a second ferroelectric material; a fifth structure adjacent to the fourth structure, wherein the fifth structure comprises a metal; and a sixth structure adjacent to the fifth structure, wherein the sixth structure comprises a second gate electrode, wherein the second gate is adjacent to a drain; and a semiconductor body adjacent to the first and second gates, and between the source and the drain.

[00114] Example 19. The apparatus of example 18 comprises a second capacitor including a ferroelectric material, wherein the second capacitor is coupled to the second terminal of the capacitor.

[00115] Example 20. The apparatus of example 19 comprises a second plurality of double gate transistors, wherein one of gate terminals of each double gate transistor of the second plurality is coupled to the second capacitor.

[00116] Example 21. The apparatus of example 19 comprises a first voltage source to apply a first encoded voltage to the first gate of a first double gate transistor of the plurality, and wherein the first encoded voltage is above a threshold level of a ferroelectric material, wherein the first voltage source is to apply the first encoded voltage as a pulse.

[00117] Example 22. The apparatus of example 21 comprises a second voltage source to apply a second encoded voltage to the second gate of the first double grate transistor of the plurality, wherein the second gate comprises a ferroelectric material, and wherein the second encoded voltage is close to the threshold level of the ferroelectric material.

[00118] Example 23. The apparatus of example 22, wherein the ferroelectric material is according to any one of examples 2 to 10. [00119] Example 24. A system comprising: a memory; a processor coupled to the memory, the processor including an apparatus according to any one of apparatus examples 1 to 17 or any one of apparatus examples 18 to 23; and a wireless interface to allow the processor to communicate with another device.

[00120] Example 25. A method comprising: forming a first gate including: forming a first structure comprising forming a first ferroelectric material; forming a second structure adjacent to the first structure, wherein forming the second structure comprises depositing a metal having a first work function; and forming a third structure adjacent to the second structure, wherein forming the third structure comprises forming a gate electrode, wherein the first gate is adjacent to one of a source or drain; and forming a second gate including:

forming a fourth structure comprising forming a second ferroelectric material; and forming a fifth structure adjacent to the fourth structure, wherein forming the fifth structure comprises depositing a metal having a second work function; forming a sixth structure adjacent to the fifth structure, wherein forming the sixth structure comprises forming a second gate electrode, wherein the second gate is adjacent to one of the source or drain; and forming a semiconductor body adjacent to the first and second gates, and between the source and the drain.

[00121] Example 26. The method of example 25, wherein forming the first and/or second ferroelectric materials include: forming a seventh structure comprising metal; forming an eighth structure comprising metal; and forming two or more structures coupled between the seventh and eighth structures, wherein forming the two or more structures include:

forming a ninth structure comprising a conductive oxide, forming a tenth structure comprising a conductive oxide, and forming an eleventh structure comprising a perovskite, wherein the eleventh structure is adjacent to the ninth and tenth structures.

[00122] Example 27. The method of example 26, wherein forming the two or more structures comprise forming a twelfth structure adjacent to one of the ninth or tenth structures, wherein forming the twelfth structure comprises forming a conductive seed structure.

[00123] Example 28. The method of example 27, wherein the twelfth structure includes one of: Ti, Al, Nb, La, or STO.

[00124] Example 29. The method according to any of preceding method examples, wherein the seventh and eighth structures include one of: Sr, Ru, La, Sr, Mn, Nb, Cr, Ni, Cu, Fe, or O. [00125] Example 30. The method according to any of preceding method examples, wherein the eleventh structure includes one of: Sr, Ti, O, Bi, Fe, or Ba.

[00126] Example 31. The method of example 26, wherein forming the eleventh structure includes forming a super lattice comprising: forming a first structure including Pb, Ti, and O; and forming a second structure comprising Sr, Ti, and O.

[00127] Example 32. The method of example 31, wherein the first and second structures of the super lattice and are repeated in a range of 2 to 100 times.

[00128] Example 33. The method according to any of the preceding method examples, wherein forming the first and/or second ferroelectric materials include forming one or more of: Barium titanate, Bismuth titanate, Germanium telluride, Lead titanate, Lead zirconate titanate, Lithium niobate, Potassium niobate, or Bismuth iron oxide.

[00129] Example 34. The method according to any of the preceding method examples, wherein the first and/or second ferroelectric materials include: Ba, Ti, O, Bi, Ge, Te, Pb, Zr, Li, Nb, K, or Fe.

[00130] Example 35. The method according to any one of the preceding method examples, wherein the source and drain comprise n-doped material.

[00131] Example 36. The method of example 25 comprises forming an implant adjacent to the second gate and the drain.

[00132] Example 37. The method of example 25, wherein the first work function is same as the second work function.

[00133] Example 38. The method of example 25, wherein the first work function is different from the second work function.

[00134] Example 39. The method of example 25, wherein the metal of the second structure and/or fifth structure comprises: Ag, Mo, Pb, Ti, V, Al, Bi, Cr, Zn, Nb, Ta, or Zr.

[00135] Example 40. The method of example 25, wherein the metal of the second structure and/or fifth structure comprises: Au, Be, Co, Cu, Ru, Ni, W, Fe, Ir, or Pt.

[00136] Example 41. The method of example 24, wherein the first and second gate electrodes includes one or more of: tungsten, tantalum, titanium or nitrogen.

[00137] Example 42. An apparatus comprising: a first gate including: a first structure comprising a first ferroelectric material; and a second structure adjacent to the first structure, wherein the second structure comprises a first gate electrode; a source adjacent to the first gate; a second gate including: a third structure comprising a second ferroelectric material; and a fourth structure adjacent to the third structure, wherein the fourth structure comprises a second gate electrode; a drain adjacent to the second gate; and a semiconductor body adjacent to the first and second gates, and between the source and the drain.

[00138] Example 43. The apparatus of example 43 further including: a fifth structure between the first and second structures, wherein the fifth structure comprises a metal having a first work function; and a sixth structure between the third and fourth structures, wherein the sixth structure comprises a metal with a second work function.

[00139] Example 44. The apparatus of any one of examples 42 to 43, wherein the first and/or second ferroelectric materials include: Barium titanate, Bismuth titanate, Germanium telluride, Lead titanate, Lead zirconate titanate, Lithium niobate, Potassium niobate, or Bismuth iron oxide.

[00140] Example 45. The apparatus of any one of examples 42 to 43, wherein the first and/or second ferroelectric materials include: Ba, Ti, O, Bi, Ge, Te, Pb, Zr, Li, Nb, K, or Le.

[00141] Example 46. The apparatus of any one of claims 42 to 45, wherein the source and drain comprise n-doped material.

[00142] Example 47. The apparatus of any one of examples 42 to 45 comprises an implant adjacent to the second gate and the drain.

[00143] Example 48. The apparatus of any one of examples 43 to 47, wherein the first work function is same as the second work function.

[00144] Example 49. The apparatus of any one of examples 43 to 47, wherein the first work function is different from the second work function.

[00145] Example 50. The apparatus of any one of examples 43 to 47, wherein the metal of the fifth structure and/or sixth structure comprises: Ag, Mo, Pb, Ti, V, Al, Bi, Cr,

Zn, Nb, Ta, or Zr.

[00146] Example 51. The apparatus of any one of examples 43 to 47, wherein the metal of the fifth structure and/or sixth structure comprises: Au, Be, Co, Cu, Ru, Ni, W, Fe,

Ir, or Pt.

[00147] Example 52. The apparatus of any one of examples 42 to 51, wherein the first and second gate electrodes includes one or more of: tungsten, tantalum, titanium or nitrogen.

[00148] Example 53. A method comprising: forming a first gate including: forming a first structure comprising a first ferroelectric material; and forming a second structure adjacent to the first structure, wherein forming a the second structure comprises forming a first gate electrode; forming a source adjacent to the first gate; forming a second gate including: forming a third structure comprising forming a second ferroelectric material; and forming a fourth structure adjacent to the third structure, wherein forming the fourth structure comprises forming a second gate electrode; forming a drain adjacent to the second gate; and forming a semiconductor body adjacent to the first and second gates, and between the source and the drain.

[00149] Example 54. The method of example 53 further including: forming a fifth structure between the first and second structures, wherein forming the fifth structure comprises forming a metal having a first work function; and forming a sixth structure between the third and fourth structures, wherein forming the sixth structure comprises forming a metal with a second work function.

[00150] Example 55. The method of any one of examples 53 to 54, wherein forming the first and/or second ferroelectric materials include: Barium titanate, Bismuth titanate, Germanium telluride, Lead titanate, Lead zirconate titanate, Lithium niobate, Potassium niobate, or Bismuth iron oxide.

[00151] Example 56. The method of any one of examples 53 to 54, wherein forming the first and/or second ferroelectric materials include: Ba, Ti, O, Bi, Ge, Te, Pb, Zr, Li, Nb,

K, or Le.

[00152] Example 57. The method of any one of examples 53 to 56, wherein the source and drain comprise n-doped material.

[00153] Example 58. The method of any one of examples 53 to 56 comprises an implant adjacent to the second gate and the drain.

[00154] Example 59. The method of any one of examples 53 to 58, wherein the first work function is same as the second work function.

[00155] Example 60. The method of any one of examples 53 to 59, wherein the first work function is different from the second work function.

[00156] Example 61. The method of any one of examples 53 to 60, wherein the metal of the fifth structure and/or sixth structure comprises: Ag, Mo, Pb, Ti, V, Al, Bi, Cr, Zn, Nb, Ta, or Zr. Example 62. The method of any one of examples 53 to 60, wherein the metal of the fifth structure and/or sixth structure comprises: Au, Be, Co, Cu, Ru, Ni, W, Fe, Ir, or Pt. Example 63. The method of any one of examples 53 to 62, wherein the first and second gate electrodes includes one or more of: tungsten, tantalum, titanium or nitrogen.

[00157] An abstract is provided that will allow the reader to ascertain the nature and gist of the technical disclosure. The abstract is submitted with the understanding that it will not be used to limit the scope or meaning of the claims. The following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.

Claims

CLAIMS We claim:

1. An apparatus comprising:

a first gate including: a first structure comprising a first ferroelectric material; a second structure adjacent to the first structure, wherein the second structure comprises a metal having a first work function; and a third structure adjacent to the second structure, wherein the third structure comprises a gate electrode, wherein the first gate is adjacent to one of a source or drain; and

a second gate including: a fourth structure comprising a second ferroelectric material; a fifth structure adjacent to the fourth structure, wherein the fifth structure comprises a metal having a second work function; and a sixth structure adjacent to the fifth structure, wherein the sixth structure comprises a second gate electrode, wherein the second gate is adjacent to one of the source or drain; and

a semiconductor body adjacent to the first and second gates, and between the source and the drain.

2. The apparatus of claim 1, wherein the first or second ferroelectric materials include:

a seventh structure comprising metal;

an eighth structure comprising metal; and

two or more structures coupled between the seventh and eighth structures, wherein the two or more structures include:

a ninth structure comprising a conductive oxide,

a tenth structure comprising a conductive oxide, and

an eleventh structure comprising a perovskite, wherein the eleventh structure is adjacent to the ninth and tenth structures.

3. The apparatus of claim 2, wherein the two or more structures comprise a twelfth structure adjacent to one of the ninth or tenth structures, wherein the twelfth structure comprises a conductive seed structure.

4. The apparatus of claim 3, wherein the twelfth structure includes one of: Ti, Al, Nb, La,

Sr, or O.

5. The apparatus according to any of claims 1 to 4, wherein the seventh and eighth structures include one of: Sr, Ru, La, Sr, Mn, Nb, Cr, Ni, Cu, Fe, or O.

6. The apparatus according to any of claims 1 to 4, wherein the eleventh structure includes one of: Sr, Ti, O, Bi, Fe, or Ba.

7. The apparatus of claim 3, wherein the eleventh structure includes a super lattice

comprising:

a first structure including Pb, Ti, and O; and

a second structure comprising Sr, Ti, and O.

8. The apparatus of claim 7, wherein the first and second structures of the super lattice and are repeated in a range of 2 to 100 times.

9. The apparatus according to any of the preceding claims, wherein the first and/or second ferroelectric materials include: Barium titanate, Bismuth titanate, Germanium telluride, Lead titanate, Lead zirconate titanate, Lithium niobate, Potassium niobate, or Bismuth iron oxide.

10. The apparatus according to any of the preceding claims, wherein the first and/or second ferroelectric materials include: Ba, Ti, O, Bi, Ge, Te, Pb, Zr, Li, Nb, K, or Fe.

11. The apparatus according to any one of the preceding claims, wherein the source and drain comprise n-doped material.

12. The apparatus of claim 1 comprises an implant adjacent to the second gate and the drain.

13. The apparatus of claim 1, wherein the first work function is same as the second work function.

14. The apparatus of claim 1, wherein the first work function is different from the second work function.

15. The apparatus of claim 1, wherein the metal of the second structure and/or fifth structure comprises: Ag, Mo, Pb, Ti, V, Al, Bi, Cr, Zn, Nb, Ta, or Zr.

16. The apparatus of claim 1, wherein the metal of the second structure and/or fifth structure comprises: Au, Be, Co, Cu, Ru, Ni, W, Fe, Ir, or Pt.

17. The apparatus of claim 1, wherein the first and second gate electrodes includes one or more of: tungsten, tantalum, titanium or nitrogen.

18. An apparatus comprising:

a plurality of double gate transistors wherein each double gate transistor is to receive a first voltage and a second voltage on its respective first and second gates; and a capacitor having a first terminal and a second terminal, wherein the first terminal is coupled to one of source or drain terminals of each double gate transistor of the plurality of double gate transistors, wherein:

the first gate comprises:

a first structure comprising a first ferroelectric material;

a second structure adjacent to the first structure, wherein the second structure comprises a metal having a first work function; and

a third structure adjacent to the second structure, wherein the third structure comprises a gate electrode, wherein the first gate is adjacent to a source; and

the second gate comprises:

a fourth structure comprising a second ferroelectric material;

a fifth structure adjacent to the fourth structure, wherein the fifth structure comprises a metal; and

a sixth structure adjacent to the fifth structure, wherein the sixth structure comprises a second gate electrode, wherein the second gate is adjacent to a drain; and

19. The apparatus of claim 18 comprises a second capacitor including a ferroelectric material, wherein the second capacitor is coupled to the second terminal of the capacitor.

20. The apparatus of claim 19 comprises a second plurality of double gate transistors, wherein one of gate terminals of each double gate transistor of the second plurality is coupled to the second capacitor.

21. The apparatus of claim 19 comprises a first voltage source to apply a first encoded

voltage to the first gate of a first double gate transistor of the plurality, and wherein the first encoded voltage is above a threshold level of a ferroelectric material, wherein the first voltage source is to apply the first encoded voltage as a pulse.

22. The apparatus of claim 21 comprises a second voltage source to apply a second encoded voltage to the second gate of the first double grate transistor of the plurality, wherein the second gate comprises a ferroelectric material, and wherein the second encoded voltage is close to the threshold level of the ferroelectric material.

23. The apparatus of claim 22, wherein the ferroelectric material is according to any one of claims 2 to 10.

24. A system comprising: a memory; a processor coupled to the memory, the processor including an apparatus according to any one of apparatus claims 1 to 17 or any one of apparatus claims 18 to 23; and a wireless interface to allow the processor to communicate with another device.

25. A method comprising:

forming a first gate including:

forming a first structure comprising forming a first ferroelectric material; forming a second structure adjacent to the first structure, wherein forming the second structure comprises depositing a metal having a first work function; and

forming a third structure adjacent to the second structure, wherein forming the third structure comprises forming a gate electrode, wherein the first gate is adjacent to one of a source or drain; and

forming a second gate including:

forming a fourth structure comprising forming a second ferroelectric material; and forming a fifth structure adjacent to the fourth structure, wherein forming the fifth structure comprises depositing a metal having a second work function;

forming a sixth structure adjacent to the fifth structure, wherein forming the sixth structure comprises forming a second gate electrode, wherein the second gate is adjacent to one of the source or drain; and forming a semiconductor body adjacent to the first and second gates, and between the source and the drain.