WO2019139592A1 - Systèmes et procédés de serdes ayant un canal arrière indirect - Google Patents

Systèmes et procédés de serdes ayant un canal arrière indirect Download PDF

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Publication number
WO2019139592A1
WO2019139592A1 PCT/US2018/013361 US2018013361W WO2019139592A1 WO 2019139592 A1 WO2019139592 A1 WO 2019139592A1 US 2018013361 W US2018013361 W US 2018013361W WO 2019139592 A1 WO2019139592 A1 WO 2019139592A1
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WIPO (PCT)
Prior art keywords
backchannel
information
integrated
lane
substrate
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PCT/US2018/013361
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English (en)
Inventor
Haoli Qian
Junqing Sun
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Credo Technology Group Limited
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Priority to PCT/US2018/013361 priority Critical patent/WO2019139592A1/fr
Publication of WO2019139592A1 publication Critical patent/WO2019139592A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M9/00—Parallel/series conversion or vice versa
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/0272—Arrangements for coupling to multiple lines, e.g. for differential transmission
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03343—Arrangements at the transmitter end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4904—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using self-synchronising codes, e.g. split-phase codes

Definitions

  • IEEE Institute of Electrical and Electronics Engineers
  • IEEE Std 802.3-2015 The Institute of Electrical and Electronics Engineers (IEEE) Standards Association publishes an IEEE Standard for Ethernet, IEEE Std 802.3-2015, which will be familiar to those of ordinary skill in the art to which this application pertains.
  • This standard provides a common media access control specification for local area network (LAN) operations at selected speeds from 1 Mb/s to 100 Gb/s over coaxial cable, twisted wire pair cable, fiber optic cable, and electrical backplanes, with various channel signal constellations.
  • LAN local area network
  • extensions to the standard must account for increased channel attenuation and dispersion even as the equalizers are forced to operate at faster symbol rates.
  • One potential course of action employs enhanced equalization techniques, which if not carefully implemented will unduly magnify the implementation cost and complexity of the system.
  • a first illustrative communications method embodiment is implemented by a transceiver module: (a) receiving, with an integrated receiver substrate, a receive signal on each of multiple receive lanes, the receive signals being sent by a remote node; (b) converting each said receive signal into a lane of a multi-lane receive data stream, wherein said converting includes demodulation and error measurement; (c) deriving remote adaptation information based at least in part on the error measurement; (d) conveying the remote adaptation information via a control bus to an integrated transmitter substrate; and (e) sending to the remote node, using the integrated transmitter substrate, a transmit signal on each of multiple transmit lanes, the transmit signals including the remote adaptation information on an embedded backchannel.
  • SerDes serializer-deserializer
  • a first illustrative transceiver module embodiment includes an integrated multi-channel receiver substrate that receives on each of multiple receive lanes a receive signal from a remote node and demodulates each of said receive signals into a lane of a multi-lane receive data stream.
  • the multi-channel receiver substrate also determines remote adaptation information based on errors measured during the demodulation process.
  • An integrated multi-channel transmitter substrate sends on each of multiple transmit lanes a transmit signal to the remote node, the multiple transmit signals including an embedded backchannel.
  • a control bus that conveys the remote adaptation information to the multi-channel transmitter substrate for communication via the embedded backchannel.
  • a second illustrative method embodiment is implemented by a transceiver module: (a) receiving, with an integrated receiver substrate, a receive signal on each of multiple receive lanes, the receive signals being sent by a remote node; (b) converting each said receive signal into a lane of a multi-lane receive data stream, wherein said converting includes demodulation and error measurement; (c) deriving remote adaptation information based at least in part on the error measurement; (d) using a module controller to collect the remote adaptation information from the integrated receiver substrate and to pass the remote adaptation information to the integrated transmitter substrate; and (e) sending from the integrated transmitter substrate to the remote node, a transmit signal on each of multiple transmit lanes, the transmit signals including the remote adaptation information on an embedded backchannel.
  • a second illustrative transceiver module embodiment includes an integrated multi channel receiver substrate that receives on each of multiple receive lanes a receive signal from a remote node and demodulates each of said receive signals into a lane of a multi-lane receive data stream, the multi-channel receiver substrate further determining remote adaptation information based on errors measured during the demodulation process.
  • An integrated multi-channel transmitter substrate sends on each of multiple transmit lanes a transmit signal to the remote node, the multiple transmit signals including an embedded backchannel.
  • a module controller obtains the remote adaptation information from the integrated receiver substrate and passes the remote adaptation information to the integrated transmitter substrate for inclusion on the embedded backchannel.
  • a third illustrative method embodiment is implemented by a network node: (a) receiving, with an integrated receiver substrate, a receive signal on each of multiple receive lanes, the receive signals being sent by a remote node; (b) converting each said receive signal into a lane of a multi-lane receive data stream, wherein said converting includes demodulation and error measurement; (c) deriving remote adaptation information based at least in part on the error measurement; and (d) collecting the remote adaptation information from the integrated receiver substrate with a host controller that communicates the remote adaptation information via a separate backchannel to the remote node.
  • An illustrative network node embodiment includes a transceiver module having an integrated multi-channel receiver substrate and an integrated multi-channel transmitter substrate.
  • the multi-channel receiver substrate receives on each of multiple receive lanes a receive signal from a remote node and demodulates each of said receive signals into a lane of a multi-lane receive data stream, the multi-channel receiver substrate further determining remote adaptation information based on errors measured during the demodulation process.
  • the multi channel transmitter substrate uses a pre-equalizer on each of multiple transmit lanes to send a transmit signal to the remote node.
  • the network node's host controller collects the remote adaptation information from the integrated receiver substrate and passes the remote adaptation information to the remote node using a separate backchannel, and further obtains backchannel information from the remote node and passes the backchannel information to the integrated transceiver substrate for adaptation of the pre-equalizers.
  • Each of the foregoing embodiments may be implemented individually or conjointly, and may be implemented together with any one or more of the following features in any suitable combination: (1) extracting backchannel information from at least one lane of the multi-lane receive data stream. (2) conveying the backchannel information via the control bus to the integrated transmitter substrate. (3) adapting pre-equalizers on the integrated transmitter substrate which are used for said sending. (4) the embedded backchannel is hidden by the transmitter substrate sending backchannel information fields in place of alignment markers in the transmit signals. (5) the integrated receiver substrate substitutes valid alignment markers for backchannel information fields in the multi-lane receive data stream. (6) the control bus is an I2C bus. (7) the transceiver module is an optical transceiver module.
  • the module controller collects and passes the backchannel information to the multi-channel transmitter substrate. (9) obtaining backchannel information from the remote node with the host controller, the host controller passing the backchannel information to the integrated transmitter substrate. (10) the separate backchannel includes a wireless communications link. (11) the separate backchannel includes a shared bus or a control channel. (12) the host controller uses a control channel to collect the remote adaptation information from the integrated receiver substrate and to pass the backchannel information to the integrated transmitter substrate.
  • FIG. 1 shows an illustrative communications network.
  • Fig. 2 is a block diagram of optical modules coupled to a network switch.
  • Fig. S is a diagram of a point-to-point multi-lane communications link model.
  • FIG. 4 is a block diagram of a transmit chain in an illustrative multi-lane transceiver.
  • Fig. 5 is a block diagram of a receive chain in an illustrative multi-lane transceiver.
  • Figs. 6A-6C show fields of an illustrative training frame.
  • Fig. 7A shows grouped alignment markers in an illustrative multi-lane data stream.
  • Fig. 7B shows an illustrative data stream having hidden backchannel fields.
  • FIG. 8 is a flowchart of an illustrative multi-lane communications receive method.
  • FIG. 9 is a flowchart of an illustrative multi-lane communications transmit method.
  • Fig. 1 shows an illustrative communications network 100 having communications links 108 interconnecting nodes 102, 104, 106 (representing switches, routers, base stations, gateways, and other forms of communications equipment) that direct and relay communications signals between terminal nodes 110-122 (which may represent mobile devices, portable computers, workstations, servers, network- attached storage systems, and other such communications sources and destinations).
  • the communications network 100 may be or include, for example, the Internet, a wide area network, or a local area network, and in addition to the physical cables may also include microwave, satellite, wifi, Bluetooth, and other forms of wireless communication links.
  • Communication links 108 may be fiberoptic cables having bundles of optical fibers each carrying multiple modulated light signals on corresponding channels. Many fiberoptic cables have multiple bundles of optical fibers, with each fiber carrying multiple channels. With such dense packing of information signals, highly integrated communications transceivers are advantageous for efficient interfacing with communications equipment. It is desirable to combine the integrated circuits for multiple transmitter modules and multiple receiver modules together in a multi-chip module to obtain a highly integrated, yet cost-effective, multi-channel transceiver.
  • FIG. 2 shows an illustrative network node 200 in the form of a network switch coupled to fiberoptic cables 202A, 202B by optical modules 204A, 204B, respectively, and further coupled to other communication links by transceiver modules 205A, 205B.
  • Transceiver modules 205A, 205B may also be optical modules that couple to optical fibers, or alternatively may be pluggable modules for front panel connections to copper cables, or transceivers for backplane bus connections.
  • the optical modules 204A, 204B act as a pluggable connector for coupling the optical fibers in fiberoptic cables 202A, 202B to the network node 200.
  • Optical module 204A includes an optical circulator 206 that couples incoming light signals from an optical fiber to a channel splitter 208, which separates the various channels and provides one to each detector 210.
  • the multiple detectors 210 each convert one of the light signals into an electrical receive signal.
  • An integrated multi-channel receiver 212 operates on the electrical receive signals to extract the corresponding streams of digital data.
  • An interface module 242A buffers the streams of digital data and disassembles the streams into data packets suitable for routing on the network switch's internal bus.
  • the conversion performed by the interface module includes error correction and payload extraction.
  • the interface module 242A also accepts packets of digital data for transmission.
  • the interface module 242A assembles the incoming data packets into streams with appropriate headers and end-of-frame markers, optionally adding a layer of error correction coding and/or a checksum.
  • a multi-channel transmitter 222 accepts the transmit data streams from interface module 242A and converts the digital signals into analog electrical drive signals for emitters 220, causing the emitters to generate optical signals that are coupled to a channel multiplexer 218.
  • the channel multiplexer 218 provides them as a combined optical signal to the circulator 206, which forwards it as an outgoing signal to an optical fiber in cable 202A.
  • Optical module 204A further includes an optical module controller 224 that sets operating parameters for the multi-channel receiver 212, the multi-channel transmitter 222, and other programmable components of the optical module 204A. Controller 224 coordinates the operations of the various optical module components and may further provide performance monitoring, fault detection, and a host interface for reporting and debugging.
  • the network switch provides multiple interface modules 242A-242D that each couple to an optical module or other form of communications link transceiver to send and receive high- rate data streams.
  • the interface modules 242A-242D are interconnected by internal buses for routing data packets between the link transceivers.
  • a switch controller 244 coordinates operation of the interface modules 242A-242D via a control bus 246 and provides exception handling and link performance monitoring.
  • At least some of the links 110 in network 106 are high-speed multi lane links such as Ethernet links operating in compliance with the IEEE Std 802.B-2015 (or later) at 10 Gb/s or more.
  • Fig. 3 shows a point-to-point communications link between two nodes 302A, 302B, that operate in accordance with the ISO/I EC Model for Open Systems Interconnection (See ISO/IEC 7498-1:1994.1) to communicate over a physical medium represented by transmit and receive channels 304, arranged in multiple lanes 306A, 306B.
  • the interconnection reference model employs a hierarchy of layers with defined functions and interfaces to facilitate the design and implementation of compatible systems by different teams or vendors.
  • a point-to-point communications link may include intermediate "repeater" nodes that implement a subset of the hierarchy. It is expected that the higher layers in the hierarchy will be implemented primarily by software or firmware operating on programmable processors in the terminal nodes while the lower layers may be implemented as application-specific hardware on the terminal nodes and intermediate network nodes, if any.
  • the Application Layer 308 is the uppermost layer in the model, and it represents the user applications or other software operating on different systems (e.g., terminal node 110), which need a facility for communicating messages or data.
  • the Presentation Layer 310 provides such applications with a set of application programming interfaces (APIs) that provide formal syntax, along with services for data transformations (e.g., compression), establishing communication sessions, connectionless communication modes, and negotiation to enable the application software to identify the available service options and select therefrom.
  • APIs application programming interfaces
  • the Session Layer 312 provides services for coordinating data exchange including: session synchronization, token management, full- or half-duplex mode implementation, and establishing, managing, and releasing a session connection. In connectionless mode, the Session Layer may merely map between session addresses and transport addresses.
  • the Transport Layer 314 provides services for multiplexing, end-to-end sequence control, error detection, segmenting, blocking, concatenation, flow control on individual connections (including suspend/resume), and implementing end-to-end service quality specifications.
  • the focus of the Transport Layer 314 is end-to-end performance/behavior.
  • the Transport Layer 314 and higher layers 308-310 would typically be implemented only in the terminal nodes of a communications network, and may be omitted from routers, switches, repeaters, and other such intermediate nodes of the communications network.
  • the Network Layer 316 provides a routing service, determining the links used to make the end-to-end connection and when necessary acting as a relay service to couple together such links.
  • the Data link layer B18 serves as the interface to physical connections, providing delimiting, synchronization, sequence and flow control across the physical connection. It may also detect and optionally correct errors that occur across the physical connection.
  • the Physical layer 322 provides the mechanical, electrical, functional, and procedural means to activate, maintain, and deactivate channels 304, and to use the channels 304 for transmission of bits across the physical media.
  • the Data Link Layer 318 and Physical Layer 322 are subdivided and modified slightly by IEEE Std 802.3-2015, which provides a Media Access Control (MAC) Sublayer 320 in the Data Link Layer 318 to define the interface with the Physical Layer 322, including a frame structure and transfer syntax.
  • MAC Media Access Control
  • the standard provides a variety of possible subdivisions such as the one illustrated in Fig. 3, which includes an optional Reconciliation Sublayer 324, a Physical Coding Sublayer (PCS) 326, a Forward Error Correction (FEC) Sublayer 328, a Physical Media Attachment (PMA) Sublayer 330, a Physical Medium Dependent (PMD) Sublayer 332, and an Auto-Negotiation (AN) Sublayer 334.
  • PCS Physical Coding Sublayer
  • FEC Forward Error Correction
  • PMA Physical Media Attachment
  • PMD Physical Medium Dependent
  • AN Auto-Negotiation
  • the optional Reconciliation Sublayer 324 merely maps between interfaces defined for the MAC Sublayer 320 and the PCS Sublayer 326.
  • the PCS Sublayer 326 provides scrambling/descrambling, data encoding/decoding (with a transmission code that enables clock recovery and bit error detection), block and symbol redistribution, PCS alignment marker insertion/removal, and block-level lane synchronization and deskew.
  • the PCS alignment markers include Bit- Interleaved-Parity (BIP) values derived from the preceding bits in the lane up to and including the preceding PCS alignment marker.
  • BIP Bit- Interleaved-Parity
  • the FEC Sublayer 328 provides, e.g., Reed-Solomon coding/decoding that distributes data blocks with controlled redundancy across the lanes to enable error correction.
  • the FEC Sublayer 328 modifies the number of lanes. For example, under proposed Article 134, a four-lane outgoing data stream (including PCS alignment markers) may be converted into a two- lane transmit data stream for lanes 306A, 306B. Conversely, the FEC Sublayer 328 may convert the two receive data streams from lanes 306A, 306B into a four-lane incoming data stream.
  • the PCS alignment markers may be preserved, yielding pairs (or more generally, "sets") of grouped PCS alignment markers in the multi-lane data streams being communicated to and from the PMA Sublayer SSO.
  • Article 91 provides for a 20-to-4 lane conversion, yielding sets of 5 grouped PCS alignment markers in each lane of the data streams communicated between the FEC and PMA sublayers.
  • the PMA Sublayer SSO provides lane remapping, symbol encoding/decoding, framing, and octet/symbol synchronization.
  • the PMD Sublayer 332 specifies the transceiver conversions between transmitted/received channel signals and the corresponding bit (or digital symbol) streams.
  • the AN Sublayer 334 implements an initial start-up of the communications channels 304, conducting an auto-negotiation phase and a link-training phase before entering a normal operating phase.
  • the auto-negotiation phase enables the end nodes to exchange information about their capabilities, and the training phase enables the end nodes to adapt both transmit- side and receive-side equalization filters in a fashion that combats the channel non-idealities.
  • Figs. 4 and 5 provide a block diagram of illustrative transmit and receive chains implementing the sublayers below the PCS. These illustrative transmit and receive chains are first described as implementing a hidden backchannel for communicating adaptation information for a transmit pre-equalizer. Other backchannel variations are then described.
  • the transmit chain in Fig. 4 accepts a four-lane data stream from the PCS.
  • the PCS data stream is already encoded with a transmission code that provides DC balance and enables timing recovery.
  • the PCS data stream lanes further include PCS alignment markers for synchronizing the lanes with each other.
  • an alignment marker removal module 402 removes the alignment markers from each lane, passing them to a downstream alignment marker insertion module 406.
  • a transcoding module 404 modifies the transmission code from a 64b/66b code to a 256b/257b code more appropriate for use with the Reed-Solomon encoder. By repeatedly transcoding four 66-bit blocks taken in parallel from the four incoming lanes into individual 257-bit blocks, the transcoding module may essentially convert the four lanes into a single lane data stream.
  • the previously-mentioned alignment marker insertion module 406 accepts the PCS alignment marker information from removal module 402 and the single-lane data stream from transcoding module 404.
  • the insertion module 406 combines the alignment marker information from the four lanes (in a manner discussed further below) to form a set of grouped alignment markers in a 257-bit block and, accounting for the operation of the transcoding module 404, inserts the alignment block in a fashion that preserves its location relative to the other data in the data stream 407.
  • the alignment block is designed to account for the operation of the encoder module 408 and symbol distribution modules 409 such that the alignment markers appear essentially intact and in order in the two- lane transmit data stream crossing boundary 410.
  • a Reed-Solomon (RS) encoder module 408 operates on blocks of 10-bit "symbols" of the data stream 407 from the insertion module 406, adding redundancy to enable downstream correction of symbol errors.
  • the encoder module 408 operates to preserve the original data stream content while appending so-called "parity” information, e.g., 30 parity symbol blocks appended to 514 data symbol blocks to form a complete code word block.
  • parity e.g., 30 parity symbol blocks appended to 514 data symbol blocks to form a complete code word block.
  • a symbol distribution module 409 distributes code word symbols across multiple transmission lanes in round-robin fashion, directing each lane to a corresponding transmitter.
  • Boundary 410 may be considered as the boundary between the FEC sublayer 228 and the PMA sublayer 230. Where it is desired to maintain this boundary as strongly as possible, the PMA sublayer may include an alignment marker detection module 411A (and 411B) for each lane of the transmit data stream to detect the alignment markers inserted by module 406 with suitable data buffering. Alternatively, this boundary can be relaxed and the alignment marker detection modules 411A, 411B omitted in favor of appropriate direct signaling from the alignment marker insertion module 406. In either case, the training control modules 420A, 420B control the multiplexers 412A, 412B in each lane, based at least in part on detection signals indicating the presence of the alignment markers.
  • Multiplexers 412A, 412B forward the encoded data streams to serializer modules 414A, 414B during normal operations and in the absence of alignment markers.
  • the multiplexers supply negotiation and training data streams from the training control modules 420A, 420B to the serializers.
  • the multiplexers 412A, 412B (acting as alignment marker replacement modules) supply the serializer modules with modified alignment markers as discussed further below.
  • the serializers 414A, 414B each accept a stream of transmit data blocks and convert the stream of blocks into a (higher-rate) stream of channel symbols. Where, for example, a 4-PAM signal constellation is employed, each serializer may produce a stream of two- bit symbols.
  • Each stream of channel symbols is filtered by a pre-equalizer module 416A, 416B to produce a transmit signal, which is amplified and supplied to the transmit channel by a driver 418A, 418B.
  • the pre-equalizer modules compensate for at least some of the channel dispersion, reducing or eliminating the need for receiver-side equalization.
  • Such pre-equalization may be advantageous in that it avoids the noise enhancement often associated with receiver-side equalization and enables digital filtering with a reduced bit-width.
  • the bit width reduction directly reduces power consumption by requiring a less complex filter, but may further reduce power consumption by obviating the parallelization that a more complex filter might require to operate at the required bandwidth.
  • pre-equalization generally requires knowledge of the channel.
  • One or more training controllers 420A, B operate to characterize the channel after conducting an initial auto-negotiation phase.
  • at least one training controller generates a sequence of auto-negotiation frames conveying capabilities of the local node to the remote node and negotiating to select a combination of features to be used for subsequent communications.
  • each training controller When the auto-negotiation phase is complete, each training controller generates a sequence of training frames, so that training is carried out independently on each of the lanes.
  • the training frame 602 begins with a frame marker 604 indicating the start of the training frame.
  • the frame marker 604 is followed by a coefficient update field 606, a status report field 608, and a training pattern 610.
  • the preceding fields are sent using differential Manchester encoding to facilitate timing recovery and ensure reliable communication even with untrained equalizers.
  • Fig. 6B shows an illustrative coefficient update field 606, having a two-bit request field 612 to indicate whether a selected coefficient should be incremented, decremented, maintained at the present value, or disabled; a six-bit selection field 614 to select one of up to 64 pre equalizer coefficients; a two-bit modulation field 616 to select a desired modulation scheme (e.g., 2-PAM, 4-PAM, with or without precoding); a one-bit filter length field 618 to indicate whether the pre-equalization filter should be short (no more than four coefficients) or long (more than four coefficients); and a two-bit initialization request field 620 to select a pre-programmed set of pre-equalization coefficient values.
  • the unlabeled fields may be reserved for future use.
  • the training controller(s) may use the coefficient update field 606 to convey backchannel information, i.e., adjustments to the pre-equalization filter coefficients of the remote transmitter.
  • Fig. 6C shows an illustrative status report field 608, having a three-bit coefficient status field 622 to report a successful update to a coefficient, an unsuccessful update, or an error condition (e.g., coefficient not supported, maximum voltage or coefficient limit reached); a one- bit and five-bit (totaling six bit) coefficient selection echo field 624 to echo back the coefficient selection from the remote node; a one bit initial condition status field 626 to report successful or unsuccessful setting of the coefficient values to an initial set of preprogrammed values; a one-bit lock status field 628 to indicate whether the receiver has achieved frame lock; a modulation status field 630 to report which modulation scheme is being employed by the transmitter; and a one-bit receiver ready field 632 to indicate whether the local node has finished training and is ready to begin data transmission.
  • the training controller(s) may use the status report field 608 to convey confirmations and other local status information to the remote node.
  • the one or more training controllers 420A, B receive backchannel information extracted by the receiver from the received data stream and use the backchannel information to adjust the coefficients of the pre-equalization filters.
  • the controllers further receive "remote info", which includes locally-generated information for adapting the coefficients of the pre-equalization filter in the remote node. Based on this information the controllers populate the coefficient selection field 614 and request field 612 of the training frames to provide backchannel information to the remote node.
  • the training controller(s) 420 may include similar backchannel information in or with the modified alignment markers supplied via multiplexers 412A, 412B during normal operations.
  • the 10-bit symbol blocks of data stream 407 can conceptually be arranged into two lanes in anticipation of the operation of symbol distribution module 409, which places adjacent symbol blocks in alternate lanes.
  • Fig. 7A shows a 514 symbol message word 702 (corresponding to the length of twenty 257-bit blocks from transcoding module 404) in this fashion, with broken outline for the 30 parity symbols 719 to be appended by the Reed-Solomon encoder 408 to form a complete 544 symbol code word.
  • the spacing of the alignment markers in the four-lane PCS data stream is such that when a set of grouped alignment markers are inserted in the data stream 407, the grouped alignment markers form the first 257 bits of a message word 702 (and also the first 257 bits of the resulting Reed-Solomon codeword) while data blocks 718 occupy the remainder of the message word.
  • the information from the four PCS data stream alignment markers are arranged in alternating 10-bit symbol blocks so that within each lane the information appears, in order, and as essentially intact PCS alignment markers 704, 706, 708, and 710.
  • a one-bit pad 714 is appended to the grouped alignment markers. Moreover, within these first 257 bits of the message word 702, the alignment markers don't align well with the 10-bit symbol block boundaries. To fill out a full 10-bit symbol in lane 0, a 2-bit portion of marker 710 is excerpted from position 712.
  • the alignment markers in the four lane PCS data stream carry bit-interleaved parity values (A, B, C, D in inverted and non-inverted versions) and employ unique marker (UM) patterns that are lane specific.
  • the alignment insertion module 406 modifies the pattern of alignment marker 706 to agree with that of alignment marker 704, so that they share a common marker (CM) pattern to facilitate detection and synchronization of the two lanes at the receiver.
  • CM common marker
  • the BIP values are preserved. While alignment makers 708, 710 could in theory be used to make the synchronization process more robust, their presence is only necessary for identifying lanes at the beginning of the communications process and thereafter only to convey the contents of their BIP fields.
  • multiplexers 412A, 412B may replace the sets of grouped alignment markers with modified versions, e.g., as shown in Fig. 7B.
  • the replacements begin only after a "settling period" (e.g., for one second after the multi-lane communications begin) or after a predetermined number (e.g., 100) of grouped alignment markers have been sent, with all sets of grouped alignment markers being modified thereafter.
  • the replacements occur periodically, with 1 out of every 2 sets being replaced, or 2 out of 3, or (N-l) out of N, with N potentially ranging as high as 10 5 to provide at least one unmodified set on the order of once per second.
  • the replacement may occur on an as-needed basis, e.g., when degradation or drift is observed in the performance of the equalizers. In these as-needed embodiments, the replacements may begin upon detection of the reduced performance and continue until training convergence is achieved.
  • Fig. 7B the UM alignment markers 708 and 710 are replaced in their entireties by a backchannel adaptation field 722 having 66 bits and a backchannel status field 724 having 63 bits (including the former pad bit 714).
  • the backchannel information is extracted and the alignment markers 708, 710 restored with placeholders for the lost BIP (inverted and non- inverted) values.
  • the BIP values are no longer essential for determining bit error rates, and in this implementation the BIP values are sacrificed for additional backchannel bandwidth that will not substantively impact the operation or throughput of the higher sublayers and layers.
  • the backchannel information field(s) of the modified alignment markers may provide a six-bit field for selecting pre-equalization filter coefficients; a two-bit field for specifying that the selected coefficient should be incremented, decremented, maintained, or disabled; and perhaps a one-bit field for indicating whether the backchannel information field contains a valid command or should be ignored.
  • the backchannel information field(s) may further provide a status report, with a six-bit field for echoing a filter coefficient selection; a two-bit field for indicating whether the coefficient has been updated, not updated, is at its limit, or is not supported; and perhaps a one-bit field for indicating that the receiver has obtained a lock on the lane alignments.
  • each coefficient of the pre-equalization filter may have a bit pair allocated within the modified alignment markers to indicate (in the adaptation field) whether that coefficient should be incremented, decremented, maintained, or disabled; or (in the status field) to indicate whether that coefficient is maximized, minimized, updated, or not updated.
  • the backchannel information fields of the modified alignment markers may be encoded using differential Manchester encoding to ensure reliable delivery. Additionally or alternatively, reliability of the backchannel information field delivery may be enhanced using other techniques.
  • the backchannel information field may be sent redundantly, using multiple copies of a field to enable error detection and (for three or more copies) voting-based error correction.
  • a standards-compliant alignment marker includes a bitwise-inverted duplication of each element, which can be extended to include the backchannel information field. If an odd number of copies is desired, the last field may be partly inverted.
  • a parity check or short FEC code may also provide controlled redundancy enabling the detection and possible correction of bit errors.
  • the receive chain obtains analog electrical signals from different receive channels (indicated by LaneO-rx and Lanel-rx).
  • Low noise amplifiers (LNA) 502A,B each provide a high input impedance to minimize channel loading and amplifies the receive signal to drive the input of a continuous time linear equalizer (CTLE) filter 504A,B.
  • CTL continuous time linear equalizer
  • CTLE filters 504A,B provide continuous time filtering to shape the receive signal spectrum in an adaptive fashion to reduce the length of the channel impulse response while minimizing leading inter-symbol interference (ISI).
  • Decision feedback equalizers (DFE) 506A,B operate on the filtered signals to correct for trailing ISI and detect each transmitted channel bit or symbol, thereby producing a demodulated digital data stream. Some embodiments employ oversampling.
  • Clock recovery and adaptation modules 508A,B derive a sampling clock signal from the input and/or output of the DFE's decision element and supply it back to the DFE to control timing of the symbol detection.
  • the adaptation modules 508A,B further derive an error signal of the DFE decision element's input relative to the output or (during the training phase) to a known training pattern, and use the error signal to adapt the DFE coefficient(s) and the response of the CTLE filters.
  • the adaptation modules still further use the error signal to generate "remote info", i.e., adaptation information for the remote pre-equalizers. This remote info is supplied to the training controller(s) 420 (Fig. 4).
  • Deserializers 509A,B group the digital receive data stream bits or symbols into blocks to enable the use of lower clock rates for subsequent on-chip operations.
  • Alignment marker detection modules 510A, 510B monitor the receive data stream to detect the CM pattern of the alignment markers and achieve alignment marker lock during normal operations, or during training operations to detect the training frame markers and achieve lock thereto.
  • the backchannel information extraction modules 511A, 511B extract the backchannel information from the appropriate portions of the training frames and alignment markers, providing the pre equalizer adaptation information and status report information to the training controller(s) 420.
  • the multiplexers 512A, 512B operating under control of the extraction modules 511A, 511B, replace the modified alignment markers with sets of grouped PCS alignment markers, thereby hiding the backchannel information fields from the higher layers.
  • the receive chain may impose a hard boundary 526 between the PMA sublayer and the FEC sublayer, or alternatively, the alignment marker detection information may be communicated to the FEC lane deskew module 513.
  • the receive data streams from the deserializers are aligned by an FEC lane deskew module 513. If the FEC lanes have somehow gotten switched, an FEC lane reordering module 514 detects the switch based on the contents of the alignment markers and compensates for the switch as the two lanes are multiplexed on a symbol-block basis into a single lane. An RS decoder module 516 operates on the single lane data stream to detect and correct any symbol errors, removing the FEC coding redundancy (parity symbols) during the decoding process.
  • a transcoding module 520 converts the 256b/257b transmission code words into blocks of four 64b/66b transmission code words distributing the 66-bit code word blocks across four PCS lanes.
  • An alignment marker insertion module 524 converts the sets of grouped alignment markers into individual alignment markers having lane-specific UM patterns, and inserts the individual alignment markers at appropriate positions in the four lanes, accounting for the operation of the transcoding module 520.
  • the four lane PCS data stream is provided to the higher hierarchy layers of the node for eventual communication of the conveyed data to the destination application.
  • the DFE feedback filter may be kept quite short, at say 1 or 2 taps, and even when the channel has a relatively lengthy channel response, the pre-equalization filter may obviate the need for a long digital feed forward equalizer (FFE) filter.
  • FFE digital feed forward equalizer
  • the transmit and receive chains for a given link share a common substrate
  • the training controllers can also be directly coupled to other receive chain components to receive auto-negotiation phase information from the remote end of the link.
  • the receive chains of multi-channel receiver 212 are expected to be integrated on a separate substrate from the transmit chains of multi-channel transmitter 222. While it may be technically possible in a multi chip module to provide dedicated connections for directly coupling the noted receive chain modules to the training controller modules in the transmit chains (e.g., via an interposer), it is not expected that this is always the case at higher levels of integration.
  • the bit rates associated with the remote adaptation and backchannel information for each lane (hereafter collectively referred to as the "training information”) will be substantially smaller than the lane's bit rate. While the ratio depends on a number of design factors, even a conservative calculation indicates that the training information conveyed between receive and transmit chains for each lane requires a bit rate no larger than 1/8192 of the lane's bit rate. It is expected that even lower bit rates can be achieved with negligible performance loss.
  • the training information can be conveyed via a bus or an indirect route.
  • optical module controller 224 can poll registers of the multi-channel receiver 212 to retrieve the training information and write that training information to corresponding registers in multi-channel transmitter 222.
  • the multi-channel receiver chip may employ a local control bus, such as an inter- integrated circuit ("I2C") bus, to communicate the training information to the multi-channel transmitter chip.
  • I2C inter- integrated circuit
  • Such a bus may serve multiple purposes including the providing of start-up configuration information and collecting of debugging information.
  • the interface modules 242 may convey the training information between the receive chain and transmit chain for each lane.
  • the multi-channel receiver 212 may insert provide an extra PCS lane having code words for conveying the training information to the interface module 242A, which the interface module then forwards to the multi-channel transmitter 222.
  • the training information code words may be inserted into one of the existing PCS lanes, or systematically distributed across each of the existing PCS lanes, for the interface module to transfer to the PCS lanes being sent to the multi-channel transmitter 222.
  • a separate control bus e.g., an I2C bus
  • the training information conveyed by the multi-channel receiver 212 to the interface module 242A may just include the remote adaptation information, and this information may in turn be obtained by the switch controller 244 via the control bus 246.
  • the switch controller 244 may employ an external bus or separate communication link to send the remote adaptation information to the remote end of the communications link, and to receive backchannel information from the remote end of the communications link.
  • the external bus or separate communications link may be, e.g., a wireless link, a shared bus, a control channel, or another such supporting communications link.
  • the backchannel information can then be provided via the control bus 246 to interface module 242A, which in turn can provide the backchannel information to the multi-channel transmitter 222 for adaptation of the pre equalizers.
  • the transceiver module is coupled to a host such as a server, an I/O bus controller or a central processing unit (CPU) may be configured to perform the above- described operations of the switch controller 244.
  • Fig. 8 is a flow diagram of an illustrative receive method.
  • the receive chain obtains receive signals on one or more receive lanes.
  • the receive signals should begin with initialization signals designed to enable fast timing synchronization and determination of frame boundaries.
  • the receive chain determines whether timing synchronization has been achieved, and if not, control returns to block 802 for further attempts to achieve synchronization.
  • the receive chain sends a "Ready to Train” notification to the transmit chain in block 806.
  • This notification gets communicated to the remote end of the communications link as described elsewhere.
  • the receive chain obtains receive signals on one or more receive lanes. By this time, the receive signals should include training patterns suitable for adaptation of the filter coefficients.
  • the receive chain filters and demodulates the receive signals, thereby obtaining receive data and error signals.
  • the receive data signals may include backchannel information as discussed previously.
  • the receive chain extracts the backchannel information and derives adaptation information for both the local filter coefficients and the remote (pre-equalizer) filter coefficients.
  • the receive chain sends training information (including the backchannel information and the remote adaptation information) to the transmit chain.
  • the receive chain adapts the local filter coefficients based on the adaptation information.
  • the receive chain determines whether convergence has been achieved (e.g., because the error is sufficiently negligible and/or the filter coefficient values have stabilized). If not, control returns to block 808 to perform further training.
  • the receive chain sends a "Training Complete" notification to the transmit chain.
  • This notification gets communicated to the remote end of the communications link as described elsewhere, enabling the remote end to begin sending user data when ready.
  • the operations in blocks 822-830 largely parallel the operations of blocks 808-816, with more conservative adaptation rates designed to track slow channel variations rather than to achieve rapid convergence.
  • Fig. 9 is a flow diagram of an illustrative transmit method.
  • the transmit chain begins sending initialization signals on one or more transmit lanes.
  • initialization signals are designed to enable rapid timing synchronization at the receiver and delineation of frame boundaries.
  • the transmit chain determines whether a "ready to train" notification has been received via a backchannel from the remote end of the link. If not, control returns to block 902 for further transmission of initialization signals.
  • the transmit chain begins sending training signals, which may be training patterns enclosed between frame alignment markers.
  • the transmit chain receives training information from the local receive chain, the information including remote adaptation information (generated locally) and backchannel information from the remote end of the link.
  • the transmit chain communicates the remote adaptation information to the remote end of the link, optionally via a hidden backchannel as described previously.
  • the transmit chain adjusts the pre-equalizer coefficients based on the backchannel information.
  • the transmit chain determines whether a "training complete" notification has been received via backchannel from the remote end of the link. If not, blocks 906-910 are repeated to provide additional training time.
  • the transmit chain begins conveying user data signals via the one or more transmit lanes.
  • the operations in blocks 916-918 parallel the operations of blocks 908-910, enabling the filter coefficients to track channel variation.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)

Abstract

L'invention concerne des modules convertisseur parallèle-série et convertisseur série-parallèle (SerDes) et des procédés utilisant un canal arrière indirect approprié pour communiquer des informations d'égalisation et/ou d'autres données liées à une liaison en l'absence d'un canal de retour apparié sur le substrat récepteur. Un mode de réalisation de la présente invention mis en œuvre par un module émetteur-récepteur consiste à : (a) recevoir, avec un substrat récepteur intégré, un signal de réception sur chacune de multiples voies de réception, les signaux de réception étant envoyés par un nœud distant; (b) convertir chaque signal de réception en une voie d'un flux de données de réception à voies multiples, ladite conversion comprenant une démodulation et une mesure d'erreur; (c) dériver des informations d'adaptation à distance sur la base, au moins en partie, de la mesure d'erreur; (d) transporter les informations d'adaptation à distance par l'intermédiaire d'un bus de commande vers un substrat d'émetteur intégré; et (e) envoyer au nœud distant, à l'aide du substrat émetteur intégré, un signal d'émission sur chacune de multiples voies de transmission, les signaux d'émission comprenant les informations d'adaptation à distance sur un canal arrière intégré.
PCT/US2018/013361 2018-01-11 2018-01-11 Systèmes et procédés de serdes ayant un canal arrière indirect WO2019139592A1 (fr)

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