WO2019132962A1 - Structures thermiques pour ensembles microélectroniques - Google Patents

Structures thermiques pour ensembles microélectroniques Download PDF

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Publication number
WO2019132962A1
WO2019132962A1 PCT/US2017/068908 US2017068908W WO2019132962A1 WO 2019132962 A1 WO2019132962 A1 WO 2019132962A1 US 2017068908 W US2017068908 W US 2017068908W WO 2019132962 A1 WO2019132962 A1 WO 2019132962A1
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WO
WIPO (PCT)
Prior art keywords
die
thermal layer
thermal
layer
microelectronic assembly
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Application number
PCT/US2017/068908
Other languages
English (en)
Inventor
Adel A. ELSHERBINI
Johanna M. SWAN
Shawna M. Liff
Patrick Morrow
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Intel Corporation
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Publication date
Application filed by Intel Corporation filed Critical Intel Corporation
Priority to PCT/US2017/068908 priority Critical patent/WO2019132962A1/fr
Publication of WO2019132962A1 publication Critical patent/WO2019132962A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4871—Bases, plates or heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3736—Metallic materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3738—Semiconductor materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Definitions

  • Integrated circuit devices e.g., dies
  • Integrated circuit devices are typically coupled together to integrate features or functionality and to facilitate connections to other components, such as circuit boards.
  • current techniques for coupling integrated circuit devices are limited by manufacturing, device size, thermal considerations, and interconnect congestion, which may impact costs and implementations.
  • FIG. 1 is a side, cross-sectional view of an example microelectronic assembly, in accordance with various embodiments.
  • FIG. 2 is a side, cross-sectional view of another example microelectronic assembly, in accordance with various embodiments.
  • FIG. 3 is a side, cross-sectional view of another example microelectronic assembly, in accordance with various embodiments.
  • FIG. 4 is a top view of the microelectronic assembly of FIG. 3, in accordance with various embodiments.
  • FIGS. 5-8 are side, cross-sectional views of other example microelectronic assemblies, in accordance with various embodiments.
  • FIGS. 9A-9D are side, cross-sectional views of various stages in an example process for manufacturing the microelectronic assembly of FIG. 1, in accordance with various embodiments.
  • FIGS. 10A-10E are side, cross-sectional views various stages in an example process for manufacturing the microelectronic assembly of FIG. 3, in accordance with various embodiments.
  • FIGS. 11A-11F are side, cross-sectional views various stages in an example process for manufacturing the microelectronic assembly of FIG. 7, in accordance with various embodiments.
  • FIGS. 12 is a side, cross-sectional view of another example microelectronic assembly, in accordance with various embodiments.
  • FIG. 13 is a top view of the microelectronic assembly of FIG. 12, in accordance with various embodiments.
  • FIGS. 14-15 are side, cross-sectional views of other example microelectronic assemblies, in accordance with various embodiments.
  • FIG. 16A-16B are side, cross-sectional views of various stages in an example process for manufacturing the microelectronic assembly of FIG. 12, in accordance with various embodiments.
  • FIG. 17 is a top view of a wafer and dies that may include a microelectronic assembly, in accordance with any of the embodiments disclosed herein.
  • FIG. 18 is a cross-sectional side view of an integrated circuit (1C) device that may be included in a microelectronic assembly, in accordance with any of the embodiments disclosed herein.
  • FIG. 19 is a cross-sectional side view of one example type of a double-sided 1C device that may be included in a microelectronic assembly, in accordance with any of the embodiments disclosed herein.
  • FIG. 20 is a cross-sectional side view of an 1C device assembly that may include a
  • microelectronic assembly in accordance with any of the embodiments disclosed herein.
  • FIG. 21 is a block diagram of an example computing device that may include a
  • a microelectronic assembly may include a die having a front side and an opposing back side; and a thermal layer at the back side of the die, wherein the thermal layer has an X-Y area that is less than or equal to an X-Y area of the die.
  • Various ones of the embodiments disclosed herein may help achieve reliable attachment of multiple 1C dies at a lower cost, with improved power efficiency, with higher bandwidth, and/or with greater design flexibility, relative to conventional approaches.
  • Various ones of the microelectronic assemblies disclosed herein may exhibit better power delivery, thermal dissipation (e.g., moving heat away from a die), and/or signal speed while reducing the size of the package relative to conventional approaches.
  • the microelectronic assemblies disclosed herein may be particularly advantageous for small and low-profile applications in computers, tablets, industrial robots, server architectures, and consumer electronics (e.g., wearable devices).
  • the phrase “A and/or B” means (A), (B), or (A and B).
  • the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).
  • the drawings are not necessarily to scale (e.g., aspect ratios may differ from those illustrated). Although many of the drawings illustrate rectilinear structures with flat walls and right-angle corners, this is simply for ease of illustration, and actual devices made using these techniques will exhibit rounded corners, surface roughness, and other features.
  • the phrase “between X and Y” represents a range that includes X and Y.
  • the phrase “FIG. 9” may be used to refer to the collection of drawings of FIGS. 9A-9D
  • the phrase “FIG. 10” may be used to refer to the collection of drawings of FIGS. 10A-10E, etc. although certain elements may be referred to in the singular herein, such elements may include multiple sub- elements.
  • an insulating material may include one or more insulating materials.
  • a "conductive contact” may refer to a portion of conductive material (e.g., metal) serving as an electrical interface between different components; conductive contacts may be recessed in, flush with, or extending away from a surface of a component, and may take any suitable form (e.g., a conductive pad, socket, bump, or pillar, or portion of a conductive line or via).
  • FIG. 1 is a side, cross-sectional view of a microelectronic assembly 100, in accordance with various embodiments. A number of elements are illustrated in FIG. 1 as included in the
  • microelectronic assembly 100 but a number of these elements may not be present in a
  • FIG. 1 illustrates a number of elements that are omitted from subsequent drawings for ease of illustration, but may be included in any of the microelectronic assemblies 100 disclosed herein. Examples of such elements include the first-level interconnects 112, the package substrate 160, and/or the second-level interconnects 162. Many of the elements of the microelectronic assembly 100 of FIG. 1 are included in other ones of the accompanying figures; the discussion of these elements is not repeated when discussing these figures, and any of these elements may take any of the forms disclosed herein.
  • individual ones of the microelectronic assemblies 100 disclosed herein may serve as a system-in-package (SiP) in which multiple dies 110 having different functionality are included.
  • SiP system-in-package
  • the microelectronic assembly 100 may be referred to as a SiP.
  • the microelectronic assembly 100 may include a die 110, a first thermal layer 120, and a second thermal layer 140.
  • the die may have a front side 102 and an opposing back side 104; the first thermal layer 120 may have a front side 122 and an opposing back side 124; and the second thermal layer 140 may have a front side 142 and an opposing back side 144.
  • the first thermal layer 120 and the second thermal layer 140 may be formed as a composite die; however, in other embodiments, the first thermal layer 120 and the second thermal layer 140 may not be formed as a composite die.
  • the front side 122 of the first thermal layer 120 may be attached to the die 110 at the back side 104 of the die 110 and the back side 124 of first thermal layer 120 may be attached to the second thermal layer 140 at the front side 142 of the second thermal layer 140.
  • the first thermal layer 120 may cover an X-Y area of the die 110 that is less than or equal to the X-Y area of the die 110.
  • the elements of the microelectronic assembly 100 may have any suitable dimensions.
  • the die 110 may have a thickness 132; the second thermal layer 140 may have a thickness 133; and the first thermal layer 120 may have a thickness 130.
  • the thickness 132 of the die 110 may range between 10 microns and 30 microns for ultra-thin dies. In other embodiments, the thickness 132 of the die 110 may range between 10 and 780 microns for other types of dies.
  • the thickness 133 of the second thermal layer 140 may range between 50 microns and 300 microns.
  • the thickness 130 of the first thermal layer 120 may range between 5 microns and 50 microns.
  • the die 110 may include conductive contacts 106 at the front side of the die 110. In various embodiments, the conductive contacts 106 may have a pitch between 5 microns and 250 microns.
  • the die 110 may be a single-sided die. In other embodiments, the die 110 may be a double-sided die. As referred to herein in this Specification, a double-sided die is a die that has interconnect layers (e.g., a metallization stack) on both sides (e.g., a front side and an opposing back side) of a device layer (which can potentially include multiple device layers) of the die.
  • interconnect layers e.g., a metallization stack
  • a device layer (which can potentially include multiple device layers) may be sandwiched by two metallization stacks providing conductive pathways (e.g., conductive lines and vias) between the device layer and the conductive contacts at the sides or faces of the die, or by a metallization stack providing conductive pathways between the device layer and the conductive contacts at one face (side) of the die and a semiconductor substrate with TSVs providing conductive pathways between the device layer and the conductive contacts at the other face (side) of the die.
  • conductive pathways e.g., conductive lines and vias
  • the first thermal layer 120 may be composed of a material (e.g., a semiconductor material) having a thermal conductivity that is greater than the thermal conductivity of the second thermal layer 140.
  • silicon has a thermal conductivity between 100 Watts per meter-Kelvin (W/m-K) and 150 W/m-K, which may vary depending on the temperature of the silicon.
  • W/m-K Watts per meter-Kelvin
  • the then first thermal layer may be composed of a material having a thermal conductivity that is greater than the thermal conductivity of silicon.
  • the material of the first thermal layer 120 may be a metal such as copper, aluminum, gold, silver, combinations thereof (e.g., alloys or layers of different metals), or the like.
  • copper has a thermal conductivity between 300 W/m-K and 380 W/m-K, which may also vary depending on the temperature of the copper.
  • the conductive material may be a composite such as aluminum nitride, barium oxide, graphene, ceramic, or the like.
  • the die 110 may be composed of a first semiconductor material and the second thermal layer 140 may be composed of a second semiconductor material.
  • the first semiconductor material of the die 110 and the second semiconductor material of the second thermal layer 140 may be different; however, in other embodiments, the first semiconductor material of the die 110 and the second semiconductor material of the second thermal layer 140 may be the same.
  • the second semiconductor material of the second thermal layer 140 and/or the material of the first thermal layer 120 may be selected based on a coefficient of thermal expansion (CTE) of the second semiconductor material being similar to the CTE of the material of the first thermal layer 120 and/or to the CTE of the first semiconductor material of the die 110.
  • CTE coefficient of thermal expansion
  • the second semiconductor material of the second thermal layer 140 may be selected based on the second semiconductor material of the second thermal layer 140 having a higher modulus of elasticity than the first semiconductor material of the die 110 (e.g., to increase the overall stiffness of the microelectronic assembly 100) and/or higher than the modulus of elasticity of the first thermal layer 120.
  • the second semiconductor material of the second thermal layer 140 may be selected based on electrical characteristics (e.g., resistivity, loss, etc.) of the semiconductor material.
  • the material of the first thermal layer 120 may be selected based on a tradeoff between thermal conductivity of the material and modulus of the material to increase the overall stiffness of the microelectronic assembly 100.
  • the second thermal layer 140 may not be electrically active; however, in other embodiments, the second thermal layer 140 may be electrically active.
  • the first thermal layer 120 may be attached to the die 110 and/or the second thermal layer 140 using any suitable technique including, but not limited to layer transfer techniques, direct bonding techniques, hybrid bonding techniques, sputtering processes, plating processes, or the like.
  • conductive pathways (FIG. 5) may be formed in the second thermal layer 140 and may be interconnected to conductive contacts at the back side 104 of the die 110 using direct or hybrid bonding techniques.
  • a first die or wafer (if die are redistributed) having a pristine, planar, and active surface may be placed, typically at room temperature, on a second die or wafer also having a pristine, planar, and active surface (e.g., to perform die-to-wafer bonding, die-to-die bonding, or wafer-to-wafer bonding).
  • a force is applied to the dies (in batch) and/or wafers to form a van der Waals bond between the dies and/or wafers.
  • the bonded dies and/or wafers are then annealed at a high temperature (typically 150° Celsius (C) or higher) to form permanent bonds between the dies or wafers (e.g., between conductive contacts or pathways that provide associated conductive contacts, if present) and between dielectric surfaces.
  • a high temperature typically 150° Celsius (C) or higher
  • a dielectric material e.g., silicon oxide, silicon nitride, or silicon carbide, among others
  • dies or wafers may be bonded together under elevated pressure and/or temperature (e.g., thermal compression bonding, , typically performed at temperatures greater than 150° C and greater than 20 megapascals (MPa), which may vary depending on bump pitch, materials, etc.).
  • a spin-on-dielectric material may be patterned around the conductive to fill any void spaces during bonding.).
  • the first thermal layer 120 may be formed on the front side 142 of the second thermal layer 140 using a sputtering and/or plating process and the second thermal layer 140 and first thermal layer 120 may then be mechanically attached to the die 110 using any suitable technique.
  • the first thermal layer 120 may be formed on the back side 104 of the die 110 using a sputtering and/or plating process and the die 110 and first thermal layer 120 may then be mechanically attached to the front side 142 of the second thermal layer 140 using any suitable technique.
  • a barrier layer and/or an adhesion layer may be included in the sputtering and/or plating processes.
  • a barrier layer (not shown in FIG.
  • a barrier layer may have a thickness that is greater than 250 nanometers and less than 1 micron, which may not inhibit thermal spreading of the first thermal layer 120.
  • An adhesion layer may be a same or different material than the material of which the first thermal layer 120 is composed and may provide for improved adhesion between the first thermal layer 120 and the die 110 and/or the second thermal layer 140, as appropriate.
  • copper may be used as an adhesion layer for a first thermal layer 120 that is composed of copper.
  • titanium may be used as an adhesion layer for a first thermal layer 120 that is composed copper.
  • Other adhesion layers may be employed.
  • the first thermal layer 120 may provide various advantages to improve thermal cooling for the die 110.
  • the first thermal layer 120 may be included in the microelectronic assembly during wafer-level processing and may be placed in close proximity to a device layer of the die 110 to improve thermal spreading (illustrated as the horizontal dashed-lines in FIG. 1) for the microelectronic assembly 100.
  • the separation between the first thermal layer 120 and the device layer of the die 110 may be a distance based on the native substrate for the die 110 or may be based on interconnect structures that may be present for a particular side of the die 110.
  • Fleat spread through the first thermal layer 120 may be dissipated (illustrated as the vertical dashed-lines in FIG. 1) from the microelectronic assembly 100 via the second thermal layer 140.
  • Improved thermal spreading may be particularly useful for ultra-thin dies, which may have limited area through which to spread heat generated by the die.
  • improved thermal spreading may lower the junction temperature (T ) of transistors operating within the die 110. Lowering the junction temperature may enable higher performance of the die 110.
  • transistors within the die 110 may be designed with a maximum junction temperature (TIMAX), which may represent a maximum junction temperature at which the transistors may operate in the sense that temperatures higher than the maximum junction temperature may result in damage to the transistors.
  • a maximum junction temperature TIMAX
  • the junction temperature for the transistors at a given clock frequency or speed may be lowered in comparison to junction temperatures for the transistors at the given clock frequency or speed when the first thermal layer 120 is not included in the assembly.
  • the clock frequency or speed of the transistors may be increased, thereby improving performance of the die 110.
  • the first thermal layer 120 may advantageously reduce thermal congestion for the microelectronic assembly 100 by being integrated in intimate contact with the die 110 and the second thermal layer 140, which may eliminate the use of elements such as underfill, and/or molding compound between the die 110 and the first thermal layer 120 and between the first thermal layer 120 and the second thermal layer 140.
  • the first thermal layer 120 may provide for the ability to provide a layer of high thermal conductivity to be provided between dies as well as on top of dies for various designs and/or implementations.
  • the microelectronic assembly of FIG. 1 may also include a package substrate 160.
  • the microelectronic assembly may be coupled to the package substrate 160 by first-level interconnects 112.
  • conductive contacts 106 at the front side 102 of the die 110 may be electrically and mechanically coupled to conductive contacts (not shown) of the package substrate 160 by the first-level interconnects 112.
  • the first-level interconnects 112 illustrated in FIG. 1 are solder balls (e.g., for a ball grid array arrangement), but any suitable first-level interconnects 112 may be used (e.g., solder, non-solder, pins in a pin grid array arrangement, lands in a land grid array arrangement, wirebond, or copper pillar with solder cap).
  • the package substrate 160 may be coupled to a circuit board (not shown) by second-level interconnects 162 using any suitable technique.
  • the second-level interconnects 162 illustrated in FIG. 1 are solder balls (e.g., for a ball grid array arrangement), but any suitable second-level interconnects 162 may be used (e.g., solder, non-solder, pins in a pin grid array arrangement, lands in a land grid array arrangement, wirebond, or copper pillar with solder cap).
  • the package substrate 160 may include an insulating material (e.g., e.g., a dielectric material formed in multiple layers, as known in the art) and one or more conductive pathways through the dielectric material (e.g., including conductive traces and/or conductive vias).
  • the insulating material of the package substrate 160 may be a dielectric material, such as an organic dielectric material, a fire retardant grade 4 material (FR-4), bismaleimide triazine (BT) resin, polyimide materials, glass reinforced epoxy matrix materials, or low-k and ultra low-k dielectric (e.g., carbon-doped dielectrics, fluorine-doped dielectrics, porous dielectrics, and organic polymeric dielectrics).
  • the package substrate 160 when the package substrate 160 is formed using standard printed circuit board (PCB) processes, the package substrate 160 may include FR-4, and the conductive pathways in the package substrate 160 may be formed by patterned sheets of copper separated by build-up layers of the FR-4.
  • the conductive pathways in the package substrate 160 may be bordered by liner materials, such as adhesion liners and/or barrier liners, as suitable.
  • an integrated heat spreader may be included in the microelectronic assembly 100 at the back side 144 of the second thermal layer 140 and may further be in contact with the package substrate.
  • the integrated heat spreader may be used to move heat away from the die 110 and the thermal layers 120/140 (e.g., so that the heat may be more readily dissipated by a heat sink or other thermal management device).
  • the integrated heat spreader may include any suitable thermally conductive material (e.g., metal, appropriate composite, etc.), and may include any suitable features (e.g., fins).
  • a thermal interface material (not shown) may be included in the microelectronic assembly 100 between the integrated heat spreader and the back side 144 of the second thermal layer 140.
  • the TIM may include a thermally conductive material (e.g., metal particles) in a polymer or other binder.
  • the TIM may be a thermal interface material paste or a thermally conductive epoxy (which may be a fluid when applied and may harden upon curing, as known in the art).
  • the TIM may provide a path for heat generated by the die 110 to readily flow to the heat spreader, where the heat may be further spread and/or dissipated.
  • the thickness of the TIM may range between 10 microns and 50 microns.
  • the die 110 may include circuitry, which may include one or more device layers including active or passive circuitry (e.g., transistors, diodes, resistors, inductors, capacitors, among others) and one or more interconnect layers (e.g., as discussed below with reference to FIGS. 18-19).
  • one or more interconnect layers may be present on one or both sides of circuitry for the die 110 (e.g., as discussed below with reference to FIGS. 18- 19).
  • the die 110 may be the source and/or destination of signals
  • interconnect layers for a die may include conductive pathways to route power, ground, and/or signals between different ones of the die 110 and/or between the die 110 and the package substrate 160.
  • the die 110 may include an insulating material (e.g., a dielectric material formed in multiple layers, or semiconductor material, as known in the art) and multiple conductive pathways formed through the insulating material.
  • the insulating material of the die 110 may include a dielectric material, such as BT resin, polyimide materials, glass reinforced epoxy matrix materials, oxide-based materials (e.g., silicon dioxide or spin on oxide), or low-k and ultra low-k dielectric (e.g., carbon-doped dielectrics, fluorine-doped dielectrics, porous dielectrics, and organic polymeric dielectrics).
  • the die 110 may include a dielectric build-up film.
  • the active material of the die 110 may be a semiconductor material, such as silicon, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Further active materials classified as group ll-VI, lll-V, or IV may also be used as the active substrate materials of die 110.
  • the die 110 may also include a bulk or native substrate on one, both, or no sides of circuitry for a given die.
  • the bulk substrate may be a crystalline substrate formed using a bulk silicon or a silicon-on-insulator (SOI) substructure. Other insulating materials may be used, as desired depending on design and/or implementation.
  • SOI silicon-on-insulator
  • the second thermal layer 140 may be composed of a semiconductor material such as silicon, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, sapphire, diamond, glass, ceramic or gallium antimonide.
  • the second thermal layer 140 may also be composed of materials classified as group ll-VI, lll-V, or IV materials.
  • FIG. 2 is a side, cross-sectional view of another example microelectronic assembly 100, in accordance with various embodiments.
  • a third thermal layer 150 may be included between the front side 122 of first thermal layer 120 and the back side 104 of the die 110.
  • the third thermal layer 150 may have a thickness 131 comparable to the first thermal layer 120.
  • the third thermal layer 150 may have an X-Y area that is equal to the X-Y area of the first thermal layer 120.
  • the first thermal layer 120 illustrated for the embodiment of FIGS. 1-2 is illustrated as covering an X-Y area equal to the X-Y area of the die 110, in some embodiments, the first thermal layer 120 may have an X-Y area that is less than the X-Y area of the die or may be patterned to form one or more portions such that individual ones of the portions of the first thermal layer 120 may an X-Y area smaller than the X-Y area of the die 110 to provide thermal spreading for "hot spot" areas of the die 110, which may generate more heat than other areas of the die 110.
  • FIG. 3 is a side, cross- sectional view of another example microelectronic assembly 100 in which the first thermal layer 120 may be patterned to align with a number of "hot spot" areas 310 of the die 110.
  • a first portion of the first thermal layer 120-1 having a front side 122-1 and an opposing back side 124-1 may be patterned to align with a first hot spot area 310-1 of the die 110; a second portion of the first thermal layer 120-2 having a front side 122-2 and an opposing back side 124-2 may be patterned to align with a second hot spot area 310-2 of the die 110; and a third portion of the first thermal layer 120-3 having a front side 122-3 and an opposing back side 124-3 may be patterned to align with a third hot spot area 310-3 of the die 110.
  • Each portion of the first thermal layer 120-1/120-2/120-3 may have a corresponding X-Y area that overlays each of the corresponding hot spot areas 310-1/310-2/310-3. Fleat absorbed by the respective portions of the first thermal layer 120-1/120-2/120-3 may be spread away from the respective hot spot areas 310-1/310-2/310-3.
  • the portions of the first thermal layer 120 may be formed within the second thermal layer 140 such that the front sides 122 of the portions of the first thermal layer 120 may align along a same plane as the front side 142 of the second thermal layer 140.
  • FIG. 4 is a top view of the microelectronic assembly 100 of FIG. 3, in accordance with various embodiments.
  • the top view of FIG. 4 is from the perspective of the back side 144 of the second thermal layer 140.
  • FIG. 4 illustrates that the patterned portions of the first thermal layer 120-1/120- 2/120-3 may have a same or a different X-Y area relative to each other.
  • the X-Y area of the die 110 may be greater than the X-Y areas of each individual portion of the first thermal layer 120-1/120-2/120-3.
  • patterning the first thermal layer 120 to align with hot spots of the die 110 may improve thermal spreading for the hot spots; however, such patterning may decrease thermal spreading for areas in which the thermal layer is not present.
  • the embodiments of FIGS. 3-4 illustrate features related to patterning the first thermal layer 120 to provide improved thermal spreading for various hot spot areas of the die 110
  • the first thermal layer 120 may be patterned to improve mechanical performance of the microelectronic assembly 100 in addition to or in lieu of improving thermal spreading for the die 110.
  • the first thermal layer 120 may be patterned to reduce mechanical stresses (e.g., compressive stresses) that may occur between the first thermal layer 120 and the die 110 due to heating and cooling of the first thermal layer 120 and/or the die 110 due to different CTEs between the thermal layer and the die 110.
  • FIG. 5 is a side, cross-sectional view of another example microelectronic assembly 100 in which conductive pathways 149 may be formed in the second thermal layer 140, in various embodiments.
  • the conductive pathways 149 may extend between the back side 124 of the first thermal layer 120 and the back side 144 of the second thermal layer 140.
  • the conductive pathways 149 may have a width 134, which may range between 1 micron and 300 microns.
  • other conductive pathways 149 may be formed between the front side 122 of the first thermal layer 120 and the front side of a third thermal layer (e.g., third thermal layer 150), if present for a microelectronic assembly.
  • a third thermal layer e.g., third thermal layer 150
  • the thickness of the conductive pathways 149 may be the same as the thickness 133 of the second thermal layer 140.
  • the thickness of the conductive pathways 149 may have a same thickness 131 as the third thermal layer 150.
  • the first thermal layer 120 may improve thermal spreading for the die 110
  • the conductive pathways 149 may improve thermal dissipation of heat away from the die 110 (as illustrated by the vertical dashed-line arrows) through the second thermal layer 140.
  • the first thermal layer 120 may decrease thermal resistance for heat transferred from the die 110 and spread through the first thermal layer 120 to the conductive pathways 149, which may improve thermal dissipation of heat away from the die 110.
  • the conductive pathways 149 may be formed in the second thermal layer 140 using any suitable techniques such as laser drilling, mechanical drilling, or plasma etching and filling with a material using sputtering or plating.
  • the conductive pathways 149 may be bordered by liner materials, such as adhesion liners and/or barrier liners, as suitable.
  • FIG. 5 illustrates a specific number and arrangement of conductive pathways 149 in the second thermal layer 140, these are simply illustrative, and any suitable number and arrangement may be used for a microelectronic assembly 100.
  • the conductive pathways 149 are shown as having substantially parallel sidewalls, the conductive pathways 149 may have any profile (e.g., as may be dictated by the manufacturing processes used to form the conductive pathways 149).
  • the sidewalls of a conductive pathway 149 may be tapered, scalloped, or may be otherwise non parallel with each other.
  • the conductive pathways 149 may be composed of a metal or a composite material, as discussed herein. In some embodiments, the conductive pathways 149 may be composed of a same material as the first thermal layer 120; however, in other embodiments, the conductive pathways 149 may be composed of a different material than the first thermal layer 120.
  • conductive pathways 149 may also be used when the thermal layer is patterned.
  • FIG. 6 is a side, cross-sectional view of another example microelectronic assembly 100 in which corresponding sets of conductive pathways 149-1/149-2/149-3 may be included in the second thermal layer 140 between corresponding ones of portions of the first thermal layer 120-1/120- 2/120-3 and the back side 144 of the second thermal layer 140, in various embodiments.
  • conductive pathways 149 may be included in the second thermal layer 140 for areas in which the first thermal layer 120 may not be present.
  • FIG. 7 is a side, cross- sectional view of another example microelectronic assembly 100 in which conductive pathways 149- 4 may be included in the second thermal layer 140 for areas in which the first thermal layer 120 may not be present.
  • the conductive pathways 149-4 may extend between the front side 142 of the second thermal layer 140 and the back side 144 of the second thermal layer 140.
  • one or more of the conductive pathways 149-4 may be electrically active in the sense that they may be electrically connected to one or more electronic devices (e.g., transistors) of the device layer(s) of the die 110.
  • electronic devices e.g., transistors
  • certain ones of the conductive pathways 149-4 at the front side 142 of the second thermal layer 140 may be electrically and mechanically coupled to conductive contacts 108 at the back side 104 of the die 110 by interconnects 107.
  • the interconnects 107 may be metal-to-metal (e.g., copper-to-copper) interconnects or anisotropic conductive material interconnects, as discussed herein.
  • the conductive pathways 149-4 may be electrically active to facilitate integrating additional dies (FIG. 8) into the microelectronic assembly 100.
  • one or more interconnect layers may be formed on the back side 144 of the second thermal layer 140 to provide routing or other electrical interconnects for one or more other dies that may be integrated into the microelectronic assembly 100.
  • one or more of the conductive pathways 149-4 may be electrically passive in the sense that they may not be electrically connected to one or more electronic device of the device layer(s) of the die 110.
  • the conductive pathways 149-4 that are at least partially between the first portion of the first thermal layer 120-1 and the second portion of the first thermal layer 120-2 may be electrically passive but may still improve thermal dissipation away from the die 110.
  • any combination of the conductive pathways 149 and/or the first thermal layer 120 (or portions thereof) may be utilized for a microelectronic assembly 100.
  • the die 110 may be a memory.
  • power consumption across the die may be more uniform because devices in the device layer are generally operating in a uniform manner (e.g., at a same clock frequency), in which case overall dissipation of heat away from the die may be improved by conductive pathways 129.
  • the die 110 may be a processor.
  • some areas (e.g., hot spots) of the die 110 may be consuming more power and generating more heat than other areas of the die.
  • the first thermal layer 120 may be used to improve heat spreading, thereby reducing the temperature of the hot spot areas. By reducing the temperature of the hot areas may allow them to be operated at higher clock frequency, which may improve operating efficiency for the processor.
  • conductive pathways 149 may be used to improve heat dissipation away from the die 110.
  • FIG. 8 is a side, cross-sectional view of another microelectronic assembly 100 in which another die 910 may be coupled to the second thermal layer 140, in various embodiments.
  • the die 910 may be electrically and mechanically coupled to conductive pathways 149-4 at the back side 144 of the second thermal layer 140 by interconnects 911.
  • the interconnects 911 may take any of the forms disclosed herein (e.g., solder interconnects, anisotropic conductive material interconnects, or metal-to-metal interconnects), and any suitable technique may be used to form the interconnects 911.
  • the die 910 may take any of the forms disclosed herein (e.g., single sided or double-sided).
  • an underfill material may extend between the die 910 and the second thermal layer 140 around associated interconnects 911 and/or between the die 110 and the package substrate 160 around associated first-level interconnects 112.
  • the underfill material may be an insulating material, such as an appropriate epoxy material or carbon-doped or spin-on-dielectric or oxide.
  • the underfill material may be an epoxy flux that assists with coupling the dies to the second thermal layer 140 or the package substrate 160 when forming the interconnects, and then polymerizes and encapsulates the interconnects.
  • the underfill material may be selected to have a CTE that may mitigate or minimize the stress between the die 910 and the second thermal layer 140 and/or between the die 110 and the package substrate 160 arising from uneven thermal expansion in the microelectronic assembly 100.
  • FIGS. 9A-9D are side, cross-sectional views of various stages in an example process for manufacturing the microelectronic assembly of FIG. 1, in accordance with various embodiments.
  • FIGS. 9A-9D are illustrated in a particular order, these operations may be performed in any suitable order.
  • FIGS. 9A-9D and others of the accompanying drawings representing manufacturing processes
  • the operations discussed below with reference to FIGS. 9A-9D may be used to form any suitable assemblies.
  • die 110 and the second thermal layer 140 may first be assembled into a "composite die,” and then the composite die may be coupled to the package substrate 160; however, in other embodiments, the die 110 and the second thermal layer 140 may not be assembled into a "composite die.”
  • a composite die may refer to a semiconductor structure in which multiple dies may be coupled together and assembled such that the assembly can be treated as a single die.
  • the assembly may have a planar surface with conductive contacts for first-level interconnects. This approach may allow for tighter tolerances in the formation of interconnects, and may be particularly desirable for integrating relatively small dies into a composite die assembly.
  • FIG. 9A illustrates a thermal layer 1040 having a front side 1042 and an opposing back side 1044.
  • the thermal layer 1040 may have a thickness 1033.
  • the thermal layer 1040 may take the form of any of the thermal layers discussed herein with reference to the second thermal layer 140.
  • the thermal layer 1040 may be "upside down" relative to the second thermal layer 140 illustrated in the embodiment of FIG. 1.
  • FIG. 9B illustrates an assembly 1100 subsequent to forming another thermal layer 1020 over the front side 1042 of the thermal layer 1040.
  • the thermal layer 1020 may take the form of any of the thermal layers discussed herein with reference to the first thermal layer 120.
  • the thermal layer 1020 may be formed using any suitable technique.
  • the thermal layer 1020 may be formed by sputtering an adhesion layer (sometimes referred to as a "seed" layer) at the front side 1042 of the thermal layer 1040 and then additionally sputtering or plating material of the thermal layer 1020 to a desired thickness 1030.
  • the thermal layer 1020 may be formed to a first thickness and then reduced (e.g., ground) to a second thickness.
  • the thermal layer 1020 may be a wafer (e.g., a copper wafer) that may be attached (e.g., bonded) to the thermal layer 1020 using any suitable technique.
  • FIG. 9C illustrates an assembly 1102 subsequent to "flipping" the assembly 1100 and attaching the thermal layer 1020 to a die 1010.
  • the die 1010 may take the form of any of the dies discussed herein with reference to the die 110.
  • the die 1010 may have a front side 1002 and an opposing back side 1004 and be composed of a semiconductor material.
  • the die 1010 may have a thickness 1032.
  • the die 1010 may include conductive contacts 1006 at the front side 1002 of the die 1010.
  • the thermal layer 1020 may be attached to the die 1010 using any suitable technique, as discussed herein (e.g., direct bonding, hybrid bonding, metal-to-metal attachment, solder attachment, etc.).
  • the attaching may include wafer-to-wafer bonding, die-to-wafer bonding, or die- to-die bonding in various embodiments.
  • FIG. 9D illustrates an assembly 1104 subsequent to coupling the assembly 1102 to a package substrate 1060 using first-level interconnects 1012.
  • the package substrate 1060 may to take the form of any of the package substrates discussed herein with reference to package substrate 160.
  • the first-level interconnects 1012 may take any of the forms disclosed herein (e.g., solder interconnects or anisotropic conductive material interconnects), and any suitable techniques may be used to form the first-level interconnects 1012 (e.g., a mass reflow process or a thermal compression bonding process).
  • the assembly 1104 may take the form the microelectronic assembly 100 of FIG. 1.
  • FIGS. 10A-10E are side, cross-sectional views various stages in an example process for manufacturing the microelectronic assembly of FIG. 3, in accordance with various embodiments.
  • FIG. 10A illustrates a thermal layer 1040 having a front side 1042 and an opposing back side 1044.
  • the thermal layer 1040 may have a thickness 1033.
  • the thermal layer 1040 may take the form of any of the thermal layers discussed herein with reference to the second thermal layer 140.
  • the thermal layer 1040 may be "upside down" relative to the second thermal layer 140 illustrated in the embodiment of FIG. 3.
  • FIG. 10B illustrates an assembly 1200 subsequent to recesses 1070 (e.g., 1070-1/1070- 2/1070-3) extending to a distance into the thermal layer 1040.
  • the distance may be equal to a desired thickness 1030 of portions of another thermal layer to be formed in the recesses.
  • Any suitable technique may be used to form the recesses 1070.
  • the recesses 1070 may be laser-drilled down to a planar metal stop (not shown) in the thermal layer 1040; once the metal stop is reached, the metal stop may be removed.
  • the recesses 1070 may be formed by a mechanical drill.
  • the recesses 1070 may be formed using a plasma etching process.
  • FIG. 10C illustrates an assembly 1202 subsequent to forming portions of another thermal layer 1020-1/1020-2/1020-3 in the recesses of the assembly 1200.
  • Each portion of the thermal layer 1020 may have a front side 1022 and a back side 1024.
  • the portions of the thermal layer 1020 may take the form of any of the thermal layers discussed herein with reference to portions of the first thermal layer 120.
  • the portions of the thermal layer 1020-1/1020-2/1020-3 may be formed using any suitable technique.
  • the portions of the thermal layer 1020- 1/1020-2/1020-3 may be formed by sputtering an adhesion layer (sometimes referred to as a "seed" layer) at the front side 1042 of the thermal layer 1040 (including the recesses 1070) and then additionally sputtering or plating material of the thermal layer 1020 to fill the recesses.
  • the thermal layer 1020 may be formed to a first thickness and then reduced (e.g., ground) to a second thickness to achieve the desired thickness 1030 for the portions of the thermal layer 1020-1/1020-2/1020-3.
  • FIG. 10D illustrates an assembly 1204 subsequent to "flipping" the assembly 1202 and attaching the thermal layer 1020 and the thermal layer 1040 to a die 1010.
  • the die 1010 may take the form of any of the dies discussed herein with reference to the die 110.
  • the die 1010 may have a front side 1002 and an opposing back side 1004 and be composed of a
  • the die 1010 may have a thickness 1032.
  • the die 1010 may include conductive contacts 1006 at the front side 1002 of the die 1010.
  • the thermal layers 1020/1040 and may be attached to the die 1010 using any suitable technique, as discussed herein (e.g., direct bonding, hybrid bonding, metal-to-metal attachment, solder attachment, etc.).
  • the attaching may include wafer-to-wafer bonding, die-to-wafer bonding, or die-to-die bonding in various
  • FIG. 10E illustrates an assembly 1206 subsequent to coupling the assembly 1204 to a package substrate 1060 using first-level interconnects 1012.
  • the package substrate 1060 may to take the form of any of the package substrates discussed herein with reference to package substrate 160.
  • the first-level interconnects 1012 may take any of the forms disclosed herein (e.g., solder interconnects or anisotropic conductive material interconnects), and any suitable techniques may be used to form the first-level interconnects 1012 (e.g., a mass reflow process or a thermal compression bonding process).
  • the assembly 1206 may take the form the microelectronic assembly 100 of FIG. 3.
  • FIGS. 11A-11E are side, cross-sectional views various stages in an example process for manufacturing the microelectronic assembly of FIG. 7, in accordance with various embodiments.
  • FIG. 11A illustrates a thermal layer 1040 having a front side 1042 and an opposing back side 1044.
  • the thermal layer 1040 may have a thickness 1033.
  • the thermal layer 1040 may take the form of any of the thermal layers discussed herein with reference to the second thermal layer 140.
  • the thermal layer 1040 may be "upside down" relative to the second thermal layer 140 illustrated in the embodiment of FIG. 7.
  • FIG. 11B illustrates an assembly 1300 subsequent to recesses 1070 (e.g., 1070-1/1070- 2/1070-3) extending to a distance into the thermal layer 1040.
  • the distance may be equal to the desired thickness 130 of the portions of another thermal layer to be formed in the recesses.
  • Any suitable technique may be used to form the recesses 1070.
  • the recesses 1070 may be laser-drilled down to a planar metal stop (not shown) in the thermal layer 1040; once the metal stop is reached, the metal stop may be removed.
  • the recesses 1070 may be formed by a mechanical drill.
  • the recesses 1070 may be formed using a plasma etching process.
  • FIG. 11C illustrates an assembly 1302 subsequent to forming pathways 1079 (e.g., 1079- 1/1079-2/1079-3/1079-4) through the thermal layer 1040.
  • Any suitable technique may be used to form the pathways 1079 (e.g., laser drilling, mechanical drilling, plasma etching, etc.).
  • FIG. 11D illustrates an assembly 1304 subsequent to forming conductive pathways 1049 (e.g., 1049-1/1049-2/1049-3/1049-4) in the pathways 1079 of the assembly 1302 and forming portions of another thermal layer 1020-1/1020-2/1020-3 in the recesses of the assembly 1302.
  • Each portion of the thermal layer 1020 may have a front side 1022 and a back side 1024.
  • the portions of the thermal layer 1020 may take the form of any of the thermal layers discussed herein with reference to portions of the first thermal layer 120.
  • the conductive pathways 1049-1/1049-2/1049- 3/1049-4 and the portions of the thermal layer 1020-1/1020-2/1020-3 may be formed using any suitable technique.
  • the conductive pathways 1049 and the portions of the thermal layer 1020 may be formed by sputtering or plating to fill the pathways and the recesses.
  • the thermal layer 1020 may be formed to a first thickness and then reduced (e.g., ground) to a second thickness to achieve the desired thickness 1030 for the portions of the thermal layer 1020-1/1020-2/1020-3.
  • FIG. HE illustrates an assembly 1306 subsequent to "flipping" the assembly 1304 and attaching the thermal layer 1020 to a die 1010.
  • the die 1010 may take the form of any of the dies discussed herein with reference to the die 1010.
  • the die 1010 may have a front side 1002 and an opposing back side 1004 and be composed of a semiconductor material.
  • the die 1010 may have a thickness 1032.
  • the die 1010 may include conductive contacts 1006 at the front side 1002 of the die 1010.
  • the thermal layers 1020/1040 may be attached to the die 1010 using any suitable technique, as discussed herein (e.g., direct bonding, hybrid bonding, metal-to-metal attachment, solder attachment, etc.).
  • the attaching may include wafer-to-wafer bonding, die-to- wafer bonding, or die-to-die bonding in various embodiments.
  • the attaching can include forming interconnects 1007 (e.g., metal-to-metal interconnects or anisotropic conductive material interconnects) between certain ones of the conductive pathways 1049-4 and conductive contacts 1006 at the back side 1004 of the die 1010.
  • the attaching may not include forming interconnects between certain ones of the conductive pathways 1049-4 and conductive contacts at the back side 1004 of the die 1010.
  • FIG. 11F illustrates an assembly 1308 subsequent to coupling the assembly 1306 to a package substrate 1060 using first-level interconnects 1012.
  • the package substrate 1060 may to take the form of any of the package substrates discussed herein with reference to package substrate 160.
  • the first-level interconnects 1012 may take any of the forms disclosed herein (e.g., solder interconnects or anisotropic conductive material interconnects), and any suitable techniques may be used to form the first-level interconnects 1012 (e.g., a mass reflow process or a thermal compression bonding process).
  • the assembly 1308 may take the form the microelectronic assembly 100 of FIG. 7.
  • thermal spreading for a microelectronic assembly may be improved by forming a thermal layer over one or more dies coupled together.
  • FIG. 12 is a side, cross-sectional view of an example microelectronic assembly 1400 in which a thermal layer 1420 may be formed over dies 1410 coupled together.
  • the microelectronic assembly 1400 may include a first die 1410-1 having a first surface 1402-1 (e.g., a front side) and a second surface 1404-1 (e.g., a back side) and at least one second die 1410-2 having a first surface 1402-2 and a second surface 1404-2.
  • the first die 1410-1 may be referred to interchangeably herein as a "base" die.
  • the first surface 1402-2 of the at least one second die 1410-2 may be coupled to the second surface 1404-1 of the first die by interconnects (not labeled) using any suitable technique, as discussed herein.
  • additional dies e.g., a third die 1410-3 and a fourth die 1410-4
  • the thermal layer 1420 may be formed over the second surfaces 1404 of the dies 1410 to a desired thickness 1430.
  • the thermal layer 1420 may have a first surface 1422 and a second surface 1424.
  • an underfill material 1406 may be present between any of the dies 1410 coupled together and/or between the first die 1410-1 and a package substrate 1460.
  • the underfill material 1406 may take any form as discussed herein.
  • barrier and adhesion liners may be used, as may be appropriate to limit diffusion of the thermal layer 1420 into the dies 1410.
  • the package substrate 1460 may be coupled to a circuit board via second-level interconnects 1462.
  • the thermal layer 1420 may be composed of a material (e.g., a semiconductor material) having a thermal conductivity that is greater than the thermal conductivity of the dies 1410.
  • the material of the thermal layer 1420 may be a metal such as copper, aluminum, gold, silver, combinations thereof (e.g., alloys or layers of different metals), or the like.
  • the conductive material may be a composite such as aluminum nitride, barium oxide, graphene, ceramic, or the like.
  • the elements of the microelectronic assembly 100 may have any suitable dimensions.
  • the dies 1410 may have a thickness 1431. In some embodiments, the thickness 1431 of the dies 1410 may range between 10 microns and 780 microns.
  • the second die 1410-2 may be thinner than the first die 1410-1. In other embodiments, the second die 1410-2 may be thicker than the first die 1410-1. In still other embodiments, the second die 1410-2 may be a same thickness as the first die 1410-1.
  • the thickness 1430 of the thermal layer 1420 may range between 5 microns and 300 microns; however, in some embodiments, the thickness 1430 of the thermal layer 1420 may be as great as ten times the thickness 1431 of the first die 1410- 1.
  • the second surface 1424 of the thermal layer 1420 may be substantially planar in the sense that the thickness 1430 of the thermal layer 1420 may have a total thickness variation across the second surface 1424 of the thermal layer 1420 that is less than or equal to 10 microns, in various embodiments.
  • the thermal layer 1420 may have an X-Y area that is less than or equal to an X-Y area of the first die 1410-1.
  • the X-Y area of the thermal layer 1420 may be greater than an X-Y area of the second die 1410-2 such that the thermal layer 1420 covers the second surface 1404-2 of the second die 1420-2, extends down the sides of the second die 1420-2, and covers at least a portion of the second surface 1404-1 of the first die 1410-1.
  • the thermal layer 1420 may cover the first die 1410-1 and the second die 1410-2 in a conformal manner such that the thickness 1430 of the thermal layer may be substantially uniform across the first and second dies 1410-1/1410-2.
  • the thermal layer 1420 may be formed over dies 1410-2/1410-3/1410-4 having different thicknesses 1431, in which embodiments, the thermal layer 1420 may have a varying thickness 1430 to accommodate variations in the die 1410-2/1410-3/1410-4 thicknesses 1431 in order to form the substantially planar second surface 1424 for the thermal layer 1420.
  • the thermal layer 1420 is illustrated for the embodiment of FIG. 12 as covering the sides of the second die 1410-2 at right (90°) angles, in some embodiments, the slope 1426 of the second surface 1424 of the thermal layer 1420 as the thermal layer 1420 extends between the second surface 1404-2 of the second die 1410-2 and the second surface 1404-1 of the first die 1410- 1 may vary between 90° and 30°. In some embodiments, the slope 1426 may be impacted based on the interconnect type (e.g., solder or metal-to-metal) and the type of underfill material 1406 (if present) between the second die 1410-2 and the first die 1410-1.
  • the interconnect type e.g., solder or metal-to-metal
  • the slope 1426 may be greater for solder interconnects in which underfill material 1406 may more substantially extend beyond the X-Y area of the second die 1410-2 in comparison to metal-to-metal interconnects in which underfill material 1406 may be less substantially extend beyond the X-Y area of the second die 1410-2.
  • the slope 1426 of the second surface 1424 of thermal layer 1420 may be substantially planar (e.g., approximately 180° and/or having a total thickness variation of less than 10 microns across the second surface 1424 of the thermal layer 1420) as the thermal layer 1420 extends between the second surface 1404-2 of the second die 1410-2 and the second surface 1404-1 of the first die 1410-1.
  • the thermal layer 1420 may be formed to "fill" the area between the dies in order to form the substantially planar second surface 1424 of the thermal layer across the second surfaces 1404 of the dies 1410.
  • the thermal layer 1420 may improve thermal spreading for the dies 1410, which may improve operating performance for the dies, as discussed herein.
  • the X-Y area of the thermal layer 1420 may be less than or equal to the X-Y area of the first (base) die 1410-1 and may be greater than the X-Y area of the second die 1410-2.
  • FIG. 13 is a top view of the microelectronic assembly 1400 of FIG. 12, in accordance with various embodiments. As illustrated in FIG.
  • Au may be less than or equal to Ai
  • Au may be greater than A2
  • Au may be greater than A3
  • Au Xu
  • FIG. 14 is a side, cross-sectional view of another example microelectronic assembly 1400 in which a heat spreader 1440 and TIM 1450 may be included in the microelectronic assembly 1400.
  • the heat spreader 1440 may be attached over the second surface 1424 of the thermal layer 1420, down the sides of the first die 1410-2, and on the package substrate 1460.
  • the heat spreader 1440 may have an X-Y area that is greater than the X-Y area of the first die 1410-1.
  • the heat spreader 1440 may be used to move heat away from the dies 1410 (e.g., so that the heat may be more readily dissipated by a heat sink or other thermal management device).
  • the heat spreader 1440 may include any suitable thermally conductive material (e.g., metal, appropriate ceramics, etc.), and may include any suitable features (e.g., fins).
  • the heat spreader 1440 may be an integrated heat spreader.
  • the TIM 1450 may include a thermally conductive material (e.g., metal particles) in a polymer or other binder.
  • the TIM 1450 may be a thermal interface material paste or a thermally conductive epoxy (which may be a fluid when applied and may harden upon curing, as known in the art).
  • the TIM 1450 may provide a path for heat generated by the dies 1410 to readily flow to the heat spreader 1440, where the heat may be further spread and/or dissipated.
  • the TIM 1450 may have a thickness 1433, which may range between 10 microns and 50 microns, in various embodiments.
  • FIG. 15 is a side, cross-sectional view of another microelectronic assembly 1400, in accordance with various embodiments.
  • dies 1410- 2/1410-3/1410-4 may have varying thicknesses 1431 and the thermal layer 1420 may be formed over the dies 1410 in a manner such that the second surface 1424 of the thermal layer 1420 is substantially planar.
  • the thermal layer 1420 may be formed to a first thickness and then reduced (e.g., ground, etched, etc.) to achieve the desired thickness 1430.
  • FIG. 16A-16B are side, cross-sectional views of various stages in an example process for manufacturing the microelectronic assembly of FIG. 12, in accordance with various embodiments.
  • FIG. 16A illustrates an assembly 1800 in which dies 1410-2/1410-3/1410-4 may be coupled to the first die 1410-1 using any suitable technique (e.g., solder interconnect techniques or non-solder interconnect techniques).
  • any suitable technique e.g., solder interconnect techniques or non-solder interconnect techniques.
  • FIG. 16B illustrates an assembly 1802 subsequent to forming the thermal layer 1420 over the second surfaces 1404 of the dies 1410.
  • Any suitable technique e.g., sputtering or plating
  • the forming may include forming the thermal layer to a first thickness and then reducing (e.g., grinding, etching, etc.) the thermal layer 1420 to achieve a desired thickness 1430.
  • the thermal layer 1420 may have an X-Y area that is greater than the X-Y area of individual ones of dies 1410-2/1410-3/1410-4 and that is less than or equal to the X-Y area of the first die 1410-1. Further operations may be performed as suitable (e.g., providing a TIM 1450 and providing a heat spreader 1440.
  • microelectronic assemblies disclosed herein may be used for any suitable application.
  • a microelectronic assembly 100/1400 may be used to provide an ultra-high density and high bandwidth interconnect for field programmable gate array (FPGA) transceivers (or other transceivers) between the transceivers and RF devices, power delivery devices, and/or other devices that may be interconnected.
  • FPGA field programmable gate array
  • Such applications may be particularly suitable for military electronics, 5G wireless communications, WiGig communications, and/or millimeter wave communications.
  • the microelectronic assemblies 100 disclosed herein may allow "blocks" of different kinds of functional circuits to be distributed into different ones of the dies 110/910/1410, instead of having all of the circuits included in a single large die, per some conventional approaches.
  • a single large die would include all of these different circuits to achieve high bandwidth, low loss communication between the circuits, and some or all of these circuits may be selectively disabled to adjust the capabilities of the large die.
  • microelectronic assemblies 100/1400 may allow high bandwidth, low loss communications, power delivery, etc., different circuits may be distributed into different dies 110/910/1410, reducing the total cost of manufacture, improving yield, and increasing design flexibility by allowing different dies 110/910/1410 (e.g., dies 110/910/1410 formed using different fabrication technologies) to be readily swapped to achieve different functionality.
  • different dies 110/910/1410 e.g., dies 110/910/1410 formed using different fabrication technologies
  • the dies 110/910 in a microelectronic assembly 100 or the dies 1410 a microelectronic assembly 1400 may be processing devices (e.g., a central processing unit, a graphics processing unit, a FPGA, a modem, an applications processor, etc.).
  • the die 110 in a microelectronic assembly 100 may be a cache memory (e.g., a third level cache memory), and one or more dies 910 may be processing devices (e.g., a central processing unit, a graphics processing unit, a FPGA, a modem, an applications processor, etc.) that share the cache memory of the die 110.
  • the first die 1410-1 in a microelectronic assembly 1400 may be a cache memory (e.g., a third level cache memory), and one or more dies 1410-2/1410-3/1410-4 may be processing devices (e.g., a central processing unit, a graphics processing unit, a FPGA, a modem, an applications processor, etc.) that share the cache memory of the first die 1410-1.
  • a cache memory e.g., a third level cache memory
  • processing devices e.g., a central processing unit, a graphics processing unit, a FPGA, a modem, an applications processor, etc.
  • FIGS. 17-21 illustrate various examples of apparatuses that may include, or be included in, any of the microelectronic assemblies 100 disclosed herein.
  • FIG. 17 is a top view of a wafer 1900 and dies 1902 that may be included in any of the microelectronic assemblies 100/1400 disclosed herein (e.g., as any suitable ones of the dies 110/910/1410 and/or the second thermal layer 140).
  • the wafer 1900 may be composed of semiconductor material and may include one or more dies 1902 having 1C structures formed on a surface of the wafer 1900.
  • Each of the dies 1902 may be a repeating unit of a semiconductor product that includes any suitable 1C.
  • the wafer 1900 may undergo a singulation process in which the dies 1902 are separated from one another to provide discrete "chips" of the semiconductor product.
  • the die 1902 may be any of the dies 110/910/1410 and/or the second thermal layer 140 disclosed herein.
  • the die 1902 may include one or more transistors (e.g., some of the transistors 2040 of FIG. 18, discussed below), supporting circuitry to route electrical signals to the transistors, passive components (e.g., signal traces, resistors, capacitors, or inductors), and/or any other 1C components.
  • the wafer 1900 or the die 1902 may include a memory device (e.g., a random access memory (RAM) device, such as a static RAM (SRAM) device, a magnetic RAM (MRAM) device, a resistive RAM (RRAM) device, a conductive-bridging RAM (CBRAM) device, etc.), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuit element.
  • RAM random access memory
  • SRAM static RAM
  • MRAM magnetic RAM
  • RRAM resistive RAM
  • CBRAM conductive-bridging RAM
  • NOR gate e.g., NOR gate
  • microelectronic assemblies 100 may be manufactured using a die-to-wafer assembly technique in which some dies 110/910/1410 are attached to a wafer 1900 that include others of the dies 110/910/1410, and the wafer 1900 is subsequently singulated.
  • FIG. 18 is a cross-sectional side view of an example 1C device 2000 that may be included in any of the microelectronic assemblies 100/1400 disclosed herein (e.g., in any of the dies
  • One or more of the 1C devices 2000 may be included in one or more dies 1902 (FIG. 17).
  • the 1C device 2000 may be formed on a substrate 2002 (e.g., the wafer 1900 of FIG. 17) and may be included in a die (e.g., the die 1902 of FIG. 17).
  • the substrate 2002 may be a semiconductor substrate composed of semiconductor material systems including, for example, n-type or p-type materials systems (or a combination of both).
  • the substrate 2002 may include, for example, a crystalline substrate formed using a bulk silicon or a SOI substructure.
  • the substrate 2002 may be formed using alternative materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Further materials classified as group ll-VI, lll-V, or IV may also be used to form the substrate 2002. Although a few examples of materials from which the substrate 2002 may be formed are described here, any material that may serve as a foundation for an 1C device 2000 may be used.
  • the substrate 2002 may be part of a singulated die (e.g., the dies 1902 of FIG. 17) or a wafer (e.g., the wafer 1900 of FIG. 17).
  • the 1C device 2000 may include one or more device layers 2004 disposed on the substrate 2002.
  • the device layer 2004 may include features of one or more transistors 2040 (e.g., metal oxide semiconductor field-effect transistors (MOSFETs)) formed on the substrate 2002 and/or any other active and/or passive circuitry as may be desired by a device manufacturer.
  • the device layer 2004 may include, for example, one or more source and/or drain (S/D) regions 2020, a gate 2022 to control current flow in the transistors 2040 between the S/D regions 2020, and one or more S/D contacts 2024 to route electrical signals to/from the S/D regions 2020.
  • the transistors 2040 may include additional features not depicted for the sake of clarity, such as device isolation regions, gate contacts, and the like.
  • the transistors 2040 are not limited to the type and configuration depicted in FIG. 18 and may include a wide variety of other types and configurations such as, for example, planar transistors, non-planar transistors, or a combination of both.
  • Non-planar transistors may include FinFET transistors, such as double-gate transistors or tri-gate transistors, and wrap-around or all- around gate transistors, such as nanoribbon and nanowire transistors.
  • Each transistor 2040 may include a gate 2022 formed of at least two layers, a gate dielectric and a gate electrode.
  • the gate dielectric may include one layer or a stack of layers.
  • the one or more layers may include silicon oxide, silicon dioxide, silicon carbide, and/or a high-k dielectric material.
  • the high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc.
  • high-k materials that may be used in the gate dielectric include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.
  • an annealing process may be carried out on the gate dielectric to improve its quality when a high-k material is used.
  • the gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or n-type work function metal, depending on whether the transistor 2040 is to be a p-type metal oxide semiconductor (PMOS) or an n-type metal oxide semiconductor (NMOS) transistor.
  • the gate electrode may consist of a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer.
  • metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the metals discussed below with reference to an NMOS transistor (e.g., for work function tuning).
  • metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to a PMOS transistor (e.g., for work function tuning).
  • the gate electrode when viewed as a cross-section of the transistor 2040 along the source-channel-drain direction, may consist of a U-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate.
  • at least one of the metal layers that form the gate electrode may simply be a planar layer that is
  • the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures.
  • the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.
  • a pair of sidewall spacers may be formed on opposing sides of the gate stack to bracket the gate stack.
  • the sidewall spacers may be formed from materials such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In some embodiments, a plurality of spacer pairs may be used; for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack. [0107]
  • the S/D regions 2020 may be formed within the substrate 2002 adjacent to the gate 2022 of each transistor 2040.
  • the S/D regions 2020 may be formed using an implantation/diffusion process or an etching/deposition process, for example.
  • dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate 2002 to form the S/D regions 2020.
  • An annealing process that activates the dopants and causes them to diffuse farther into the substrate 2002 may follow the ion-implantation process.
  • the substrate 2002 may first be etched to form recesses at the locations of the S/D regions 2020.
  • An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the S/D regions 2020.
  • the S/D regions 2020 may be fabricated using a silicon alloy such as silicon germanium or silicon carbide.
  • the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous.
  • the S/D regions 2020 may be formed using one or more alternate semiconductor materials such as germanium or a group lll-V material or alloy.
  • one or more layers of metal and/or metal alloys may be used to form the S/D regions 2020.
  • Electrical signals such as power and/or input/output (I/O) signals, may be routed to and/or from the devices (e.g., transistors 2040) of the device layer 2004 through one or more interconnect layers disposed on the device layer 2004 (illustrated in FIG. 18 as interconnect layers 2006, 2008, and 2010).
  • interconnect layers 2006, 2008, and 2010 electrically conductive features of the device layer 2004 (e.g., the gate 2022 and the S/D contacts 2024) may be electrically coupled with the interconnect structures 2028 of the interconnect layers 2006-2010.
  • the one or more interconnect layers 2006-2010 may form a metallization stack (also referred to as an "ILD stack") 2019 of the 1C device 2000.
  • the interconnect structures 2028 may be arranged within the interconnect layers 2006-2010 to route electrical signals according to a wide variety of designs. In particular, the arrangement is not limited to the particular configuration of interconnect structures 2028 depicted in FIG. 18.
  • interconnect layers 2006-2010 Although a particular number of interconnect layers 2006-2010 is depicted in FIG. 18, embodiments of the present disclosure include 1C devices having more or fewer interconnect layers than depicted.
  • the interconnect structures 2028 may include lines 2028a and/or vias 2028b filled with an electrically conductive material such as a metal.
  • the lines 2028a may be arranged to route electrical signals in a direction of a plane that is substantially parallel with a surface of the substrate 2002 upon which the device layer 2004 is formed.
  • the lines 2028a may route electrical signals in a direction in and out of the page from the perspective of FIG. 18.
  • the vias 2028b may be arranged to route electrical signals in a direction of a plane that is substantially perpendicular to the surface of the substrate 2002 upon which the device layer 2004 is formed.
  • the vias 2028b may electrically couple lines 2028a of different interconnect layers 2006-2010 together.
  • the interconnect layers 2006-2010 may include a dielectric material 2026 disposed between the interconnect structures 2028, as shown in FIG. 18.
  • the dielectric material 2026 disposed between the interconnect structures 2028 in different ones of the interconnect layers 2006-2010 may have different compositions; in other embodiments, the composition of the dielectric material 2026 between different interconnect layers 2006-2010 may be the same.
  • a first interconnect layer 2006 (referred to as Metal 1 or “Ml”) may be formed directly on the device layer 2004.
  • the first interconnect layer 2006 may include lines 2028a and/or vias 2028b, as shown.
  • the lines 2028a of the first interconnect layer 2006 may be coupled with contacts (e.g., the S/D contacts 2024) of the device layer 2004.
  • a second interconnect layer 2008 (referred to as Metal 2 or "M2") may be formed directly on the first interconnect layer 2006.
  • the second interconnect layer 2008 may include vias 2028b to couple the lines 2028a of the second interconnect layer 2008 with the lines 2028a of the first interconnect layer 2006.
  • the lines 2028a and the vias 2028b are structurally delineated with a line within each interconnect layer (e.g., within the second
  • the lines 2028a and the vias 2028b may be structurally and/or materially contiguous (e.g., simultaneously filled during a dual-damascene process) in some embodiments.
  • a third interconnect layer 2010 (referred to as Metal 3 or "M3") (and additional interconnect layers, as desired) may be formed in succession on the second interconnect layer 2008 according to similar techniques and configurations described in connection with the second interconnect layer 2008 or the first interconnect layer 2006.
  • the interconnect layers that are "higher up” in the metallization stack 2019 in the 1C device 2000 i.e., farther away from the device layer 2004
  • the 1C device 2000 may include a solder resist material 2034 (e.g., polyimide or similar material) and one or more conductive contacts 2036 formed on the interconnect layers 2006-2010.
  • a solder resist material 2034 e.g., polyimide or similar material
  • conductive contacts 2036 formed on the interconnect layers 2006-2010.
  • the conductive contacts 2036 are illustrated as taking the form of bond pads.
  • the conductive contacts 2036 may be electrically coupled with the interconnect structures 2028 and configured to route the electrical signals of the transistor(s) 2040 to other external devices.
  • solder bonds may be formed on the one or more conductive contacts 2036 to mechanically and/or electrically couple a chip including the 1C device 2000 with another component (e.g., a circuit board).
  • the 1C device 2000 may include additional or alternate structures to route the electrical signals from the interconnect layers 2006-2010; for example, the conductive contacts 2036 may include other analogous features (e.g., posts) that route the electrical signals to external components.
  • the conductive contacts 2036 may serve as the conductive contacts for any of dies 110/910/1410, as appropriate.
  • the 1C device 2000 may include another metallization stack (not shown) on the opposite side of the device layer(s)
  • This metallization stack may include multiple interconnect layers as discussed above with reference to the interconnect layers 2006-2010, to provide conductive pathways (e.g., including conductive lines and vias) between the device layer(s) 2004 and additional conductive contacts (not shown) on the opposite side of the 1C device 2000 from the conductive contacts 2036.
  • the 1C device 2000 may include one or more TSVs through the die substrate 2002; these TSVs may make contact with the device layer(s) 2004, and may provide conductive pathways between the device layer(s) 2004 and additional conductive contacts (not shown) on the opposite side of the 1C device 2000 from the conductive contacts 2036.
  • These additional conductive contacts may serve as the conductive contacts for any of the double-sided dies discussed herein, as appropriate. Example details of one example type of a double-sided 1C device are discussed in further detail in FIG. 19.
  • FIG. 19 is a side, cross-sectional view of one example type of a double-sided 1C device 2100 that may be included in any of the microelectronic assemblies 100 disclosed herein (e.g., in any of the dies 110/910).
  • One or more of the double-sided 1C devices 2100 may be included in one or more dies 1902 (FIG. 17).
  • the double-sided 1C device 2100 may be composed of semiconductor material systems including, for example, n-type or p-type materials systems (or a combination of both).
  • the 1C device may be composed of alternative materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Further materials classified as group ll-VI, lll-V, or IV may also be used to form the double-sided 1C device 2100.
  • the double-sided 1C device 2100 may include one or more device layers 2104.
  • the device layers 2104 may include features of one or more transistors (e.g., as discussed in FIG. 18) and/or any other active and/or passive circuitry as may be desired by a device manufacturer.
  • Electrical signals such as power and/or input/output (I/O) signals, may be routed to and/or from the devices of the device layers 2104 through one or more interconnect layers disposed on opposing sides of the device layers 2104 (illustrated in FIG. 19 as first interconnect layers 2106, 2108, and 2110 on a first side 2101 of the device layers 2104 and second interconnect layers 2156, 2158, and 2160 on an opposing second side 2102 of the device layers 2104).
  • electrically conductive features of the device layers 2104 may be electrically coupled with the first interconnect structures 2128 of the first interconnect layers 2106-2110 and/or with the second interconnect structures 2178 of the second interconnect layers 2156-2160.
  • the one or more first interconnect layers 2106-2110 may form a first metallization stack (e.g., an ILD stack) 2119 and the one or more second interconnect layers 2156-2160 may form a second metallization stack 2169 of the double sided 1C device 2100.
  • a first metallization stack e.g., an ILD stack
  • the one or more second interconnect layers 2156-2160 may form a second metallization stack 2169 of the double sided 1C device 2100.
  • the first interconnect structures 2128 may be arranged within the first interconnect layers 2106-2110 and the second interconnect structures 2178 may be arranged within the second interconnect layers 2156-2160 to route electrical signals according to a wide variety of designs (in particular, the arrangement is not limited to the particular configuration of the first interconnect structures 2128 and the second interconnect structures 2178 depicted in FIG. 19). Although a particular number of first interconnect layers 2106-2110 and a particular number of second interconnect layers 2156-2160 are depicted in FIG. 19, embodiments of the present disclosure include 1C devices having more or fewer first and/or second interconnect layers than depicted. Further, the particular number of first interconnect layers and second interconnect layers on opposing sides of the device layers 2104 may be the same or different from each other.
  • the first interconnect structures 2128 and/or the second interconnect structures 2178 may include lines and/or vias as discussed herein filled with an electrically conductive material such as a metal.
  • the first interconnect layers 2106-2110 may include a first dielectric material 2126 disposed between the first interconnect structures 2128, as shown in FIG. 19.
  • the first dielectric material 2126 disposed between the first interconnect structures 2128 in different ones of the first interconnect layers 2106-2110 may have different compositions; in other embodiments, the composition of the first dielectric material 2126 between different first interconnect layers 2106-2110 may be the same.
  • the second interconnect layers 2156-2160 may include a second dielectric material 2176 disposed between the second interconnect structures 2178, as shown in FIG. 19.
  • the second dielectric material 2176 disposed between the second interconnect structures 2178 in different ones of the second interconnect layers 2156-2160 may have different compositions; in other embodiments, the composition of the second dielectric material 2176 between different second interconnect layers 2156-2160 may be the same.
  • the composition of the first dielectric material 2126 and the second dielectric material 2176 may be different; in other embodiments, the composition of the first dielectric material 2126 and the second dielectric material 2176 may be the same.
  • the first interconnect layers 2106-2110 and the second interconnect layers 2156-2160 may be formed using any techniques as discussed herein (e.g., composed of M 1-M3 layers, etc.).
  • the double-sided 1C device 2100 may include a first solder resist material 2134 (e.g., polyimide or similar material) and one or more first conductive contacts 2136 formed on the first interconnect layers 2106-2110.
  • the double-sided 1C device 2100 may include a second solder resist material 2184 (e.g., polyimide or similar material) and one or more second conductive contacts 2186 formed on the second interconnect layers 2156-2160.
  • the composition of the first solder resist material 2134 and the second solder resist material 2184 may be the same; in other embodiments, the composition of the first solder resist material 2134 and the second solder resist material 2184 may be different.
  • first conductive contacts 2136 and the second conductive contacts 2186 are illustrated as taking the form of bond pads.
  • the first conductive contacts 2136 may be electrically coupled with the first interconnect structures 2128 and the second conductive contacts 2186 may be electrically coupled with the second interconnect structures 2178.
  • TSV interconnect structures may be integrated into the double-sided 1C device 2100; in such
  • the first conductive contacts 2136 and the second conductive contacts 2186 may be electrically coupled via one or more TSV interconnect structures.
  • the double-sided 1C device 2100 may include additional or alternate structures to route the electrical signals from the first interconnect layers 2106-2110 and/or the second interconnect layers 2156-2160; for example, the first conductive contacts 2136 and/or the second conductive contacts 2186 may include other analogous features (e.g., posts) that route the electrical signals to external components.
  • the conductive contacts 2136 and/or 2186 may serve as the conductive contacts for any of dies 110/910/1410 as appropriate.
  • FIG. 20 is a cross-sectional side view of an 1C device assembly 2200 that may include any of the microelectronic assemblies 100 disclosed herein.
  • the 1C device assembly 2200 may be a microelectronic assembly 100/1400.
  • the 1C device assembly 2200 includes a number of components disposed on a circuit board 2202 (which may be, e.g., a motherboard).
  • the 1C device assembly 2200 includes components disposed on a first face 2240 of the circuit board 2202 and an opposing second face 2242 of the circuit board 2202; generally, components may be disposed on one or both faces 2240 and 2242.
  • Any of the 1C packages discussed below with reference to the 1C device assembly 2200 may take the form of any suitable ones of the embodiments of the microelectronic assemblies 100 disclosed herein.
  • the circuit board 2202 may be a PCB including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 2202. In other embodiments, the circuit board 2202 may be a non-PCB substrate.
  • the 1C device assembly 2200 illustrated in FIG. 20 includes a package-on-interposer structure 2236 coupled to the first face 2240 of the circuit board 2202 by coupling components 2216.
  • the coupling components 2216 may electrically and mechanically couple the package-on-interposer structure 2236 to the circuit board 2202, and may include solder balls (as shown in FIG. 20), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure.
  • the package-on-interposer structure 2236 may include an 1C package 2220 coupled to an interposer 2204 by coupling components 2218.
  • the coupling components 2218 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 2216. Although a single 1C package 2220 is shown in FIG. 20, multiple 1C packages may be coupled to the interposer 2204; indeed, additional interposers may be coupled to the interposer 2204.
  • the interposer 2204 may provide an intervening substrate used to bridge the circuit board 2202 and the 1C package 2220.
  • the 1C package 2220 may be or include, for example, a die (the die 1902 of FIG. 17), an 1C device (e.g., the 1C device 2000 of FIG.
  • the interposer 2204 may spread a connection to a wider pitch or reroute a connection to a different connection.
  • the interposer 2204 may couple the 1C package 2220 (e.g., a die) to a set of ball grid array (BGA) conductive contacts of the coupling components 2216 for coupling to the circuit board 2202.
  • BGA ball grid array
  • the 1C package 2220 and the circuit board 2202 are attached to opposing sides of the interposer 2204; in other embodiments, the 1C package 2220 and the circuit board 2202 may be attached to a same side of the interposer 2204.
  • three or more components may be interconnected by way of the interposer 2204.
  • the interposer 2204 may be formed as a PCB, including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias.
  • the interposer 2204 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, an epoxy resin with inorganic fillers, a ceramic material, or a polymer material such as polyimide.
  • the interposer 2204 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group lll-V and group IV materials.
  • the interposer 2204 may include metal interconnects 2208 and vias 2210, including but not limited to TSVs 2206.
  • the interposer 2204 may further include embedded devices 2214, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer 2204.
  • the package-on-interposer structure 2236 may take the form of any of the package-on-interposer structures known in the art.
  • the 1C device assembly 2200 may include an 1C package 2224 coupled to the first face 2240 of the circuit board 2202 by coupling components 2222.
  • the coupling components 2222 may take the form of any of the embodiments discussed above with reference to the coupling components 2216
  • the 1C package 2224 may take the form of any of the embodiments discussed above with reference to the 1C package 2220.
  • the 1C device assembly 2200 illustrated in FIG. 20 includes a package-on-package structure 2234 coupled to the second face 2242 of the circuit board 2202 by coupling components 2228.
  • the package-on-package structure 2234 may include an 1C package 2226 and an 1C package 2232 coupled together by coupling components 2230 such that the 1C package 2226 is disposed between the circuit board 2202 and the 1C package 2232.
  • the coupling components 2228 and 2230 may take the form of any of the embodiments of the coupling components 2216 discussed above, and the 1C packages 2226 and 2232 may take the form of any of the embodiments of the 1C package 2220 discussed above.
  • the package-on-package structure 2234 may be configured in accordance with any of the package-on-package structures known in the art.
  • FIG. 21 is a block diagram of an example computing device 2300 that may include one or more of the microelectronic assemblies 100/1400 disclosed herein.
  • any suitable ones of the components of the computing device 2300 may include one or more of the 1C device assemblies 2200, 1C devices 2000, double-sided 1C devices 2100 or dies 1902 disclosed herein, and may be arranged in any of the microelectronic assemblies 100/1400 disclosed herein.
  • a number of components are illustrated in FIG. 21 as included in the computing device 2300, but any one or more of these components may be omitted or duplicated, as suitable for the application.
  • some or all of the components included in the computing device 2300 may be attached to one or more motherboards.
  • some or all of these components are fabricated onto a single system-on-a-chip (SoC) die.
  • SoC system-on-a-chip
  • the computing device 2300 may not include one or more of the components illustrated in FIG. 21, but the computing device 2300 may include interface circuitry for coupling to the one or more components.
  • the computing device 2300 may not include a display device 2306, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a display device 2306 may be coupled.
  • the computing device 2300 may not include an audio input device 2324 or an audio output device 2308, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device 2324 or audio output device 2308 may be coupled.
  • the computing device 2300 may include a processing device 2302 (e.g., one or more processing devices).
  • processing device e.g., one or more processing devices.
  • the term "processing device” or “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
  • the processing device 2302 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices.
  • DSPs digital signal processors
  • ASICs application-specific integrated circuits
  • CPUs central processing units
  • GPUs graphics processing units
  • cryptoprocessors specialized processors that execute cryptographic algorithms within hardware
  • server processors or any other suitable processing devices.
  • the computing device 2300 may include a memory 2304, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM)), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid state memory, and/or a hard drive.
  • volatile memory e.g., dynamic random access memory (DRAM)
  • nonvolatile memory e.g., read-only memory (ROM)
  • flash memory solid state memory
  • solid state memory solid state memory
  • a hard drive e.g., solid state memory, and/or a hard drive.
  • the memory 2304 may include memory that shares a die with the processing device 2302. This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).
  • eDRAM embedded dynamic random access memory
  • STT-MRAM spin transfer torque magnetic random access memory
  • the computing device 2300 may include a communication chip 2312 (e.g., one or more communication chips).
  • the communication chip 2312 may be configured for managing wireless communications for the transfer of data to and from the computing device 2300.
  • wireless and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
  • the communication chip 2312 may implement any of a number of wireless standards or protocols, including but not limited to Institute of Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), 3rd Generation Partnership Project (3GPP) Long-Term Evolution (LTE), 5G, 5G New Radio, along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultra-mobile broadband (UMB) project (also referred to as "3GPP2”), etc.).
  • IEEE Institute of Electrical and Electronic Engineers
  • 3GPP 3rd Generation Partnership Project
  • LTE Long-Term Evolution
  • 5G 5G New Radio
  • 3GPP2 ultra-mobile broadband
  • WiMAX Broadband Wireless Access
  • the communication chip 2312 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network.
  • GSM Global System for Mobile Communication
  • GPRS General Packet Radio Service
  • UMTS Universal Mobile Telecommunications System
  • HSPA High Speed Packet Access
  • E-HSPA Evolved HSPA
  • LTE Long Term Evolution
  • the communication chip 2312 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E- UTRAN).
  • EDGE Enhanced Data for GSM Evolution
  • GERAN GSM EDGE Radio Access Network
  • UTRAN Universal Terrestrial Radio Access Network
  • E- UTRAN Evolved UTRAN
  • the communication chip 2312 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless
  • the communication chip 2312 may operate in accordance with other wireless protocols in other embodiments.
  • the computing device 2300 may include an antenna 2322 to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions).
  • the communication chip 2312 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication chip 2312 may include multiple communication chips. For instance, a first communication chip 2312 may be dedicated to shorter-range wireless
  • a second communication chip 2312 may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others.
  • GPS global positioning system
  • EDGE EDGE
  • GPRS global positioning system
  • CDMA Code Division Multiple Access
  • WiMAX Long Term Evolution
  • LTE Long Term Evolution
  • EV-DO EV-DO
  • a first communication chip 2312 may be dedicated to wireless communications
  • a second communication chip 2312 may be dedicated to wired communications.
  • the computing device 2300 may include battery/power circuitry 2314.
  • the battery/power circuitry 2314 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the computing device 2300 to an energy source separate from the computing device 2300 (e.g., AC line power).
  • the computing device 2300 may include a display device 2306 (or corresponding interface circuitry, as discussed above).
  • the display device 2306 may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.
  • the computing device 2300 may include an audio output device 2308 (or corresponding interface circuitry, as discussed above).
  • the audio output device 2308 may include any device that generates an audible indicator, such as speakers, headsets, or earbuds.
  • the computing device 2300 may include an audio input device 2324 (or corresponding interface circuitry, as discussed above).
  • the audio input device 2324 may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).
  • MIDI musical instrument digital interface
  • the computing device 2300 may include a GPS device 2318 (or corresponding interface circuitry, as discussed above).
  • the GPS device 2318 may be in communication with a satellite-based system and may receive a location of the computing device 2300, as known in the art.
  • the computing device 2300 may include an other output device 2310 (or corresponding interface circuitry, as discussed above).
  • Examples of the other output device 2310 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.
  • the computing device 2300 may include an other input device 2320 (or corresponding interface circuitry, as discussed above).
  • Examples of the other input device 2320 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.
  • RFID radio frequency identification
  • the computing device 2300 may have any desired form factor, such as a hand-held or mobile electrical device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra-mobile personal computer, etc.), a desktop electrical device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable electrical device.
  • the computing device 2300 may be any other electronic device that processes data.
  • Example 1 is a microelectronic assembly, including: a die having a front side and an opposing back side; and a thermal layer at the back side of the die, wherein the thermal layer has an X-Y area that is less than or equal to an X-Y area of the die.
  • Example 2 may include the subject matter of Example 1 and may further specify that the thermal layer includes metal.
  • Example 3 may include the subject matter of Example 1 and may further specify that the thermal layer includes a composite material.
  • Example 4 may include the subject matter of Example 1 and may further specify that the thermal layer is a first thermal layer, and the microelectronic assembly further comprises a second thermal layer at a back side of the first thermal layer.
  • Example 5 may include the subject matter of Example 4 and may further specify that the first thermal layer has a thermal conductivity that is greater than a thermal conductivity of the second thermal layer.
  • Example 6 may include the subject matter of Example 4 and may further specify that the second thermal layer includes a semiconductor material.
  • Example 7 may include the subject matter of Example 6 and may further specify that the semiconductor material is silicon.
  • Example 8 may include the subject matter of Example 4 and may further include a third thermal layer between the back side of the die and a front side of the first thermal layer.
  • Example 9 may include the subject matter of Example 8 and may further specify that the die has a thickness between 10 microns and 780 microns.
  • Example 10 may include the subject matter of Example 4 and may further include at least one conductive pathway extending between the back side of the first thermal layer and a back side of the second thermal layer.
  • Example 11 may include the subject matter of Example 4 and may further specify that the second thermal layer has a thickness between 50 microns and 300 microns.
  • Example 12 may include the subject matter of any of Examples 1-11 and may further specify that the thermal layer has a thickness between 5 microns and 30 microns.
  • Example 13 is a computing device including: a die having a front side and an opposing back side;
  • a first thermal layer at the back side of the die and a second thermal layer at the back side of the first thermal layer, wherein the second thermal layer has an X-Y area that is less than or equal to an X-Y area of the die.
  • Example 14 may include the subject matter of Example 13 and may further include a third thermal layer between the back side of the die and a front side of the first thermal layer.
  • Example 15 may include the subject matter of Example 13 and may further specify that the first thermal layer has a thermal conductivity that is greater than a thermal conductivity of the second thermal layer.
  • Example 16 may include the subject matter of Example 13 and may further include at least one conductive pathway extending between the back side of the first thermal layer and a back side of the second thermal layer.
  • Example 17 may include the subject matter of Example 13 and may further specify that the first thermal layer includes a metal.
  • Example 18 may include the subject matter of Example 13 and may further specify that the first thermal layer includes a composite material.
  • Example 19 may include the subject matter of Example 13 and may further specify that the second thermal layer includes a semiconductor material.
  • Example 20 may include the subject matter of Example 19 and may further specify that the semiconductor material is silicon.
  • Example 21 may include the subject matter of Example 19 and may further specify that the semiconductor material is glass.
  • Example 22 may include the subject matter of Example 19 and may further specify that the semiconductor material is sapphire.
  • Example 23 may include the subject matter of Example 19 and may further specify that the semiconductor material includes germanium.
  • Example 24 may include the subject matter of Example 19 and may further specify that the semiconductor material includes arsenide.
  • Example 25 may include the subject matter of Example 13 and may further specify that the second thermal layer includes a lll-V material.
  • Example 26 may include the subject matter of any of Example 13-25 and may further specify that the computing device is a wearable computing device.
  • Example 27 is a microelectronic assembly including: a first die having a front side and an opposing back side; a second die having a front side and an opposing back side, wherein the second die is coupled to the back side of the first die; and a thermal layer at the back side of the first die and at the back side of the second die, wherein the thermal layer has an X-Y area that is greater than an X-Y area of the second die and that is less than or equal to an X-Y area of the first die.
  • Example 28 may include the subject matter of Example 27 and may further specify that the thermal layer has a thermal conductivity that is greater than a thermal conductivity of silicon.
  • Example 29 may include the subject matter of Example 27 and may further specify that the second die is an individual one of a plurality of second dies coupled to the back side of the first die, and the X-Y area of the thermal layer is greater than an X-Y area of individual ones of the plurality of second dies.
  • Example 30 may include the subject matter of Example 29 and may further specify that at least second die of the plurality of second dies has a thickness that is different from a thickness of at least one other of the plurality of second dies.
  • Example 31 may include the subject matter of Example 27 and may further specify that the thermal layer includes a metal.
  • Example 32 may include the subject matter of Example 27 and may further specify that the thermal layer includes a composite material.
  • Example 33 may include the subject matter of Example 27 and may further include a heat spreader over a top surface of the thermal layer, wherein the heat spreader has an X-Y area that is greater than the X-Y area of the first die.
  • Example 34 may include the subject matter of any of Examples 27-33 and may further specify that the thermal layer has a thickness between 5 microns and 300 microns.
  • Example 35 may include the subject matter of any of Examples 27-34 and may further specify that the thermal layer has a total thickness variation across the X-Y area that is less than 10 microns.
  • Example 36 may include the subject matter of any of Examples 27-35 and may further include a heat spreader at a back side of the thermal layer.
  • Example 37 may include the subject matter of Example 36 and may further include a thermal interface material between the heat spreader and at least a portion of the back side of the thermal layer.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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Abstract

L'invention concerne des substrats microélectroniques et des dispositifs et des procédés associés. Par exemple, dans certains modes de réalisation, un ensemble microélectronique peut comprendre une puce ayant un côté avant et un côté arrière opposé ; et une couche thermique sur le côté arrière de la puce, la couche thermique ayant une zone X-Y qui est inférieure ou égale à une zone X-Y de la puce.
PCT/US2017/068908 2017-12-29 2017-12-29 Structures thermiques pour ensembles microélectroniques WO2019132962A1 (fr)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090217961A1 (en) * 2004-11-12 2009-09-03 International Business Machines Corporation Integrated Thermoelectric Cooling Devices and Methods for Fabricating Same
US20150155218A1 (en) * 2013-12-04 2015-06-04 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC Packaging with Hot Spot Thermal Management Features
US9401315B1 (en) * 2015-03-26 2016-07-26 Globalfoundries Inc. Thermal hot spot cooling for semiconductor devices
US20170200667A1 (en) * 2014-06-19 2017-07-13 Dow Corning Corporation Photopatternable Silicones For Wafer Level Z-Axis Thermal Interposer
US20170372979A1 (en) * 2016-06-24 2017-12-28 Xilinx, Inc. Stacked silicon package assembly having conformal lid

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090217961A1 (en) * 2004-11-12 2009-09-03 International Business Machines Corporation Integrated Thermoelectric Cooling Devices and Methods for Fabricating Same
US20150155218A1 (en) * 2013-12-04 2015-06-04 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC Packaging with Hot Spot Thermal Management Features
US20170200667A1 (en) * 2014-06-19 2017-07-13 Dow Corning Corporation Photopatternable Silicones For Wafer Level Z-Axis Thermal Interposer
US9401315B1 (en) * 2015-03-26 2016-07-26 Globalfoundries Inc. Thermal hot spot cooling for semiconductor devices
US20170372979A1 (en) * 2016-06-24 2017-12-28 Xilinx, Inc. Stacked silicon package assembly having conformal lid

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