WO2019132905A1

WO2019132905A1 - Multiple channel layers for vertical thin film transistors

Info

Publication number: WO2019132905A1
Application number: PCT/US2017/068625
Authority: WO
Inventors: Abhishek A. Sharma; Van H. Le; Sean T. MA; Gilbert Dewey; Benjamin Chu-Kung; Jack T. Kavalieros; Yih Wang; Shriram SHIVARAMAN; Tahir Ghani
Original assignee: Intel Corporation
Priority date: 2017-12-28
Filing date: 2017-12-28
Publication date: 2019-07-04

Abstract

Embodiments herein describe techniques for a vertical TFT, which may include a gate electrode vertically above a substrate. A gate dielectric layer may be vertically above the substrate and around the gate electrode. A first layer may include a first material and may be vertically above the substrate and around the gate dielectric layer. A second layer may include a second material comprising an amorphous metal oxide, and may be vertically above the substrate and around the first layer. A third layer may include a third material, and may be vertically above the substrate and around the second layer. A source electrode may be above the substrate and adjacent to a source area of the third layer, and a drain electrode may be above the substrate and adjacent to a drain area of the third layer. Other embodiments may be described and/or claimed.

Description

MULTIPLE CHANNEL LAYERS FOR VERTICAL THIN FILM TRANSISTORS

Field

Embodiments of the present disclosure generally relate to the field of integrated circuits, and more particularly, to transistors.

Background

A thin-film transistor (TFT) is a kind of field-effect transistor including a channel layer, a gate electrode, and source and drain electrodes, over a supporting but non-conducting substrate. A TFT differs from a conventional transistor, where a channel of the conventional transistor is typically within a substrate, such as a silicon substrate. TFTs have emerged as an attractive option to fuel Moore’s law by integrating TFTs vertically in the backend, while leaving the silicon substrate areas for high-speed transistors. TFTs hold great potential for large area and flexible electronics, e.g., displays. Other applications of TFTs may include memory arrays.

TFTs may be fabricated in various architectures. For examples, a TFT may have a source electrode, a drain electrode, and a gate electrode in coplanar positions. However, such a coplanar TFT may have a large footprint. A TFT may have a back gate below a channel layer while a source electrode and a drain electrode above the channel layer. Such a back-gated TFT may still be insufficient for continuous scaling of the current technology. In addition, typical channel materials for a TFT may be susceptible to oxygen vacancy formation that may reduce the performance of the TFT.

Brief Description of the Drawings

Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example and not by way of limitation in the figures of the accompanying drawings.

Figure 1 schematically illustrates a diagram of a cross-sectional view of a vertical thin- film transistor (TFT) having multiple channel layers, in accordance with some embodiments.

Figure 2 schematically illustrates a diagram of a top view of a vertical TFT having multiple channel layers, in accordance with some embodiments.

Figure 3 illustrates a process for forming a vertical TFT having multiple channel layers, in accordance with some embodiments.

Figure 4 schematically illustrates a diagram of a vertical TFT having multiple channel layers, and formed in back-end-of-line (BEOL) on a substrate, in accordance with some embodiments.

Figure 5 schematically illustrates a memory array with multiple memory cells, where a vertical TFT may have multiple channel layers, in accordance with some embodiments.

Figure 6 schematically illustrates an interposer implementing one or more embodiments of the disclosure, in accordance with some embodiments.

Figure 7 schematically illustrates a computing device built in accordance with an embodiment of the disclosure, in accordance with some embodiments.

Detailed Description

A vertical thin-film transistor (TFT) may have a gate electrode and a channel layer in a vertical position with respect to a substrate in a horizontal direction. A source electrode or a drain electrode of a vertical TFT may not land horizontally on the channel layer. Therefore, a vertical TFT may be more compact compared to a TFT in other architectures, such as coplanar or back-gated architectures. As such, vertical TFTs may enable the continuous scaling of devices. However, materials in a channel layer of a vertical TFT may interact easily with the surrounding materials, and may have reduced performance.

Embodiments herein may include a vertical TFT having multiple channel layers. A channel layer including an amorphous metal oxide material for a vertical TFT may provide high mobility for the channel layer and high speed for the vertical TFT. However, such an amorphous metal oxide channel layer may be less stable. Two additional crystalline channel layers may be around the amorphous metal oxide channel layer to provide passivation protection for the amorphous metal oxide channel layer. Accordingly, the resulting vertical TFT having an amorphous metal oxide channel layer surrounded by crystalline channel layers may have improved stability as well as high performance.

Embodiments herein may present a vertical TFT, which may include a gate electrode vertically above a substrate and the substrate is below the gate electrode in a horizontal direction. A gate dielectric layer may include a dielectric material and may be vertically above the substrate and around the gate electrode. A first layer may include a first material and may be vertically above the substrate and around the gate dielectric layer. A second layer may include a second material comprising an amorphous metal oxide, and may be vertically above the substrate and around the first layer. A third layer may include a third material, and may be vertically above the substrate and around the second layer. A source electrode may be above the substrate and adjacent to a source area of the third layer, and a drain electrode may be above the substrate and adjacent to a drain area of the third layer.

Embodiments herein may present a method for forming a TFT. The method may include: forming a gate electrode vertically above a substrate, where the substrate may be below the gate electrode in a horizontal direction; and forming a gate dielectric layer including a dielectric material, vertically above the substrate and around the gate electrode, and conformally covering sidewall of the gate electrode. In addition, the method may include: forming a first layer including a first material, vertically above the substrate and around the gate dielectric layer; forming a second layer including a second material comprising an amorphous metal oxide, vertically above the substrate and around the first layer; and forming a third layer including a third material, vertically above the substrate and around the second layer. Furthermore, the method may include forming a source electrode above the substrate and adjacent to a source area of the third layer; and forming a drain electrode above the substrate and adjacent to a drain area of the third layer.

Embodiments herein may present a computing device, which may include a circuit board, and a memory device coupled to the circuit board and including a memory array. In more detail, the memory array may include a plurality of memory cells. A memory cell of the plurality of memory cells may include a transistor and a storage cell, where the storage cell may have an electrode coupled to a source line of the memory array. The transistor in the memory cell may include a gate electrode coupled to a word line of the memory array, wherein the gate electrode is vertically above a substrate, and the substrate is below the gate electrode in a horizontal direction; a gate dielectric layer including a dielectric material, and vertically above the substrate and around the gate electrode; a first layer including a first material, vertically above the substrate and around the gate dielectric layer; a second layer including a second material comprising an amorphous metal oxide, and vertically above the substrate and around the first layer; a third layer including a third material, and vertically above the substrate and around the second layer; a source electrode above the substrate, adjacent to a source area of the third layer, and coupled to a bit line of the memory array; a drain electrode above the substrate, adjacent to a drain area of the third layer, and coupled to a first electrode of the storage cell; and the storage cell further includes a second electrode coupled to a source line of the memory array.

In the following description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. However, it will be apparent to those skilled in the art that the present disclosure may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative implementations. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without the specific details. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative implementations.

Various operations will be described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the present disclosure. However, the order of description should not be construed to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order of presentation.

For the purposes of the present disclosure, the phrase“A and/or B” means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase“A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

The terms“over,”“under,”“between,”“above,” and“on” as used herein may refer to a relative position of one material layer or component with respect to other layers or components. For example, one layer disposed over or under another layer may be directly in contact with the other layer or may have one or more intervening layers. Moreover, one layer disposed between two layers may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first layer“on” a second layer is in direct contact with that second layer. Similarly, unless explicitly stated otherwise, one feature disposed between two features may be in direct contact with the adjacent features or may have one or more intervening features.

The description may use the phrases“in an embodiment,” or“in embodiments,” which may each refer to one or more of the same or different embodiments. Furthermore, the terms “comprising,”“including,”“having,” and the like, as used with respect to embodiments of the present disclosure, are synonymous.

The term“coupled with,” along with its derivatives, may be used herein. “Coupled” may mean one or more of the following.“Coupled” may mean that two or more elements are in direct physical or electrical contact. However,“coupled” may also mean that two or more elements indirectly contact each other, but yet still cooperate or interact with each other, and may mean that one or more other elements are coupled or connected between the elements that are said to be coupled with each other. The term“directly coupled” may mean that two or more elements are in direct contact.

In various embodiments, the phrase“a first feature formed, deposited, or otherwise disposed on a second feature” may mean that the first feature is formed, deposited, or disposed over the second feature, and at least a part of the first feature may be in direct contact (e.g., direct physical and/or electrical contact) or indirect contact (e.g., having one or more other features between the first feature and the second feature) with at least a part of the second feature.

Where the disclosure recites“a” or“a first” element or the equivalent thereof, such disclosure includes one or more such elements, neither requiring nor excluding two or more such elements. Further, ordinal indicators (e.g., first, second, or third) for identified elements are used to distinguish between the elements, and do not indicate or imply a required or limited number of such elements, nor do they indicate a particular position or order of such elements unless otherwise specifically stated.

As used herein, the term“circuitry” may refer to, be part of, or include an Application Specific Integrated Circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or group), and/or memory (shared, dedicated, or group) that execute one or more software or firmware programs, a combinational logic circuit, and/or other suitable hardware components that provide the described functionality. As used herein,“computer-implemented method” may refer to any method executed by one or more processors, a computer system having one or more processors, a mobile device such as a smartphone (which may include one or more processors), a tablet, a laptop computer, a set-top box, a gaming console, and so forth.

Implementations of the disclosure may be formed or carried out on a substrate, such as a semiconductor substrate. In one implementation, the semiconductor substrate may be a crystalline substrate formed using a bulk silicon or a silicon-on-insulator substructure. In other implementations, the semiconductor substrate may be formed using alternate materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of group III-V or group IV materials. Although a few examples of materials from which the substrate may be formed are described here, any material that may serve as a foundation upon which a semiconductor device may be built falls within the spirit and scope of the present disclosure.

A plurality of transistors, such as metal-oxide-semiconductor field-effect transistors (MOSFET or simply MOS transistors), may be fabricated on the substrate. In various implementations of the disclosure, the MOS transistors may be planar transistors, nonplanar transistors, or a combination of both. Nonplanar transistors include FinFET transistors such as double-gate transistors and tri-gate transistors, and wrap-around or all-around gate transistors such as nanoribbon and nanowire transistors. Although the implementations described herein may illustrate only planar transistors, it should be noted that the disclosure may also be carried out using nonplanar transistors.

Each MOS transistor includes a gate stack formed of at least two layers, a gate dielectric layer and a gate electrode layer. The gate dielectric layer may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide (S1O2) and/or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric layer to improve its quality when a high-k material is used.

The gate electrode layer is formed on the gate dielectric layer and may consist of at least one P-type work function metal or N-type work function metal, depending on whether the transistor is to be a PMOS or an NMOS transistor. In some implementations, the gate electrode layer may consist of a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer.

For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide. A P-type metal layer will enable the formation of a PMOS gate electrode with a work function that is between about 4.9 eV and about 5.2 eV. For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. An N-type metal layer will enable the formation of an NMOS gate electrode with a work function that is between about 3.9 eV and about 4.2 eV.

In some implementations, when viewed as a cross-section of the transistor along the source-channel-drain direction, the gate electrode may consist of a“U”-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In another implementation, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In further implementations of the disclosure, the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.

In some implementations of the disclosure, a pair of sidewall spacers may be formed on opposing sides of the gate stack that bracket the gate stack. The sidewall spacers may be formed from a material such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process operations. In an alternate implementation, a plurality of spacer pairs may be used, for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.

As is well known in the art, source and drain regions are formed within the substrate adjacent to the gate stack of each MOS transistor. The source and drain regions are generally formed using either an implantation/diffusion process or an etching/deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate to form the source and drain regions. An annealing process that activates the dopants and causes them to diffuse further into the substrate typically follows the ion implantation process. In the latter process, the substrate may first be etched to form recesses at the locations of the source and drain regions. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the source and drain regions. In some implementations, the source and drain regions may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some implementations the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In further embodiments, the source and drain regions may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. And in further embodiments, one or more layers of metal and/or metal alloys may be used to form the source and drain regions.

One or more interlayer dielectrics (ILD) are deposited over the MOS transistors. The ILD layers may be formed using dielectric materials known for their applicability in integrated circuit structures, such as low-k dielectric materials. Examples of dielectric materials that may be used include, but are not limited to, silicon dioxide (SiCh), carbon doped oxide (CDO), silicon nitride, organic polymers such as perfluorocyclobutane or polytetrafluoroethylene, fluorosilicate glass (FSG), and organosilicates such as silsesquioxane, siloxane, or

organosilicate glass. The ILD layers may include pores or air gaps to further reduce their dielectric constant.

Figure 1 schematically illustrates a diagram of a cross-sectional view of a vertical thin- film transistor (TFT) 100 having multiple channel layers, e.g., a first layer 191, a second layer 193, and a third layer 195, in accordance with some embodiments. For clarity, features of the vertical TFT 100, the first layer 191, the second layer 193, and the third layer 195 may be described below as examples for understanding an example vertical TFT having multiple channel layers. It is to be understood that there may be more or fewer components within a vertical TFT and multiple channel layers. Further, it is to be understood that one or more of the components within a vertical TFT and multiple channel layers may include additional and/or varying features from the description below, and may include any device that one having ordinary skill in the art would consider and/or refer to as a vertical TFT and multiple channel layers.

In embodiments, the vertical TFT 100 may include a substrate 101, an ILD layer 103 above the substrate 101, and a gate electrode 105 vertically above the ILD layer 103 and the substrate 101. The substrate 101 and the ILD 103 may be below the gate electrode 105 in a horizontal direction. In detail, the gate electrode 105 vertically above the substrate 101 may mean that the gate electrode 105 may be oriented in a vertical direction substantially

perpendicular or orthogonal to the plane defined by the substrate 101 that is oriented in the horizontal direction. A first direction may be substantially perpendicular or orthogonal to a second direction when there is +/- 10 degrees of orthogonality between the two directions. For example, the substrate 101 may be in the horizontal direction, while the gate electrode 105 may be vertically above the substrate 101 when the gate electrode 105 may form 80 degree or 100 degree with the horizontal direction.

In embodiments, a gate dielectric layer 107 may include a dielectric material and may be vertically above the substrate 101 and around the gate electrode 105. The first layer 191 may be vertically above the substrate 101 and around the gate dielectric layer 107. The second layer 193 may be vertically above the substrate 101 and around the first layer 191. The third layer 195 may be vertically above the substrate 101 and around the second layer 193. In addition, a source electrode 111 may be above the substrate 101 and adjacent to a source area of the third layer 195, while a drain electrode 113 may be above the substrate 101 and adjacent to a drain area of the third layer 195. An outer dielectric layer 117 may be above the substrate 101 and around the third layer 195, the source electrode 111, and the drain electrode 113. Furthermore, an isolation area 121 and an isolation area 123, which may be shallow trench isolation areas, may be within the outer dielectric layer 117, surrounding the source electrode 111, the drain electrode 113, the first layer 191, the second layer 193, the third layer 195, the gate dielectric layer 107, and the gate electrode 105. The isolation area 121 and the isolation area 123 may separate the vertical TFT 100 from other devices.

In embodiments, the gate dielectric layer 107 may further include a horizontal part 171 to extend in a horizontal direction above the substrate 101. The first layer 191 may further include a horizontal part 181 to extend in a horizontal direction above the horizontal part 171 of the gate dielectric layer 107. The second layer 193 may further include a horizontal part 183 to extend in a horizontal direction above the horizontal part 181 of the first layer 191. The third layer 195 may further include a horizontal part 185 to extend in a horizontal direction above the horizontal part 183 of the second layer 193. The first layer 191 may have a thickness in a range of about 2 nanometer (nm) to about 20 nm, the second layer 193 may have a thickness in a range of about 2 nm to about 20 nm, and the third layer 195 may have a thickness in a range of about 2 nm to about 20 nm.

In embodiments, the first layer 191 may include a first material, the second layer 193 may include a second material comprising an amorphous metal oxide, and the third layer 195 may include a third material. The first material or the third material may include one or more of: crystalline indium gallium zinc oxide (IGZO), c-axis aligned crystalline (CAAC) IGZO, yttrium- doped zinc oxide (YZO), zinc oxide (ZnO), indium zinc oxide (IZO), zinc tin oxide (ZTO), low temperature (LT) poly silicon, LT poly germanium (Ge), or transition metal dichalcogenides (TMDs). For example, the first material or the third material may include one or more of: In, Ga, Zn, O, Y, Sn, Ge, Si, MO, Se, W, S, or Te. In some embodiments, the first material may be different from the third material, while in some other embodiments, the first material may be the same as the third material. The second material for the second layer 193 comprising an amorphous metal oxide may include indium gallium zinc oxide (IGZO). The second material comprising an amorphous metal oxide for the second layer 193 may have high mobility, but may interact easily with the surrounding materials and become unstable, resulting in reduced performance for the vertical TFT 100. The first material for the first layer 191 and the third material for the third layer 195 may provide crystalline passivation for the second layer 193. Hence, the first layer 191, the second layer 193, and the third layer 195 together may form a channel layer that may have high mobility and yet stable with high performance.

In embodiments, a conductive contact 151 may be within the ILD 103, where the conductive contact 151 may be a contact for a word line of a memory array. Furthermore, an etching stop layer 115 may be below the gate electrode 105, the gate dielectric layer 107, and above the ILD 103. A via 153 may be through the etching stop layer 115 and coupled to an end of the gate electrode 105 and the conductive contact 151. In some embodiments, there may be an etching stop layer and a conductive contact above the gate electrode 105. A via may be within the etching stop layer above the gate electrode 105 to couple the gate electrode 105 to a conductive contact.

In embodiments, the substrate 101 may be a silicon substrate, a glass substrate, such as soda lime glass or borosilicate glass, a metal substrate, a plastic substrate, or another suitable substrate. Other dielectric layer or other devices may be formed on the substrate 101, not shown for clarity.

In embodiments, the ILD layer 103 may include a silicon oxide (SiO) film, a silicon nitride (SiN) film, 03-tetraethylorthosilicate (TEOS), 03-hexamethyldisiloxane (HMDS), plasma-TEOS oxide layer, or other suitable materials.

In embodiments, the gate electrode 105, the source electrode 111, the drain electrode 113, or the conductive contact 151 may be formed as a single layer or a stacked layer using one or more conductive films including a conductive material. For example, the gate electrode 105, the source electrode 111, the drain electrode 113, or the conductive contact 151, may include gold (Au), platinum (Pt), ruthenium (Ru), iridium (Ir), titanium (Ti), aluminum (Al), molybdenum (Mo), copper (Cu), tantalum (Ta), tungsten (W), nickel (Ni), chromium (Cr), hafnium (Hf), indium (In), or an alloy of Ti, Mo, Au, Pt, Al Ni, Cu, Cr, TiAlN, HfAlN, or InAlO. For example, the gate electrode 105, the source electrode 111, the drain electrode 113, or the conductive contact 151 may include tantalum nitride (TaN), titanium nitride (TiN), iridium-tantalum alloy (Ir-Ta), indium-tin oxide (ITO), the like, and/or a combination thereof.

In embodiments, the gate dielectric layer 107 may include a dielectric material, which may be a high-K dielectric material that includes one or more of: hafnium silicate, zirconium silicate, hafnium dioxide, zirconium dioxide, aluminum oxide, or nitride hafnium silicate. In some other embodiments, the gate dielectric layer 107 may include silicon and oxygen, silicon and nitrogen, yttrium and oxygen, silicon, oxygen, and nitrogen, aluminum and oxygen, hafnium and oxygen, tantalum and oxygen, or titanium and oxygen. For example, the gate dielectric layer 107 may include silicon oxide (SiC ), silicon nitride (SiN_x), yttrium oxide

(Y2O3), silicon oxynitride (8iO_xN_y), aluminum oxide (AI2O3), hafnium(IV) oxide (FlfCh), tantalum oxide (TanOs), titanium dioxide (TiCh), or other materials.

In embodiments, the outer dielectric layer 117 may include silicon dioxide (S1O2), carbon doped oxide (CDO), silicon nitride, perfluorocyclobutane, polytetrafluoroethylene, fluorosilicate glass (FSG), organic polymer, silsesquioxane, siloxane, or organosilicate glass.

Figure 2 schematically illustrates a diagram of a top view of a vertical TFT 200 having multiple channel layers, e.g., a first layer 291, a second layer 293, and a third layer 295, in accordance with some embodiments. In embodiments, the vertical TFT 200 may be the same TFT as the vertical TFT 100, shown in a top down view. The first layer 291, the second layer 293, and the third layer 295 may be the same as the first layer 191, the second layer 193, and the third layer 195, respectively, shown in Figure 1.

In embodiments, the vertical TFT 200 may include a gate electrode 205 vertically above an ILD layer and a substrate, not shown. A gate dielectric layer 207 may include a dielectric material and may be vertically above a substrate and around the gate electrode 205. The first layer 291 may be vertically above the substrate and around the gate dielectric layer 207. The second layer 293 may be vertically above the substrate and around the first layer 291. The third layer 295 may be vertically above the substrate and around the second layer 293. In addition, a source electrode 211 may be adjacent to a source area of the third layer 295, while a drain electrode 213 may be adjacent to a drain area of the third layer 295. An outer dielectric layer 217 may be around the third layer 295, the source electrode 211, and the drain electrode 213. Furthermore, an isolation area 221 and an isolation area 223, which may be shallow trench isolation areas, may be within the outer dielectric layer 217, surrounding the source electrode 211, the drain electrode 213, the first layer 291, the second layer 293, the third layer 295, the gate dielectric layer 207, and the gate electrode 205. The isolation area 221 and the isolation area 223 may separate the vertical TFT 200 from other devices.

Figure 3 illustrates a process 300 for forming a vertical TFT having multiple channel layers, in accordance with some embodiments. In embodiments, the process 300 may be applied to form the vertical TFT 100 in Figure 1, or the vertical TFT 200 in Figure 2.

At block 301, the process 300 may include forming a gate electrode above a substrate, wherein the substrate is below the gate electrode in a horizontal direction, and wherein the gate electrode is oriented in a vertical direction substantially orthogonal to the horizontal direction. For example, the process 300 may include forming the gate electrode 105 vertically above the substrate 101, where the substrate 101 may be below the gate electrode 105 in a horizontal direction, as shown in Figure 1.

At block 303, the process 300 may include forming a gate dielectric layer including a dielectric material, the gate dielectric layer oriented above the substrate in the vertical direction and around the gate electrode, and conformally covering sidewall of the gate electrode. For example, the process 300 may include forming the gate dielectric layer 107 including a dielectric material, and may be vertically above the substrate 101 and around the gate electrode 105, and conformally covering sidewall of the gate electrode 105, as shown in Figure 1.

At block 305, the process 300 may include forming a first layer including a first material, the first layer oriented above the substrate in the vertical direction and around the gate dielectric layer. For example, the process 300 may include forming the first layer 191 including a first material, vertically above the substrate 101 and around the gate dielectric layer 107.

At block 307, the process 300 may include forming a second layer including a second material comprising an amorphous metal oxide, the second layer oriented above the substrate in the vertical direction and around the first layer. For example, the process 300 may include forming the second layer 193 including a second material comprising an amorphous metal oxide, and may be vertically above the substrate 101 and around the first layer 191.

At block 309, the process 300 may include forming a third layer including a third material, the third layer oriented above the substrate in the vertical direction and around the second layer. For example, the process 300 may include forming the third layer 195 including a third material, and may be vertically above the substrate 101 and around the second layer 193.

At block 311, the process 300 may include forming a source electrode above the substrate and adjacent to a source area of the third layer. For example, the process 300 may include forming the source electrode 111 above the substrate 101 and adjacent to a source area of the third layer 195.

At block 313, the process 300 may include forming a drain electrode above the substrate and adjacent to a drain area of the third layer. For example, the process 300 may include forming the drain electrode 113 above the substrate 101 and adjacent to a drain area of the third layer 195.

In addition, the process 300 may include additional operations to form other layers, e.g., ILD layers, encapsulation layers, insulation layers, or an outer dielectric layer above the substrate, not shown.

Figure 4 schematically illustrates a diagram of a vertical TFT 400 having multiple channel layers, e.g., a first layer 491, a second layer 493, a third layer 495 and formed in back- end-of-line (BEOL) on a substrate 451, in accordance with some embodiments. The vertical TFT 400 may be an example of the vertical TFT 100 in Figure 1. Various layers in the vertical TFT 400, e.g., the first layer 491, the second layer 493, the third layer 495, may be similar to corresponding layers, e.g., the first layer 191, the second layer 193, the third layer 195, in the vertical TFT 100 in Figure 1. The structure of the vertical TFT 400 may be for illustration purpose only and is not limiting.

In embodiments, the vertical TFT 400 may be formed on the substrate 451. A gate electrode 405 may be vertically above an ILD layer 452 and the substrate 451. The substrate 451 and the ILD 452 may be below the gate electrode 405 in a horizontal direction. A gate dielectric layer 407 may include a dielectric material and may be vertically above the substrate 451 and around the gate electrode 405. The first layer 491 may be vertically above the substrate 451 and around the gate dielectric layer 407. The second layer 493 may be vertically above the substrate 451 and around the first layer 491. The third layer 495 may be vertically above the substrate 451 and around the second layer 493. In addition, a source electrode 411 may be above the substrate 451 and adjacent to a source area of the third layer 495, while a drain electrode 413 may be above the substrate 451 and adjacent to a drain area of the third layer 495. An outer dielectric layer 417 may be above the substrate 451 and around the third layer 495, the source electrode 411, and the drain electrode 413. Furthermore, an isolation area 421 and an isolation area 423, which may be shallow trench isolation areas, may be within the outer dielectric layer 417, surrounding the source electrode 411, the drain electrode 413, the first layer 491, the second layer 493, the third layer 495, the gate dielectric layer 407, and the gate electrode 405. The isolation area 421 and the isolation area 423 may separate the vertical TFT 100 from other devices.

In embodiments, the gate dielectric layer 407 may further include a horizontal part 471 to extend in a horizontal direction above the substrate 451. The first layer 491 may further include a horizontal part 481 to extend in a horizontal direction above the horizontal part 471 of the gate dielectric layer 407. The second layer 493 may further include a horizontal part 483 to extend in a horizontal direction above the horizontal part 481 of the first layer 491. The third layer 495 may further include a horizontal part 485 to extend in a horizontal direction above the horizontal part 483 of the second layer 493.

In embodiments, a conductive contact 455 may be within the ILD 452, where the conductive contact 452 may be a contact for a word line of a memory array. Furthermore, an etching stop layer 415 may be below the gate electrode 405, the gate dielectric layer 407, and above the ILD 452. A via 453 may be through the etching stop layer 415 and coupled to an end of the gate electrode 405 and the conductive contact 455.

In embodiments, the vertical TFT 400 may be formed at the BEOL 440. In addition to the vertical TFT 400, the BEOL 440 may further include a dielectric layer 460, where one or more vias, e.g., a via 468, may be connected to one or more interconnect, e.g., an interconnect 466, and an interconnect 462 within the dielectric layer 460. In embodiments, the interconnect 466 and the interconnect 462 may be of different metal layers at the BEOL 440. The dielectric layer 460 is shown for example only. Although not shown by Figure 4, in various embodiments there may be multiple dielectric layers included in the BEOL 440.

In embodiments, the BEOL 440 may be formed on the front-end-of-line (FEOL) 430.

The FEOL 430 may include the substrate 451. In addition, the FEOL 430 may include other devices, e.g., a transistor 464. In embodiments, the transistor 464 may be a FEOL transistor, including a source 461, a drain 463, and a gate 465, with a channel 467 between the source 461 and the drain 463 under the gate 465. Furthermore, the transistor 464 may be coupled to interconnects, e.g., the interconnect 462, through a via 469.

Figure 5 schematically illustrates a memory array 500 with multiple memory cells (e.g., a memory cell 502, a memory cell 504, a memory cell 506, and a memory cell 508), where a TFT, e.g., a TFT 514, may be a selector of a memory cell, e.g., the memory cell 502, in accordance with various embodiments. In embodiments, the TFT 514 may be an example of the vertical TFT 100 in Figure 1, the vertical TFT 200 in Figure 2, or the vertical TFT 400 in Figure 4. The TFT 514 may include a gate electrode 511 coupled to a word line W 1.

In embodiments, the multiple memory cells may be arranged in a number of rows and columns coupled by bit lines, e.g., bit line Bl and bit line B2, word lines, e.g., word line Wl and word line W2, and source lines, e.g., source line Sl and source line S2. The memory cell 502 may be coupled in series with the other memory cells of the same row, and may be coupled in parallel with the memory cells of the other rows. The memory array 500 may include any suitable number of one or more memory cells.

In embodiments, multiple memory cells, such as the memory cell 502, the memory cell 504, the memory cell 506, and the memory cell 508, may have a similar configuration. For example, the memory cell 502 may include the TFT 514 coupled to a storage cell 512 that may be a capacitor, which may be called a 1T1C configuration. The memory cell 502 may be controlled through multiple electrical connections to read from the memory cell, write to the memory cell, and/or perform other memory operations. In some embodiments, the storage cell 512 may be another type of storage device, e.g., a resistive random access memory (RRAM) cell.

The TFT 514 may be a selector for the memory cell 502. A word line Wl of the memory array 500 may be coupled to a gate electrode 511 of the TFT 514. When the word line Wl is active, the TFT 514 may select the storage cell 512. A source line Sl of the memory array 500 may be coupled to an electrode 501 of the storage cell 512, while another electrode 507 of the storage cell 512 may be shared with the TFT 514. In addition, a bit line Bl of the memory array 500 may be coupled to another electrode, e.g., an electrode 509 of the TFT 514. The shared electrode 507 may be a source electrode or a drain electrode of the TFT 514, while the electrode 509 may be a drain electrode or a source electrode of the TFT 514. A drain electrode and a source electrode may be used interchangeably herein. Additionally, a source line and a bit line may be used interchangeably herein.

In various embodiments, the memory cells and the transistors, e.g., the memory cell 502 and the TFT 514, included in the memory array 500 may be formed in BEOL, as shown in Figure 4. For example, the TFT 514 may be illustrated as the vertical TFT 400 shown in Figure 4 at the BEOL. Accordingly, the memory array 500 may be formed in higher metal layers, e.g., metal layer 3 and/or metal layer 5, of the integrated circuit above the active substrate region, and may not occupy the active substrate area that is occupied by conventional transistors or memory devices.

Figure 6 illustrates an interposer 600 that includes one or more embodiments of the disclosure. The interposer 600 is an intervening substrate used to bridge a first substrate 602 to a second substrate 604. The first substrate 602 may be, for instance, a substrate support for a TFT, e.g., the vertical TFT 100 shown in Figure 1, the vertical TFT 200 shown in Figure 2, or the vertical TFT 400 shown in Figure 4. The second substrate 604 may be, for instance, a memory module, a computer motherboard, or another integrated circuit die. For example, the second substrate 604 may be a memory module including the memory array 500 as shown in Figure 5. Generally, the purpose of an interposer 600 is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, an interposer 600 may couple an integrated circuit die to a ball grid array (BGA) 606 that can subsequently be coupled to the second substrate 604. In some embodiments, the first and second substrates 602/604 are attached to opposing sides of the interposer 600. In other embodiments, the first and second substrates 602/604 are attached to the same side of the interposer 600. And in further embodiments, three or more substrates are interconnected by way of the interposer 600.

The interposer 600 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further implementations, the interposer may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials.

The interposer may include metal interconnects 608 and vias 610, including but not limited to through-silicon vias (TSVs) 612. The interposer 600 may further include embedded devices 614, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio- frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer 600.

In accordance with embodiments of the disclosure, apparatuses or processes disclosed herein may be used in the fabrication of interposer 600.

Figure 7 illustrates a computing device 700 in accordance with one embodiment of the disclosure. The computing device 700 may include a number of components. In one embodiment, these components are attached to one or more motherboards. In an alternate embodiment, some or all of these components are fabricated onto a single system-on-a-chip (SoC) die, such as a SoC used for mobile devices. The components in the computing device 700 include, but are not limited to, an integrated circuit die 702 and at least one

communications logic unit 708. In some implementations the communications logic unit 708 is fabricated within the integrated circuit die 702 while in other implementations the

communications logic unit 708 is fabricated in a separate integrated circuit chip that may be bonded to a substrate or motherboard that is shared with or electronically coupled to the integrated circuit die 702. The integrated circuit die 702 may include a processor 704 as well as on-die memory 706, often used as cache memory, which can be provided by technologies such as embedded DRAM (eDRAM), or SRAM. For example, the on-die memory 706 may include the vertical TFT 100 shown in Figure 1, the vertical TFT 200 shown in Figure 2, the vertical TFT 400 shown in Figure 4, or a vertical TFT formed according to the process 300 shown in Figure 3.

In embodiments, the computing device 700 may include a display or a touchscreen display 724, and a touchscreen display controller 726. A display or the touchscreen display 724 may include a FPD, an AMOLED display, a TFT LCD, a micro light-emitting diode (pLED) display, or others. For example, the touchscreen display 724 may include the vertical TFT 100 shown in Figure 1, the vertical TFT 200 shown in Figure 2, the vertical TFT 400 shown in Figure 4, or a vertical TFT formed according to the process 300 shown in Figure 3.

Computing device 700 may include other components that may or may not be physically and electrically coupled to the motherboard or fabricated within a SoC die. These other components include, but are not limited to, volatile memory 710 (e.g., dynamic random access memory (DRAM), non-volatile memory 712 (e.g., ROM or flash memory), a graphics processing unit 714 (GPU), a digital signal processor (DSP) 716, a crypto processor 742 (e.g., a specialized processor that executes cryptographic algorithms within hardware), a chipset 720, at least one antenna 722 (in some implementations two or more antenna may be used), a battery 730 or other power source, a power amplifier (not shown), a voltage regulator (not shown), a global positioning system (GPS) device 728, a compass, a motion coprocessor or sensors 732 (that may include an accelerometer, a gyroscope, and a compass), a microphone (not shown), a speaker 734, a camera 736, user input devices 738 (such as a keyboard, mouse, stylus, and touchpad), and a mass storage device 740 (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth). The computing device 700 may incorporate further transmission, telecommunication, or radio functionality not already described herein. In some implementations, the computing device 700 includes a radio that is used to communicate over a distance by modulating and radiating electromagnetic waves in air or space. In further implementations, the computing device 700 includes a transmitter and a receiver (or a transceiver) that is used to communicate over a distance by modulating and radiating electromagnetic waves in air or space.

The communications logic unit 708 enables wireless communications for the transfer of data to and from the computing device 700. The term“wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communications logic unit 708 may implement any of a number of wireless standards or protocols, including but not limited to Wi- Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Infrared (IR), Near Field Communication (NFC), Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 700 may include a plurality of communications logic units 708. For instance, a first communications logic unit 708 may be dedicated to shorter range wireless communications such as Wi-Fi, NFC, and Bluetooth and a second communications logic unit 708 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

The processor 704 of the computing device 700 includes one or more devices, such as transistors. The term“processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The communications logic unit 708 may also include one or more devices, such as transistors.

In further embodiments, another component housed within the computing device 700 may contain one or more devices, such as DRAM, that are formed in accordance with implementations of the current disclosure, e.g., the vertical TFT 100 shown in Figure 1, the vertical TFT 200 shown in Figure 2, the vertical TFT 400 shown in Figure 4, or a vertical TFT formed according to the process 300 shown in Figure 3.

In various embodiments, the computing device 700 may be a laptop computer, a netbook computer, a notebook computer, an ultrabook computer, a smartphone, a dumbphone, a tablet, a tablet/laptop hybrid, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 700 may be any other electronic device that processes data.

Some non-limiting Examples are provided below.

Example 1 may include a vertical thin film transistor (TFT), comprising: a gate electrode above a substrate, wherein the substrate is below the gate electrode in a horizontal direction, and wherein the gate electrode is oriented in a vertical direction substantially orthogonal to the horizontal direction; a gate dielectric layer including a dielectric material, the gate dielectric layer oriented above the substrate in the vertical direction and around the gate electrode; a first layer including a first material, the first layer oriented above the substrate in the vertical direction and around the gate dielectric layer; a second layer including a second material comprising an amorphous metal oxide, the second layer oriented above the substrate in the vertical direction and around the first layer; a third layer including a third material, the third layer oriented above the substrate in the vertical direction and around the second layer; a source electrode above the substrate and adjacent to a source area of the third layer; and a drain electrode above the substrate and adjacent to a drain area of the third layer

Example 2 may include the vertical TFT of example 1 and/or some other examples herein, wherein: the gate dielectric layer further includes a horizontal part to extend in the horizontal direction above the substrate; the first layer further includes a horizontal part to extend in the horizontal direction above the horizontal part of the gate dielectric layer; the second layer further includes a horizontal part to extend in the horizontal direction above the horizontal part of the first layer; and the third layer further includes a horizontal part to extend in the horizontal direction above the horizontal part of the second layer.

Example 3 may include the vertical TFT of any one of examples 1-2 and/or some other examples herein, wherein the dielectric material is a high-K dielectric material that includes one or more of: hafnium silicate, zirconium silicate, hafnium dioxide, zirconium dioxide, aluminum oxide, or nitride hafnium silicate.

Example 4 may include the vertical TFT of any one of examples 1-2 and/or some other examples herein, wherein the first material or the third material include one or more of:

crystalline indium gallium zinc oxide (IGZO), c-axis aligned crystalline (CAAC) IGZO, yttrium-doped zinc oxide (YZO), zinc oxide (ZnO), indium zinc oxide (IZO), zinc tin oxide (ZTO), low temperature (LT) poly silicon, LT poly germanium (Ge), or transition metal dichalcogenides (TMDs).

Example 5 may include the vertical TFT of any one of examples 1-2 and/or some other examples herein, wherein the first material or the third material includes one or more of: In, Ga, Zn, O, Y, Sn, Ge, Si, MO, Se, W, S, or Te.

Example 6 may include the vertical TFT of any one of examples 1-2 and/or some other examples herein, wherein the first material is different from the third material.

Example 7 may include the vertical TFT of any one of examples 1-2 and/or some other examples herein, wherein the amorphous metal oxide of the second layer includes indium gallium zinc oxide (IGZO).

Example 8 may include the vertical TFT of any one of examples 1-2 and/or some other examples herein, wherein the first layer has a thickness in a range of about 2 nanometer (nm) to about 20 nm, the second layer has a thickness in a range of about 2 nm to about 20 nm, and the third layer has a thickness in a range of about 2 nm to about 20 nm.

Example 9 may include the vertical TFT of any one of examples 1-2 and/or some other examples herein, wherein the source electrode or the drain electrode includes titanium (Ti), molybdenum (Mo), gold (Au), platinum (Pt), aluminum (Al), nickel (Ni), copper (Cu), chromium (Cr), hafnium (Hf), indium (In), or an alloy of Ti, Mo, Au, Pt, Al, Ni, Cu, Cr, TiAlN, HfAlN, or InAlO.

Example 10 may include the vertical TFT of any one of examples 1-2 and/or some other examples herein, further comprising: a via through an etching stop layer and coupled to an end of the gate electrode; and a conductive contact coupled to the via and within a dielectric layer next to the etching stop layer.

Example 11 may include the vertical TFT of any one of examples 1-2 and/or some other examples herein, further comprising: an outer dielectric layer above the substrate and around the third layer, the source electrode, and the drain electrode.

Example 12 may include the vertical TFT of example 11 and/or some other examples herein, wherein the outer dielectric layer includes silicon dioxide (SiCh), carbon doped oxide (CDO), silicon nitride, perfluorocyclobutane, polytetrafluoroethylene, fluorosilicate glass (FSG), organic polymer, silsesquioxane, siloxane, or organosilicate glass.

Example 13 may include the vertical TFT of any one of examples 1-2 and/or some other examples herein, wherein the vertical TFT is above an interconnect that is above the substrate.

Example 14 may include a method for forming a vertical thin film transistor (TFT), the method comprising: forming a gate electrode above a substrate, wherein the substrate is below the gate electrode in a horizontal direction, and wherein the gate electrode is oriented in a vertical direction substantially orthogonal to the horizontal direction; forming a gate dielectric layer including a dielectric material, the gate dielectric layer oriented above the substrate in the vertical direction and around the gate electrode, and conformally covering sidewall of the gate electrode; forming a first layer including a first material, the first layer oriented above the substrate in the vertical direction and around the gate dielectric layer; forming a second layer including a second material comprising an amorphous metal oxide, the second layer oriented above the substrate in the vertical direction and around the first layer; forming a third layer including a third material, the third layer oriented above the substrate in the vertical direction and around the second layer; forming a source electrode above the substrate and adjacent to a source area of the third layer; and forming a drain electrode above the substrate and adjacent to a drain area of the third layer.

Example 15 may include the method of example 14 and/or some other examples herein, wherein: the gate dielectric layer further includes a horizontal part to extend in the horizontal direction above the substrate; the first layer further includes a horizontal part to extend in the horizontal direction above the horizontal part of the gate dielectric layer; the second layer further includes a horizontal part to extend in the horizontal direction above the horizontal part of the first layer; and the third layer further includes a horizontal part to extend in the horizontal direction above the horizontal part of the second layer.

Example 16 may include the method of example 14 and/or some other examples herein, further comprising: forming an outer dielectric layer above the substrate and around the third layer, the source electrode, and the drain electrode.

Example 17 may include the method of example 14 and/or some other examples herein, further comprising: forming a via through an etching stop layer, wherein the via is coupled to an end of the gate electrode; and forming a conductive contact within a dielectric layer next to the etching stop layer, wherein the conductive contact is coupled to the via.

Example 18 may include the method of any one of examples 14-17 and/or some other examples herein, wherein the first material or the third material include one or more of:

Example 19 may include the method of any one of examples 14-17 and/or some other examples herein, wherein the first material is different from the third material.

Example 20 may include the method of any one of examples 14-17 and/or some other examples herein, wherein the amorphous metal oxide of the second layer includes indium gallium zinc oxide (IGZO).

Example 21 may include the method of any one of examples 14-17 and/or some other examples herein, wherein the first layer has a thickness in a range of about 2 nanometer (nm) to about 20 nm, the second layer has a thickness in a range of about 2 nm to about 20 nm, and the third layer has a thickness in a range of about 2 nm to about 20 nm.

Example 22 may include a computing device, comprising: a circuit board; and a memory device coupled to the circuit board and including a memory array, wherein the memory array includes a plurality of memory cells, a memory cell of the plurality of memory cells includes a transistor and a storage cell, and wherein the transistor includes: a gate electrode coupled to a word line of the memory array, wherein the substrate is below the gate electrode in a horizontal direction, and the gate electrode is oriented in a vertical direction substantially orthogonal to the horizontal direction; a gate dielectric layer including a dielectric material, the gate dielectric layer oriented above the substrate in the vertical direction and around the gate electrode; a first layer including a first material, the first layer oriented above the substrate in the vertical direction and around the gate dielectric layer; a second layer including a second material comprising an amorphous metal oxide, the second layer oriented above the substrate in the vertical direction and around the first layer; a third layer including a third material, the third layer oriented above the substrate in the vertical direction and around the second layer; a source electrode above the substrate, adjacent to a source area of the third layer, and coupled to a bit line of the memory array; a drain electrode above the substrate, adjacent to a drain area of the third layer, and coupled to a first electrode of the storage cell; and the storage cell further includes a second electrode coupled to a source line of the memory array.

Example 23 may include the computing device of example 22 and/or some other examples herein, wherein: the gate dielectric layer further includes a horizontal part to extend in the horizontal direction above the substrate; the first layer further includes a horizontal part to extend in the horizontal direction above the horizontal part of the gate dielectric layer; the second layer further includes a horizontal part to extend in the horizontal direction above the horizontal part of the first layer; and the third layer further includes a horizontal part to extend in the horizontal direction above the horizontal part of the second layer.

Example 24 may include the computing device of any one of examples 22-23 and/or some other examples herein, wherein the first material or the third material include one or more of: crystalline indium gallium zinc oxide (IGZO), c-axis aligned crystalline (CAAC) IGZO, yttrium-doped zinc oxide (YZO), zinc oxide (ZnO), indium zinc oxide (IZO), zinc tin oxide (ZTO), low temperature (LT) poly silicon, LT poly germanium (Ge), or transition metal dichalcogenides (TMDs).

Example 25 may include the computing device of any one of examples 22-23 and/or some other examples herein, wherein the computing device is a wearable device or a mobile computing device, the wearable device or the mobile computing device including one or more of an antenna, a touchscreen controller, a display, a battery, a processor, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, a Geiger counter, an accelerometer, a gyroscope, a speaker, or a camera coupled with the memory device.

Example 26 may include one or more computer-readable media having instructions for forming a vertical thin film transistor (TFT), upon execution of the instructions by one or more processors, to perform the method of any one of examples 14-21.

Example 27 may include an apparatus for forming a vertical thin film transistor (TFT), the apparatus comprising: means for forming a gate electrode above a substrate, wherein the substrate is below the gate electrode in a horizontal direction, and wherein the gate electrode is oriented in a vertical direction substantially orthogonal to the horizontal direction; means for forming a gate dielectric layer including a dielectric material, the gate dielectric layer oriented above the substrate in the vertical direction and around the gate electrode, and conformally covering sidewall of the gate electrode; means for forming a first layer including a first material, the first layer oriented above the substrate in the vertical direction and around the gate dielectric layer; means for forming a second layer including a second material comprising an amorphous metal oxide, the second layer oriented above the substrate in the vertical direction and around the first layer; means for forming a third layer including a third material, the third layer oriented above the substrate in the vertical direction and around the second layer; means for forming a source electrode above the substrate and adjacent to a source area of the third layer; and means for forming a drain electrode above the substrate and adjacent to a drain area of the third layer.

Example 28 may include the apparatus of example 27 and/or some other examples herein, wherein: the gate dielectric layer further includes a horizontal part to extend in the horizontal direction above the substrate; the first layer further includes a horizontal part to extend in the horizontal direction above the horizontal part of the gate dielectric layer; the second layer further includes a horizontal part to extend in the horizontal direction above the horizontal part of the first layer; and the third layer further includes a horizontal part to extend in the horizontal direction above the horizontal part of the second layer.

Example 29 may include the apparatus of example 27 and/or some other examples herein, further comprising: means for forming an outer dielectric layer above the substrate and around the third layer, the source electrode, and the drain electrode.

Example 30 may include the apparatus of example 27 and/or some other examples herein, further comprising: means for forming a via through an etching stop layer, wherein the via is coupled to an end of the gate electrode; and means for forming a conductive contact within a dielectric layer next to the etching stop layer, wherein the conductive contact is coupled to the via.

Example 31 may include the apparatus of any one of examples 27-30 and/or some other examples herein, wherein the first material or the third material include one or more of:

Example 32 may include the apparatus of any one of examples 27-30 and/or some other examples herein, wherein the first material is different from the third material.

Example 33 may include the apparatus of any one of examples 27-30 and/or some other examples herein, wherein the amorphous metal oxide of the second layer includes indium gallium zinc oxide (IGZO).

Example 34 may include the apparatus of any one of examples 27-30 and/or some other examples herein, wherein the first layer has a thickness in a range of about 2 nanometer (nm) to about 20 nm, the second layer has a thickness in a range of about 2 nm to about 20 nm, and the third layer has a thickness in a range of about 2 nm to about 20 nm.

Various embodiments may include any suitable combination of the above-described embodiments including alternative (or) embodiments of embodiments that are described in conjunctive form (and) above (e.g., the“and” may be“and/or”). Furthermore, some embodiments may include one or more articles of manufacture (e.g., non-transitory computer- readable media) having instructions, stored thereon, that when executed result in actions of any of the above-described embodiments. Moreover, some embodiments may include apparatuses or systems having any suitable means for carrying out the various operations of the above- described embodiments.

The above description of illustrated implementations, including what is described in the Abstract, is not intended to be exhaustive or to limit the embodiments of the present disclosure to the precise forms disclosed. While specific implementations and examples are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the present disclosure, as those skilled in the relevant art will recognize.

These modifications may be made to embodiments of the present disclosure in light of the above detailed description. The terms used in the following claims should not be construed to limit various embodiments of the present disclosure to the specific implementations disclosed in the specification and the claims. Rather, the scope is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.

Claims

Claims What is claimed is:

1. A vertical thin film transistor (TFT), comprising:

a gate electrode above a substrate, wherein the substrate is below the gate electrode in a horizontal direction, and wherein the gate electrode is oriented in a vertical direction substantially orthogonal to the horizontal direction;

a gate dielectric layer including a dielectric material, the gate dielectric layer oriented above the substrate in the vertical direction and around the gate electrode;

a first layer including a first material, the first layer oriented above the substrate in the vertical direction and around the gate dielectric layer;

a second layer including a second material comprising an amorphous metal oxide, the second layer oriented above the substrate in the vertical direction and around the first layer; a third layer including a third material, the third layer oriented above the substrate in the vertical direction and around the second layer;

a source electrode above the substrate and adjacent to a source area of the third layer; and

a drain electrode above the substrate and adjacent to a drain area of the third layer.

2. The vertical TFT of claim 1, wherein:

the gate dielectric layer further includes a horizontal part to extend in the horizontal direction above the substrate;

the first layer further includes a horizontal part to extend in the horizontal direction above the horizontal part of the gate dielectric layer;

the second layer further includes a horizontal part to extend in the horizontal direction above the horizontal part of the first layer; and

the third layer further includes a horizontal part to extend in the horizontal direction above the horizontal part of the second layer.

3. The vertical TFT of any one of claims 1-2, wherein the dielectric material is a high-K dielectric material that includes one or more of: hafnium silicate, zirconium silicate, hafnium dioxide, zirconium dioxide, aluminum oxide, or nitride hafnium silicate.

4. The vertical TFT of any one of claims 1-2, wherein the first material or the third material include one or more of: crystalline indium gallium zinc oxide (IGZO), c-axis aligned crystalline (CAAC) IGZO, yttrium-doped zinc oxide (YZO), zinc oxide (ZnO), indium zinc oxide (IZO), zinc tin oxide (ZTO), low temperature (LT) poly silicon, LT poly germanium (Ge), or transition metal dichalcogenides (TMDs).

5. The vertical TFT of any one of claims 1-2, wherein the first material or the third material includes one or more of: In, Ga, Zn, O, Y, Sn, Ge, Si, MO, Se, W, S, or Te.

6. The vertical TFT of any one of claims 1-2, wherein the first material is different from the third material.

7. The vertical TFT of any one of claims 1-2, wherein the amorphous metal oxide of the second layer includes indium gallium zinc oxide (IGZO).

8. The vertical TFT of any one of claims 1-2, wherein the first layer has a thickness in a range of about 2 nanometer (nm) to about 20 nm, the second layer has a thickness in a range of about 2 nm to about 20 nm, and the third layer has a thickness in a range of about 2 nm to about 20 nm.

9. The vertical TFT of any one of claims 1-2, wherein the source electrode or the drain electrode includes titanium (Ti), molybdenum (Mo), gold (Au), platinum (Pt), aluminum (Al), nickel (Ni), copper (Cu), chromium (Cr), hafnium (Hf), indium (In), or an alloy of Ti, Mo, Au, Pt, Al, Ni, Cu, Cr, TiAlN, HfAlN, or InAlO.

10. The vertical TFT of any one of claims 1-2, further comprising:

a via through an etching stop layer and coupled to an end of the gate electrode; and a conductive contact coupled to the via and within a dielectric layer next to the etching stop layer.

11. The vertical TFT of any one of claims 1-2, further comprising:

an outer dielectric layer above the substrate and around the third layer, the source electrode, and the drain electrode.

12. The vertical TFT of claim 11, wherein the outer dielectric layer includes silicon dioxide (SiC ), carbon doped oxide (CDO), silicon nitride, perfluorocyclobutane,

polytetrafluoroethylene, fluorosilicate glass (FSG), organic polymer, silsesquioxane, siloxane, or organosilicate glass.

13. The vertical TFT of any one of claims 1-2, wherein the vertical TFT is above an interconnect that is above the substrate.

14. A method for forming a vertical thin film transistor (TFT), the method comprising: forming a gate electrode above a substrate, wherein the substrate is below the gate electrode in a horizontal direction, and wherein the gate electrode is oriented in a vertical direction substantially orthogonal to the horizontal direction;

forming a gate dielectric layer including a dielectric material, the gate dielectric layer oriented above the substrate in the vertical direction and around the gate electrode, and conformally covering sidewall of the gate electrode;

forming a first layer including a first material, the first layer oriented above the substrate in the vertical direction and around the gate dielectric layer;

forming a second layer including a second material comprising an amorphous metal oxide, the second layer oriented above the substrate in the vertical direction and around the first layer;

forming a third layer including a third material, the third layer oriented above the substrate in the vertical direction and around the second layer;

forming a source electrode above the substrate and adjacent to a source area of the third layer; and

forming a drain electrode above the substrate and adjacent to a drain area of the third layer.

15. The method of claim 14, wherein:

16. The method of claim 14, further comprising:

forming an outer dielectric layer above the substrate and around the third layer, the source electrode, and the drain electrode.

17. The method of claim 14, further comprising:

forming a via through an etching stop layer, wherein the via is coupled to an end of the gate electrode; and

forming a conductive contact within a dielectric layer next to the etching stop layer, wherein the conductive contact is coupled to the via.

18. The method of any one of claims 14-17, wherein the first material or the third material include one or more of: crystalline indium gallium zinc oxide (IGZO), c-axis aligned crystalline (CAAC) IGZO, yttrium-doped zinc oxide (YZO), zinc oxide (ZnO), indium zinc oxide (IZO), zinc tin oxide (ZTO), low temperature (LT) poly silicon, LT poly germanium (Ge), or transition metal dichalcogenides (TMDs).

19. The method of any one of claims 14-17, wherein the first material is different from the third material.

20. The method of any one of claims 14-17, wherein the amorphous metal oxide of the second layer includes indium gallium zinc oxide (IGZO).

21. The method of any one of claims 14-17, wherein the first layer has a thickness in a range of about 2 nanometer (nm) to about 20 nm, the second layer has a thickness in a range of about 2 nm to about 20 nm, and the third layer has a thickness in a range of about 2 nm to about 20 nm.

22. A computing device, comprising:

a circuit board; and

a memory device coupled to the circuit board and including a memory array, wherein the memory array includes a plurality of memory cells, a memory cell of the plurality of memory cells includes a transistor and a storage cell, and wherein the transistor includes:

a gate electrode coupled to a word line of the memory array, wherein the substrate is below the gate electrode in a horizontal direction, and the gate electrode is oriented in a vertical direction substantially orthogonal to the horizontal direction;

a gate dielectric layer including a dielectric material, the gate dielectric layer oriented above the substrate in the vertical direction and around the gate electrode; a first layer including a first material, the first layer oriented above the substrate in the vertical direction and around the gate dielectric layer;

a second layer including a second material comprising an amorphous metal oxide, the second layer oriented above the substrate in the vertical direction and around the first layer;

a third layer including a third material, the third layer oriented above the substrate in the vertical direction and around the second layer;

a source electrode above the substrate, adjacent to a source area of the third layer, and coupled to a bit line of the memory array;

a drain electrode above the substrate, adjacent to a drain area of the third layer, and coupled to a first electrode of the storage cell; and

the storage cell further includes a second electrode coupled to a source line of the memory array.

23. The computing device of claim 22, wherein:

24. The computing device of any one of claims 22-23, wherein the first material or the third material include one or more of: crystalline indium gallium zinc oxide (IGZO), c-axis aligned crystalline (CAAC) IGZO, yttrium-doped zinc oxide (YZO), zinc oxide (ZnO), indium zinc oxide (IZO), zinc tin oxide (ZTO), low temperature (LT) poly silicon, LT poly germanium (Ge), or transition metal dichalcogenides (TMDs).

25. The computing device of any one of claims 22-23, wherein the computing device is a wearable device or a mobile computing device, the wearable device or the mobile computing device including one or more of an antenna, a touchscreen controller, a display, a battery, a processor, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, a Geiger counter, an accelerometer, a gyroscope, a speaker, or a camera coupled with the memory device.