WO2019127694A1

WO2019127694A1 - Gate driver and drive circuit

Info

Publication number: WO2019127694A1
Application number: PCT/CN2018/072888
Authority: WO
Inventors: 陈帅
Original assignee: 深圳市华星光电技术有限公司
Priority date: 2017-12-26
Filing date: 2018-01-16
Publication date: 2019-07-04
Also published as: CN107978290A

Abstract

Embodiments of the present invention disclose a gate driver and a drive circuit. The gate driver comprises a pull-up control module, a pull-down maintenance module, a pull-up module, a signal download module, a pull-down module, and a bootstrap module; the pull-up control module, the pull-down maintenance module, the pull-up module, the signal download module, the pull-down module, and the bootstrap module are connected, and a connection point thereof is a gate signal point; the pull-down maintenance module, the bootstrap module, the pull-up module, and the pull-down module are separately connected to a horizontal scanning line. According to the embodiments of the present invention, the level on the horizontal scanning line is pulled down by using both the pull-up module and the pull-down module, so that the pull-down effect of the gate driver can be effectively improved and the circuit stability can be increased.

Description

Gate driver and driving circuit

Technical field

The present invention relates to the field of electronic technologies, and in particular, to a gate driver and a driving circuit.

Background technique

A Gate Driver on Array (GOA) is an electronic device for scanning and driving a liquid crystal panel. Since the gate driver has the advantages of low cost and high efficiency, it is often used in various display screens, such as an active-matrix organic light emitting diode (AMOLED) of a self-luminous display screen, and The practical application of AMOLED is faster, so the gate driver is also the key technology for the development of LCD panels in the future.

In more sophisticated circuits, capacitive coupling is a problem that cannot be ignored. Capacitive coupling refers to the presence of capacitance between any two energized conductors, such as between power transmission lines, between power transmission lines and ground, between transistors, and between components. If the capacitive coupling of the data line in the liquid crystal panel to the horizontal signal scan line of the gate driver is serious, the gate driver may not be able to pull down the potential of the horizontal scanning line of the liquid crystal panel, and the gate of the liquid crystal panel may not be effectively turned off. , thus causing the screen to display an abnormality.

Since the capacitive coupling in the circuit is severe and the gate driver has insufficient pulling force, the level of the horizontal scan line of the gate driver cannot be effectively pulled down.

Summary of the invention

The embodiment of the invention provides a gate driver, which can effectively lower the level of the horizontal scan line of the gate driver and improve the stability of the circuit.

In a first aspect, an embodiment of the present invention provides a gate driver, including a pull-up control module, a pull-down maintenance module, a pull-up module, a signal downlink module, a pull-down module, and a bootstrap module; the pull-up control module includes a port; the pull-down maintaining module includes a first port, a second port, and a third port; the pull-up module includes a first port, a second port, and a third port; the signal downlink module includes a first port and a second port; the pull-down module includes a first port, a second port, a third port, a fourth port, and a fifth port; the bootstrap module includes a first port and a second port;

a first port of the pull-up control module, a first port of the pull-up module, a first port of the signal downlink module, a first port of the pull-down module, and a first port of the pull-down maintenance module Connected to the first port of the bootstrap module, the connection point is a gate signal point; the second port of the pull-down maintenance module, the second port of the pull-down module, the second port of the bootstrap module, and The second port of the pull-up module is respectively connected to the horizontal scan line; the third port of the pull-down maintenance module and the third port of the pull-down module are respectively connected to the low-level signal line; the third of the pull-up module The port and the second port of the signal downlink module are respectively connected to the clock signal line;

The pull-up control module is configured to precharge the gate signal point, and when the gate signal point is at a high level, control the pull-up module to output the signal of the clock signal line to the a horizontal scan line; in a case where the first control signal received by the fourth port of the pull-down module is at a high level, the pull-down module outputs a signal of the low-level signal line to the horizontal scan line In a case where the second control signal received by the fifth port of the pull-down module is a high level, the pull-down module outputs a signal of the low-level signal line to the gate signal point, and the control station a pull-down maintaining module outputs a signal of the low-level signal line to the horizontal scan line; the bootstrap module is configured to increase and maintain a level of the gate signal point; and the signal downlink module is used to When the gate signal point is at a high level, the signal of the clock signal line is transmitted to other electronic devices.

In conjunction with the first aspect, in a first implementation of the first aspect, the first control signal is different from the second control signal.

In conjunction with the first aspect, and any one of the foregoing first aspects, in the second implementation of the first aspect, the pull-up control module includes: a first transistor; a source and a source of the first transistor a gate signal point connection; controlling a drain of the first transistor to input a received signal to a source of the first transistor when a gate of the first transistor is at a high level; pole.

In conjunction with the first aspect and any one of the foregoing first aspects, in a third implementation of the first aspect, the pull-up circuit includes a second one transistor; a gate of the second one transistor and the gate a pole signal point connection; a drain of the second transistor is coupled to a second port of the signal downlink module; a source of the second transistor is coupled to the horizontal scan line; When the gate of the transistor is at a high level, the drain of the second transistor is controlled to input a signal of the clock signal line to a source of the second transistor.

In conjunction with the first aspect, and any one of the foregoing first aspects, in a fourth implementation of the first aspect, the signal downlink module includes a third transistor; a gate of the third transistor and the a gate signal point is connected; a drain of the third transistor is connected to a third port of the pull-up module; and in a case where a gate of the third transistor is at a high level, the third is controlled A drain of a transistor inputs a signal of the clock signal line to a source of the third transistor.

In combination with the first aspect and any one of the foregoing first aspects, in a fifth implementation of the first aspect, the pull-down module includes a fourth transistor and a fourth transistor; a drain of the fourth transistor Connected to the horizontal scan line, the drain of the fourth transistor is connected to the gate signal point; the source of the fourth transistor and the source of the fourth transistor are maintained with the pull-down a module connection; a gate of the fourth transistor and a gate of the fourth transistor are respectively configured to receive a first control signal and a second control signal; and a gate of the fourth transistor is at a high level a case where a source of the fourth transistor is controlled to input a signal of the low level signal line to a drain of the fourth transistor; and a gate of the fourth transistor is at a high level In a case, the source of the fourth transistor is controlled to input a signal of the low-level signal line to a drain of the fourth transistor.

In conjunction with the first aspect, and any one of the foregoing first aspects, in the sixth implementation of the first aspect, the pull-down maintaining module includes an inverter, a fifth one transistor, and a fifth two transistor; The input end of the device is connected to the gate signal point, the output end of the inverter is connected to the gate of the fifth transistor and the gate of the fifth transistor; the fifth transistor a drain is connected to the horizontal scan line, a source of the fifth transistor is connected to a third port of the pull-down module, and a drain of the fifth transistor is connected to the gate signal point, a source of the fifth transistor is connected to the third port of the pull-down module; and when the input of the inverter is at a low level, an output of the inverter is toward the fifth transistor The gate outputs a high level, and a signal for controlling the low level signal line is transmitted from a source of the fifth transistor to a drain of the fifth transistor.

In conjunction with the first aspect, and any one of the foregoing first aspects, in the seventh implementation of the first aspect, the bootstrap module includes a first capacitor; one end of the first capacitor and the gate signal point Connected, the other end is connected to the horizontal scan line.

In conjunction with the sixth implementation of the first aspect, in an eighth implementation of the first aspect, the inverter includes a fifth three transistor, a fifth four transistor, a fifth five transistor, and a fifth six transistor; a pole signal point is connected to a gate of the fifth five transistor and a gate of the fifth six transistor; a source of the fifth five transistor and a source of the fifth six transistor and the pull-down module a third port connection; a drain of the fifth five transistor is connected to a source of the fifth three transistor and a gate of the five or four transistor; a drain of the fifth six transistor and the five or four transistor a source, a gate connection of the five-one transistor, and a gate connection of the five-two transistor; a gate of the five-three transistor, a drain of the five-three transistor, and a drain of the five-four transistor connection.

In a second aspect, an embodiment of the present invention provides a driving circuit, wherein the driving circuit includes a plurality of gate drivers according to any one of claims 1-9; The signal downlink module further includes a third port; the pull-up control module of the gate driver further includes a second port; and the third port and the (N+) of the signal downlink module of the Nth-level gate driver 1) The second port of the pull-up control module of the stage gate driver is connected.

In the embodiment of the present invention, by using the pull-down module and the pull-up module to jointly pull down the level on the horizontal scan line, the pull-down effect of the gate driver can be effectively improved, and the stability of the circuit is improved.

DRAWINGS

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly described below.

1 is a schematic structural diagram of a gate driver according to an embodiment of the present invention;

2 is a schematic diagram of voltage variation in a gate driver according to an embodiment of the present invention;

3 is a schematic structural diagram of a gate driver according to another embodiment of the present invention;

4 is a schematic structural diagram of a gate driver according to another embodiment of the present invention;

FIG. 5 is a schematic block diagram of a terminal device according to another embodiment of the present invention; FIG.

6 is a schematic diagram of voltage variation in a gate driver according to an embodiment of the present invention;

FIG. 7 is a schematic diagram of voltage changes in a gate signal point of a gate driver according to an embodiment of the present invention.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described in the following with reference to the accompanying drawings.

The use of the terms "comprising", "comprising", "","," The presence or addition of a plurality of other features, integers, steps, operations, elements, components, and/or collections thereof.

It is also to be understood that the terminology of the present invention is to be construed as a The singular forms "", ",",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,

It is further understood that the term "and/or" used in the description of the invention and the appended claims means any combination and all possible combinations of one or more of the associated listed items, .

As used in this specification and the appended claims, the term "if" can be interpreted as "when" or "on" or "in response to determining" or "in response to detecting" depending on the context. . Similarly, the phrase "if determined" or "if detected [condition or event described]" may be interpreted in context to mean "once determined" or "in response to determining" or "once detected [condition or event described] ] or "in response to detecting [conditions or events described]".

A device including a display panel includes a driving circuit for driving the display panel, and the driving circuit is often cascaded by a plurality of gate drivers. As shown in FIG. 1, FIG. 1 is a schematic structural diagram of a gate driver according to an embodiment of the present invention. The gate driver as shown in FIG. 1 includes a pull-up control module 1', a pull-down maintenance module 5', a pull-up module 2', a signal downlink module 3', a pull-down module 4', and a bootstrap module 6'; The control module 1', the pull-down maintenance module 5', the pull-up module 2', the signal downlink module 3', the pull-down module 4', and the bootstrap module 6' are connected, and the connection point is the gate signal point Q(N); The module 5', the bootstrap module 6', the pull-up module 2', and the pull-down module 4' are connected to the horizontal scanning line G(N), respectively. Wherein, the pull-up control module 1' is used for pre-charging the gate signal point Q(N), the pull-up module 2' is used to increase the point potential on the horizontal scanning line G(N); the signal downlink module 3' is used for Controlling the opening and closing of the next stage gate driver connected to the gate driver; the pull-down module 4' is for pulling the potentials of Q(N) and G(N) to be consistent with the low level signal VSS; the pull-down sustaining unit The point potential for controlling Q(N) and G(N) is maintained at VSS; the bootstrap capacitor is used to increase and maintain the point potential of Q(N).

When the signals in the pull-up control signals ST(N-1) and G(N-1) are at a high level, the pull-up control module 1' precharges Q(N) when the point potential in Q(N) When the high level capable of driving the pull-up module 2' is reached, the pull-up module 2' transmits the clock signal CK to the pull-up control signal ST(N) of the G(N) and pull-up control module 1' of the next gate driver. When the control signal G(N+1) is high, the pull-down module 4' transmits the low-level signal VSS to G(N), so that the level of G(N) is pulled low to low level, so VSS The signal not only stabilizes the stability of the entire gate driver, but also pulls the high potential G(N) low to a low level, which may result in insufficient VSS pull, resulting in the gate driver not being able to pull down the gate. The potential on the line, the gate on the display panel cannot be turned off immediately, causing the screen to display an abnormality.

Specifically, the signal change in the circuit is as shown in FIG. 2. In the time period t1, the pull-up control signal ST(N-1) and the horizontal scan signal G(N-1) transmitted by the previous driver are at a high level, essentially The signals of ST(N-1) and G(N-1) at time t1 are derived from the clock signal obtained by the previous driver, so the pull-up control module 1' precharges Q(N) so that Q(N) At a high level v1, the pull-up module 2' transmits the signal of the clock signal line obtained by the third port of the pull-up module 2' from the second port of the pull-up module 2' to the horizontal scan line, so that G(N The point is at a low level; during the time period t2, the point potential of Q(N) due to capacitive coupling is raised to another higher level v2, so that the pull-up module 2' will pull up the module 2' The signal of the clock signal line obtained by the three ports is transmitted from the second port of the pull-up module 2' to the horizontal scanning line, so that the G(N) point is at a high level, so the pull-up module 2' is used to raise the horizontal scanning line. Point G (N) point potential; during the time period t3, since the control signal G(N-1) obtained by the pull-down module 4' is at a high level, the pull-down module 4' will pull down the module The VSS obtained by the third port of 4' is transmitted from the first port and the second port of the pull-down module 4' to Q(N) and G(N), respectively, such that Q(N) and G(N) are at a low level, Therefore, the pull-down module 4' is used to pull down the point potential of a point G(N) on the horizontal scanning line, and thus it seems that VSS not only needs to stabilize the low level of the horizontal scanning line of the entire liquid crystal panel, but also needs to be The high level of the horizontal scan line of the level gate driver is pulled low to a low level, so the problem of insufficient pulling force of the gate driver may be caused, so that the horizontal scanning line of the liquid crystal panel cannot be pulled down in time, causing the liquid crystal panel to display abnormal.

In view of the above problems, embodiments of the present invention provide a gate driver that can effectively lower the level of a gate line of a liquid crystal panel and improve stability of the circuit. The details are described below.

3 is a schematic structural diagram of a gate driver according to an embodiment of the present invention. As shown, the gate driver includes a pull-up control module, a pull-down maintenance module 5, a pull-up module 2, a signal downlink module 3, and a pull-down module. Module 4 and bootstrap module 6; pull-up control module 1 includes a first port; pull-down maintenance module 5 includes a first port, a second port, and a third port; pull-up module 2 includes a first port, a second port, and a third a port; the signal downlink module 3 includes a first port and a second port; the pull-down module 4 includes a first port, a second port, a third port, a fourth port, and a fifth port; the bootstrap module 6 includes a first port and a Two ports

The first port 11 of the pull-up control module 1, the first port 21 of the pull-up module 2, the first port 31 of the signal downlink module 3, the first port 41 of the pull-down module 4, and the first port 51 of the pull-down maintenance module 5 Connected to the first port 61 of the bootstrap module 6, the connection point is the gate signal point Q(N); the second port 52 of the pull-down maintenance module 5, the second port 42 of the pull-down module 4, and the second of the bootstrap module 6 The port 62 and the second port 22 of the pull-up module 2 are respectively connected to the horizontal scanning line G(N); the third port 53 of the pull-down maintaining module 5 and the third port 43 of the pull-down module 4 are respectively connected to the low-level signal line VSS. The third port 23 of the pull-up module 2 and the second port 32 of the signal downlink module 3 are respectively connected to the clock signal line CK;

The pull-up control module 1 is configured to precharge the gate signal point Q(N), and in the case that the gate signal point Q(N) is at a high level, the pull-up module 2 is controlled to output the signal of the clock signal line CK to Horizontal scanning line G(N); in the case where the first control signal G(N+1) received by the fourth port 44 of the pull-down module 4 is at a high level, the pull-down module 4 sets the signal VSS of the low-level signal line Output to the horizontal scan line G(N); in the case where the second control signal G(N+2) received by the fifth port 45 of the pull-down module 4 is at a high level, the pull-down module 4 sets the low-level signal line The signal VSS is output to the gate signal point Q(N), and the pull-down maintaining module 5 outputs the signal VSS of the low-level signal line to the horizontal scanning line G(N); the bootstrap module 6 is used to raise and maintain the gate signal point Q. The level of (N); the signal downlink module 3 is for transmitting the signal CK of the clock signal line to other electronic devices when the gate signal point Q(N) is at a high level.

Optionally, the first control signal G(N+1) is different from the second control signal G(N+2).

It should be noted that the pull-up control module 1 is used to precharge the gate signal point Q(N), and the pull-up module 2 is used to increase the point potential of a point G(N) on the horizontal scanning line; the signal downlink module 3 For controlling the opening and closing of the next-stage gate driver connected to the gate driver; the pull-down module 4 is for pulling the potentials of Q(N) and G(N) to be consistent with the low-level signal VSS; The unit is used to control the point potentials of Q(N) and G(N) to remain unchanged at VSS; the bootstrap capacitor is used to increase and maintain the point potential of Q(N).

Specifically, the signal changes are shown in Figures 6 and 7. During the t1 period, the pull-up control module 1 pre-charges Q(N) to a level v1 capable of driving the pull-up module 2, so the pull-up module 2 transmits the signal CK in the clock signal line to G(N), Let G(N) be low (essentially the pull-up control signal ST(N-1) at time t1 and the signal G(N-1) on the horizontal scan line of the upper driver are derived from the previous driver) The clock signal), at this time, the signal for pulling down G(N) is CK; during the time period t2, the point potential in Q(N) continues to be raised to V2 due to capacitive coupling, so that the pull-up module 2 Continue to transfer CK to G(N) so that G(N) is high, so pull-up module 2 is used to increase the point potential of a point G(N) on the horizontal scanning line; during time t3, Q( The N) point is pulled low to the high level V3 due to the end of the capacitive coupling of the CL signal, so the pull-up module 2 continues to transfer CK to G(N), so that G(N) is low, and at the same time, the second The control signal Q(N+1) is at a high level, and the pull-down module 4 transmits a low-level signal VSS to G(N). At this time, the signal for pulling down G(N) is CK and VSS; at time t4 Inside, the first control signal Q(N+2) is high level, under The pull module 4 transmits the low level signal VSS to Q(N), so that the first port of the pull-down maintaining module 5 inputs a low level, so the pull-down maintaining module 5 pulls down the VSS signal obtained by the third port of the pull-down maintaining module 5 The second port of the maintenance module 5 is transmitted to G(N), and the signal for pulling down G(N) is VSS.

In summary, the gate driver provided by the embodiment of the present invention is directly shifted by the pull-up module 2 and the pull-down module 4 to lower the level of the horizontal scan line of the current gate driver, which can effectively improve the gate driver. Pull down the effect to improve the stability of the circuit.

Please refer to FIG. 4, which is further refined on the basis of FIG. 4 is a schematic structural view of a gate driver disclosed in an embodiment of the present invention. As shown in Figure 4:

Optionally, the pull-up control module 1 includes: a first transistor T11; a source 11 of the first transistor T11 is connected to a gate signal point Q(N); and a gate of the first transistor T11 is high. In the flat case, the drain of the first transistor T11 is controlled to input the received signal to the source 11 of the first transistor.

Optionally, the pull-up circuit includes a second transistor T21; the gate 21 of the second transistor T21 is connected to the gate signal point Q(N); and the drain 23 of the second transistor T21 is connected to the signal downlink module 3. The second port 32 is connected; the source 22 of the second transistor T11 is connected to the horizontal scanning line G(N); and when the gate 21 of the second transistor T21 is at the high level, the second transistor T21 is controlled. The drain 23 inputs the signal CK of the clock signal line to the source 22 of the second transistor T21.

Optionally, the signal downlink module 3 includes a third transistor T31; the gate 31 of the third transistor T31 is connected to the gate signal point Q(N); and the drain 32 and the pull-up module of the third transistor T31. The third port 23 of 2 is connected; in the case where the gate 31 of the third transistor T31 is at a high level, the drain 32 of the third transistor T31 is controlled to input the signal CK of the clock signal line to the third transistor T31. Source 33.

Optionally, the pull-down module 4 includes a fourth transistor T41 and a fourth transistor T42; the drain 42 of the fourth transistor is connected to the horizontal scan line G(N), and the drain 41 and the gate of the fourth transistor T42 are connected. The pole signal point Q(N) is connected; the source 43 of the fourth transistor and the source 43 of the fourth transistor are connected to the pull-down maintaining module 5; the gate of the fourth transistor and the gate of the fourth transistor are respectively used Receiving the first control signal G(N+1) and the second control signal G(N+2); controlling the source 43 of the fourth transistor T41 when the gate of the fourth transistor is at a high level The signal of the low level signal line VSS is input to the drain 42 of the fourth transistor T41; and when the gate of the fourth transistor receives the high level, the source 43 of the fourth transistor T42 is controlled to be low. The signal of the level signal line VSS is input to the drain 41 of the fourth transistor T42.

Optionally, the pull-down maintaining module 5 includes an inverter, a fifth transistor T51, and a fifth transistor T52; the input terminal 51 of the inverter is connected to the gate signal point Q(N), and the output end of the inverter Connected to the gate of the fifth transistor T51 and the gate of the fifth two transistor T52; the drain 52 of the fifth transistor T51 is connected to the horizontal scanning line G(N), and the source and the pull-down module of the fifth transistor T51 The third port 43 of the fourth port 43 is connected; the drain 51 of the fifth two transistor T52 is connected to the gate signal point Q(N), and the source 53 of the fifth two transistor T52 is connected to the third port 43 of the pull-down module 4; When the input end of the phase comparator is at a low level, the output terminal of the inverter outputs a high level to the gate of the fifth transistor T51, and the signal VSS of the low level signal line is controlled from the source of the fifth transistor T51. The pole 53 is transmitted to the drain 52 of the fifth transistor T51.

Further, as shown in FIG. 5, the inverter includes a fifth three transistor T53, a fifth four transistor T54, a fifth five transistor T55, and a fifth six transistor T56; the gate signal point Q(N) and the fifth five The gate of the transistor T55 and the gate of the fifth six transistor T56 are connected; the source of the fifth five transistor T55 and the source of the fifth six transistor T56 are connected to the third port 43 of the pull-down module 4; the fifth five transistor T55 The drain is connected to the source of the fifth three transistor T53 and the gate of the five-four transistor T54; the drain of the fifth six transistor T56 is connected to the source of the five-four transistor T54, the gate of the five-one transistor T51, and the five-two transistor. The gate of T52 is connected; the gate of the five-three transistor T53, the drain of the five-three transistor T53, and the drain of the five-four transistor T54 are connected. The drain input terminal LC of the fifth four-transistor of the pull-down maintenance module is a high-level signal of a direct current. XCK is the reverse signal of the clock signal CK.

Optionally, the bootstrap module 6 includes a first capacitor; one end of the first capacitor is connected to the gate signal point Q(N), and the other end is connected to the horizontal scan line G(N).

Specifically, the signal changes are shown in Figures 6 and 7. During the t1 period, the pull-up control signal ST(N-1) and the horizontal scan signal G(N-1) transmitted by the previous driver are at a high level, thus causing the gate of the first transistor T11 of the pull-up control module 1 The pole is at a high level, and the ST (N-1) signal is outputted to Q(N), thereby precharging Q(N) to a level V1 of the gate of the second transistor T21 capable of driving the pull-up module 2. Therefore, the second transistor T21 of the pull-up module 2 transmits the clock signal CK from the drain of the second transistor T21 to the source, that is, to the G(N) point on the horizontal scanning line, so that G(N) Low level; during the time period t2, the point potential in Q(N) continues to be raised to V2 due to capacitive coupling, so the second transistor T21 of the pull-up module 2 continues to transmit CK to G(N) , so that G(N) is high level; in the time period t3, the Q(N) point is pulled down to the high level V3 due to the end of the capacitive coupling action of the CK signal, so the second transistor T21 of the pull-up module 2 Continue to transfer CK to G(N), so that G(N) is low. At the same time, the second control signal G(N+1) is high, and the fourth transistor T41 of the pull-down module 4 is controlled. Low level letter VSS is transmitted to G(N). At this time, the signal for pulling down G(N) is CK and VSS; during the time period t4, the first control signal G(N+2) is high level, and the pull-down module 4 is controlled. The fourth transistor T42 transmits the level signal VSS to Q(N), so that the input port of the inverter is input to a low level, so that the inverter of the pull-down maintaining module 5 outputs a high level to the gate of the fifth transistor. The pole causes the fifth transistor to transfer the obtained VSS signal of the source from the drain of the fifth transistor to G(N), and the signal for pulling down G(N) is VSS.

In summary, the gate driver described in the embodiment of the present invention can lower the potential on the gate signal point Q(N) by using the low-level signal VSS and the clock signal CK, thereby improving the pull-down effect of the gate driver. Improve the stability of the circuit.

The embodiment of the present invention further provides a driving circuit including the gate driver described in the foregoing embodiments of the present invention, the signal downlink module 3 of the gate driver further includes a third port 33; and the pull-up control module 1 of the gate driver A second port 12 is also included; the third port of the signal downlink module 3 of the Nth stage gate driver is coupled to the second port of the pullup control module 1 of the (N+1)th stage gate driver.

Claims

A gate driver, comprising: a pull-up control module, a pull-down maintenance module, a pull-up module, a signal downlink module, a pull-down module, and a bootstrap module; the pull-up control module includes a first port; The maintenance module includes a first port, a second port, and a third port; the pull-up module includes a first port, a second port, and a third port; the signal downlink module includes a first port and a second port; The pull-down module includes a first port, a second port, a third port, a fourth port, and a fifth port; the bootstrap module includes a first port and a second port;

a first port of the pull-up control module, a first port of the pull-up module, a first port of the signal downlink module, a first port of the pull-down module, and a first port of the pull-down maintenance module Connected to the first port of the bootstrap module, the connection point is a gate signal point; the second port of the pull-down maintenance module, the second port of the pull-down module, the second port of the bootstrap module, and The second port of the pull-up module is respectively connected to the horizontal scan line; the third port of the pull-down maintenance module and the third port of the pull-down module are respectively connected to the low-level signal line; the third of the pull-up module The port and the second port of the signal downlink module are respectively connected to the clock signal line;

The pull-up control module is configured to precharge the gate signal point, and when the gate signal point is at a high level, control the pull-up module to output the signal of the clock signal line to the a horizontal scan line; in a case where the first control signal received by the fourth port of the pull-down module is at a high level, the pull-down module outputs a signal of the low-level signal line to the horizontal scan line In a case where the second control signal received by the fifth port of the pull-down module is a high level, the pull-down module outputs a signal of the low-level signal line to the gate signal point, and the control station a pull-down maintaining module outputs a signal of the low-level signal line to the horizontal scan line; the bootstrap module is configured to increase and maintain a level of the gate signal point; and the signal downlink module is used to When the gate signal point is at a high level, the signal of the clock signal line is transmitted to other electronic devices.
The gate driver of claim 1 wherein said first control signal is different from said second control signal.
The gate driver according to claim 1, wherein the pull-up control module comprises: a first transistor;

a source of the first transistor is connected to the gate signal point;

In a case where the gate of the first transistor is at a high level, the drain of the first transistor is controlled to input the received signal to the source of the first transistor.
The gate driver according to claim 1, wherein said pull-up circuit comprises a second transistor;

a gate of the second transistor is connected to the gate signal point; a drain of the second transistor is connected to a second port of the signal downlink module; and a source of the second transistor is The horizontal scan line is connected;

In a case where the gate of the second transistor is at a high level, controlling a drain of the second transistor to input a signal of the clock signal line to a source of the second transistor.
The gate driver according to claim 1, wherein the signal downlink module comprises a third transistor;

a gate of the third transistor is connected to the gate signal point; a drain of the third transistor is connected to a third port of the pull-up module;

In a case where the gate of the third transistor is at a high level, the drain of the third transistor is controlled to input a signal of the clock signal line to a source of the third transistor.
The gate driver according to claim 1, wherein the pull-down module comprises a fourth transistor and a fourth transistor;

a drain of the fourth transistor is connected to the horizontal scan line, a drain of the fourth transistor is connected to the gate signal point; a source of the fourth transistor is connected to the fourth a source of the transistor is connected to the pull-down maintaining module; a gate of the fourth transistor and a gate of the fourth transistor are respectively configured to receive the first control signal and the second control signal;

Controlling, by the source of the fourth transistor, a signal of the low-level signal line to a drain of the fourth transistor when the gate of the fourth transistor is at a high level; In a case where the gate of the fourth transistor is at a high level, the source of the fourth transistor is controlled to input a signal of the low-level signal line to a drain of the fourth transistor.
The gate driver according to claim 1, wherein the pull-down maintaining module comprises an inverter, a fifth transistor, and a fifth transistor;

An input end of the inverter is connected to the gate signal point, and an output end of the inverter is connected to a gate of the fifth transistor and a gate of the fifth two transistor; a drain of the fifth transistor is connected to the horizontal scan line, a source of the fifth transistor is connected to a third port of the pull-down module; a drain of the fifth transistor and the gate signal point Connecting, a source of the fifth diode is connected to a third port of the pull-down module;

In a case where the input end of the inverter is at a low level, an output end of the inverter outputs a high level to a gate of the fifth transistor, and controls a signal of the low-level signal line The source of the fifth transistor is transferred to the drain of the five-first transistor.
The gate driver according to claim 1, wherein the bootstrap module comprises a first capacitor;

One end of the first capacitor is connected to the gate signal point, and the other end is connected to the horizontal scan line.
The gate driver according to claim 7, wherein the inverter comprises a fifth three transistor, a fifth four transistor, a fifth five transistor, and a fifth six transistor;

The gate signal point is connected to a gate of the fifth five transistor and a gate of the fifth six transistor; a source of the fifth five transistor and a source of the fifth six transistor and the a third port of the pull-down module is connected; a drain of the fifth five transistor is connected to a source of the fifth three transistor and a gate of the five-four transistor; a drain of the fifth six transistor is a source of a five-four transistor, a gate connection of the five-one transistor, and a gate connection of the five-two transistor; a gate of the five-three transistor, a drain of the five-three transistor, and the five-four transistor The drain connection.
A driving circuit, characterized in that the driving circuit comprises a plurality of gate drivers according to any one of claims 1-9; the signal downlink module of the gate driver further comprises a third port; The pull-up control module of the gate driver further includes a second port;

A third port of the signal downlink module of the Nth stage gate driver is coupled to a second port of the pull up control module of the (N+1)th stage gate driver.