WO2019125362A1 - High mobility oxide thin film transistor - Google Patents

High mobility oxide thin film transistor Download PDF

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Publication number
WO2019125362A1
WO2019125362A1 PCT/US2017/066996 US2017066996W WO2019125362A1 WO 2019125362 A1 WO2019125362 A1 WO 2019125362A1 US 2017066996 W US2017066996 W US 2017066996W WO 2019125362 A1 WO2019125362 A1 WO 2019125362A1
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WIPO (PCT)
Prior art keywords
channel
channel layer
layer
gate
drain
Prior art date
Application number
PCT/US2017/066996
Other languages
French (fr)
Inventor
Ravi Pillarisetty
Abhishek A. Sharma
Gilbert Dewey
Van H. Le
Jack T. Kavalieros
Original Assignee
Intel Corporation
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Publication date
Application filed by Intel Corporation filed Critical Intel Corporation
Priority to PCT/US2017/066996 priority Critical patent/WO2019125362A1/en
Publication of WO2019125362A1 publication Critical patent/WO2019125362A1/en

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    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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Definitions

  • Embodiments of the invention are in the field of semiconductor devices and, in particular, thin film transistors.
  • a thin film transistor may include a field effect transistor implemented using thin film technology.
  • the thin films may include films of polycrystalline or amorphous silicon (or other thin film semiconductors) and a variety of insulating substrates. More specifically, a TFT may include a special kind of metal-oxide-semiconductor field effect transistor (MOSFET) made by depositing thin films of an active semiconductor layer as well as metallic contacts over a supporting (but relatively low-conducting or non-conducting) substrate.
  • MOSFET metal-oxide-semiconductor field effect transistor
  • TFTs differ from conventional MOSFETs because the semiconductor material (and channel) of conventional MOSFETs is typically the substrate, such as a silicon wafer (instead of a thin film as is the case with a TFT).
  • Figure 1 includes a conventional TFT.
  • Figure 2 includes a TFT in an embodiment.
  • Figure 3 depicts a cross-sectional view of the embodiment of Figure 2.
  • Figure 4 includes a TFT in an embodiment.
  • Figure 5 includes a TFT in an embodiment.
  • Figure 6 depicts a package in an embodiment.
  • Figures 7, 8, and 9 include systems that include embodiments. Detailed Description
  • Figure 1 includes a conventional TFT 100.
  • Substrate 101 includes an inter-layer dielectric (ILD) material.
  • a semiconductor material 103 comprising a channel is on the ILD layer.
  • Source, drain, and gate contacts 104, 105, 106 are on the channel layer 103.
  • the gate contact 106 is separated from the channel by gate oxide 108.
  • Additional ILD material 102, 107 is adjacent contacts 104, 105, 106.
  • channel layer 103 includes a single layer of material, such as indium gallium zinc oxide (IGZO), amorphous silicon, amorphous germanium, and the like. These materials have low carrier mobility and the non-phonon component of the carrier mobility is low.
  • IGZO indium gallium zinc oxide
  • Applicant determined moving from a single layer of material to a crystalline oxide heterostructure (having more than 1 layer in the channel layer) can result in high mobility that is non-phonon limited.
  • Applicant further determined these oxide heterostructures have high phonon scattering. High phonon scattering can result in TFTs that have lower on-current, lower intrinsic cut-off frequency, and overall degraded performance.
  • oxide heterostructures use non crystalline materials to limit phonon scattering.
  • Embodiments use, for example, amorphous, polysilicon, and/or sub-stoichiometric materials to limit phonon scattering.
  • Certain embodiments locate a portion of the channel material (e.g., one of the layers of a multilayer channel) in a fin structure to suppress phonon scattering and generally increase TFT density and scalability.
  • Figure 2 includes a frontend 231 and a backend 230.
  • Frontend processing refers to the initial steps in device fabrication. In this stage semiconductor devices (e.g., transistors) are created.
  • a typical front end (also referred to herein as“frontend”) process includes: preparation of the wafer surface (e.g., fin formation for a FinFET), patterning and subsequent implantation of dopants to obtain desired electrical properties, growth or deposition of a gate dielectric, and growth or deposition of insulating materials to isolate neighboring devices.
  • BEOL Back End Processing
  • M layers layers (see layers 210, 211 of Figure 2) used to form traces, bit lines, word lines, and the like)
  • insulating material sometimes referred to herein as V layers because such layers often include vias
  • the metal layers consist of aluminum, copper, and the like.
  • the insulating material may include Si0 2 , low-K materials, and the like.
  • a backend portion may include, for example, 12 metal layers: a bottom metal layer (MO), a top metal layer (Ml l), and a plurality of metal layers (Ml, M2, M3, M4, M5, M6, M7, M8, M9, and/or M10) between the bottom and top metal layers.
  • The“bottom metal layer” is so named because the backend portion includes no metal layer between the bottom metal layer and a top of the frontend portion.
  • The“top metal layer” is so named because the backend portion includes no metal layer between the top metal layer and the top of the backend portion. Having 12 metal layers is just an example and backend portions may include more (e.g., 14, 16, 18, 20 or more) or less (e.g., 4, 6, 8) metal layers.
  • system 200 includes a substrate 213.
  • System 200 further includes a first layer 210, including a metal (i.e., a metal layer or“M” layer), on the substrate and a second layer 211, including the metal (another M layer), on the first layer.
  • System 200 includes a switching device (e.g., a TFT) between the first and second layers, the switching device comprising a source region 204’, a channel region 206’, and a drain region 205’.
  • System 200 further includes a source contact 204 corresponding to the source region, a gate contact 206 corresponding to the channel region, and a drain contact 205 corresponding to the drain region.
  • Channel region 206’ includes a first channel layer 203 and a second channel layer 209.
  • the first channel layer 203 is between the gate contact 206 and the second channel layer 209.
  • the first channel layer 203 directly contacts the second channel layer 209.
  • the first channel layer 203 includes a first material having a first bandgap and the second channel layer 209 includes a second material having a second bandgap that is smaller than the first bandgap.
  • the first material of layer 203 includes magnesium, zinc, and oxygen and the second material of layer 209 includes zinc and oxygen.
  • the border or seam 212 may include traces of magnesium but any such amount would be incredibly low in comparison to layer 203.
  • materials in one or both layers may be amorphous, polycrystalline, and/or sub-stoichiometric.
  • An amorphous material is a non-crystalline solid with no or low periodicity and long-range order.
  • Polycrystalline materials have long-range order that exists only within limited areas. Grains are randomly connected to form a solid. The size of grains in x-y-z directions varies and there is no preferential extension of the single-crystal within the grain in any direction.
  • a sub stoichiometric material has less than the stoichiometric amount of a reagent.
  • a sub stoichiometric (i.e., nonstoichiometric) compound is any solid chemical compound in which the numbers of atoms of the elements present cannot be expressed as a ratio of small whole numbers.
  • a gate dielectric 208 directly contacts the first channel layer 203.
  • Other dielectric portions 201, 202, 207 are further included in system 200.
  • FIG. 3 shows a cross-sectional view of Figure 2.
  • the second channel layer 209 includes a horizontal width 209’ and a vertical height 209”. Height 209” is greater than the horizontal width 209’.
  • layer 209 is formed as a fin similar to fins included in FinFETs.
  • vertical plane 233 intersects the gate 206 and the first and second channel layers 203, 209.
  • Figure 3 shows an embodiment wherein the layer 209 forms a fin in other embodiments layer 209 is planar.
  • Figure 4 includes a gate-all-around embodiment.
  • a vertical plane intersects first opposing sidewalls 209’, 209” of the second channel layer 209, first opposing sidewalls 203’, 203” of the first channel layer 203, and first opposing sidewalls 206’, 206” of the gate 206; and a horizontal plane, orthogonal to the vertical plane, intersects second opposing sidewalls 209*, 209** of the second channel layer, second opposing sidewalls 203*, 203** of the first channel layer, and second opposing sidewalls 206*, 206** of the gate.
  • the channel region 206’ has first and second opposing channel surfaces 212’, 212”.
  • the first channel surface 212’ is between the second channel surface 212” and the source contact 204.
  • the first channel surface 212’ is between the second channel surface 212” and the gate contact 208.
  • the first channel surface 212’ is between the second channel surface 212” and the drain contact 205.
  • Figure 5 layer 203 is between the gate contact 206 and at least one of the source and drain contacts 204, 205.
  • Other elements of Figure 5 are directly analogous to elements in Figure 2 and are not described again herein for the sake of brevity.
  • Figure 5 illustrates contact arrangements with regard to the channel layer vary and embodiments are not constrained to any one arrangement of contacts with respect to the source, drain, and channel regions.
  • layer 203 includes magnesium, zinc, and oxygen and layer 209 includes zinc and oxygen.
  • the materials may be selected from the following list provided (at least in some embodiments but not necessarily in others) layer 203 has a higher bandgap than the material of layer 209.
  • the list includes: zinc oxide, indium oxide, gallium oxide, indium gallium oxide, amorphous silicon, amorphous germanium, amorphous silicon germanium, polysilicon, polygermanium, poly germanium doped with boron, poly germanium doped with aluminum, poly germanium doped with phosphorous, poly germanium doped with arsenic, amorphous III-V materials, poly III-V materials, tin oxide, cupric oxide (CuO), cuprous oxide (Cu 2 0), indium gallium zinc oxide (IGZO), IGZO with ratios 1 : 1 : 1 of each oxide, indium gallium zinc (IGZ), crystalline IGZO, amorphous IGZ, nanocrystalline IGZ, tungsten antimonide, indium antimonide, nickel oxide, cobalt oxide, indium tin oxide, tungsten disulphide, molybdenum disulphide, molybdenum selenide, black phosphorus, graphene, graphyne, boro
  • An embodiment comprises a memory cell and the TFT of Figure 2, 3, 4, or 5 serves as an access transistor corresponding to the memory cell.
  • the memory cell may include (or be included in) a magnetic tunnel junction (MTJ), spin torque transfer random access memory (STTRAM), random access memory (RAM), dynamic random access memories (DRAMs), static random access memory (SRAM), programmable metallization cell (PMC) memory cells (also sometimes referred to as conductive bridge random access memory (CBRAM)), and the like.
  • MTJ magnetic tunnel junction
  • STTRAM spin torque transfer random access memory
  • RAM random access memory
  • DRAMs dynamic random access memories
  • SRAM static random access memory
  • PMC programmable metallization cell
  • CBRAM conductive bridge random access memory
  • At least one of the first and second M layers includes a write line corresponding to the memory cell; and at least another of the first and second M layers (e.g., M layer 211) includes a bit line corresponding to the memory cell.
  • Other M layers that may include contacts for source and/or drain nodes are not necessarily depicted in a figure but are included in the M layers of the backend portion 230 above substrate 213.
  • Figure 6 includes a package system in an embodiment.
  • the system includes a processor die 801 (a first package) on a package substrate 803.
  • a memory die (a second package) 802 couples to the substrate 803 by way of interposer system 807.
  • Underfill material 805 exists between die 801 and substrate 803.
  • Substrate 803 may include controlled collapse chip connection (C4) interconnects 806.
  • C4 controlled collapse chip connection
  • die 801 may couple to a metal stiffener 804.
  • Die 801 (and/or die 802) may include a die stack (e.g., multiple dies which may have the same function or differing functions) that may be molded as one unit that functions as a single die. For example, one die of the stack may have a first logic function while another die of the stack has another logic function that differs from the first logic function.
  • Die 801 includes a device such as the device of Figure 2, 3, 4 or 5.
  • die 802 includes a device such as the device of Figure 2, 3, 4 or 5.
  • die 801 includes a device such as the device of Figure 2, 3, 4 or 5
  • die 802 includes a device such as the device of Figure 2, 3, 4 or 5.
  • element 804 is not a stiffener but instead is a heat spreader (or is both a stiffener and a heat spreader).
  • a heat spreader is a heat exchanger that moves heat between a heat source and a secondary heat exchanger whose surface area and geometry are more favorable than the source.
  • Such a spreader may be a plate made of copper, which has a high thermal conductivity. By definition, heat is "spread out" over this geometry, so that the secondary heat exchanger may be more fully utilized. This has the potential to increase the heat capacity of the total assembly.
  • system 900 may be a smartphone or other wireless communicator or any other Internet of Things (IoT) device.
  • a baseband processor 905 (which may be included in a package such as the package of Figure and/or may include devices such as the device of Figure 2, 3, 4 or 5) is configured to perform various signal processing with regard to communication signals to be transmitted from or received by the system.
  • baseband processor 905 is coupled to an application processor 910 (which may be included in a package such as the package of Figure 6 and/or may include devices such as the device of Figure 2, 3, 4 or 5), which may be a main CPU of the system to execute an OS and other system software, in addition to user applications such as many well-known social media and multimedia apps.
  • Application processor 910 may further be configured to perform a variety of other computing operations for the device.
  • application processor 910 can couple to a user interface/display 920 (e.g., touch screen display).
  • application processor 910 may couple to a memory system including a non-volatile memory, namely a flash memory 930 (which may be included in a package such as the package of Figure 6 and/or may include devices such as the device of Figure 2, 3, 4 or 5) and a system memory, namely a DRAM 935 (which may be included in a package such as the package of Figure 6 and/or may include devices such as the device of Figure 2, 3, 4 or 5).
  • flash memory 930 may include a secure portion 932 in which secrets and other sensitive information may be stored.
  • application processor 910 also couples to a capture device 945 such as one or more image capture devices that can record video and/or still images.
  • a universal integrated circuit card (UICC) 940 comprises a subscriber identity module, which in some embodiments includes a secure storage 942 to store secure user information.
  • System 900 may further include a security processor 950 (e.g., Trusted Platform Module (TPM)) (which may be included in a package such as the package of Figure 6 and/or may include devices such as the device of Figure 2, 3, 4 or 5) that may couple to application processor 910.
  • TPM Trusted Platform Module
  • a plurality of sensors 925 including one or more multi-axis accelerometers may couple to application processor 910 to enable input of a variety of sensed information such as motion and other environmental information.
  • one or more authentication devices 995 may be used to receive, for example, user biometric input for use in authentication operations.
  • a near field communication (NFC) contactless interface 960 is provided that communicates in a NFC near field via an NFC antenna 965. While separate antennae are shown, understand that in some implementations one antenna or a different set of antennae may be provided to enable various wireless functionalities.
  • NFC near field communication
  • a power management integrated circuit (PMIC) 915 (which may be included in a package such as the package of Figure 6 and/or may include devices such as the device of Figure 2, 3, 4 or 5) couples to application processor 910 to perform platform level power management. To this end, PMIC 915 may issue power management requests to application processor 910 to enter certain low power states as desired. Furthermore, based on platform constraints, PMIC 915 may also control the power level of other components of system 900.
  • PMIC power management integrated circuit
  • RF transceiver 970 may be used to receive and transmit wireless data and calls according to a given wireless communication protocol such as 3G or 4G wireless communication protocol such as in accordance with a code division multiple access (CDMA), global system for mobile communication (GSM), long term evolution (LTE) or other protocol.
  • CDMA code division multiple access
  • GSM global system for mobile communication
  • LTE long term evolution
  • a GPS sensor 980 may be present, with location information being provided to security processor 950 for use as described herein when context information is to be used in a pairing process.
  • Other wireless communications such as receipt or transmission of radio signals (e.g., AM/FM) and other signals may also be provided.
  • radio signals e.g., AM/FM
  • WLAN transceiver 975 local wireless communications, such as according to a BluetoothTM or IEEE 802.11 standard can also be realized.
  • Multiprocessor system 1000 is a point-to-point interconnect system such as a server system, and includes a first processor 1070 (which may be included in a package such as the package of Figure 6 and/or may include devices such as the device of Figure 2, 3, 4 or 5) and a second processor 1080 (which may be included in a package such as the package of Figure 6 and/or may include devices such as the device of Figure 2, 3, 4 or 5) coupled via a point-to-point interconnect 1050.
  • a first processor 1070 which may be included in a package such as the package of Figure 6 and/or may include devices such as the device of Figure 2, 3, 4 or 5
  • a second processor 1080 which may be included in a package such as the package of Figure 6 and/or may include devices such as the device of Figure 2, 3, 4 or 5 coupled via a point-to-point interconnect 1050.
  • processors 1070 and 1080 may be multicore processors such as SoCs, including first and second processor cores (i.e., processor cores l074a and l074b and processor cores l084a and l084b), although potentially many more cores may be present in the processors.
  • processors 1070 and 1080 each may include a secure engine 1075 and 1085 to perform security operations such as attestations, IoT network onboarding or so forth.
  • First processor 1070 further includes a memory controller hub (MCH) 1072 and point-to-point (P-P) interfaces 1076 and 1078.
  • second processor 1080 includes a MCH 1082 and P-P interfaces 1086 and 1088.
  • MCH’s 1072 and 1082 couple the processors to respective memories, namely a memory 1032 and a memory 1034, which may be portions of main memory (e.g., a DRAM) locally attached to the respective processors.
  • First processor 1070 and second processor 1080 may be coupled to a chipset 1090 (which may be included in a package such as the package of Figure 6 and/or may include devices such as the device of Figure 2, 3, 4 or 5) via P-P interconnects 1052 and 1054, respectively.
  • Chipset 1090 includes P-P interfaces 1094 and 1098.
  • chipset 1090 includes an interface 1092 to couple chipset 1090 with a high performance graphics engine 1038, by a P-P interconnect 1039.
  • chipset 1090 may be coupled to a first bus 1016 via an interface 1096.
  • Various input/output (I/O) devices 1014 may be coupled to first bus 1016, along with a bus bridge 1018 which couples first bus 1016 to a second bus 1020.
  • Various devices may be coupled to second bus 1020 including, for example, a keyboard/mouse 1022, communication devices 1026 and a data storage unit 1028 such as a non-volatile storage or other mass storage device.
  • data storage unit 1028 (which may be included in a package such as the package of Figure 6 and/or may include devices such as the device of Figure 2, 3, 4 or 5) may include code 1030, in one embodiment.
  • data storage unit 1028 also includes a trusted storage 1029 to store sensitive information to be protected.
  • an audio I/O 1024 may be coupled to second bus 1020.
  • Embodiments may be used in environments where IoT devices may include wearable devices or other small form factor Internet of Things (IoT) devices.
  • IoT Internet of Things
  • module 1300 (which may be included in a package such as the package of Figure 6 and/or may include devices such as the device of Figure 2, 3, 4 or 5) may be an Intel® CurieTM module that includes multiple components adapted within a single small module that can be implemented as all or part of a wearable device.
  • module 1300 includes a core 1310 (of course in other embodiments more than one core may be present).
  • core 1310 may be a relatively low complexity in-order core, such as based on an Intel Architecture® QuarkTM design.
  • core 1310 may implement a Trusted Execution Environment (TEE).
  • TEE Trusted Execution Environment
  • Core 1310 couples to various components including a sensor hub 1320, which may be configured to interact with a plurality of sensors 1380, such as one or more biometric, motion environmental or other sensors.
  • a power delivery circuit 1330 is present, along with a non-volatile storage 1340.
  • this circuit may include a rechargeable battery and a recharging circuit, which may in one embodiment receive charging power wirelessly.
  • One or more input/output (IO) interfaces 1350 may be present.
  • IO input/output
  • a wireless transceiver 1390 which may be a BluetoothTM low energy or other short-range wireless transceiver is present to enable wireless communications as described herein.
  • a wearable module can take many other forms. Wearable and/or IoT devices have, in comparison with a typical general purpose CPET or a GPET, a small form factor, low power requirements, limited instruction sets, relatively slow computation throughput, or any of the above.
  • Example 1 includes a system comprising: a substrate; a first layer, including a metal, on the substrate; a second layer, including the metal, on the first layer; a switching device between the first and second layers, the switching device comprising a source region, a channel region, and a drain region; a source contact corresponding to the source region, a gate contact corresponding to the channel region, and a drain contact corresponding to the drain region; wherein (a) the channel region includes a first channel layer and a second channel layer, (b) the first channel layer is between the gate contact and the second channel layer, and (c) the first channel layer directly contacts the second channel layer.
  • Example 1 includes a third channel layer.
  • the second channel may be between the first and second channel layers.
  • the first channel layer may include a bandgap greater than a bandgap of the second channel layer.
  • the third channel layer may include a bandgap greater than a bandgap of the second channel layer.
  • Example 2 includes the system of example 1 wherein the switching device is a thin film transistor (TFT).
  • TFT thin film transistor
  • Example 3 includes the system of example 2 wherein the first channel layer includes a first material having a first bandgap and the second channel layer includes a second material having a second bandgap that is smaller than the first bandgap.
  • Example 4 includes the system of example 3 wherein at least one of the first and second materials is amorphous.
  • Example 5 includes the system of example 3 wherein at least one of the first and second materials is polycrystalline.
  • Example 6 includes the system of example 3 wherein at least one of the first and second materials is sub-stoichiometric.
  • the first material can be any of amorphous, polycrystalline, and sub-stoichiometric and the second material can be any of amorphous, polycrystalline, and sub-stoichiometric.
  • At least one of the first and second materials is stoichiometric.
  • Example 7 includes the system of example 3 comprising a seam where the first channel layer directly contacts the second channel layer.
  • Example 8 includes the system of example 3 wherein the first channel layer is between the gate contact and at least one of the source and drain contacts.
  • Example 9 includes the system of example 3 wherein: the channel region has first and second opposing channel surfaces; the first channel surface is between the second channel surface and the source contact; the first channel surface is between the second channel surface and the gate contact; and the first channel surface is between the second channel surface and the drain contact.
  • Example 10 includes the system of example 2 wherein the first material includes magnesium, zinc, and oxygen.
  • Example 11 includes the system of example 10 wherein the second material includes zinc and oxygen.
  • Example 12 includes the system of example 3 wherein the second material includes zinc and oxygen.
  • Example 13 includes the system of example 3 comprising a gate dielectric that directly contacts the first channel layer.
  • Example 14 includes the system of example 3 comprising a long axis that intersects the source region, the channel region, and the drain region, wherein in a vertical plane orthogonal to the long axis the second channel layer includes a horizontal width and a vertical height that is greater than the horizontal width.
  • Example 15 includes the system of example 14 wherein the second channel layer comprises a fin.
  • Example 16 includes the system of example 3 wherein: the vertical plane intersects the gate and the first and second channel layers; a horizontal plane, orthogonal to the vertical plane, intersects opposing sidewalls of the first channel layer, opposing sidewalls of the second channel layer, and opposing sidewalls of the gate.
  • Example 17 includes the system of example 3 wherein: the vertical plane intersects first opposing sidewalls of the first channel layer, first opposing sidewalls of the second channel layer, and first opposing sidewalls of the gate; and a horizontal plane, orthogonal to the vertical plane, intersects second opposing sidewalls of the first channel layer, second opposing sidewalls of the second channel layer, and second opposing sidewalls of the gate.
  • Example 18 includes a memory cell, wherein the switching device is an access transistor corresponding to the memory cell.
  • Example 19 includes a system comprising: a memory; and a processor coupled to the memory, wherein at least one of the processor and the memory includes the switching device according to any one of examples 1 to 18.
  • Example 19 includes a package comprising: a package substrate; a first die on the package substrate; a second die on the package substrate; wherein the first die includes: a first layer including a metal; a second layer, including the metal, on the first layer; a thin film transistor (TFT) coupled to the first and second layers, the switching device comprising a source, a channel, and a drain; a source contact corresponding to the source, a gate contact corresponding to the channel, and a drain contact corresponding to the drain; wherein (a) the channel includes first and second channel layers, the first channel layer being between the gate contact and the second channel layer, and (b) the first channel layer directly contacts the second channel layer.
  • TFT thin film transistor
  • Example 20 includes the package according to any of example 19 comprising at least one of (a) a stiffener coupled to the first die, and (b) a heat spreader coupled to the first die.
  • Example 21 includes the package of example 19 wherein: the first channel layer includes a first material having a first bandgap and the second channel layer includes a second material having a second bandgap that is smaller than the first bandgap; at least one of the first and second materials is at least one of amorphous, polycrystalline, and sub- stoichiometric.
  • Example 22 includes the package of example 21 comprising a seam where the first channel layer directly contacts the second channel layer, the first and second channel layers being non-monolithic with each other.
  • Example 23 includes the package of example 22 wherein: the second channel layer comprises a fin; the vertical plane intersects the gate and the first and second channel layers; a horizontal plane, orthogonal to the vertical plane, intersects opposing sidewalls of the first channel layer, opposing sidewalls of the second channel layer, and opposing sidewalls of the gate.
  • Example 24 includes a system comprising: a first layer including a metal; a second layer, including the metal, on the first layer; a thin film transistor (TFT) comprising a source, a channel, and a drain; source, gate, and drain contacts respectively for the source, channel, and drain; wherein (a) the channel includes first and second channel layers, (b) the first channel layer is between the gate contact and the second channel layer, (c) the first channel layer directly contacts the second channel layer, and (d) the second channel layer includes a fin with a height and a width, the width being less than the height.
  • TFT thin film transistor
  • Example 25 includes the system of example 24 wherein the first channel layer includes magnesium, zinc, and oxygen and the second channel layer includes zinc and oxygen.
  • Example la includes a system comprising: a substrate; a first layer, including a metal, on the substrate; a second layer, including the metal, on the first layer; a switching device between the first and second layers, the switching device comprising a source region, a channel region, and a drain region; a source contact corresponding to the source region, a gate contact corresponding to the channel region, and a drain contact corresponding to the drain region; wherein (a) the channel region includes a first channel layer and a second channel layer, (b) the first channel layer is between the gate contact and the second channel layer, and (c) the first channel layer directly contacts the second channel layer.
  • Example 2a includes the system of claim la wherein the switching device is a thin film transistor (TFT).
  • TFT thin film transistor
  • Example 3a includes the system according to any of claims la-2a wherein: the first channel layer includes a first material having a first bandgap; the second channel layer includes a second material having a second bandgap; the second bandgap is smaller than the first bandgap.
  • Example 4a includes the system according to any of claims la-3a wherein at least one of the first and second materials is amorphous.
  • Example 5a includes the system according to any of claims la-4a wherein at least one of the first and second materials is polycrystalline.
  • Example 6a includes the system according to any of claims la-5a wherein at least one of the first and second materials is sub-stoichiometric.
  • Example 7a includes the system according to any of claims la-6a comprising a seam where the first channel layer directly contacts the second channel layer.
  • Example 8a includes the system according to any of claims la-7a wherein the first channel layer is between the gate contact and at least one of the source and drain contacts.
  • Example 9a includes the system according to any of claims la-7a wherein: the channel region has first and second opposing channel surfaces; the first channel surface is between the second channel surface and the source contact; the first channel surface is between the second channel surface and the gate contact; and the first channel surface is between the second channel surface and the drain contact.
  • Example lOa includes the system according to any of claims la-9a wherein the first material includes magnesium, zinc, and oxygen.
  • Example l la includes the system according to any of claims la-lOa wherein the second material includes zinc and oxygen.
  • Example l2a includes the system according to any of claims la-lOa wherein the second material includes zinc and oxygen.
  • Example l3a includes the system according to any of claims la-l2a comprising a gate dielectric that directly contacts the first channel layer.
  • Example l4a includes the system according to any of claims la-l3a comprising a long axis that intersects the source region, the channel region, and the drain region, wherein: in a vertical plane, which is orthogonal to the long axis, the second channel layer includes a horizontal width and a vertical height; the vertical height is greater than the horizontal width.
  • Example l5a includes the system according to any of claims la-l4a wherein the second channel layer comprises a fin.
  • Example l6a includes the system according to claim l4a wherein: the vertical plane intersects the gate and the first and second channel layers; a horizontal plane, orthogonal to the vertical plane, intersects: (a) opposing sidewalls of the first channel layer, (b) opposing sidewalls of the second channel layer, and (c) opposing sidewalls of the gate.
  • Example l7a includes the system according to claim l4a wherein: the vertical plane intersects first opposing sidewalls of the first channel layer, first opposing sidewalls of the second channel layer, and first opposing sidewalls of the gate; and a horizontal plane, orthogonal to the vertical plane, intersects second opposing sidewalls of the first channel layer, second opposing sidewalls of the second channel layer, and second opposing sidewalls of the gate.
  • Example l8a includes the system according to any of claims la-l7a comprising a memory cell, wherein the switching device is an access transistor corresponding to the memory cell.
  • Example 19 a includes a system comprising: a memory; and a processor coupled to the memory, wherein at least one of the processor and the memory includes the switching device according to any one of claims la to l8a.
  • Example 20a includes a package comprising: a package substrate; a first die on the package substrate; a second die on the package substrate; wherein the first die includes: a first layer including a metal; a second layer, including the metal, on the first layer; a thin film transistor (TFT) coupled to the first and second layers, the switching device comprising a source, a channel, and a drain; a source contact corresponding to the source, a gate contact corresponding to the channel, and a drain contact corresponding to the drain; wherein (a) the channel includes first and second channel layers, the first channel layer being between the gate contact and the second channel layer, and (b) the first channel layer directly contacts the second channel layer.
  • TFT thin film transistor
  • Example 2la includes the package according to claim 20a comprising at least one of (a) a stiffener coupled to the first die, and (b) a heat spreader coupled to the first die.
  • Example 22a includes the package according to any of claims 20a-2la wherein: the first channel layer includes a first material having a first bandgap; the second channel layer includes a second material having a second bandgap; the second bandgap is smaller than the first bandgap; at least one of the first and second materials is at least one of amorphous, polycrystalline, and sub-stoichiometric.
  • Example 23a includes the package according to any of claims 20a-22a comprising a seam where the first channel layer directly contacts the second channel layer, the first and second channel layers being non-monolithic with each other.
  • Example 24a includes the package according to any of claims 20a-23a wherein: the second channel layer comprises a fin; the vertical plane intersects the gate and the first and second channel layers; a horizontal plane, orthogonal to the vertical plane, intersects: (a) opposing sidewalls of the first channel layer, (b) opposing sidewalls of the second channel layer, and (c) opposing sidewalls of the gate.
  • Example 25a includes a system comprising: a first layer including a metal; a second layer, including the metal, on the first layer; a thin film transistor (TFT) comprising a source, a channel, and a drain; source, gate, and drain contacts respectively for the source, the channel, and the drain; wherein (a) the channel includes first and second channel layers, (b) the first channel layer is between the gate contact and the second channel layer, (c) the first channel layer directly contacts the second channel layer, and (d) the second channel layer includes a fin with a height and a width, the width being less than the height.
  • TFT thin film transistor
  • Example 26a includes the system of claim 25a wherein the first channel layer includes magnesium, zinc, and oxygen and the second channel layer includes zinc and oxygen.
  • terms designating relative vertical position refer to a situation where a device side (or active surface) of a substrate or integrated circuit is the "top” surface of that substrate; the substrate may actually be in any orientation so that a "top” side of a substrate may be lower than the “bottom” side in a standard terrestrial frame of reference and still fall within the meaning of the term “top.”
  • the term “on” as used herein does not indicate that a first layer “on” a second layer is directly on and in immediate contact with the second layer unless such is specifically stated; there may be a third layer or other structure between the first layer and the second layer on the first layer.
  • the embodiments of a device or article described herein can be manufactured, used, or shipped in a number of positions and orientations.

Abstract

An embodiment includes a system comprising: a first layer including a metal; a second layer, including the metal, on the first layer; a thin film transistor (TFT) comprising a source, a channel, and a drain; source, gate, and drain contacts respectively for the source, channel, and drain; wherein (a) the channel includes first and second channel layers, (b) the first channel layer is between the gate contact and the second channel layer, (c) the first channel layer directly contacts the second channel layer, and (d) the second channel layer includes a fin with a height and a width, the width being less than the height. Other embodiments are described herein.

Description

HIGH MOBILITY OXIDE THIN FILM TRANSISTOR
Technical Field
[0001] Embodiments of the invention are in the field of semiconductor devices and, in particular, thin film transistors.
Background
[0002] A thin film transistor (TFT) may include a field effect transistor implemented using thin film technology. The thin films may include films of polycrystalline or amorphous silicon (or other thin film semiconductors) and a variety of insulating substrates. More specifically, a TFT may include a special kind of metal-oxide-semiconductor field effect transistor (MOSFET) made by depositing thin films of an active semiconductor layer as well as metallic contacts over a supporting (but relatively low-conducting or non-conducting) substrate. TFTs differ from conventional MOSFETs because the semiconductor material (and channel) of conventional MOSFETs is typically the substrate, such as a silicon wafer (instead of a thin film as is the case with a TFT).
Brief Description of the Drawings
[0003] Features and advantages of embodiments of the present invention will become apparent from the appended claims, the following detailed description of one or more example embodiments, and the corresponding figures. Where considered appropriate, reference labels have been repeated among the figures to indicate corresponding or analogous elements.
[0004] Figure 1 includes a conventional TFT.
[0005] Figure 2 includes a TFT in an embodiment.
[0006] Figure 3 depicts a cross-sectional view of the embodiment of Figure 2.
[0007] Figure 4 includes a TFT in an embodiment.
[0008] Figure 5 includes a TFT in an embodiment.
[0009] Figure 6 depicts a package in an embodiment.
[0010] Figures 7, 8, and 9 include systems that include embodiments. Detailed Description
[0011] Reference will now be made to the drawings wherein like structures may be provided with like suffix reference designations. In order to show the structures of various embodiments more clearly, the drawings included herein are diagrammatic representations of semiconductor/circuit structures. Thus, the actual appearance of the fabricated integrated circuit structures, for example in a photomicrograph, may appear different while still incorporating the claimed structures of the illustrated embodiments. Figures herein may have elements with sidewalls orthogonal to a lower layer, whereas actual devices may have sloped walls that are non-orthogonal to a lower layer due to processing (e.g., etching, annealing, and the like). Moreover, the drawings may only show the structures useful to understand the illustrated embodiments. Additional structures known in the art may not have been included to maintain the clarity of the drawings. For example, not every layer (e.g., barrier layer, seed layer, etch stop layer) of a semiconductor device is necessarily shown.“An embodiment”, “various embodiments” and the like indicate embodiment(s) so described may include particular features, structures, or characteristics, but not every embodiment necessarily includes the particular features, structures, or characteristics. Some embodiments may have some, all, or none of the features described for other embodiments.“First”,“second”,“third” and the like describe a common object and indicate different instances of like objects are being referred to. Such adjectives do not imply objects so described must be in a given sequence, either temporally, spatially, in ranking, or in any other manner. “Connected” may indicate elements are in direct physical or electrical contact with each other and“coupled” may indicate elements co-operate or interact with each other, but they may or may not be in direct physical or electrical contact.
[0012] Figure 1 includes a conventional TFT 100. Substrate 101 includes an inter-layer dielectric (ILD) material. A semiconductor material 103 comprising a channel is on the ILD layer. Source, drain, and gate contacts 104, 105, 106 are on the channel layer 103. The gate contact 106 is separated from the channel by gate oxide 108. Additional ILD material 102, 107 is adjacent contacts 104, 105, 106.
[0013] Applicant determined the conventional TFT 100 has several shortcomings. For example, channel layer 103 includes a single layer of material, such as indium gallium zinc oxide (IGZO), amorphous silicon, amorphous germanium, and the like. These materials have low carrier mobility and the non-phonon component of the carrier mobility is low. Applicant determined moving from a single layer of material to a crystalline oxide heterostructure (having more than 1 layer in the channel layer) can result in high mobility that is non-phonon limited. Applicant further determined these oxide heterostructures have high phonon scattering. High phonon scattering can result in TFTs that have lower on-current, lower intrinsic cut-off frequency, and overall degraded performance.
[0014] However, embodiments described herein address these issues based at least in part on using, for example, oxide heterostructures. These oxide heterostructures use non crystalline materials to limit phonon scattering. Embodiments use, for example, amorphous, polysilicon, and/or sub-stoichiometric materials to limit phonon scattering. Certain embodiments locate a portion of the channel material (e.g., one of the layers of a multilayer channel) in a fin structure to suppress phonon scattering and generally increase TFT density and scalability.
[0015] Figure 2 includes a frontend 231 and a backend 230.
[0016] Regarding the“backend”, once semiconductor wafers are prepared, a large number of process steps are still necessary to produce desired semiconductor integrated circuits. In general the steps can be grouped into four areas: Frontend Processing, Backend Processing, Test, and Packaging. Frontend and backend processing are pertinent to embodiments and are therefore described below.
[0017] Frontend processing refers to the initial steps in device fabrication. In this stage semiconductor devices (e.g., transistors) are created. A typical front end (also referred to herein as“frontend”) process includes: preparation of the wafer surface (e.g., fin formation for a FinFET), patterning and subsequent implantation of dopants to obtain desired electrical properties, growth or deposition of a gate dielectric, and growth or deposition of insulating materials to isolate neighboring devices.
[0018] Once the semiconductor devices have been created they must be interconnected to form the desired electrical circuits. This "Back End Processing" (BEOL) of the back end (also referred to herein as“backend”) involves depositing various layers of metal (sometimes referred to herein as M layers (see layers 210, 211 of Figure 2) used to form traces, bit lines, word lines, and the like) and insulating material (sometimes referred to herein as V layers because such layers often include vias) in the desired pattern. Typically the metal layers consist of aluminum, copper, and the like. The insulating material may include Si02, low-K materials, and the like. The various metal layers are interconnected by etching holes, called "vias", in the insulating material and depositing metal (e.g., Tungsten) in them. Thus, a backend portion may include, for example, 12 metal layers: a bottom metal layer (MO), a top metal layer (Ml l), and a plurality of metal layers (Ml, M2, M3, M4, M5, M6, M7, M8, M9, and/or M10) between the bottom and top metal layers. The“bottom metal layer” is so named because the backend portion includes no metal layer between the bottom metal layer and a top of the frontend portion. The“top metal layer” is so named because the backend portion includes no metal layer between the top metal layer and the top of the backend portion. Having 12 metal layers is just an example and backend portions may include more (e.g., 14, 16, 18, 20 or more) or less (e.g., 4, 6, 8) metal layers.
[0019] Returning to Figure 2, system 200 includes a substrate 213. System 200 further includes a first layer 210, including a metal (i.e., a metal layer or“M” layer), on the substrate and a second layer 211, including the metal (another M layer), on the first layer. System 200 includes a switching device (e.g., a TFT) between the first and second layers, the switching device comprising a source region 204’, a channel region 206’, and a drain region 205’. System 200 further includes a source contact 204 corresponding to the source region, a gate contact 206 corresponding to the channel region, and a drain contact 205 corresponding to the drain region.
[0020] Channel region 206’ includes a first channel layer 203 and a second channel layer 209. The first channel layer 203 is between the gate contact 206 and the second channel layer 209. The first channel layer 203 directly contacts the second channel layer 209.
[0021] In an embodiment the first channel layer 203 includes a first material having a first bandgap and the second channel layer 209 includes a second material having a second bandgap that is smaller than the first bandgap.
[0022] For example, in an embodiment the first material of layer 203 includes magnesium, zinc, and oxygen and the second material of layer 209 includes zinc and oxygen. Of course there may be diffusion of elements at the border or seam 212 that forms where layer 203 directly contacts layer 209. Thus, in the embodiment immediately above layer 209 may include traces of magnesium but any such amount would be incredibly low in comparison to layer 203.
[0023] Regarding the elements of layers 203, 209, materials in one or both layers may be amorphous, polycrystalline, and/or sub-stoichiometric.
[0024] An amorphous material is a non-crystalline solid with no or low periodicity and long-range order.
[0025] Polycrystalline materials have long-range order that exists only within limited areas. Grains are randomly connected to form a solid. The size of grains in x-y-z directions varies and there is no preferential extension of the single-crystal within the grain in any direction.
[0026] A sub stoichiometric material has less than the stoichiometric amount of a reagent. A sub stoichiometric (i.e., nonstoichiometric) compound is any solid chemical compound in which the numbers of atoms of the elements present cannot be expressed as a ratio of small whole numbers.
[0027] In system 200 a gate dielectric 208 directly contacts the first channel layer 203. Other dielectric portions 201, 202, 207 are further included in system 200.
[0028] Long axis 232 intersects the source region 204’, the channel region 206’, and the drain region 205’. Figure 3 shows a cross-sectional view of Figure 2. In a vertical plane 233 (orthogonal to the long axis 232) the second channel layer 209 includes a horizontal width 209’ and a vertical height 209”. Height 209” is greater than the horizontal width 209’. For example, layer 209 is formed as a fin similar to fins included in FinFETs.
[0029] In an embodiment, vertical plane 233 intersects the gate 206 and the first and second channel layers 203, 209. A horizontal plane 232’, orthogonal to the vertical plane 233, intersects opposing sidewalls 203’, 203” of the first channel layer 203, opposing sidewalls 209’, 209” of the second channel layer 209, and opposing sidewalls 206’, 206” of the gate. This describes a tri-gate arrangement where the gate is on three sides of the channel.
[0030] While Figure 3 shows an embodiment wherein the layer 209 forms a fin in other embodiments layer 209 is planar. [0031] Figure 4 includes a gate-all-around embodiment. A vertical plane intersects first opposing sidewalls 209’, 209” of the second channel layer 209, first opposing sidewalls 203’, 203” of the first channel layer 203, and first opposing sidewalls 206’, 206” of the gate 206; and a horizontal plane, orthogonal to the vertical plane, intersects second opposing sidewalls 209*, 209** of the second channel layer, second opposing sidewalls 203*, 203** of the first channel layer, and second opposing sidewalls 206*, 206** of the gate.
[0032] Returning to Figure 2, the channel region 206’ has first and second opposing channel surfaces 212’, 212”. The first channel surface 212’ is between the second channel surface 212” and the source contact 204. The first channel surface 212’ is between the second channel surface 212” and the gate contact 208. The first channel surface 212’ is between the second channel surface 212” and the drain contact 205.
[0033] However, in Figure 5 layer 203 is between the gate contact 206 and at least one of the source and drain contacts 204, 205. Other elements of Figure 5 are directly analogous to elements in Figure 2 and are not described again herein for the sake of brevity. Figure 5 illustrates contact arrangements with regard to the channel layer vary and embodiments are not constrained to any one arrangement of contacts with respect to the source, drain, and channel regions.
[0034] Returning to Figure 2, above an embodiment provides layer 203 includes magnesium, zinc, and oxygen and layer 209 includes zinc and oxygen. However, in other embodiments the materials may be selected from the following list provided (at least in some embodiments but not necessarily in others) layer 203 has a higher bandgap than the material of layer 209. The list includes: zinc oxide, indium oxide, gallium oxide, indium gallium oxide, amorphous silicon, amorphous germanium, amorphous silicon germanium, polysilicon, polygermanium, poly germanium doped with boron, poly germanium doped with aluminum, poly germanium doped with phosphorous, poly germanium doped with arsenic, amorphous III-V materials, poly III-V materials, tin oxide, cupric oxide (CuO), cuprous oxide (Cu20), indium gallium zinc oxide (IGZO), IGZO with ratios 1 : 1 : 1 of each oxide, indium gallium zinc (IGZ), crystalline IGZO, amorphous IGZ, nanocrystalline IGZ, tungsten antimonide, indium antimonide, nickel oxide, cobalt oxide, indium tin oxide, tungsten disulphide, molybdenum disulphide, molybdenum selenide, black phosphorus, graphene, graphyne, borophene, germanene, silicene, Si2BN, stanene, phosphorene, molybdenite, poly- III-V (e.g., InAs, InGaAs, InP, amorphous InGaZnO (a-IGZO)), crystal (e.g., InGaZnO, (c- IGZO), GaZnON, ZnON), C-Axis Aligned Crystal (CAAC) (e.g., InGaZnO), and the like.
[0035] An embodiment comprises a memory cell and the TFT of Figure 2, 3, 4, or 5 serves as an access transistor corresponding to the memory cell. The memory cell may include (or be included in) a magnetic tunnel junction (MTJ), spin torque transfer random access memory (STTRAM), random access memory (RAM), dynamic random access memories (DRAMs), static random access memory (SRAM), programmable metallization cell (PMC) memory cells (also sometimes referred to as conductive bridge random access memory (CBRAM)), and the like.
[0036] In an embodiment at least one of the first and second M layers (e.g., M layer 210) includes a write line corresponding to the memory cell; and at least another of the first and second M layers (e.g., M layer 211) includes a bit line corresponding to the memory cell. Other M layers that may include contacts for source and/or drain nodes are not necessarily depicted in a figure but are included in the M layers of the backend portion 230 above substrate 213.
[0037] Figure 6 includes a package system in an embodiment. The system includes a processor die 801 (a first package) on a package substrate 803. A memory die (a second package) 802 couples to the substrate 803 by way of interposer system 807. Underfill material 805 exists between die 801 and substrate 803. Substrate 803 may include controlled collapse chip connection (C4) interconnects 806. Further, to prevent warping of die 801, die 801 may couple to a metal stiffener 804. Die 801 (and/or die 802) may include a die stack (e.g., multiple dies which may have the same function or differing functions) that may be molded as one unit that functions as a single die. For example, one die of the stack may have a first logic function while another die of the stack has another logic function that differs from the first logic function.
[0038] Die 801 includes a device such as the device of Figure 2, 3, 4 or 5. In another embodiment die 802 includes a device such as the device of Figure 2, 3, 4 or 5. In an embodiment die 801 includes a device such as the device of Figure 2, 3, 4 or 5 and die 802 includes a device such as the device of Figure 2, 3, 4 or 5. [0039] In an embodiment element 804 is not a stiffener but instead is a heat spreader (or is both a stiffener and a heat spreader). A heat spreader is a heat exchanger that moves heat between a heat source and a secondary heat exchanger whose surface area and geometry are more favorable than the source. Such a spreader may be a plate made of copper, which has a high thermal conductivity. By definition, heat is "spread out" over this geometry, so that the secondary heat exchanger may be more fully utilized. This has the potential to increase the heat capacity of the total assembly.
[0040] Referring now to Figure 7, shown is a block diagram of an example system with which embodiments can be used. As seen, system 900 may be a smartphone or other wireless communicator or any other Internet of Things (IoT) device. A baseband processor 905 (which may be included in a package such as the package of Figure and/or may include devices such as the device of Figure 2, 3, 4 or 5) is configured to perform various signal processing with regard to communication signals to be transmitted from or received by the system. In turn, baseband processor 905 is coupled to an application processor 910 (which may be included in a package such as the package of Figure 6 and/or may include devices such as the device of Figure 2, 3, 4 or 5), which may be a main CPU of the system to execute an OS and other system software, in addition to user applications such as many well-known social media and multimedia apps. Application processor 910 may further be configured to perform a variety of other computing operations for the device.
[0041] In turn, application processor 910 can couple to a user interface/display 920 (e.g., touch screen display). In addition, application processor 910 may couple to a memory system including a non-volatile memory, namely a flash memory 930 (which may be included in a package such as the package of Figure 6 and/or may include devices such as the device of Figure 2, 3, 4 or 5) and a system memory, namely a DRAM 935 (which may be included in a package such as the package of Figure 6 and/or may include devices such as the device of Figure 2, 3, 4 or 5). In some embodiments, flash memory 930 may include a secure portion 932 in which secrets and other sensitive information may be stored. As further seen, application processor 910 also couples to a capture device 945 such as one or more image capture devices that can record video and/or still images.
[0042] A universal integrated circuit card (UICC) 940 comprises a subscriber identity module, which in some embodiments includes a secure storage 942 to store secure user information. System 900 may further include a security processor 950 (e.g., Trusted Platform Module (TPM)) (which may be included in a package such as the package of Figure 6 and/or may include devices such as the device of Figure 2, 3, 4 or 5) that may couple to application processor 910. A plurality of sensors 925, including one or more multi-axis accelerometers may couple to application processor 910 to enable input of a variety of sensed information such as motion and other environmental information. In addition, one or more authentication devices 995 may be used to receive, for example, user biometric input for use in authentication operations.
[0043] As further illustrated, a near field communication (NFC) contactless interface 960 is provided that communicates in a NFC near field via an NFC antenna 965. While separate antennae are shown, understand that in some implementations one antenna or a different set of antennae may be provided to enable various wireless functionalities.
[0044] A power management integrated circuit (PMIC) 915 (which may be included in a package such as the package of Figure 6 and/or may include devices such as the device of Figure 2, 3, 4 or 5) couples to application processor 910 to perform platform level power management. To this end, PMIC 915 may issue power management requests to application processor 910 to enter certain low power states as desired. Furthermore, based on platform constraints, PMIC 915 may also control the power level of other components of system 900.
[0045] To enable communications to be transmitted and received such as in one or more IoT networks, various circuitry may be coupled between baseband processor 905 and an antenna 990. Specifically, a radio frequency (RF) transceiver 970 and a wireless local area network (WLAN) transceiver 975 may be present. In general, RF transceiver 970 may be used to receive and transmit wireless data and calls according to a given wireless communication protocol such as 3G or 4G wireless communication protocol such as in accordance with a code division multiple access (CDMA), global system for mobile communication (GSM), long term evolution (LTE) or other protocol. In addition a GPS sensor 980 may be present, with location information being provided to security processor 950 for use as described herein when context information is to be used in a pairing process. Other wireless communications such as receipt or transmission of radio signals (e.g., AM/FM) and other signals may also be provided. In addition, via WLAN transceiver 975, local wireless communications, such as according to a Bluetooth™ or IEEE 802.11 standard can also be realized.
[0046] Referring now to Figure 8, shown is a block diagram of a system in accordance with another embodiment of the present invention. Multiprocessor system 1000 is a point-to-point interconnect system such as a server system, and includes a first processor 1070 (which may be included in a package such as the package of Figure 6 and/or may include devices such as the device of Figure 2, 3, 4 or 5) and a second processor 1080 (which may be included in a package such as the package of Figure 6 and/or may include devices such as the device of Figure 2, 3, 4 or 5) coupled via a point-to-point interconnect 1050. Each of processors 1070 and 1080 may be multicore processors such as SoCs, including first and second processor cores (i.e., processor cores l074a and l074b and processor cores l084a and l084b), although potentially many more cores may be present in the processors. In addition, processors 1070 and 1080 each may include a secure engine 1075 and 1085 to perform security operations such as attestations, IoT network onboarding or so forth.
[0047] First processor 1070 further includes a memory controller hub (MCH) 1072 and point-to-point (P-P) interfaces 1076 and 1078. Similarly, second processor 1080 includes a MCH 1082 and P-P interfaces 1086 and 1088. MCH’s 1072 and 1082 couple the processors to respective memories, namely a memory 1032 and a memory 1034, which may be portions of main memory (e.g., a DRAM) locally attached to the respective processors. First processor 1070 and second processor 1080 may be coupled to a chipset 1090 (which may be included in a package such as the package of Figure 6 and/or may include devices such as the device of Figure 2, 3, 4 or 5) via P-P interconnects 1052 and 1054, respectively. Chipset 1090 includes P-P interfaces 1094 and 1098.
[0048] Furthermore, chipset 1090 includes an interface 1092 to couple chipset 1090 with a high performance graphics engine 1038, by a P-P interconnect 1039. In turn, chipset 1090 may be coupled to a first bus 1016 via an interface 1096. Various input/output (I/O) devices 1014 may be coupled to first bus 1016, along with a bus bridge 1018 which couples first bus 1016 to a second bus 1020. Various devices may be coupled to second bus 1020 including, for example, a keyboard/mouse 1022, communication devices 1026 and a data storage unit 1028 such as a non-volatile storage or other mass storage device. As seen, data storage unit 1028 (which may be included in a package such as the package of Figure 6 and/or may include devices such as the device of Figure 2, 3, 4 or 5) may include code 1030, in one embodiment. As further seen, data storage unit 1028 also includes a trusted storage 1029 to store sensitive information to be protected. Further, an audio I/O 1024 may be coupled to second bus 1020.
[0049] Embodiments may be used in environments where IoT devices may include wearable devices or other small form factor Internet of Things (IoT) devices. Referring now to Figure 9, shown is a block diagram of a wearable module 1300 in accordance with another embodiment. In one particular implementation, module 1300 (which may be included in a package such as the package of Figure 6 and/or may include devices such as the device of Figure 2, 3, 4 or 5) may be an Intel® Curie™ module that includes multiple components adapted within a single small module that can be implemented as all or part of a wearable device. As seen, module 1300 includes a core 1310 (of course in other embodiments more than one core may be present). Such core may be a relatively low complexity in-order core, such as based on an Intel Architecture® Quark™ design. In some embodiments, core 1310 may implement a Trusted Execution Environment (TEE). Core 1310 couples to various components including a sensor hub 1320, which may be configured to interact with a plurality of sensors 1380, such as one or more biometric, motion environmental or other sensors. A power delivery circuit 1330 is present, along with a non-volatile storage 1340. In an embodiment, this circuit may include a rechargeable battery and a recharging circuit, which may in one embodiment receive charging power wirelessly. One or more input/output (IO) interfaces 1350, such as one or more interfaces compatible with one or more of ETSB/SPI/I2C/GPIO protocols, may be present. In addition, a wireless transceiver 1390, which may be a Bluetooth™ low energy or other short-range wireless transceiver is present to enable wireless communications as described herein. ETnderstand that in different implementations a wearable module can take many other forms. Wearable and/or IoT devices have, in comparison with a typical general purpose CPET or a GPET, a small form factor, low power requirements, limited instruction sets, relatively slow computation throughput, or any of the above.
[0050] The following examples pertain to further embodiments.
[0051] Example 1 includes a system comprising: a substrate; a first layer, including a metal, on the substrate; a second layer, including the metal, on the first layer; a switching device between the first and second layers, the switching device comprising a source region, a channel region, and a drain region; a source contact corresponding to the source region, a gate contact corresponding to the channel region, and a drain contact corresponding to the drain region; wherein (a) the channel region includes a first channel layer and a second channel layer, (b) the first channel layer is between the gate contact and the second channel layer, and (c) the first channel layer directly contacts the second channel layer.
[0052] However, other versions of Example 1 include a third channel layer. For example, the second channel may be between the first and second channel layers. The first channel layer may include a bandgap greater than a bandgap of the second channel layer. The third channel layer may include a bandgap greater than a bandgap of the second channel layer.
[0053] Example 2 includes the system of example 1 wherein the switching device is a thin film transistor (TFT).
[0054] Example 3 includes the system of example 2 wherein the first channel layer includes a first material having a first bandgap and the second channel layer includes a second material having a second bandgap that is smaller than the first bandgap.
[0055] Example 4 includes the system of example 3 wherein at least one of the first and second materials is amorphous.
[0056] Example 5 includes the system of example 3 wherein at least one of the first and second materials is polycrystalline.
[0057] Example 6 includes the system of example 3 wherein at least one of the first and second materials is sub-stoichiometric.
[0058] Regarding examples 4-6, in various embodiments the first material can be any of amorphous, polycrystalline, and sub-stoichiometric and the second material can be any of amorphous, polycrystalline, and sub-stoichiometric.
[0059] In some embodiments at least one of the first and second materials is stoichiometric.
[0060] Example 7 includes the system of example 3 comprising a seam where the first channel layer directly contacts the second channel layer. [0061] Example 8 includes the system of example 3 wherein the first channel layer is between the gate contact and at least one of the source and drain contacts.
[0062] For instance, see Figure 5.
[0063] Example 9 includes the system of example 3 wherein: the channel region has first and second opposing channel surfaces; the first channel surface is between the second channel surface and the source contact; the first channel surface is between the second channel surface and the gate contact; and the first channel surface is between the second channel surface and the drain contact.
[0064] For instance, see Figure 2.
[0065] Example 10 includes the system of example 2 wherein the first material includes magnesium, zinc, and oxygen.
[0066] Example 11 includes the system of example 10 wherein the second material includes zinc and oxygen.
[0067] Example 12 includes the system of example 3 wherein the second material includes zinc and oxygen.
[0068] Example 13 includes the system of example 3 comprising a gate dielectric that directly contacts the first channel layer.
[0069] Example 14 includes the system of example 3 comprising a long axis that intersects the source region, the channel region, and the drain region, wherein in a vertical plane orthogonal to the long axis the second channel layer includes a horizontal width and a vertical height that is greater than the horizontal width.
[0070] Example 15 includes the system of example 14 wherein the second channel layer comprises a fin.
[0071] Example 16 includes the system of example 3 wherein: the vertical plane intersects the gate and the first and second channel layers; a horizontal plane, orthogonal to the vertical plane, intersects opposing sidewalls of the first channel layer, opposing sidewalls of the second channel layer, and opposing sidewalls of the gate. [0072] Example 17 includes the system of example 3 wherein: the vertical plane intersects first opposing sidewalls of the first channel layer, first opposing sidewalls of the second channel layer, and first opposing sidewalls of the gate; and a horizontal plane, orthogonal to the vertical plane, intersects second opposing sidewalls of the first channel layer, second opposing sidewalls of the second channel layer, and second opposing sidewalls of the gate.
[0073] Example 18 includes a memory cell, wherein the switching device is an access transistor corresponding to the memory cell.
[0074] Example 19 includes a system comprising: a memory; and a processor coupled to the memory, wherein at least one of the processor and the memory includes the switching device according to any one of examples 1 to 18.
[0075] Another version of Example 19 includes a package comprising: a package substrate; a first die on the package substrate; a second die on the package substrate; wherein the first die includes: a first layer including a metal; a second layer, including the metal, on the first layer; a thin film transistor (TFT) coupled to the first and second layers, the switching device comprising a source, a channel, and a drain; a source contact corresponding to the source, a gate contact corresponding to the channel, and a drain contact corresponding to the drain; wherein (a) the channel includes first and second channel layers, the first channel layer being between the gate contact and the second channel layer, and (b) the first channel layer directly contacts the second channel layer.
[0076] Example 20 includes the package according to any of example 19 comprising at least one of (a) a stiffener coupled to the first die, and (b) a heat spreader coupled to the first die.
[0077] Example 21 includes the package of example 19 wherein: the first channel layer includes a first material having a first bandgap and the second channel layer includes a second material having a second bandgap that is smaller than the first bandgap; at least one of the first and second materials is at least one of amorphous, polycrystalline, and sub- stoichiometric.
[0078] Example 22 includes the package of example 21 comprising a seam where the first channel layer directly contacts the second channel layer, the first and second channel layers being non-monolithic with each other. [0079] Example 23 includes the package of example 22 wherein: the second channel layer comprises a fin; the vertical plane intersects the gate and the first and second channel layers; a horizontal plane, orthogonal to the vertical plane, intersects opposing sidewalls of the first channel layer, opposing sidewalls of the second channel layer, and opposing sidewalls of the gate.
[0080] Example 24 includes a system comprising: a first layer including a metal; a second layer, including the metal, on the first layer; a thin film transistor (TFT) comprising a source, a channel, and a drain; source, gate, and drain contacts respectively for the source, channel, and drain; wherein (a) the channel includes first and second channel layers, (b) the first channel layer is between the gate contact and the second channel layer, (c) the first channel layer directly contacts the second channel layer, and (d) the second channel layer includes a fin with a height and a width, the width being less than the height.
[0081] Example 25 includes the system of example 24 wherein the first channel layer includes magnesium, zinc, and oxygen and the second channel layer includes zinc and oxygen.
[0082] Example la includes a system comprising: a substrate; a first layer, including a metal, on the substrate; a second layer, including the metal, on the first layer; a switching device between the first and second layers, the switching device comprising a source region, a channel region, and a drain region; a source contact corresponding to the source region, a gate contact corresponding to the channel region, and a drain contact corresponding to the drain region; wherein (a) the channel region includes a first channel layer and a second channel layer, (b) the first channel layer is between the gate contact and the second channel layer, and (c) the first channel layer directly contacts the second channel layer.
[0083] Example 2a includes the system of claim la wherein the switching device is a thin film transistor (TFT).
[0084] Example 3a includes the system according to any of claims la-2a wherein: the first channel layer includes a first material having a first bandgap; the second channel layer includes a second material having a second bandgap; the second bandgap is smaller than the first bandgap. [0085] Example 4a includes the system according to any of claims la-3a wherein at least one of the first and second materials is amorphous.
[0086] Example 5a includes the system according to any of claims la-4a wherein at least one of the first and second materials is polycrystalline.
[0087] Example 6a includes the system according to any of claims la-5a wherein at least one of the first and second materials is sub-stoichiometric.
[0088] Example 7a includes the system according to any of claims la-6a comprising a seam where the first channel layer directly contacts the second channel layer.
[0089] Example 8a includes the system according to any of claims la-7a wherein the first channel layer is between the gate contact and at least one of the source and drain contacts.
[0090] Example 9a includes the system according to any of claims la-7a wherein: the channel region has first and second opposing channel surfaces; the first channel surface is between the second channel surface and the source contact; the first channel surface is between the second channel surface and the gate contact; and the first channel surface is between the second channel surface and the drain contact.
[0091] Example lOa includes the system according to any of claims la-9a wherein the first material includes magnesium, zinc, and oxygen.
[0092] Example l la includes the system according to any of claims la-lOa wherein the second material includes zinc and oxygen.
[0093] Example l2a includes the system according to any of claims la-lOa wherein the second material includes zinc and oxygen.
[0094] Example l3a includes the system according to any of claims la-l2a comprising a gate dielectric that directly contacts the first channel layer.
[0095] Example l4a includes the system according to any of claims la-l3a comprising a long axis that intersects the source region, the channel region, and the drain region, wherein: in a vertical plane, which is orthogonal to the long axis, the second channel layer includes a horizontal width and a vertical height; the vertical height is greater than the horizontal width. [0096] Example l5a includes the system according to any of claims la-l4a wherein the second channel layer comprises a fin.
[0097] Example l6a includes the system according to claim l4a wherein: the vertical plane intersects the gate and the first and second channel layers; a horizontal plane, orthogonal to the vertical plane, intersects: (a) opposing sidewalls of the first channel layer, (b) opposing sidewalls of the second channel layer, and (c) opposing sidewalls of the gate.
[0098] Example l7a includes the system according to claim l4a wherein: the vertical plane intersects first opposing sidewalls of the first channel layer, first opposing sidewalls of the second channel layer, and first opposing sidewalls of the gate; and a horizontal plane, orthogonal to the vertical plane, intersects second opposing sidewalls of the first channel layer, second opposing sidewalls of the second channel layer, and second opposing sidewalls of the gate.
[0099] Example l8a includes the system according to any of claims la-l7a comprising a memory cell, wherein the switching device is an access transistor corresponding to the memory cell.
[0100] Example 19 a includes a system comprising: a memory; and a processor coupled to the memory, wherein at least one of the processor and the memory includes the switching device according to any one of claims la to l8a.
[0101] Example 20a includes a package comprising: a package substrate; a first die on the package substrate; a second die on the package substrate; wherein the first die includes: a first layer including a metal; a second layer, including the metal, on the first layer; a thin film transistor (TFT) coupled to the first and second layers, the switching device comprising a source, a channel, and a drain; a source contact corresponding to the source, a gate contact corresponding to the channel, and a drain contact corresponding to the drain; wherein (a) the channel includes first and second channel layers, the first channel layer being between the gate contact and the second channel layer, and (b) the first channel layer directly contacts the second channel layer.
[0102] Example 2la includes the package according to claim 20a comprising at least one of (a) a stiffener coupled to the first die, and (b) a heat spreader coupled to the first die. [0103] Example 22a includes the package according to any of claims 20a-2la wherein: the first channel layer includes a first material having a first bandgap; the second channel layer includes a second material having a second bandgap; the second bandgap is smaller than the first bandgap; at least one of the first and second materials is at least one of amorphous, polycrystalline, and sub-stoichiometric.
[0104] Example 23a includes the package according to any of claims 20a-22a comprising a seam where the first channel layer directly contacts the second channel layer, the first and second channel layers being non-monolithic with each other.
[0105] Example 24a includes the package according to any of claims 20a-23a wherein: the second channel layer comprises a fin; the vertical plane intersects the gate and the first and second channel layers; a horizontal plane, orthogonal to the vertical plane, intersects: (a) opposing sidewalls of the first channel layer, (b) opposing sidewalls of the second channel layer, and (c) opposing sidewalls of the gate.
[0106] Example 25a includes a system comprising: a first layer including a metal; a second layer, including the metal, on the first layer; a thin film transistor (TFT) comprising a source, a channel, and a drain; source, gate, and drain contacts respectively for the source, the channel, and the drain; wherein (a) the channel includes first and second channel layers, (b) the first channel layer is between the gate contact and the second channel layer, (c) the first channel layer directly contacts the second channel layer, and (d) the second channel layer includes a fin with a height and a width, the width being less than the height.
[0107] Example 26a includes the system of claim 25a wherein the first channel layer includes magnesium, zinc, and oxygen and the second channel layer includes zinc and oxygen.
[0108] The foregoing description of the embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. This description and the claims following include terms, such as left, right, top, bottom, over, under, upper, lower, first, second, etc. that are used for descriptive purposes only and are not to be construed as limiting. For example, terms designating relative vertical position refer to a situation where a device side (or active surface) of a substrate or integrated circuit is the "top" surface of that substrate; the substrate may actually be in any orientation so that a "top" side of a substrate may be lower than the "bottom" side in a standard terrestrial frame of reference and still fall within the meaning of the term "top." The term "on" as used herein (including in the claims) does not indicate that a first layer "on" a second layer is directly on and in immediate contact with the second layer unless such is specifically stated; there may be a third layer or other structure between the first layer and the second layer on the first layer. The embodiments of a device or article described herein can be manufactured, used, or shipped in a number of positions and orientations. Persons skilled in the relevant art can appreciate that many modifications and variations are possible in light of the above teaching. Persons skilled in the art will recognize various equivalent combinations and substitutions for various components shown in the Figures. It is therefore intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.

Claims

What is claimed is:
1. A system comprising:
a substrate;
a first layer, including a metal, on the substrate;
a second layer, including the metal, on the first layer;
a switching device between the first and second layers, the switching device comprising a source region, a channel region, and a drain region;
a source contact corresponding to the source region, a gate contact corresponding to the channel region, and a drain contact corresponding to the drain region;
wherein (a) the channel region includes a first channel layer and a second channel layer, (b) the first channel layer is between the gate contact and the second channel layer, and (c) the first channel layer directly contacts the second channel layer.
2. The system of claim 1 wherein the switching device is a thin film transistor (TFT).
3. The system according to any of claims 1-2 wherein:
the first channel layer includes a first material having a first bandgap;
the second channel layer includes a second material having a second bandgap;
the second bandgap is smaller than the first bandgap.
4. The system according to any of claims 1-3 wherein at least one of the first and second materials is amorphous.
5. The system according to any of claims 1-4 wherein at least one of the first and second materials is polycrystalline.
6. The system according to any of claims 1-5 wherein at least one of the first and second materials is sub-stoichiometric.
7. The system according to any of claims 1-6 comprising a seam where the first channel layer directly contacts the second channel layer.
8. The system according to any of claims 1-7 wherein the first channel layer is between the gate contact and at least one of the source and drain contacts.
9. The system according to any of claims 1-7 wherein:
the channel region has first and second opposing channel surfaces;
the first channel surface is between the second channel surface and the source contact; the first channel surface is between the second channel surface and the gate contact; and
the first channel surface is between the second channel surface and the drain contact.
10. The system according to any of claims 1-9 wherein the first material includes magnesium, zinc, and oxygen.
11. The system according to any of claims 1-10 wherein the second material includes zinc and oxygen.
12. The system according to any of claims 1-10 wherein the second material includes zinc and oxygen.
13. The system according to any of claims 1-12 comprising a gate dielectric that directly contacts the first channel layer.
14. The system according to any of claims 1-13 comprising a long axis that intersects the source region, the channel region, and the drain region, wherein:
in a vertical plane, which is orthogonal to the long axis, the second channel layer includes a horizontal width and a vertical height;
the vertical height is greater than the horizontal width.
15. The system according to any of claims 1-14 wherein the second channel layer comprises a fin.
16. The system according to claim 14 wherein:
the vertical plane intersects the gate and the first and second channel layers;
a horizontal plane, orthogonal to the vertical plane, intersects: (a) opposing sidewalls of the first channel layer, (b) opposing sidewalls of the second channel layer, and (c) opposing sidewalls of the gate.
17. The system according to claim 14 wherein:
the vertical plane intersects first opposing sidewalls of the first channel layer, first opposing sidewalls of the second channel layer, and first opposing sidewalls of the gate; and a horizontal plane, orthogonal to the vertical plane, intersects second opposing sidewalls of the first channel layer, second opposing sidewalls of the second channel layer, and second opposing sidewalls of the gate.
18. The system according to any of claims 1-17 comprising a memory cell, wherein the switching device is an access transistor corresponding to the memory cell.
19. A system comprising:
a memory; and
a processor coupled to the memory,
wherein at least one of the processor and the memory includes the switching device according to any one of claims 1 to 18.
20. A package comprising:
a package substrate;
a first die on the package substrate;
a second die on the package substrate;
wherein the first die includes:
a first layer including a metal;
a second layer, including the metal, on the first layer;
a thin film transistor (TFT) coupled to the first and second layers, the switching device comprising a source, a channel, and a drain; a source contact corresponding to the source, a gate contact corresponding to the channel, and a drain contact corresponding to the drain;
wherein (a) the channel includes first and second channel layers, the first channel layer being between the gate contact and the second channel layer, and (b) the first channel layer directly contacts the second channel layer.
21. The package according to claim 20 comprising at least one of (a) a stiffener coupled to the first die, and (b) a heat spreader coupled to the first die.
22. The package according to any of claims 20-21 wherein:
the first channel layer includes a first material having a first bandgap;
the second channel layer includes a second material having a second bandgap;
the second bandgap is smaller than the first bandgap;
at least one of the first and second materials is at least one of amorphous,
polycrystalline, and sub-stoichiometric.
23. The package according to any of claims 20-22 comprising a seam where the first channel layer directly contacts the second channel layer, the first and second channel layers being non-monolithic with each other.
24. The package according to any of claims 20-23 wherein:
the second channel layer comprises a fin;
the vertical plane intersects the gate and the first and second channel layers;
a horizontal plane, orthogonal to the vertical plane, intersects: (a) opposing sidewalls of the first channel layer, (b) opposing sidewalls of the second channel layer, and (c) opposing sidewalls of the gate.
25. A system comprising:
a first layer including a metal;
a second layer, including the metal, on the first layer;
a thin film transistor (TFT) comprising a source, a channel, and a drain;
source, gate, and drain contacts respectively for the source, the channel, and the drain; wherein (a) the channel includes first and second channel layers, (b) the first channel layer is between the gate contact and the second channel layer, (c) the first channel layer directly contacts the second channel layer, and (d) the second channel layer includes a fin with a height and a width, the width being less than the height.
26. The system of claim 25 wherein the first channel layer includes magnesium, zinc, and oxygen and the second channel layer includes zinc and oxygen.
PCT/US2017/066996 2017-12-18 2017-12-18 High mobility oxide thin film transistor WO2019125362A1 (en)

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US20120012840A1 (en) * 2009-03-31 2012-01-19 Vincent Korthuis Thin-film Transistor (TFT) With A Bi-layer Channel
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US20070287237A1 (en) * 2006-06-12 2007-12-13 Kovio, Inc. Printed, self-aligned, top gate thin film transistor
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