WO2019120595A1

WO2019120595A1 - Fractal phase voltage converter and method for controlling a voltage converter

Info

Publication number: WO2019120595A1
Application number: PCT/EP2017/084576
Authority: WO
Inventors: Roger Alm
Original assignee: Alm Electronic Ug (Haftungsbeschränkt)
Priority date: 2017-12-24
Filing date: 2017-12-24
Publication date: 2019-06-27

Abstract

The present invention provides a Voltage converter (100, 200, 300, 400, 500) for converting an input voltage (151) from a power source (150) with a first voltage level into an output voltage (152) for an electric load (153) with a second voltage level, the voltage converter (100, 200, 300, 400, 500) comprising an input port (101) configured to couple the voltage converter (100, 200, 300, 400, 500) to the power source (150) and receive the input voltage (151), an output port (102) configured to couple the voltage converter (100, 200, 300, 400, 500) to the electric load (153) and provide an output voltage (152) to the electric load (153), a number of voltage conversion units (103, 330, 331, 333, 403, 503) arranged in parallel between the input port (101) and the output port (102), each voltage conversion unit (103, 330, 331, 333, 403, 503) comprising a number of switching elements (104, 105, 304, 305, 404, 405), and a control unit (107, 307) that is coupled to the voltage conversion units (103, 330, 331, 333, 403, 503) and that is configured to consecutively switch the voltage conversion units (103, 330, 331, 333, 403, 503) in a charging mode or a discharging mode, wherein only one of the voltage conversion units (103, 330, 331, 333, 403, 503) is in the actively initiated charging mode or the actively initiated discharging mode, respectively, at any point in time, and to adapt the switching frequency for consecutively switching the voltage conversion units (103, 330, 331, 333, 403, 503) in the charging mode based on a power demand (108) of the electric load (153). Further, the present invention discloses a respective method.

Description

FRACTAL PHASE VOLTAGE CONVERTER AND METHOD FOR CONTROLLING A VOLTAGE CONVERTER

Technical Field

The present invention relates to a fractal phase voltage converter. The present invention further relates to a method for controlling a voltage converter.

Background

Although applicable in principal to any voltage conversion system that uses switched capacitors and inductors, like e.g. DC/DC converters, the present invention and its underlying problem will be hereinafter described in combination with DC/DC converters in automotive applications.

In modern automotive applications, the number of electronic systems constantly increases. Such applications may comprise multimedia applications, communication applications, driver assistance systems and the like. Especially with the introduction of autonomous driving and electric drive technology the power demand of the electronic systems raises.

With conventional 12 V based vehicle power supply networks high currents have to be transported over the power supply network to satisfy the respective power demands. This leads to large cross sections of the cables and heavy duty connectors in the power supply network, both increasing the space requirements in the vehicle and the overall weight of the vehicle. It is therefore increasingly difficult to satisfy the power requirements of the electronic systems in a vehicle.

In order to reduce the required sizes of the cables and the connectors in the power supply networks of vehicles, higher voltage network sections have been introduced into the power supply networks of vehicles. A possible voltage for example is 48 V. By increasing the voltage by the factor of 4, the current that has to be transported is reduced by the same factor and the dimensions of the cables and connectors may be reduced.

However, in order to supply common 12 V systems via such a 48 V network section, voltage converters, e.g. DC/DC converters are required.

However, known DC/DC converters with one or more phases suffer from large input ripple and output ripple depending on the operating point in which the DC/DC converter is operated.

Against this background, the problem addressed by the present invention is providing an improved control scheme for voltage converters.

Summary

The present invention solves this object by a voltage converter with the features of claim 1 and by a method, especially an event driven method, for operating a voltage converter with the features of claim 10.

Accordingly it is provided:

- A voltage converter for converting an input voltage from a power source with a first voltage level into an output voltage for an electric load with a second voltage level, the voltage converter comprising an input port configured to couple the voltage converter to the power source and receive the input voltage, an output port configured to couple the voltage converter to the electric load and provide an output voltage to the electric load, a number of, i.e. at least two, and especially at least three, voltage conversion units arranged in parallel between the input port and the output port, each voltage conversion unit comprising a number, i.e. one or more, of switching elements, and e.g. one or more energy storage elements, like inductors or capacitors, and a control unit that is coupled to the voltage conversion units and that is configured to consecutively switch the voltage conversion units into a charging mode or a discharging mode, wherein only one of the voltage conversion units is in the actively initiated charging mode or the actively initiated discharging mode, respectively, at any point in time, and to adapt the switching frequency or timing for consecutively switching the voltage conversion units into the charging mode or the discharging mode, respectively, also referred to as active mode or active period and the passive mode or inactive mode, based on a power demand of the electric load.

Further, it is provided:

- A method for operating a voltage converter for converting an input voltage from a power source with a first voltage level into an output voltage for an electric load with a second voltage level, the voltage converter comprising a number of voltage conversion units arranged in parallel between an input port and an output port, each voltage conversion unit comprising a number of switching elements and components for temporary storage of energy, like capacitors and inductors, the method comprising measuring a power demand of the electric load, determining the switching frequency or timing for consecutively switching the voltage conversion units in a charging mode or a discharging mode based on the measured power demand, and switching the voltage conversion units in the charging mode or the discharging mode, respectively according to the determined switching frequency or timing, wherein only one of the voltage conversion units is in the actively initiated charging mode or the actively initiated discharging mode, respectively, at any point in time.

The present invention is based on the finding that providing a flexible and floating or dynamic switching frequency that is a fractal of the normally applied phase scheme, for each single voltage conversion unit of the voltage converter will allow operating the voltage converter in an almost ideal operating point regarding ripple under any load situation.

The present invention therefore provides the voltage converter with at least two, especially at least three, voltage conversion units. According to the present invention, each voltage conversion unit will find its individual optimal phase based on the power demand of the electric load. The invention allows this optimal phase to be a fractal of the normal 2, 3, 4 and so on, phases that is normal for a clocked voltage converter. The voltage converter according to the present invention may therefore also be called a fractal voltage converter or a fractal phase voltage converter. Each of the voltage conversion units comprises at least one switching element and may further comprise one or more inductors, capacitors or the like. The voltage conversion units may e.g. comprise a high side switching element and a low side switching element, such as e.g. N-Channel or P-Channel MOSFETs or any other type of transistor or the like. The voltage conversion units may each for example comprise a buck type, a boost type or a book-boost type conversion arrangement. Just as an example, a buck type conversion arrangement may e.g. comprise an input capacitor, a switching element in the positive voltage rail, e.g. a high-side switching element, a diode in blocking direction after the switching element between the positive voltage rail and the negative voltage rail and an inductor in the positive voltage rail following the diode. It is understood, that other elements, like capacitors and additional inductors or the like may be provided. It is understood, that in addition a second switching element may be provided instead of the diode, e.g. a low side switching element.

The control unit of the voltage converter controls the switching elements of the voltage conversion units in order to generate the required output voltage and current for the electric load. It is understood, that the term electric load may refer to any consumer of the output voltage that is generated by the voltage converter, like e.g. single electronic systems, power supply network sections of a power supply network, or the like.

The control unit will however not control the single switching elements of the voltage conversion units sequentially with a fixed frequency or timing, i.e. the control unit will not switch the active voltage conversion unit with a fixed but with a variable frequency or timing. In this context, the term switching frequency does not directly refer to the duration of switching on of a single one of the switching elements, but to the frequency with which the control of the switching elements jumps from the switching elements of one voltage conversion unit to the switching elements of the next voltage conversion unit. It may therefore also be said, that in the present invention the timing, switching timing or the switch over timing for switching from one voltage conversion unit to the next voltage conversion unit is controlled. The term switching frequency may therefore also be replaced with timing or switching timing, which is the inverse of the frequency. As already indicated above, only one of the voltage conversion units may be actively controlled at any point in time to be in the charging mode or in the discharging mode, respectively. It is understood, that either the charging mode is actively controlled or the discharging mode is actively controlled for a given mode of operation of the voltage converter. In this regard, a switching cycle of a voltage conversion unit refers to a set of an active period, i.e. the charging mode, and an inactive or off period, i.e. the discharging mode, wherein charging the energy storage element of the respective voltage conversion unit is performed during the active period and the discharging in the off period. The exclusivity of either the charging mode or the discharging mode means that the end of either the charging mode or the discharging mode of one voltage conversion unit may represent a trigger or event that marks the start of the charging mode or the discharging mode, respectively, for the next voltage conversion unit. The control scheme according to the present invention may therefore also be called an event-triggered control scheme.

This means that the switching frequency or timing is dynamically adapted by the control unit, e.g. according to the above mentioned event-driven scheme, according to the power demand of the electric load. The output voltage of the voltage converter may be fixed within predefined limits, e.g. as a proportion or relation between the input voltage and the output voltage. The power demand of the electric load may be determined by the current that is drawn by the electric load from the voltage converter. It is however understood, that the output voltage and voltage limits as well as current limits may be configurable in the control unit. Accordingly, the control unit may use a current sensor connected to each voltage conversion unit or may comprise a voltage sensor that measures a voltage over a resistance that is proportional to the respective current. The resistance can e.g. comprise a dedicated resistor, the inner resistance of an inductor or the resistance over a transistor that is placed in the main current flow of a voltage conversion unit.

In the following, the working principle of the present invention will be described based on an event driven logic without a global clock. It is however also understood, that the operating principle of the present invention may be implemented with a clocked logic that is clocked with a global clock that has a high enough frequency for performing the required operations.

In case of a buck type converter arrangement, the switching frequency may e.g. be increased inversely to the power demand or the current drawn by the electric load. The on time of the single switching elements, i.e. the active period of the respective voltage conversion unit, will determine the amount of time that the inductor of the single voltage conversion units is provided with electrical power, i.e. the amount of time that is provided for a magnetic field to build up. When the switching element is then opened again, the energy stored in the magnetic field will be released as a current that generates a voltage drop over the inductor. The shorter the on time of the respective switching element is, the lower the current and the voltage drop will be that is provided by the inductor after the respective switching element is turned off or opened.

The control unit may therefore increase the switching frequency for the voltage conversion units when the power demand decreases and may decrease the switching frequency for the voltage conversion units when the power demand increases. Similar explanations apply mutatis mutandis to other arrangements, like boost-type or buck-boost-type arrangements.

With the present invention, the voltage conversion units are so arranged that they create the minimal ripple in the input voltage and the output voltage of the voltage converter using the minimal number of components.

Further embodiments of the present invention are subject of the further subclaims and of the following description, referring to the drawings.

In an embodiment, the control unit may be configured to consecutively switch the voltage conversion units in the charging mode if the ratio between the second voltage level and the first voltage level is less than 0,5 or equal to 0,5, and to consecutively switch the voltage conversion units in the discharging mode if the ratio between the second voltage level and the first voltage level is larger than 0,5. This means that of the charging and the discharging mode always the shorter mode is actively controlled.

In an embodiment, the control unit may be configured to consecutively switch the voltage conversion units in a charging mode or a discharging mode at a predetermined point in time prior to the end of the charging mode or a discharging mode of the voltage conversion unit that is at that point in time in the charging mode or the discharging mode.

This means that not only the end of the charging mode or the discharging mode may represent a trigger or event that marks the start of the charging mode or the discharging mode, respectively, for the next voltage conversion unit. The additional point in time prior to the end that is mentioned above implies that the exclusivity of the charging or the discharging mode is not 100%, but that the charging mode or the discharging mode may overlap slightly, i.e. starting from the additional point in time prior to the end of the charging mode or the discharging mode of the voltage conversion unit that is at that point in time in the charging mode or the discharging mode. The additional point in time prior to the end may e.g. be defined by a current or voltage in the respective voltage conversion unit below the maximum current or voltage for the respective charging mode or above the minimum current or voltage for the respective discharging mode. In an application the point in time may e.g. be determined by an additional comparator that compares the respective voltage or current with a respective threshold value.

In a possible embodiment, the control unit may be configured to adapt the switching frequency or timing between a predetermined minimum switching frequency for output currents starting from a first current threshold and higher and a predetermined maximum switching frequency for output currents starting from a second current threshold and lower.

The control unit will accordingly use switching frequencies between the minimum switching frequency and the maximum switching frequency. The switching frequency or timing will be adapted according to the output current, i.e. the lower the output current is, the higher the switching frequency will be chosen. It is understood, that the switching frequency will not increase above the maximum switching frequency limit in any case. As already explained above, if the voltage converter is a buck-type converter, a higher switching frequency will provide less time for the inductor to store power in its magnetic field, therefore only a lower output current will be available. In contrast, lower switching frequencies will provide more time for the inductor to store power in its magnetic field, hence the resulting output current will be increased.

The chosen frequency limits also determine the frequencies of the voltage and/or current ripples of the output power of the voltage converter. The minimum switching frequency and the maximum switching frequency may therefore be predetermined according to the respective application and the application’s demands. The maximum switching frequency may further be limited by the maximum processing speed or the clock rate of the control unit. In terms of timing, the maximum switching frequency will lead to the shortest charging or discharging mode, and the minimum switching frequency will lead to the longest charging or discharging mode.

A typical minimum switching frequency may e.g. be in the range of 50 kHz to 200 kHz, especially 150 kHz or 125 kHz or 120 kHz. It is understood, that lower frequencies may also be possible but will usually be chosen in the non-audible range. The maximum switching frequency may e.g. be in the range of 250 kHz to 1 GHz, especially about 300 kHz, 325 kHz or 350 kHz. It is understood, that higher frequencies are also possible. The resulting switching frequency is a function of the optimal efficiency depending on the switching transistors and the inductor parameters at the most likely power conversion ratio or at another power conversion ratio that fulfills the respective application’s requirements.

To prevent raising the switching frequency above the maximum switching frequency, in a possible embodiment, the control unit may be configured to use the minimum switching frequency for all currents below the second current threshold and include a respective off- time in every active period of a switching cycle, wherein the control unit may be configured to determine the duration of the off-time based on the output current.

The term off-time refers to a time in the active period of a switching cycle in which the respective switching element is not switched on. This may e.g. be a time that is inserted after the end of the charging of the respective energy storage element.

If the control unit continuously increases the switching frequency, i.e. shortens the charging or discharging mode, with decreasing output current, the switching frequency will eventually reach the maximum frequency. In this state, if the respective switching element is switched on for the complete switching period, the output voltage will increase if the output current decreases further.

To prevent an increase of the switching frequency to high and possibly inefficient switching frequencies, the control unit may introduce the respective off-times in every switching cycle. This means, that the duration of switching on the respective switching element is shorter than the respective switching cycle. Consequently, for the remaining duration of the respective switching cycle no switching element is turned on.

This arrangement allows further reducing the time that is provided to the respective inductors for storing power in the resulting magnetic field, while at the same time keeping the switching frequency constant.

In a possible embodiment, the control unit may comprise for every one of the voltage conversion units a switching signal generation circuitry that may be configured to generate switching signals based on a measured voltage or a measured current in the respective voltage conversion unit and based on a low level reference voltage and based on a high level reference voltage. It is understood, that the measured voltage may be representative of the current in the respective voltage conversion unit. For example a shunt resistor may be used to measure the current in the respective voltage conversion unit and a voltage over the shunt resistor may be used as indication of the current.

The switching signal generation circuitry may e.g. comprise two comparators, one

comparator that compares the measured voltage with the high level reference voltage and one comparator that compares the measured voltage with the low level reference voltage. The outputs of the comparators may then be fed to a SR Flip Flop that generates respective switching signals for the switching elements of the respective phase.

For example, one output of the SR Flip Flop may be provided to a high-side switching element of the respective voltage conversion unit and the second output of the SR Flip Flop may be provided to the low-side switching element of the respective voltage conversion unit, i.e. a switching element that is provided instead of a diode, as explained above. It is understood, that any other arrangement is also possible. For example, both driving signals, for the high-side switch and the low-side switch, may be generated of a single output of the SR Flip Flop.

With the switching signal generation circuitry the respective switching signals for the voltage conversion units may be generated. The details, e.g. the duration, of the switching signals may be configured by adapting the low level reference voltage and the high level reference voltage accordingly.

In a possible embodiment, the control unit may comprise for every one of the voltage conversion units an arbitration logic that is configured to allow only one of the voltage conversion units to be active simultaneously.

The arbitration logic may e.g. receive switching signals or other signals from all voltage conversion units to decide whether the respective phase may be activated or not. The arbitration logic is required to make sure that the phases are not activated concurrently but sequentially to evenly distribute the load over all phases and reduce the input and output ripple as much as possible.

The arbitration logic may e.g. comprise a logic that only provides a positive output signal if the switching signal for the respective phase indicates an active switch, while the other voltage conversion units provide signals that indicated a deactivated or inactive switch.

In a possible embodiment, the control unit may comprise for every one of the voltage conversion units a blocking unit that may be configured to block the other voltage conversion units for the duration of the switching cycle of the respective voltage conversion unit or another predetermined amount of time, like e.g. the duration of the switching cycle of the next voltage conversion unit.

The duration of the switching cycle is mainly determined by the low level reference voltage and the high level reference voltage. However, as explained above, there may exist a situation or point of operation at which switching elements of a voltage conversion unit may be deactivated, while the switching cycle of the respective voltage conversion units is still active. This may especially be the case for very low currents, where the respective inductor is not loaded during the whole of the switching cycle, as explained above.

The blocking unit therefore serves to make sure that the maximum switching frequency is not exceeded by introducing a blocking or waiting interval after the active switching time in the switching cycles.

The blocking unit may e.g. be configured to always output a signal that corresponds to the period duration of the maximum switching frequency that is allowed for the voltage converter.

In a possible embodiment, in each case the arbitration logic of one of the voltage conversion units may be coupled to the switching signal generation circuitry of the respective voltage conversion units and the blocking unit of at least the preceding voltage conversion unit according to a switching order for the voltage conversion units.

The blocking units, as explained above, introduce a blocking or waiting time and provide a respective signal. This means, that the signals from the blocking units indicate to the other voltage conversion units, e.g. to the respective arbitration logic, if the switching cycle of the respective one of the voltage conversion units is still active.

Only one of the voltage conversion units should be active at every point in time. This means that only one of the voltage conversion units may be in an active switching cycle with the respective switching elements activated or in the blocking or waiting time. Therefore the arbitration logic may use the signals from the preceding voltage conversion unit, i.e. the respective blocking unit, to determine if the preceding voltage conversion unit is in the switching cycle and only activate its own switching cycle if the preceding voltage conversion unit is not active and no other phase is active. This means that depending on whether the charging mode or the discharging mode is actively controlled, one voltage conversion unit may be in the controlled mode, while all other voltage conversion units may be in the not- controlled mode.

In an embodiment, the voltage conversion units may comprise electric components of different dimensions. It is understood, that every one of the voltage conversion units may be designed to support approximately the same voltage conversion ratios and power levels, while at the same time the exact values of the components, like e.g. inductors, capacitors, resistances, diodes, and switches are slightly varied between the single voltage conversion units. This means that the voltage conversion units are different by design and comprise slightly different timing characteristics. Consequently a jitter is designed into the voltage converter. Such a jitter leads to a broader spectrum of the noise that is generated by the voltage converter and less peaks will be present in the noise spectrum.

To further reduce the peaks in the noise spectrum, it is possible to arrange multiple separate voltage converters in parallel. It is for example possible to arrange multiple voltage converters, each with at least three voltage conversion units, in parallel. It is understood, that the number of voltage conversion units may be different in the single voltage converters. For example one voltage converter may comprise three voltage conversion units, and a second voltage converter may comprise four voltage conversion units. Any combination is possible in this regard.

It is understood, that the logic described above regarding the control unit may be

implemented using discrete elements, like e.g. logic gates, amplifiers, resistors and the like, as will be described in more detail below. It is however also understood, that the logic described above regarding the control unit may also be implemented as software or a combination of software and hardware. The function of the control unit may e.g. be implemented as a firmware or program that is stored in a memory and that is loaded from the memory and executed by a controller or processor of the voltage converter.

Further, the control unit may be configured to detect errors in single ones of the voltage conversion units and when cycling through the voltage conversion units to skip the voltage conversion units in which an error was detected.

This allows the voltage converter to fully continue operation even if one of the voltage conversion units is defective.

Brief description of the drawings

For a more complete understanding of the present invention and advantages thereof, reference is now made to the following description taken in conjunction with the

accompanying drawings. The invention is explained in more detail below using exemplary embodiments which are specified in the schematic figures of the drawings, in which:

Fig. 1 shows a block diagram of an embodiment of a voltage converter according to the present invention;

Fig. 2 shows a block diagram of another embodiment of a voltage converter according to the present invention;

Fig. 3 shows a block diagram of another embodiment of a voltage converter according to the present invention;

Fig. 4 shows a flow diagram of an embodiment of a method according to the present invention;

Fig. 5 shows a diagram of input ripple over the duty factor of a voltage converter; Fig. 6 shows a diagram of possible current levels in the voltage conversion units of an embodiment of a voltage converter according to the present invention;

Fig. 7 shows another diagram of possible current levels in the voltage conversion units of an embodiment of a voltage converter according to the present invention;

Fig. 8 shows another diagram of possible current levels in the voltage conversion units of an embodiment of a voltage converter according to the present invention;

Fig. 9 shows another diagram of possible current levels in the voltage conversion units of an embodiment of a voltage converter according to the present invention;

Fig. 10 shows a block diagram of another embodiment of a voltage converter according to the present invention;

Fig. 1 1 shows a block diagram of another embodiment of a voltage converter according to the present invention; and

Fig. 12 shows a block diagram of another embodiment of a voltage converter according to the present invention.

The appended drawings are intended to provide further under-standing of the embodiments of the invention. They illustrate embodiments and, in conjunction with the description, help to explain principles and concepts of the invention. Other embodiments and many of the advantages mentioned become apparent in view of the drawings. The elements in the drawings are not necessarily shown to scale.

In the drawings, like, functionally equivalent and identically operating elements, features and components are provided with like reference signs in each case, unless stated other-wise.

Detailed description of the drawings

Fig. 1 shows a block diagram of a voltage converter 100. The voltage converter 100 converts an input voltage 151 from a power source 150 with a first voltage level, e.g. 48 V, into an output voltage 152 for an electric load 153 with a second voltage level of e.g. 12 V.

Especially with the voltage levels of 48 V and 12 V the voltage converter 100 may e.g. be used in automotive applications, where the vehicle comprises a 48 V power supply network section and a 12 V power supply network section.

The voltage converter 100 comprises an input port 101 that couples the voltage converter 100 to the power source 150, and comprises an output port 102 that couples the voltage converter 100 to the electric load 153. The voltage converter 100 further comprises three exemplary voltage conversion units 103 arranged between the input port 101 and the output port 102. It is understood, that the number of three voltage conversion units 103 is just exemplarily chosen and that any number of voltage conversion units starting from two is possible in other embodiments. Each of the voltage conversion units 103 comprises a first switching element 104 arranged at a positive input of the respective voltage conversion unit 103, and a second switching element 105 that is arranged between the output of the first switching element 104 and a negative input of the respective voltage conversion unit 103, e.g. ground. In addition, an inductor 106 is arranged between the output of the first switching element 104 and an output of the respective voltage conversion unit 103. It is understood, that the schematic arrangement that is shown for the voltage conversion units 103 is just an exemplary arrangement of a buck-type voltage converter. It is further understood, that any type of switch mode voltage converter arrangement may be used instead in the voltage conversion units 103.

The voltage converter 100 further comprises a control unit 107 that is coupled to the voltage conversion units 103 and provides switching signals 109 to the voltage conversion units 103 in order to control the first switching element 104 and the second switching element 105 of the respective voltage conversion units 103. To this end the control unit 107 is coupled to the output of the voltage conversion units 103 to determine the power demand 108 of the electric load 153.

During operation of the voltage converter 100, the input port 101 receives the input voltage 151 , and the output port 102 provides the output voltage 152 to the electric load 153. The control unit 107 controls the switching elements 104, 105 of the voltage conversion units 103 and adapts the timing for consecutively switching the switching elements 104, 105 of the voltage conversion units 103 based on the determined power demand 108 of the electric load 153.

Controlling the first switching element 104 and the second switching element 105 may refer to closing or activating the first switching element 104 and opening the second switching element 105 during a charging mode of the respective voltage conversion unit 103.

Consequently, during a non-active period or discharging mode of the respective voltage conversion unit 103, the first switching element 104 may be opened and the second switching element 105 may be closed. The current that may be provided by the respective voltage conversion unit 103 depends on the duration of the active period of the voltage conversion units 103. As explained above, the longer the active period is, the more current may be provided by the voltage converter 100 to the electric load 153, i.e. the higher the electrical power supplied by the voltage converter 100 will be. In contrast, a low load or power demand will lead to a shorter charging period. The high level and low level reference voltages may be adapted accordingly, see e.g. Fig. 2.

The switching frequency in this context is the frequency with which the control unit 107 consecutively activates the single voltage conversion units 103 one after the other in a predetermined sequence. Since in any moment one of the voltage conversion units 103 is supposed to be in the active period (with the exception of a very low power demand 108, as will be explained below), reducing the duration of the active period automatically increases the switching frequency. It is understood, that a maximum switching frequency may be provided as a limiting factor and that the control unit 107 will not increase the switching frequency above this maximum switching frequency. In addition, a minimum switching frequency may also be provided.

With the control scheme that adapts the switching frequency for switching between the single voltage conversion units 103 according to the power demand 108 of the electric load 153, it is possible to continuously operate the voltage converter 100 in the optimal operating point and therefore reduce the input ripple as well as the output ripple to a minimum.

Fig. 2 shows a block diagram of another embodiment of a voltage converter 200, especially a section of the control unit that generates the switching signals 225, 226 for a single one of the voltage conversion units. It is understood, that the control unit may comprise the same arrangement for every one of the voltage conversion units. For sake of clarity, not every single element in Fig. 2 is referenced with a dedicated reference sign, however, every element will be explained below in detail and any element appearing in the claims is provided with a respective reference sign.

The control unit receives on the input side a measured voltage 21 1 that represents the current in the respective voltage conversion unit, i.e. on the output side of the respective voltage conversion unit. The current may e.g. be measured via a shunt resistor. The control unit further receives on the input side a high level reference voltage 212 and a low level reference voltage 213. All voltages 21 1 , 212 and 213 are provided to a switching signal generation circuitry 210. The switching signal generation circuitry 210 comprises a first comparator 214 and a second comparator 215. The high level reference voltage 212 is provided to the positive input of the first comparator 214 and the measured voltage 21 1 is provided to the negative input of the first comparator 214. Further, the measured voltage 21 1 is provided to the positive input of the second comparator 215, and the low level reference voltage 213 is provided to the negative input of the second comparator 215.

The output of the first comparator 214 is provided to the S input of a Set Reset Flip Flop 216, SR Flip Flop, and the output of the second comparator 215 is provided to the R input of the SR Flip Flop 216, in this example provided with two NAND gates. The comparators 214, 215 and the SR Flip Flop 216 together generate switching signals 225, 226. The switching signal 225 is provided by the first output of the SR Flip Flop (e.g. called Q1 ), and the switching signal 226 is provided by the second output of the SR Flip Flop (e.g. called Q2). The switching signal 226 is directly provided to a low-side driver 223 that drives the low-side switch, e.g. the second switching element 105 in Fig. 1 , of the respective voltage conversion unit. In the low-side driver 223, the switching signal 226 is inverted prior to driving the respective switching element.

The switching signal 225 is not directly provided to the high-side driver 222 that drives the high-side switch, e.g. the first switching element 104 in Fig. 1 , of the respective voltage conversion unit. Instead, the switching signal 225 is provided to an arbitration logic 217. The arbitration logic 217 performs an arbitration between the single control arrangements in the control unit for the single voltage conversion units, such that only one of the voltage conversion units may be in the active state or period at any moment in time. The high-side driver 222 may comprise any circuitry that is required to drive a high-side switching element, like e.g. a N-Channel MOSFET.

The arbitration logic 217 comprises a NOR gate. One input of the NOR gate receives the switching signal 225, the other inputs of the NOR gate are coupled to other voltage conversion units and receive respective arbitration signals 218 or blocking signals 220 (see below) from the other voltage conversion units. In addition, the arbitration logic 217 comprises an OR gate, wherein one input of the OR gate is coupled to the output of the NOR gate and one input of the OR gate is coupled to a start signal input, that initiates the switching in the voltage converter 200. It is understood, that the OR gate may be provided only in one of the arrangements for controlling the single voltage conversion units, since it is not necessary to provide the start signal in all voltage conversion units. The start signal and the respective OR gate may also be omitted entirely The output of the OR gate may be the input signal to the high-side driver 222. In addition, the output of the OR gate may also be provided as the arbitration signal 218 to further voltage conversion units.

As already hinted at above, the control unit also comprises a blocking unit 219. The blocking unit 219 also comprises a SR Flip Flop, wherein the S input of the SR Flip Flop is coupled to the output of the first comparator 214. The outputs of the SR Flip Flop are coupled to a delay circuit, and the output of the delay circuit is coupled to the R input of the SR Flip Flop. The delay circuit comprises a resistor at every one of the outputs and a capacitor that couples to the outputs of the resistors. A comparator is further arranged in parallel with the capacitor and the output of the comparator is the output of the delay circuit that is coupled to the R input of the SR Flip Flop. The dimensions of the resistors and the capacitor may be adapted according to a required delay time. The delay time will be the minimum period duration of the switching of the respective voltage conversion unit and therefore determined the maximum switching frequency. This will be explained in detail in conjunction with Fig. 9 below.

The first output, Q1 , of the SR Flip Flop in the blocking unit 219 is coupled to the NOR gate of the arbitration logic of the arrangement for the following voltage conversion unit, i.e. the signal provided by the first output Q1 is the blocking signal 220. This means, that the blocking unit 219 may block the following voltage conversion unit from entering the active period. The control scheme that is performed according to the present invention may - as indicated above - be called event-driven. The event for starting the active period of a voltage conversion unit may be represented by respective signal levels of the arbitration signal 218 and the blocking signal 220 of the preceding voltage conversion unit. This means, that the event may be the finishing of the charging of the respective energy storage element or the finishing of the minimum time period that is required to keep the switching frequency at the allowed maximum switching frequency. This will further be explained with regard to Fig. 9.

As already explained above, the control unit of the voltage converter 200 may comprise an arrangement as shown in Fig. 2 for every one of the voltage conversion units. It is however also understood, that the logic function as performed by the shown arrangement may also be implemented e.g. in a processor or in a programmable logic device, like e.g. a CPLD or FPGA.

Fig. 3 shows a block diagram of another embodiment of a voltage converter 300. The voltage converter 300 comprises a control unit 307 and four voltage conversion units 330, 331 , 332, 333 that are controller by the control unit 307. It is understood, that the control unit 307 may e.g. comprise four times the arrangement as shown in Fig. 2 for controlling the voltage conversion units 330, 331 , 332, 333. The control unit 307 is provided with the high level reference voltage 312 and the low level reference voltage 313. In addition, a start signal is provided by enable signal source 341 .

The detailed arrangement of the voltage conversion units 330, 331 , 332, 333 is exemplarily explained for the voltage conversion unit 330. It is understood, that the other voltage conversion units 331 , 332, 333 may be provided analogously. The voltage conversion unit 330 comprises a high side switch 304 that is coupled on its input with a voltage input 338 or supply voltage, e.g. a 48 V input voltage. On the output, the high side switch 304 is coupled to the input of a low side switch 305 that is coupled on its output to ground 337. An inductor 339 is coupled with its input to the node between the high side switch 304 and the low side switch 305 and a resistor 340 is coupled between the output of the inductor 339 and the output of the voltage conversion unit 330.

The control unit 307 is coupled to the voltage conversion unit 330 via a first control line that provides a switching signal to the high side switch 304, and a second control line that provides a switching signal to the low side switch 305. In addition, the control unit 307 is coupled to the node between the high side switch 304 and the low side switch 305 and to ground. Finally, the node between the inductor 339 and the resistor 340 is coupled to a sense input of the control unit 307 to determine the voltage over the resistor 340, and therefore indirectly the current in the voltage conversion unit 330.

For sake of clarity in the following description of the method based Fig. 4 the reference signs used above in the description of apparatus based Figs. 1 - 3 and 10 - 12 will be maintained.

Fig. 4 shows a flow diagram of an embodiment of a method for operating a voltage converter 100, 200, 300, 400, 500 for converting an input voltage 151 from a power source 150 with a first voltage level into an output voltage 152 for an electric load 153 with a second voltage level. The voltage converter 100, 200, 300, 400, 500 may comprise a number of voltage conversion units 103, 330, 331 , 333 , 403, 503 arranged in parallel between an input port 101 and an output port 102, each voltage conversion unit comprising a number of switching elements 104, 105, 304, 305, 404, 405 and e.g. energy storage elements like inductors and capacitors.

The method comprises measuring a power demand 108 of the electric load 153 in a first step S1 of measuring. In a second step S2 of determining, the switching frequency or timing for consecutively switching the voltage conversion units 103, 330, 331 , 333, 403, 503 into a charging mode is determined based on the measured power demand 108. Further, in a third step S3 of switching, the voltage conversion units 103, 330, 331 , 333, 403, 503 are switched into the charging mode according to the determined switching frequency, wherein only one of the voltage conversion units 103, 330, 331 , 333, 403, 503 is in the charging mode at any point in time.

The switching frequency may e.g. be determined between a predetermined minimum switching frequency for output currents of the voltage converter 100, 200, 300, 400, 500 starting from a first current threshold and higher and a predetermined maximum switching frequency for output currents of the voltage converter starting from a second current threshold and lower. It is obvious, that the second current threshold may be lower than the first current threshold. The minimum switching frequency may be used for currents below the second current threshold. In addition, a respective off-time may be provided in every switching cycle to provide the respective current. The duration of the off-time may be determined based on the output current of the voltage converter.

Switching signals 109, 225, 226 for every one of the voltage conversion units 103, 330, 331 , 333, 403, 503 may be generated based on a measured voltage 21 1 , 41 1 , 51 1 in the respective voltage conversion unit 103, 330, 331 , 333, 403, 503 and based on a low level reference voltage 213, 313, 413, 513 and based on a high level reference voltage 212, 312, 412, 512. As explained above, the measured voltage 21 1 , 41 1 , 51 1 may represent a current in the respective voltage conversion unit 103, 330, 331 , 333, 403, 503 and the respective voltage conversion unit 103, 330, 331 , 333, 403, 503 may be activated while the measured voltage 21 1 , 41 1 , 51 1 is higher than the low level reference voltage 213, 313, 413, 513 and lower than the high level reference voltage 212, 312, 412, 512.

Further, only one of the voltage conversion units 103, 330, 331 , 333, 403, 503 may be activated, i.e. charging or discharging, respectively, at any time, i.e. no two or more voltage conversion units 103, 330, 331 , 333, 403, 503 may be activated concurrently. For the duration of the switching cycle of a respective one of the voltage conversion units 103, 330, 331 , 333, 403, 503 the other ones of the voltage conversion units 103, 330, 331 , 333, 403, 503 may therefore be blocked. Further, the voltage conversion units 103, 330, 331 , 333, 403, 503 may be activated according to a predetermined switching order for the voltage conversion units 103, 330, 331 , 333, 403, 503, and defective voltage conversion units 103, 330, 331 , 333, 403, 503 may be detected and may be skipped.

Fig. 5 shows a diagram of input ripple over the duty factor, i.e. the ratio of the output voltage to the input voltage or the ratio of the active period to the inactive period of the single voltage conversion units, of a voltage converter for different numbers of phases. It can be seen, that with two phases the minimum input ripple is at a duty factor of 0,5. It can also be seen, that with an increasing number of phases more ripple minima are provided. With three phases three minima are provided at a duty factor of 0,5, approximately 0,33, and approximately 0,67. With four phases three minima are provided at a duty factor of 0,5, 0,25, and 0,75. With six phases, five minima are provided at a duty factor of 0,5, approximately 0,33, and approximately 0,67, approximately 0,17, and approximately 0,83. To provide minimum input ripple at a predetermined duty factor, in common voltage converters the number of phases would be increased until a minimum could be provided as required. However, this involves high complexity and costs for the voltage converter.

With the present invention, it is however possible, to move the minima to desired positions by applying the duty factor required and the arrangement of the present invention will adjust the timing, i.e. the switching frequency, automatically. As result the switching frequency will follow appropriately. In other words the present invention will result in one of the optimal minima as shown e.g. in Fig. 5 following the load duty factor. For example with three units, a minimum ripple could be created anywhere between the minima at approximately 0,33, and approximately 0,67. In this case any fractal phase value between 2 and 3 phases. With four units a minimum could be created anywhere between the minima at 0,25, and 0,75. In this case any fractal phase value between 2 and 4 phases. With six units a minimum could be created anywhere between the minima at approximately 0,17, and approximately 0,83. In this case any fractal phase value between 2 and 6 phases. Similarly this may be provided with any other combinations between units and phases.

The present invention therefore creates a minimum that may be called a moving minimum or provides a voltage converter with a fractal number of phases, because it allows providing the minimum at the point that would theoretically be achieved e.g. with 3,x, e.g. 3,5, phases or the like.

For better understanding of the working principle of the present invention the following formulas are presented:

The current output ripple peak-to-peak amplitude in an m-phase circuit may be described as:

where me is the number or parallel channels or voltage conversion units, m is the number of phases, D is the duty cycle between 0<D<1 , V₀ is the output voltage, T is the switching period, L_f is the capacity of the output inductor.

If m is set to a fractal value m= 2.34 =>

,note now the ripple is 0 at a fractal duty cycle of 1/(2.34), where X and

Y are two unresolved (positive) rest points.

Input Ripple Current Cancellation may be described as follows: k = f(rn-D), m = 1 ,2,...

The variable k is determined by the phase number (m) and the duty cycle (D). For example, in a five-phase converter, at 45% duty cycle, k = FLOOR(5 · 0.45) = 2. The FLOOR(x) function provides a greatest integer that is smaller than or equal to x.

, which does not depend of the current

l₀, the ripple minima are however influenced by the current:

Ripple minima:

Set m = 2 ; 0 < D < 1 => k=1

(D - - D) , minimum when ratio D = ½ Set m = 3 ; 0 < D < 1 => k=1

( D ^{_ _} £>) gives minimum when ratio D = 1/3 and D = 2/3

Set m to a fractal value m= 2.5 => 0 < D < 1 => k = 1

(^D-f)(f-^D)

At this point, reference is also made to the document: High Efficiency, High Density, PolyPhase Converters for High Current Applications by Wei Chen from Linear Technologies (Application Note 77)

The ripple phase of e.g. the fractal value 2.5 results because a voltage difference of e.g. 5/3, like for example 25V input and 15V output or vice versa, is used. The selected voltage difference or ratio between input and output voltage in combination with the event driven control scheme leads to the fractal phase as described above.

Fig. 6 shows a diagram of possible current levels in the voltage conversion units P1 - P5 of a voltage converter according to the present invention. The diagram shows a five voltage conversion unit arrangement and the single voltage conversion units are referenced as P1 , P2, P3, P4, and P5. In the diagram three current curves are shown for three different current levels. The upper current curve shows the currents in the single voltage conversion units P1 - P5 for a high current situation. The center current curve shows the currents in the single voltage conversion units P1 - P5 for a medium current situation. Finally, the lower current curve shows the currents in the single voltage conversion units P1 - P5 for a low current situation. It is however understood, that the power demand of the load for the lower current curve is still such that the maximum switching frequency is not exceeded, in contrast to the situation shown in Fig. 9.

In the current curves the current ramps that are generated in the single voltage conversion units P1 - P5 when they are activated can be seen. It can also be seen, that the duration of the current ramps is reduced with lower current demands, while the slope or gradient is the same in all current curves. This means that the altitude of the current ramps, i.e. the maximum current value in the respective voltage conversion unit, is reduced if the duration of the ramp is reduced.

It can be seen that the current curves comprise the largest duration in the upper current curve for the high current or power demand situation. The duration of the current ramps in the center current curve is about half the duration of the current ramps in the upper current curve, and the duration of the current ramps in the lower current curve is about half the duration of the current ramps in the center current curve.

It can be seen in Fig. 6 that the control scheme that modifies the switching frequency or timing for switching between the single voltage conversion units P1 - P5 may be used until the current or power demand is so low that a maximum switching frequency is reached.

It will be explained below in conjunction with Figs. 8 and 9 how such low currents may be provided anyways.

Fig. 7 shows possible current levels in the voltage conversion units P1 - P5 of a voltage converter according to the present invention. It can be seen, that during normal operation of the voltage converter and with the switching frequency being between the minimum and the maximum switching frequency, the active periods of the voltage conversion units P1 - P5 do not overlap. Instead, the end of the active period, i.e. the charging of the energy storage element of one voltage conversion unit is the trigger that starts the active period of the next voltage conversion unit.

It can be seen, that the active period of each voltage conversion unit starts with the current at a minimum current point and that the current linearly increases to a maximum current point. Speaking in the terms of Fig. 2, the respective voltage conversion unit is in an active mode while the voltage that is measured as an indicator of the current in the respective voltage conversion unit is between the high and the low reference voltages.

It can further be seen, that after the last voltage conversion unit is in the active period, the first voltage conversion unit is activated or put in the active period again.

Fig. 8 shows possible current levels in the voltage conversion units P1 - P5 of a voltage converter according to the present invention.

In the diagram of Fig. 8 the upper curve shows the currents in the single voltage conversion units P1 - P5 and the lower curve shows the resulting current. The dotted line in the lower curve shows the resulting current taking into account any smoothing effects that may e.g. be caused by capacitors or the like.

In the upper curve a blocking time tb is shown for voltage conversion unit P1 . The blocking time may be the time that is configured in the blocking unit 219 of Fig. 2. This means that no other voltage conversion unit P2 - P5 may be activated during the blocking time tb of voltage conversion unit P1 . It can be seen in Fig. 8 that there is still a small margin between the end of the blocking time tb of voltage conversion unit P1 and the beginning of the current ramp of voltage conversion unit P2. This means that the output current may be further reduced until the beginning of the current ramp of voltage conversion unit P2 matches the end of the blocking time tb.

If however, the power demand and therefore the current in the voltage conversion units P1 - P5 is further reduced, it will not be possible to further shorten the duration of the active period of voltage conversion unit P1 because it may not be reduced below the blocking time tb.

How a current or power demand with a lower current may be satisfied is further explained in Fig. 9. It can be seen, that after the current ramp of voltage conversion unit P1 reaches its maximum point, the active period of voltage conversion unit P2 is not immediately started. Instead the generation of the current ramp in voltage conversion unit P2 is delayed until the blocking time tb of the voltage conversion unit before voltage conversion unit P1 is reached. The same applies to the switch from voltage conversion unit P2 to voltage conversion unit P3, which is delayed by the blocking time tb from voltage conversion unit P1 and so on. It is understood, that blocking the next but one voltage conversion unit may simplify the circuit design. It is however understood, that in one embodiment the blocking time may be provided by the directly preceding voltage conversion unit in each case.

It can be seen in the resulting current curve that zero current periods are inserted between the current ramps of the single voltage conversion units P1 - P5. The resulting output current of the voltage converter will therefore be even lower than the current that is achieved with a switching frequency at the minimum switching frequency threshold and no blocking time tb. Fig. 9 shows that the event that starts the charging phase of the next to be charged voltage conversion unit P1 - P5 is the later one of the end of the charging mode of the preceding voltage conversion unit or the end of the blocking time of the last but one voltage conversion unit. As explained above, the end of the blocking time of the directly preceding voltage conversion unit may also be used instead of the blocking time of the last but one voltage conversion unit.

Fig. 10 shows a block diagram of another embodiment of a voltage converter 400. The voltage converter 400 comprises four voltage conversion units or channels. For sake of clarity only the first voltage conversion unit 403 will be explained in detail. It is understood, that the further three voltage conversion units are arranged analogously to the first voltage conversion unit 403.

The voltage conversion unit 403 receives the value of a measured voltage 41 1 that is measured in the respective power path of the voltage conversion unit 403 and represents the current through the inductor 439 (see Fig. 1 1 ) of the voltage conversion unit 403. The measured voltage 41 1 is provided to a comparator 414 on the positive input and to a comparator 415 on the negative input. The comparator 414 is further provided with the high level reference voltage 412 on the negative input and the comparator 415 is provided with the low level reference voltage 413 on the positive input.

This means that the comparator 414 will provide a high signal when the measured voltage 41 1 raises above the high level reference voltage 412. In contrast, the comparator 415 will provide a positive signal when the measured voltage 41 1 is below the low level reference voltage 413. The output of comparator 414 is provided to the R input of SR Flip Flop 416.The output of comparator 415 is provided to the S input of SR Flip Flop 416. Prior to feeding the output of comparator 415 to the S input of SR Flip Flop 416, it is fed to an AND gate 472. The other input of the AND gate 472 is fed with a signal of a delay circuit of the voltage conversion unit that precedes the voltage conversion unit 403. In the arrangement of the voltage converter 400 this is the third voltage conversion unit, i.e. the last but one before the voltage conversion unit 403. The AND gate 472 is therefore blocked until the delay circuit of the respective voltage conversion unit releases or enables the voltage conversion unit 403 after the respective blocking time passes. The negated output Q of the SR Flip Flop 416 is fed to the delay circuit 466 that blocks the third voltage conversion unit accordingly. The delay time of delay circuit 466 may e.g. be 1 uS.

The Q output of the SR Flip Flop 416 represents a kind of control signal for the switching elements 404, 405 (see Fig. 1 1 ). The signal from the Q output of the SR Flip Flop 416 is therefore fed into a NOR gate 473 that mainly acts as an inverter for the signal from the Q output. In addition, the NOR gate 473 is also fed with the output signal from comparator 415 to only drive the switching element 405 when indicated by the measured voltage 41 1 and the low level reference voltage 413. Finally, a third signal is provided to the NOR gate 473 that serves to make sure that the two switching elements 404, 405 are not opened at the same time to prevent a short circuit. It is understood, that any other arrangement to prevent simultaneously opening the switching elements 404, 405 may also be used as alternative.

In the voltage converter 400 the output signal 465 of the NOR gate 473 is on the one hand used to drive the low side switching element 405 (see Fig. 1 1 ) and is also fed to one input of NOR gate 474. The output signal 464 of NOR gate 474 is on the one hand used as the control signal for the high side switching element 404 and on the other hand is provided to delay circuit 467 that generates the signal that is provided to NOR gate 473 to prevent simultaneously switching on both switching elements 404, 405. The delay time may e.g. be 30 ns.

A second input of the NOR gate 474 is fed by a NAND gate 475 that is fed on one input with the Q output signal of SR Flip Flop 416 and on the other input with the inverted signal from a function generator 476. The function generator 476 has an output for every one of the voltage conversion units and is fed with the output signals of the high level comparators of all voltage conversion units, signal 462 for the voltage conversion unit 403, through NOR gate 477. The function generator 476 comprises an output for every voltage conversion unit.

Every time, the input signal to the function generator 476 changes, the function generator will switch active the next output. In the shown arrangement, the function generator 476 is low active. Therefore, the output signal u1 is inverted in the voltage conversion unit 403 prior to feeding it into the NAND gate 475.

The arrangement of the voltage converter 400 is continued in Fig. 1 1 , where the control signals 464, 465 are fed into a driving stage of the respective voltage conversion unit. The same applies to the control signals of the other voltage conversion units. The block diagram of Fig. 10 may therefore be seen as showing the control logic, while Fig. 1 1 will show the respective power or driving stages.

In Fig. 10 it becomes clear, that the present invention may be realized without using clocked logic that requires a global clock signal for operation. Instead, the single voltage control units provide the respective events that trigger the switching to the next voltage control unit. The shown block diagram may therefore also be said to show an event driven logic or control core for the voltage converter 400.

It is understood, that the above explanations regarding the voltage conversion unit 403 may be applied mutatis mutandis to the other voltage conversion units.

Fig. 1 1 shows a block diagram of the power stage of the voltage converter 400. It can be seen that the output or control signals 464, 465 are both used to control switching elements 404, 405. The switching elements 404, 405 may e.g. be N-Channel MOSFETs. To drive the high side switching element 404 the level shifter 468 is provided. The low level switching element 405 may be directly driven with signal 465. The switching elements are provided in series between a voltage input 438 and ground 437. In addition, capacitor 469 is provided between the voltage input 438 and ground 437. The node between the two switching elements 404, 405 is coupled to inductor 439. The inductor 439 is on the other end coupled to a current sensor 440, here a shunt resistor 440. The measured voltage 41 1 is taken from the node between the inductor 439 and shunt resistor 440. The other end of the shunt resistor 440 is the output 434 of the voltage converter 400 that may be coupled to the load. To improve the measurement accuracy, a measurement reference point is provided near the shunt resistor 440. Further, capacitor 470 is provided between the output 434 and ground 437.

In Fig. 1 1 it can be seen that all four power stages are provided with the same voltage input 438 and the same measurement reference 471. In addition, the outputs 434 of the single power stages are coupled to the same node or the same load, respectively.

Fig. 12 shows another block diagram of a possible voltage converter 500. The voltage converter 500 is based on the voltage converter 400 and provides the additional possibility to overlap the charging or discharging modes of two voltage conversion units by a

predetermined amount. To this end, the voltage converter 500, i.e. the voltage conversion units of the voltage converter 500, comprise circuitry that generates a further event to start a charging or discharging mode, respectively, prior to reaching the maximum current or voltage point.

As with Fig. 10, only the details of the first voltage conversion unit 503 will be described in detail. It is understood, that the explanations apply to the other voltage conversion units mutatis mutandis.

The voltage conversion unit 503 is based on the voltage conversion unit 403 and therefore comprises the elements as described above for voltage conversion unit 403. In addition, the voltage conversion unit 503 comprises a further comparator 561 that is provided with the measured voltage 51 1 on the positive input and with a pre peak reference voltage 560 on the negative input. The pre peak reference voltage 560 will therefore lay between the high level reference voltage 512 and the low level reference voltage 513. The farther below the high level reference voltage 512 the pre peak reference voltage 560 is chosen, the earlier the next voltage conversion unit will be activated.

The output signal from comparator 561 is provided to the arbitration logic of the next voltage conversion unit. At the same time, the output signal of the respective comparator of the last voltage conversion unit is provided to the arbitration logic 517 of the voltage conversion unit 503. In the arbitration logic 517 two additional NAND gates 578, 579 are provided. Instead of the invertor of Fig. 10, the NAND gate 578 is provided. An input of the NAND gate 578 is fed with the signal from function generator 576. The other input of NAND gate 578 is fed with the input from NAND gate 579. The NAND gate 579 is fed on the inputs with the signal from the additional comparator of the last voltage conversion unit and with the Q output of the SR Flip Flop of that last voltage conversion unit.

As can be seen in Fig. 12 another event source is now added to the arbitration logic 517 that allows activating, either in the charging mode or the discharging mode, of the voltage conversion unit 503 based on the voltage level that is sensed in the power stage of the alst voltage conversion unit.

The present invention as shown e.g. in Fig. 10 without the additional event source as shown in Fig. 12 favors coils or inductors that are optimized for operation in discontinuous mode or for operation at the transition point between continuous and discontinuous mode. The use of the pre peak event as shown in Fig. 12 in contrast widens the range of coils that may effectively be used with the present invention to coils that are optimized for continuous mode operation.

Since the output signals 564, 565 are identical to the output signals of Fig. 10, the

arrangement of Fig. 12 may be used with the power stage shown in Fig. 1 1 .

It is understood, that Figs. 10 to 12 show an arrangement with four voltage conversion units and that any other number of voltage conversion units may be used. Further, it is

understood, that the voltage conversion units are arranged in a circular arrangement and that therefore the last voltage conversion unit is coupled to the first voltage conversion unit, where e.g. the first voltage conversion unit is coupled to the second voltage conversion unit or where the second voltage conversion unit is coupled to the third voltage conversion unit.

Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations exist. It should be appreciated that the exemplary embodiment or exemplary embodiments are only examples, and are not intended to limit the scope, applicability, or configuration in any way. Rather, the foregoing summary and detailed description will provide those skilled in the art with a convenient road map for implementing at least one exemplary embodiment, it being understood that various changes may be made in the function and arrangement of elements described in an exemplary embodiment without departing from the scope as set forth in the appended claims and their legal equivalents. Generally, this application is intended to cover any adaptations or variations of the specific embodiments discussed herein. In the foregoing detailed description, various features are grouped together in one or more examples or examples for the purpose of streamlining the disclosure. It is understood that the above description is intended to be illustrative, and not restrictive. It is intended to cover all alternatives, modifications and equivalents as may be included within the scope of the invention. Many other examples will be apparent to one skilled in the art upon reviewing the above specification.

Specific nomenclature used in the foregoing specification is used to provide a thorough understanding of the invention. However, it will be apparent to one skilled in the art in light of the specification provided herein that the specific details are not required in order to practice the invention. Thus, the foregoing descriptions of specific embodiments of the present invention are presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed; obviously many modifications and variations are possible in view of the above teachings. The embodiments were chosen and described in order to best explain the principles of the invention and its practical applications, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. Throughout the specification, the terms“including” and“in which” are used as the plain-English equivalents of the respective terms“comprising” and“wherein,”

respectively. Moreover, the terms“first,”“second,” and“third,” etc., are used merely as labels, and are not intended to impose numerical requirements on or to establish a certain ranking of importance of their objects. List of reference signs

100, 200, 300, 400, 500 voltage converter

101 input port

102 output port

103, 330, 331 , 333, 403, 503 voltage conversion unit

104, 105, 304, 305, 404, 405 switching element

106 inductor

107, 307 control unit

108 power demand

109 switching signal

210 switching signal generation circuitry

21 1 , 41 1 , 51 1 measured voltage

212, 312, 412, 512 high level reference voltage

213, 313, 413, 513 low level reference voltage

214, 215, 414, 415 comparator

514, 515, 561 comparator

216, 416, 516 SR-Flip Flop

217, 417, 517 arbitration logic

218 arbitration signal

219 blocking unit

220 blocking signal

221 , 466, 467, 566, 567 delay circuit

222 high-side driver

223 low-side driver

225, 226 switching signal

334, 434 output

337, 437 ground

338, 438 voltage input

339, 439 inductor 340, 440 measurement resistor 341 enable signal source

560 pre peak reference voltage

462, 463, 464, 465 signal

562, 563, 564, 565 signal

468 level shifter

469, 470 capacitors

471 measurement reference

472, 572 AND gate

473, 474, 477, 573, 574, 577 NOR gate

475, 575, 578, 579 NAND gate

476, 576 function generator

150 power source

151 input voltage

152 output voltage

153 electric load

P1 - P5 voltage conversion unit tb blocking time S1 - S3 method steps

Claims

1. Voltage converter (100, 200, 300, 400, 500) for converting an input voltage (151 ) from a power source (150) with a first voltage level into an output voltage (152) for an electric load (153) with a second voltage level, the voltage converter (100, 200, 300, 400, 500) comprising: an input port (101 ) configured to couple the voltage converter (100, 200, 300, 400, 500) to the power source (150) and receive the input voltage (151 ), an output port (102) configured to couple the voltage converter (100, 200, 300, 400, 500) to the electric load (153) and provide an output voltage (152) to the electric load (153), a number of voltage conversion units (103, 330, 331 , 333, 403, 503) arranged in parallel between the input port (101 ) and the output port (102), each voltage conversion unit (103, 330, 331 , 333, 403, 503) comprising a number of switching elements (104, 105, 304, 305, 404, 405), a control unit (107, 307) that is coupled to the voltage conversion units (103, 330, 331 , 333, 403, 503) and that is configured to consecutively switch the voltage conversion units (103, 330, 331 , 333, 403, 503) in a charging mode or a discharging mode, wherein only one of the voltage conversion units (103, 330, 331 , 333, 403, 503) is in the actively initiated charging mode or the actively initiated discharging mode, respectively, at any point in time, and to adapt the switching frequency for consecutively switching the voltage conversion units (103, 330, 331 , 333, 403, 503) in the charging mode based on a power demand (108) of the electric load (153).

2. Voltage converter (100, 200, 300, 400, 500) according to claim 1 , wherein the control unit (107, 307) is configured to consecutively switch the voltage conversion units (103, 330, 331 , 333, 403, 503) in the charging mode if the ratio between the second voltage level and the first voltage level is less than 0,5 or equal to 0,5; and/or

wherein the control unit (107, 307) is configured to consecutively switch the voltage conversion units (103, 330, 331 , 333, 403, 503) in the discharging mode if the ratio between the second voltage level and the first voltage level is larger than 0,5.

3. Voltage converter (100, 200, 300, 400, 500) according to any one of the preceding claims, wherein the control unit (107, 307) is configured to consecutively switch the voltage conversion units (103, 330, 331 , 333, 403, 503) in a charging mode or a discharging mode at a predetermined point in time prior to the end of the charging mode or a discharging mode of the voltage conversion units (103, 330, 331 , 333, 403, 503) that is currently in the charging mode or discharging mode.

4. Voltage converter (100, 200, 300, 400, 500) according to any one of the preceding claims, wherein the control unit (107, 307) is configured to adapt the switching frequency between a predetermined minimum switching frequency for output currents starting from a first current threshold and higher and a predetermined maximum switching frequency for output currents starting from a second current threshold and lower.

5. Voltage converter (100, 200, 300, 400, 500) according to claim 4, wherein the control unit (107, 307) is configured to use the minimum switching frequency for currents below the second current threshold and provide a respective off-time in every switching cycle, wherein the control unit (107, 307) is configured to determine the duration of the off-time based on the output current.

6. Voltage converter (100, 200, 300, 400, 500) according to any one of the preceding claims, wherein the control unit (107, 307) comprises for every one of the voltage conversion units (103, 330, 331 , 333, 403, 503) a switching signal generation circuitry (210) that is configured to generate switching signals (109, 225, 226) based on a measured voltage (21 1 , 41 1 , 51 1 ) in the respective voltage conversion unit (103, 330, 331 , 333, 403, 503) and based on a low level reference voltage (213, 313, 413, 513) and based on a high level reference voltage (212, 312, 412, 512).

7. Voltage converter (100, 200, 300, 400, 500) according to claim 6, wherein the control unit (107, 307) comprises for every one of the voltage conversion units (103, 330, 331 , 333, 403, 503) an arbitration logic (217, 417, 517) that is configured to allow only one of the voltage conversion units (103, 330, 331 , 333, 403, 503) to be active simultaneously; and/or wherein the control unit (107, 307) comprises for every one of the voltage conversion units (103, 330, 331 , 333, 403, 503) a blocking unit (219) that is configured to block the other voltage conversion units (103, 330, 331 , 333, 403, 503) for the duration of the switching cycle of the respective voltage conversion unit (103, 330, 331 , 333, 403, 503).

8. Voltage converter (100, 200, 300, 400, 500) according to claim 7, wherein in each case the arbitration logic (217, 417, 517) of one of the voltage conversion units (103, 330,

331 , 333, 403, 503) is coupled to the switching signal generation circuitry (210) of the respective voltage conversion units (103, 330, 331 , 333, 403, 503) and the blocking unit (219) at least of the preceding voltage conversion unit (103, 330, 331 , 333, 403, 503) according to a switching order for the voltage conversion units (103, 330, 331 , 333, 403,

503).

9. Voltage converter (100, 200, 300, 400, 500) according to any one of the preceding claims, wherein the voltage conversion units comprise electric components of different dimensions.

10. Method for operating a voltage converter (100, 200, 300, 400, 500) for converting an input voltage (151 ) from a power source (150) with a first voltage level into an output voltage (152) for an electric load (153) with a second voltage level, the voltage converter (100, 200, 300, 400, 500) comprising a number of voltage conversion units (103, 330, 331 , 333, 403, 503) arranged in parallel between an input port (101 ) and an output port (102), each voltage conversion unit comprising a number of switching elements (104, 105, 304, 305, 404, 405), the method comprising: measuring (S1 ) a power demand (108) of the electric load (153), determining (S2) the switching frequency for consecutively switching the voltage conversion units (103, 330, 331 , 333, 403, 503) in a charging mode or a discharging mode based on the measured power demand (108), and switching (S3) the voltage conversion units (103, 330, 331 , 333, 403, 503) in the charging mode or the discharging mode, respectively according to the determined switching frequency, wherein only one of the voltage conversion units (103, 330, 331 , 333, 403, 503) is in the actively initiated charging mode or the actively initiated discharging mode, respectively, at any point in time.

1 1. Method according to claim 10, wherein the voltage conversion units (103, 330, 331 , 333, 403, 503) are consecutively switched in the charging mode if the ratio between the second voltage level and the first voltage level is less than 0,5 or equal to 0,5; and/or wherein the voltage conversion units (103, 330, 331 , 333, 403, 503) are consecutively switched in the discharging mode if the ratio between the second voltage level and the first voltage level is larger than 0,5.

12. Method according to any one of claims 10 to 1 1 , wherein switching (S3) comprises consecutively switching the voltage conversion units (103, 330, 331 , 333, 403, 503) in a charging mode or a discharging mode at a predetermined point in time prior to the end of the charging mode or a discharging mode of the voltage conversion units (103, 330, 331 , 333, 403, 503) that is currently in the charging mode or discharging mode.

13. Method according to any one of claims 10 to 12, wherein the switching frequency is determined between a predetermined minimum switching frequency for output currents of the voltage converter (100, 200, 300, 400, 500) starting from a first current threshold and higher and a predetermined maximum switching frequency for output currents of the voltage converter starting from a second current threshold and lower.

14. Method according to claim 13, wherein the minimum switching frequency is used for currents below the second current threshold and a respective off-time is provided in every switching cycle, wherein the duration of the off-time is determined based on the output current of the voltage converter.

15. Method according to any one of the preceding claims 10 to 14, wherein the switching signals (109, 225, 226) for every one of the voltage conversion units (103, 330, 331 , 333,

403, 503) are generated based on a measured voltage (21 1 , 41 1 , 51 1 ) in the respective voltage conversion unit (103, 330, 331 , 333, 403, 503) and based on a low level reference voltage (213, 313, 413, 513) and based on a high level reference voltage (212, 312, 412, 512).

16. Method according to any one of claims 10 to 15, wherein for the duration of the switching cycle of a respective one of the voltage conversion units (103, 330, 331 , 333, 403, 503) the other ones of the voltage conversion units (103, 330, 331 , 333, 403, 503) are blocked, and/or

wherein the voltage conversion units (103, 330, 331 , 333, 403, 503) are activated according to a predetermined switching order for the voltage conversion units (103, 330, 331 , 333, 403, 503), especially wherein defective voltage conversion units (103, 330, 331 , 333, 403, 503) are skipped.

17. Method according to any one of the preceding claims 10 to 16, wherein the voltage conversion units are provided with electric components of different dimensions.