WO2019118037A1 - Home agent based cache transfer acceleration scheme - Google Patents

Home agent based cache transfer acceleration scheme Download PDF

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Publication number
WO2019118037A1
WO2019118037A1 PCT/US2018/051756 US2018051756W WO2019118037A1 WO 2019118037 A1 WO2019118037 A1 WO 2019118037A1 US 2018051756 W US2018051756 W US 2018051756W WO 2019118037 A1 WO2019118037 A1 WO 2019118037A1
Authority
WO
WIPO (PCT)
Prior art keywords
probe
cache
early
entry
processing node
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2018/051756
Other languages
English (en)
French (fr)
Inventor
Amit P. Apte
Ganesh Balakrishnan
Vydhyanathan Kalyanasundharam
Kevin M. Lepak
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Priority to EP21202235.4A priority Critical patent/EP3961409B1/en
Priority to EP18783262.1A priority patent/EP3724772B1/en
Priority to JP2020532672A priority patent/JP6975335B2/ja
Priority to CN201880088010.1A priority patent/CN111656332B/zh
Priority to KR1020207020385A priority patent/KR102383040B1/ko
Publication of WO2019118037A1 publication Critical patent/WO2019118037A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G06F12/082—Associative directories
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/128—Replacement control using replacement algorithms adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G06F12/0824—Distributed directories, e.g. linked lists of caches
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G06F12/0826—Limited pointers directories; State-only directories without pointers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G06F12/0833—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means in combination with broadcast means (e.g. for invalidation or updating)
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0891—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G06F2212/1024—Latency reduction
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/50—Control mechanisms for virtual memory, cache or TLB
    • G06F2212/507—Control mechanisms for virtual memory, cache or TLB using speculative control
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/62—Details of cache specific to multiprocessor cache arrangements

Definitions

  • each CPU 305A-N is coupled to a pair of coherent slaves via a corresponding coherent master 315A-N and bus/fabric 318.
  • CPU 305 A is coupled through coherent master 315A and bus/fabric 318 to coherent slaves 320A-B.
  • Coherent slave (CS) 320A is coupled to memory controller (MC) 330A and coherent slave 320B is coupled to memory controller 330B.
  • Coherent slave 320A is coupled to probe filter (PF) 325A, with probe filter 325A including entries for memory regions that have cache lines cached in system 300 for the memory accessible through memory controller 330A.
  • PF probe filter
  • the corresponding demand probe generated after the lookup of probe filter 415 can be handled in different manners depending on the embodiment.
  • a demand probe is not launched if the early probe is to the correct target.
  • the early probe will cause the data to be retrieved from the target and returned to the requesting node.
  • a demand probe is sent to the correct target.
  • the early probe pulls data out of the cache subsystem of the target and then the data is stored in a temporary buffer. This data can be dropped if a timer expires before the demand probe arrives.
  • a demand probe is launched after the early probe, and the demand probe forwards the data pulled out of the cache subsystem to the requesting node.
  • FIG. 5 one embodiment of a method 500 for implementing an early probe mechanism is shown.
  • the steps in this embodiment and those of FIG. 6 are shown in sequential order. However, it is noted that in various embodiments of the described methods, one or more of the elements described are performed concurrently, in a different order than shown, or are omitted entirely. Other additional elements are also performed as desired. Any of the various systems or apparatuses described herein are configured to implement method 500.
  • the region targeted by the memory request is determined (block 615).
  • a new entry is allocated in the early probe cache for the region of the memory request (block 620). Any suitable eviction algorithm can be utilized to determine which entry to evict to make space for the new entry.
  • the confidence indicator field of the new entry is set to a default value and the LRU field of the new entry is initialized (block 625).
  • An ID of the node targeted by the demand probe is stored in the region owner field of the new entry in the early probe cache (block 630).

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
PCT/US2018/051756 2017-12-15 2018-09-19 Home agent based cache transfer acceleration scheme Ceased WO2019118037A1 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
EP21202235.4A EP3961409B1 (en) 2017-12-15 2018-09-19 Home agent based cache transfer acceleration scheme
EP18783262.1A EP3724772B1 (en) 2017-12-15 2018-09-19 Home agent based cache transfer acceleration scheme
JP2020532672A JP6975335B2 (ja) 2017-12-15 2018-09-19 ホームエージェントベースのキャッシュ転送アクセラレーションスキーム
CN201880088010.1A CN111656332B (zh) 2017-12-15 2018-09-19 基于本地代理的高速缓存传送加速方案
KR1020207020385A KR102383040B1 (ko) 2017-12-15 2018-09-19 홈 에이전트 기반 캐시 전송 가속 기법

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/844,215 US10776282B2 (en) 2017-12-15 2017-12-15 Home agent based cache transfer acceleration scheme
US15/844,215 2017-12-15

Publications (1)

Publication Number Publication Date
WO2019118037A1 true WO2019118037A1 (en) 2019-06-20

Family

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Application Number Title Priority Date Filing Date
PCT/US2018/051756 Ceased WO2019118037A1 (en) 2017-12-15 2018-09-19 Home agent based cache transfer acceleration scheme

Country Status (6)

Country Link
US (2) US10776282B2 (https=)
EP (2) EP3724772B1 (https=)
JP (1) JP6975335B2 (https=)
KR (1) KR102383040B1 (https=)
CN (1) CN111656332B (https=)
WO (1) WO2019118037A1 (https=)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10776282B2 (en) 2017-12-15 2020-09-15 Advanced Micro Devices, Inc. Home agent based cache transfer acceleration scheme
US11163688B2 (en) * 2019-09-24 2021-11-02 Advanced Micro Devices, Inc. System probe aware last level cache insertion bypassing
US11210248B2 (en) * 2019-12-20 2021-12-28 Advanced Micro Devices, Inc. System direct memory access engine offload
US11874783B2 (en) * 2021-12-21 2024-01-16 Advanced Micro Devices, Inc. Coherent block read fulfillment
US20250240156A1 (en) * 2022-12-23 2025-07-24 Advanced Micro Devices, Inc. Systems and methods relating to confidential computing key mixing hazard management
CN117651021B (zh) * 2024-01-25 2024-04-30 苏州萨沙迈半导体有限公司 过滤器及其控制方法和装置、电气设备
US20260086950A1 (en) * 2024-09-25 2026-03-26 Advanced Micro Devices, Inc. Systems and methods for region-based probe filter shootdown

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Also Published As

Publication number Publication date
US10776282B2 (en) 2020-09-15
US20210064545A1 (en) 2021-03-04
US20190188155A1 (en) 2019-06-20
CN111656332B (zh) 2024-08-27
EP3961409B1 (en) 2024-04-10
CN111656332A (zh) 2020-09-11
JP6975335B2 (ja) 2021-12-01
KR20200096975A (ko) 2020-08-14
EP3961409A1 (en) 2022-03-02
KR102383040B1 (ko) 2022-04-08
JP2021507371A (ja) 2021-02-22
EP3724772A1 (en) 2020-10-21
EP3724772B1 (en) 2021-10-27
US11782848B2 (en) 2023-10-10

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