WO2019117870A1 - Contoured traces in package substrates, and methods of forming same - Google Patents

Contoured traces in package substrates, and methods of forming same Download PDF

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Publication number
WO2019117870A1
WO2019117870A1 PCT/US2017/065822 US2017065822W WO2019117870A1 WO 2019117870 A1 WO2019117870 A1 WO 2019117870A1 US 2017065822 W US2017065822 W US 2017065822W WO 2019117870 A1 WO2019117870 A1 WO 2019117870A1
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WO
WIPO (PCT)
Prior art keywords
trace
subsequent
top surface
contoured
sidewall
Prior art date
Application number
PCT/US2017/065822
Other languages
French (fr)
Inventor
Hongxia Feng
Dingying Xu
Leonel R. Arana
Changhua Liu
Original Assignee
Intel Corporation
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Filing date
Publication date
Application filed by Intel Corporation filed Critical Intel Corporation
Priority to PCT/US2017/065822 priority Critical patent/WO2019117870A1/en
Publication of WO2019117870A1 publication Critical patent/WO2019117870A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Definitions

  • This disclosure relates to semiconductor device package traces, which are often referred to as first-layer copper for die packaging.
  • Figure 1 A is a cross-section elevation of a semiconductor package substrate during processing according to an embodiment
  • Figure IB is a cross-section elevation of the semiconductor package substrate depicted in Figure 1 A after further processing according to an embodiment
  • Figure 1C is a cross-section elevation of the semiconductor package substrate depicted in Figure 1 B after further processing according to an embodiment
  • Figure ID is a cross-section ele vation of the semiconductor package substrate depicted in Figure 1C after further processing according to an embodiment
  • Figure lDxc is a close-up view of a portion of the structure depicted in
  • Figure IE is a cross-section elevation of the semiconductor package substrate depicted in Figure ID after further processing according to an embodiment
  • Figure IF is a cross-section ele vation of the semiconductor package substrate depicted in Figure ID after further processing according to an embodiment
  • Figure 2 is a computer-enhanced and redrawn photomicrograph of a contoured trace during processing according to an embodiment
  • Figure 3 is a cross- section elevation of a computer re-drawn
  • Figure 3xc is a close-up view of a portion of the structure depicted in Figure 3 before stripping a patterned resist;
  • Figure 4 is a cross-section elevation of a semiconductor package according to an embodiment
  • Figure 5 is a process flow diagram according to an embodiment
  • Figure 6 is included to show an example of a higher level device application for the disclosed embodiments
  • Embedded trace spacing is achieved in the sub- 100 micron (pm) region for semiconductor package substrates where fine-pitch challenges are overcome by disclosed techniques.
  • Copper films are patterned and subtractively etched to achieve contoured traces adapted to critical-dimension (CD) limits For example, a dimensioned trace of 50 pm width is spaced apart from a likewise dimensioned trace of 50 pm width, by a space of about 50 pm, with may be referred to as 50/50.
  • the traces are sidewall-contoured because of the processing technique that achieves the, e.g. 50/50.
  • a resist configuration uses both resist composition and a tapered resist etch-entrant profile to achieve the sidewall-contoured traces and the useful dimensioned trace and trace spacing.
  • the sidewall-contoured traces are formed upon a substrate such as a semiconductor package core layer.
  • the sidewall- contoured traces are formed upon a substrate.
  • Figure 1A is a cross-section elevation of a semiconductor package substrate 101 during processing according to an embodiment.
  • a semiconductor package core 110 has been mated to a conductive film 112 such as a copper (Cu) film 1 12 that is useful for semiconductor package traces.
  • the Cu film 112 is about 15 pm thick in the Z-direction.
  • the Cu film 112 is about 20 pm thick in the Z-direction.
  • the Cu film 112 is about 25 pm thick in the Z-direction.
  • the Cu film 112 is about 30 pm thick in the Z-direction.
  • the Cu film 112 is about 35 pm thick in the Z-direction.
  • Other Z-direction thicknesses may be selected depending upon a useful desired application.
  • a resist 114 is formed on the Cu film 112.
  • the resist 1 14 is an organic material that is polymerizable after being formed upon the Cu film 112.
  • the resist 114 is a polymerizable acrylic monomer.
  • the resist 114 is an acrylic polymer of a content in the range from 30% to 80%, with organic additives such as wetting agents, curing agents, and dispersion agents in a range from 0% to 20%. In an embodiment, the resist 114 is an acrylic polymer of a content in the range from 40% to 60%. In an embodiment, the resist 114 is dissolvable in an alkaline solution for patterning and for removal. In an embodiment, the resist 114 includes a heavier component such as a silicon-containing portion. For example in an embodiment, the resist 114 includes a siloxane polymer where silicon is integrally part of the polymer.
  • the resist 114 contains a filler (not pictured) such as an inorganic filler.
  • a filler such as an inorganic filler.
  • the inorganic filler is present in a range from 70% to 30%, depending upon polymer amounts and additives.
  • the inorganic filler exhibits a particle size that is maximum 5 pm and a distribution of 87% passing (equal to or smaller) 1 pm. Of the majority of particles passing 1 prn, 99% of the particles passing 1 pm is larger than 0.01 pm.
  • the filler is an inorganic particle such as silica (Si0 2 ) or barium sulfate (BaS0 4 ).
  • inorganic particles including particle mixtures such as 70% silica and 30% bariu sulfate, each with the enumerated particle size and distribution may be used within the useful size distribution range.
  • Figure I B is a cross-section elevation of the semiconductor package substrate 101 depicted in Figure 1A after further processing according to an embodiment.
  • the semiconductor package substrate 102 has been processed to pattern the resist 114, seen in Figure 1 A to become the patterned resist 115.
  • the patterned resist 115 includes a free surface 116 and a copper-interface surface 1 18.
  • the paterned resist 1 15 also has a tapered resist etch-entrant profile 120 that is narrower at a copper- interface surface 118 than at a free surface 116. Accordingly, neither a re-entrant profile, nor a substantially vertical entrant profile is created according to an embodiment.
  • the tapered profile 120 is achieved by laser drilling a polymerized acrylic that contains inorganic filler embodiments and additive embodiments as disclosed.
  • Figure 1C is a cross-section elevation of the semiconductor package substrate 102 depicted in Figure I B after further processing according to an embodiment.
  • the semiconductor package substrate 103 is being processed by a directional wet etch that is creating a forming void 121 between two adjacently forming traces 123 and 125.
  • the forming void 121 is indicated by touching a contoured sidewall of the forming trace 125.
  • the forming void 121 can be dimensioned by width Xn-1 (a width before the final width Xn) and depth Zn-1 (the actual Z-direction thickness of the Cu film 112, minus an intermediate void depth). In some embodiments, the dimension Xn-1 is less than the intermediate depth Zn-1.
  • the wet etch achieves an anisotropic profile where Zn-1 is greater than Xn-1, until the wet etch has broken through the Cu film 112 to isolate the forming traces 123 and 125.
  • the void between the traces 124 and 126 may be referred to as a tall void.
  • Etching according to disclosed embodiments results in the trace sidewall having a profile that is characteristic of anisotropic wet etching.
  • Figure ID is a cross-section elevation of the semiconductor package substrate 103 depicted in Figure 1C after further processing according to an embodiment.
  • the directional wet etch on the semiconductor package substrate 104 has been completed and the forming void 121 depicted in Figure ID to become the void 122 that is touching the contoured sidewall of the trace 126 that was the forming trace 125 depicted in Figure 1C.
  • the void 122 is dimensioned by width Xn and depth Zn which is the Cu film 112 thickness.
  • Figure 2 is a computer-enhanced and redrawn photomicrograph 200 of a contoured trace during processing according to an embodiment.
  • a directional wet is creating a forming void 221 within a Cu film 212, and between two forming contoured traces 223 and 225.
  • the directional wet etch is not completed as illustrated, as a portion of the Cu film 212 still bridges between the two forming contoured traces 223 and 225.
  • a patterned resist 215 has formed an angle a with respect to the copper- interface surface 118.
  • the angle a is acute in every embodiment such that neither a re-entrant profile (obtuse angle a) not a straight profile (right angle) is formed.
  • the forming void 221 can be dimensioned by width Xn-1 (a width before the final width X) and depth Zn-1, which is less than the final Z- height of the forming contoured traces 223 and 225.
  • a copper film 212 has a thickness of 25 pm. Etching is done through a tapered-profile patterned resist 215, and a previous resolution of 50 pm (and a resolution/thicknes ratio of 2), is changed to a resolution of 43 pm and a resolution/thickness ratio of 1.72. In an embodiment, a copper film 212 has a thickness of about 32-35 pm. Etching is done through a tapered- profile patterned resist 215, and a previous resolution of 67.5 pm (and a resolution/thickness ratio of 1 93), is changed to a resolution of 59 pm and a resolution/thickness ratio of 1.84. In an embodiment, a 25 pm thick Cu film is etched to achieve a 40/40 resolution and trace spacing. In an embodiment, a 35 pm thick Cu film is etched to achieve a 50/50 resolution and trace spacing.
  • Figure IE is a cross-section elevation of the semiconductor package substrate 104 depicted in Figure I D after further processing according to an embodiment.
  • the directional wet etch on the semiconductor package substrate 105 has been completed to create useful-dimension adjacent traces upon the core 110 and the void 121 depicted in Figure ID is now the void 122.
  • the void 122 also has opened the Cu film 112 to expose the core 110 and thereby to create discrete adjacent contoured traces, e.g. 124 and 126, respectively.
  • the void 122 is dimensioned by width Xn and depth Zn, which is the Cu film 112 thickness.
  • an interlayer dielectric layer (ILD) 128 is applied to both fill the void 122 between the first trace 124 and the subsequent trace 126, and it is also applied to a useful height to facilitate formation of a filled via (see Figure IF).
  • Figure IF is a cross-section elevation of the semiconductor package substrate 105 depicted in Figure IE after further processing according to an embodiment.
  • the semiconductor package 106 has been processed with a first level of filled vias.
  • the I LD has been patterned and via filled to form corresponding filled vias 130 and 132 on the semiconductor package substrate 106 to respective contoured traces 124 and 126.
  • Figure 3 is a cross- section elevation of a computer re-drawn
  • the semiconductor package substrate 300 includes a semiconductor package core 310 that was mated to a conductive film 312 such as a Cu film 312, and that has been patterned to form a first contoured trace 234 and a subsequent contoured trace 326 that is adjacent to the first contoured trace 324.
  • Each contoured trace exhibits a neck minimum 350 (indicated on the first trace 324) at a Z-direction position that is closer to an upper surface than to the surface that contacts the package core 310.
  • Processing on the semiconductor package substrate 300 is similar to the process depicted in Figures 1A through IF such that the contoured traces 324 and 326 have been formed by subtractive etching through a tapered-entrant profile resist such as the patterned resist 115 depicted in at least figures IB 1C, ID, and Figure 2.
  • contoured first trace 324 may be referred to as IF
  • the trace layer indicated at 332 may be referred to as 2F
  • the trace 336 depicted contacted by the filled via 334 may be referred to as 3F.
  • Other trace le vels may be built above the contoured traces 324 and 326, and the next trace may be referred to as 4F.
  • Figure lDxc is a close-up view of a portion of the structure depicted in Figure ID after stripping the patterned resist 115.
  • the first contoured trace 124 exhibits a characteristic profile on the trace sidewall.
  • the characteristic profile exhibits a neck minimum that is indicated by a bisecting line 150.
  • the characteristic profile neck minimum 150 is located close to the trace top surface 124t than to the trace bottom surface 124b.
  • a first curvilinearity 129 is found between the trace top surface 1241 and the neck minimum level 150.
  • a second curviiinearity 127 is found between the trace bottom surface 124b and the neck minimum level 150.
  • the first curviiinearity 129 is greater than the second curviiinearity 127.
  • the combined curved portions 127 and 129 make up the curved sidewall of the trace 124.
  • the neck minimum 150 is formed below the top surface 124t such that at least a portion of an hourglass shape is detected.
  • Curviiinearity is quantified by measuring the arc length of the shortest arc, divided by the straight line across the beginning and end of the arc. For the longer arc, curviiinearity is quantified by the arc length of the longer arc, divided by the same straight line from the shortest arc.
  • Figure 3xc is a close-up view of a portion of the structure depicted in Figure 3 before stripping a patterned resist 315.
  • the first contoured trace 324 exhibits a characteristic profile on the trace sidewall.
  • the characteristic profile exhibits a neck minimum that is indicated by a bisecting line 350.
  • the characteristic profile neck minimum is located close to the trace top surface 324t than to the trace bottom surface 324b.
  • a first curviiinearity 329 is found between the trace top surface 324t and the neck minimum level 350.
  • a second curviiinearity 327 is found between the trace bottom surface 324b and the neck minimum level 350.
  • the first curviiinearity 329 is greater than the second curviiinearity 327.
  • the combined curved portions 327 and 329 make up the curved sidewall of the trace 324.
  • a directional wet etch allows an etching effect to penetrate deep (in the Z- direction) at a faster rate than incidental lateral etching (in the X-direction). It is observed under directional wet-etch processing conditions that an etch endpoint and usefully rapid stopping of the etch-chemistry presence is observed once the Cu foil 312 has been breached.
  • the trace height which is always the etch depth Zn, is greater than the trace width Xn as measured where the trace 324 necks at 350
  • spacing between contoured traces is substantially the same as the trace thickness at the necking feature 350. Accordingly w'here the trace thickness is Xn, the spacing is ⁇ Xn within about 96% or smaller deviation. This deviation is measured by dividing the trace thickness Xn with the inter-trace spacing -Xn.
  • Figure 4 is a cross-section elevation of a semiconductor package 400 according to an embodiment.
  • the semiconductor package substrate 400 includes a semiconductor package core 410 that was mated to a conductive film 412 such as a Cu film 412, and that has been patterned to form a first contoured trace 434 and a subsequent contoured trace 426 that is adjacent to the first contoured trace 424.
  • a semiconductor package core 410 that was mated to a conductive film 412 such as a Cu film 412, and that has been patterned to form a first contoured trace 434 and a subsequent contoured trace 426 that is adjacent to the first contoured trace 424.
  • Processing on the semiconductor package 400 is similar ⁇ to the process depicted in Figures 1A through IF such that the contoured traces 424 and 426 have been formed by subtractive etching through a tapered-entrant profile resist such as the patterned resist 115 depicted in at least figures IB, 1C, ID, and Figure 2.
  • contoured first trace 424 may be referred to as IF
  • the trace layer indicated at 432 may be referred to as 2F
  • the trace 436 may be referred to as 3F.
  • Other trace levels may be built above the contoured traces 424 and 426, and the next trace may be referred to as 4F.
  • the semiconductor package 400 includes a semiconductive device package 452 according to an embodiment.
  • the semiconductor package 400 is bumped 454 for further attachment such as to a motherboard.
  • a motherboard 40 or some other mounting substrate 40 is provided to attach the semiconductor device package 452 and the contoured-trace containing semiconductor package substrate.
  • an outer shell 411 provides at least one of physical and electrically insu!ative protection for the contoured-trace containing semiconductor package substrate.
  • Figure 5 is a process flow diagram 500 according to an embodiment.
  • the process includes forming a patterned resist above a copper film that is on a semiconductor package substrate.
  • the process includes directionally wet etching through the patterned resist to form a tall void in the copper film, and a first trace and an adjacent subsequent trace.
  • the traces exhibit contoured sidewalls with a neck minimum.
  • the process includes removing the patterned resist.
  • the process includes forming an ILD layer in the void and above the first and subsequent traces.
  • the process includes filling a via into the ILD that contacts the top of the contoured first trace.
  • the process includes completing a semiconductor package that contains the first and subsequent traces.
  • the process includes assembling the contoured-trace containing semiconductor package substrate to a computing system.
  • a computing system 600 includes, but is not limited to, a desktop computer.
  • a system 600 includes, but is not limited to a laptop computer.
  • a system 600 includes, but is not limited to a netbook.
  • a system 600 includes but is not limited to a tablet.
  • a system 600 includes, but is not limited to a notebook computer.
  • a system 600 includes, but is not limited to a personal digital assistant (PDA).
  • PDA personal digital assistant
  • a system 600 includes, but is not limited to a server.
  • the processor 610 has one or more processing cores 612 and 612N, where 612N represents the Nth processor core inside processor 610 where N is a positive integer.
  • the electronic device system 600 using a contoured-trace embodiment that includes multiple processors including 610 and 605 where the processor 605 has logic similar or identical to the logic of the processor 610.
  • the processing core 612 includes, but is not limited to, pre-fetch logic to fetch instructions, decode logic to decode the instructions, execution logic to execute instructions and the like.
  • the processor 610 has a cache memory 616 to cache at least one of instructions and data for the MAA apparatus in the system 600.
  • the cache memory 616 may be organized into a hierarchal structure including one or more levels of cache memory.
  • the processor 610 includes a memory controller 614, which is operable to perform functions that enable the processor 610 to access and communicate with memory 630 that includes at least one of a volatile memory 632 and a non-volatile memory 634.
  • the processor 610 is coupled with memory 630 and chipset 620.
  • the processor 610 may also be coupled to a wireless antenna 678 to communicate with any device configured to at least one of transmit and receive wireless signals.
  • the wireless antenna interface 678 operates in accordance with, but is not limited to, the IEEE 802.11 standard and its related family, Home Plug AV (HPAY), Ultra Wide Band (UWB), Bluetooth, WiMax, or any form of wireless communication protocol.
  • the volatile memory 632 includes, but is not limited to, Synchronous Dynamic Random Access Memory (SDRAM), Dynamic Random Access Memory (DRAM), RAMBUS Dynamic Random Access Memory (RDRAM), and/or any other type of random access memory device.
  • the non-volatile memory 634 includes, but is not limited to, flash memory, phase change memory (PCM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), or any other type of non-volatile memory device.
  • the memory 630 stores information and instructions to be executed by the processor 610. In an embodiment, the memory 630 may also store temporary variables or other intermediate information while the processor 610 is executing instructions. In the illustrated embodiment, the chipset 620 connects with processor 610 via Point- to- Point (PtP or P-P) interfaces 617 and 622.
  • PtP Point- to- Point
  • the chipset 620 is operable to communicate with the processor 610, 605N, the display device 640, and other devices 672, 676, 674, 660, 662, 664, 666, 677, etc.
  • the chipset 620 may also be coupled to a wireless antenna 678 to communicate with any device configured to at least do one of transmit and receive wireless signals.
  • the chipset 620 connects to the display device 640 via the interface 626.
  • the display 640 may be, for example, a liquid crystal display (LCD), a plasma display, cathode ray tube (CRT) display, or any other form of visual display device.
  • the processor 610 and the chipset 620 are merged into a contoured-trace package in a system.
  • the chipset 620 connects to one or more buses 650 and 655 that interconnect various elements 674, 660, 662, 664, and 666. Buses 650 and 655 may be interconnected together via a bus bridge 672 such as at least one contoured-trace package embodiment.
  • the chipset 620 via interface 624, couples with a non volatile memory 660, a mass storage device(s) 662, a keyboard/mouse 664, a network interface 666, smart TV 676, and the consumer electronics 677, etc.
  • the mass storage device 662 includes, but is not limited to, a solid state drive, a hard disk drive, a universal serial bus flash memory drive, or any other form of computer data storage medium.
  • the net work interface 666 is implemented by any type of well- known network interface standard including, but not limited to, an Ethernet interface, a universal serial bus (USB) interface, a Peripheral Component Interconnect (PCI) Express interface, a wireless interface and/or any other suitable type of interface.
  • the wireless interface operates in accordance with, but is not limited to, the IEEE 802.11 standard and its related family. Home Plug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMax, or any form of wireless communication protocol.
  • modules shown in Figure 6 are depicted as separate blocks within the contoured-trace package embodiment in a computing system 600, the functions performed by some of these blocks may be integrated within a single semiconductor circuit or may be implemented using two or more separate integrated circuits.
  • cache memory 616 is depicted as a separate block within processor 610, cache memory 616 (or selected aspects of 616) can be incorporated into the processor core 612.
  • the computing system 600 may have a broadcasting structure interface such as for affixing the contoured-trace package to a cellular tower.
  • Example 1 is a semiconductor device package, comprising: a package substrate supporting a contoured trace layer, wherein a trace within the contoured trace layer includes: a trace top surface at a trace height; a trace bottom surface disposed on the package substrate; and a trace sidewall communicating between the trace bottom surface and the trace top surface, wherein the trace sidewall includes a characteristic profile, wherein the characteristic profile exhibits a neck minimum located closer to the trace top surface than to the trace bottom surface.
  • Example 2 the subject matter of Example 1 optionally includes wherein the trace sidewall characteristic profile is characteristic of anisotropic wet etching.
  • Example 3 the subject matter of any one or more of Examples 1-2 optionally include wherein the characteristic profile exhibits a first curvilinearity between the trace top surface and the neck minimum and a second curvilinearity between the neck minimum and the trace bottom surface.
  • Example 4 the subject matter of any one or more of Examples 1-3 optionally include wherein the characteristic profile exhibits a first curvilinearity between the trace top surface and the neck minimum and a second curvilinearity between the neck minimum and the trace bottom surface, and wherein the first curvilinearity is greater than the second curvilinearity.
  • Example 5 the subject matter of any one or more of Examples 1-4 optionally include wherein the trace is a first trace further including a subsequent trace disposed adjacent the first trace, wherein the subsequent trace includes: a subsequent trace top surface at the trace height; a subsequent trace bottom surface disposed on the package substrate; and a subsequent trace sidewall communicating between the subsequent trace bottom surface and the subsequent trace top surface, wherein the subsequent trace sidewall includes a characteristic profile, wherein the characteristic profile exhibits a neck minimum located closer to the subsequent trace top surface than to the subsequent trace bottom surface.
  • Example 6 the subject matter of any one or more of Examples 1-5 optionally include wherein the trace is a first trace, further including a subsequent trace disposed adjacent the first trace wherein the subsequent trace includes: a subsequent trace top surface at the trace height; a subsequent trace bottom surface disposed on the package substrate; a subsequent trace sidewall communicating between the subsequent trace bottom surface and the subsequent trace top surface, wherein the subsequent trace sidewall includes a characteristic profile, wherein the characteristic profile exhibits a neck minimum located closer to the subsequent trace top surface than to the subsequent trace bottom surface; and wherein the first trace and subsequent trace are spaced apart by a distance that matches each trace width at the neck minimum within about 96 percent.
  • Example 8 the subject matter of any one or more of Examples 1-7 optionally include wherein the trace is a first trace, further including a subsequent trace disposed adjacent the first trace, wherein the subsequent trace includes: a subsequent trace top surface at the trace height; a subsequent trace bottom surface disposed on the package substrate; a subsequent trace sidewall communicating between the subsequent trace bottom surface and the subsequent trace top surface, wherein the subsequent trace sidewall includes a characteristic profile, wherein the characteristic profile exhibits a neck minimum located closer to the subsequent trace top surface than to the subsequent trace bottom surface; and wherein a tall void is formed by the first trace and the adjacent subsequent trace by respective adjacent trace sidewalls.
  • Example 9 the subject matter of any one or more of Examples 1-8 optionally include wherein the package substrate is a package core, further including: a through-core via that contacts the trace, wherein the trace is a first trace, further including a subsequent trace disposed adjacent the first trace, wherein the subsequent trace includes: a subsequent trace top surface at the trace height; a subsequent trace bottom surface disposed on the package substrate; a subsequent trace sidewall communicating between the subsequent trace bottom surface and the subsequent trace top surface, wherein the subsequent trace sidewall includes a characteristic profile, wherein the characteristic profile exhibits a neck minimum located closer to the subsequent trace top surface than to the subsequent trace bottom surface; and wherein the first trace and subsequent trace are spaced apart by a distance that matches each trace width at the neck minimum within about 96 percent.
  • Example 10 is a semiconductor device package, comprising: a package substrate supporting a contoured trace layer, wherein a first trace and a subsequent trace are configured within the contoured trace layer, wherein the first trace is adjacent the subsequent trace, and wherein each trace includes: a trace top surface at a trace height; a trace bottom surface disposed on the package substrate; and a contoured trace sidewall communicating between the trace bottom surface and the trace top surface, wherein the first trace width and the subsequent trace width are substantially equal, and wherein adjacent contoured trace sidewalls of the first trace and the subsequent trace, form a tall void.
  • Example 11 the subject matter of Example 10 optionally include the first and subsequent contoured traces are spaced apart by about 40, are about 40 micrometer thick at the narrowest dimension, and wherein each trace height is about 25 micrometer.
  • Example 12 the subject matter of any one or more of Examples 10-11 optionally include the first and subsequent contoured traces are spaced apart by about 40 micrometer thick at the narrowest dimension, and wherein each trace height is about 35 micrometer.
  • Example 13 the subject matter of any one or more of Examples 10-12 optionally include wherein each contoured trace sidewall characteristic profile is characteristic of anisotropic wet etching.
  • Example 14 is a process of forming a trace for a semiconductor package, comprising: patterning a resist disposed above a copper film, the resist including: an organic film; and a filler dispersed in the organic film; wherein the resist includes a free surface and a copper-interface surface, wherein the resist is patterned with a tapered profile, and wherein the tapered profile is narrower at the copper-interface surface than at the tree surface; wet etching through the tapered profile under conditions to contour the copper film to create a trace sidewall between the free surface and the copper- surface, and wherein the trace sidewall includes a characteristic profile, wherein the characteristic profile exhibits a neck minimum located closer to the trace top surface than to the trace bottom surface; and removing the resist.
  • Example 15 the subject matter of Example 14 optionally includes the trace is a first trace, and wherein the process forms a subsequent trace adjacent the first trace including a characteristic trace sidewall contour, further including wherein wet etching results in a first trace thickness and a subsequent trace thickness measured at each neck minimum, and wherein the first trace and the subsequent trace are spaced apart by a distance at least 96 percent of each trace thickness
  • Example 16 the subject matter of any one or more of Examples 14—15 optionally include wherein the polymer is an acrylic material including an inorganic filler, and wherein etching through the patterned resist include etching through a tapered entrant profile of an acute angle.
  • Example 17 the subject matter of any one or more of Examples 14-16 optionally include the polymer is present in a range from 30% to 80%, and wherein the inorganic filler is present in a range from 70% to 20%.
  • Example 18 the subject matter of any one or more of Examples 14-17 optionally include the polymer is present in a range from 30% to 80%, wherein the inorganic filler is present in a range from 70% to 20% and wherein the inorganic filler has a particle size distribution of maximum 5 micrometer, 87% passing 1 micrometer, and 99 % of the particles passing 1 micrometer are larger than 0.01 micrometer.
  • Example 19 the subject matter of any one or more of Examples 14-18 optionally include the polymer is an acrylic in a range from 30% to 80%, and wherein the inorganic filler is one of an oxide and a sulphate of a metal, and present in a range from 70% to 20%%.
  • Example 20 the subject matter of any one or more of Examples 14-19 optionally include the polymer is a siloxane acrylic in a range from 30% to 80%, and wherein the inorganic filler is selected from silica and barium sulphate and present in a range from 70% to 20%.
  • the polymer is a siloxane acrylic in a range from 30% to 80%
  • the inorganic filler is selected from silica and barium sulphate and present in a range from 70% to 20%.
  • Example 21 the subject matter of any one or more of Examples 14-20 optionally include removing the patterned resist; forming an interlayer dielectric (ILD) layer above the first trace; and filling a via in the ILD to contact the first trace.
  • ILD interlayer dielectric
  • Example 22 is a computing system, comprising: a semiconduetive device; a semiconductor device package comprising: a package substrate supporting a contoured trace layer, including a first contoured trace and a subsequent contoured trace adjacent the first contoured trace, wherein each contoured trace includes: a trace top surface at a trace height; a trace bottom surface disposed on the package substrate; and a trace sidewall communicating between the trace bottom surface and the trace top surface, wherein the trace sidewall includes a characteristic profile, wherein the characteristic profile exhibits a neck minimum located closer to the trace top surface than to the trace bottom surface; wherein a tall void is formed by the first trace and the adjacent subsequent trace by respective adjacent trace sidewalls; and an outer shell supporting the semiconductor device package.
  • Example 23 the subject matter of Example 22 optionally includes wherein the characteristic profile exhibits a first curvilinearity between the trace top surface and the neck minimum and a second curvilinearity between the neck minimum and the trace bottom surface.
  • Example 24 the subject matter of any one or more of Examples 22-23 optionally include wherein the characteristic profile exhibits a first curvilinearity between the trace top surface and the neck minimum and a second curvilinearity between the neck minimum and the trace bottom surface, and wherein the first curvilinearity is greater than the second curvilinearity.
  • present inventors also contemplate examples in which only those elements shown or described are provided. Moreover, the present inventors also contemplate examples using any combination or permutation of those elements shown or described (or one or more aspects thereof), either with respect to a particular ⁇ example (or one or more aspects thereof), or with respect to other examples (or one or more aspects thereof) shown or described herein.
  • the terms“a” or“an” are used, as is common in patent documents, to include one or more than one, independent of any other instances or usages of“at least one” or“one or more.”
  • the term“or” is used to refer to a nonexclusive or, such that“A or B” includes“A but not B,”“B but not A,” and“A and B,” unless otherwise indicated.
  • Method examples described herein can be machine or computer- implemented at least in part. Some examples can include a computer-readable medium or machine-readable medium encoded with instructions operable to configure an electrical device to perform methods as described in the above examples.
  • An implementation of such methods can include code, such as microcode, assembly language code, a higher- level language code or the like. Such code can include computer readable instructions for performing various methods. The code may form portions of computer program products. Further in an example, the code can be tangibly stored on one or more volatile, non- transitory, or non-volatile tangible computer-readable media, such as during execution or at other times.
  • tangible computer-readable media can include, but are not limited to, hard disks, removable magnetic disks removable optical disks (e.g., compact disks and digital video disks), magnetic cassettes, memory cards or sticks, random access memories (RAMs), read only memories (ROMs), and the like.
  • hard disks removable magnetic disks removable optical disks (e.g., compact disks and digital video disks), magnetic cassettes, memory cards or sticks, random access memories (RAMs), read only memories (ROMs), and the like.

Abstract

A contoured trace is formed by a directional wet etch through a copper film that is on a semiconductor package substrate. The contoured trace exhibits a curvilinear sidewall with a neck minimum above a height middle. The directional wet etch process provides a fine-pitch spacing such as a 40 micrometer trace thickness and about 40 micrometer spacing between adjacent contoured traces for a 25 micrometer thick copper film from which the contoured trace has been wet subtractively etched.

Description

CONTOURED TRACES IN PACKAGE SUBSTRATES,
AND METHODS OF FORMING SAME
FIELD
This disclosure relates to semiconductor device package traces, which are often referred to as first-layer copper for die packaging.
BACKGROUND
Semiconductive device miniaturization includes challenges for fine-pitch and usefully defined traces. BRIEF DESCRIPTION OF THE DRAWINGS
Disclosed embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings where like reference numerals may refer to similar elements, in which:
Figure 1 A is a cross-section elevation of a semiconductor package substrate during processing according to an embodiment;
Figure IB is a cross-section elevation of the semiconductor package substrate depicted in Figure 1 A after further processing according to an embodiment;
Figure 1C is a cross-section elevation of the semiconductor package substrate depicted in Figure 1 B after further processing according to an embodiment;
Figure ID is a cross-section ele vation of the semiconductor package substrate depicted in Figure 1C after further processing according to an embodiment;
Figure lDxc is a close-up view of a portion of the structure depicted in
Figure ID after stripping the patterned resist;
Figure IE is a cross-section elevation of the semiconductor package substrate depicted in Figure ID after further processing according to an embodiment; Figure IF is a cross-section ele vation of the semiconductor package substrate depicted in Figure ID after further processing according to an embodiment;
Figure 2 is a computer-enhanced and redrawn photomicrograph of a contoured trace during processing according to an embodiment;
Figure 3 is a cross- section elevation of a computer re-drawn
photomicrograph of a semiconductor package 300 according to an embodiment;
Figure 3xc is a close-up view of a portion of the structure depicted in Figure 3 before stripping a patterned resist;
Figure 4 is a cross-section elevation of a semiconductor package according to an embodiment;
Figure 5 is a process flow diagram according to an embodiment; and
Figure 6 is included to show an example of a higher level device application for the disclosed embodiments
DETAILED DESCRIPTION
Embedded trace spacing is achieved in the sub- 100 micron (pm) region for semiconductor package substrates where fine-pitch challenges are overcome by disclosed techniques. Copper films are patterned and subtractively etched to achieve contoured traces adapted to critical-dimension (CD) limits For example, a dimensioned trace of 50 pm width is spaced apart from a likewise dimensioned trace of 50 pm width, by a space of about 50 pm, with may be referred to as 50/50. The traces are sidewall-contoured because of the processing technique that achieves the, e.g. 50/50.
A resist configuration uses both resist composition and a tapered resist etch-entrant profile to achieve the sidewall-contoured traces and the useful dimensioned trace and trace spacing. In an embodiment, the sidewall-contoured traces are formed upon a substrate such as a semiconductor package core layer. Hereinafter and unless explicitly called out as a core layer, the sidewall- contoured traces are formed upon a substrate.
Figure 1A is a cross-section elevation of a semiconductor package substrate 101 during processing according to an embodiment. The
semiconductor package substrate 101 is illustrated in simplified detail to further highlight disclosed processes and structures. A semiconductor package core 110 has been mated to a conductive film 112 such as a copper (Cu) film 1 12 that is useful for semiconductor package traces. In an embodiment, the Cu film 112 is about 15 pm thick in the Z-direction. In an embodiment, the Cu film 112 is about 20 pm thick in the Z-direction. In an embodiment, the Cu film 112 is about 25 pm thick in the Z-direction. In an embodiment, the Cu film 112 is about 30 pm thick in the Z-direction. In an embodiment, the Cu film 112 is about 35 pm thick in the Z-direction. Other Z-direction thicknesses may be selected depending upon a useful desired application.
A resist 114 is formed on the Cu film 112. In an embodiment, the resist 1 14 is an organic material that is polymerizable after being formed upon the Cu film 112. In an embodiment, the resist 114 is a polymerizable acrylic monomer.
In an embodiment, the resist 114 is an acrylic polymer of a content in the range from 30% to 80%, with organic additives such as wetting agents, curing agents, and dispersion agents in a range from 0% to 20%. In an embodiment, the resist 114 is an acrylic polymer of a content in the range from 40% to 60%. In an embodiment, the resist 114 is dissolvable in an alkaline solution for patterning and for removal. In an embodiment, the resist 114 includes a heavier component such as a silicon-containing portion. For example in an embodiment, the resist 114 includes a siloxane polymer where silicon is integrally part of the polymer.
In an embodiment, the resist 114 contains a filler (not pictured) such as an inorganic filler. In an embodiment, the inorganic filler is present in a range from 70% to 30%, depending upon polymer amounts and additives. In an embodiment, the inorganic filler exhibits a particle size that is maximum 5 pm and a distribution of 87% passing (equal to or smaller) 1 pm. Of the majority of particles passing 1 prn, 99% of the particles passing 1 pm is larger than 0.01 pm.
In an embodiment, the filler is an inorganic particle such as silica (Si02) or barium sulfate (BaS04). Other inorganic particles, including particle mixtures such as 70% silica and 30% bariu sulfate, each with the enumerated particle size and distribution may be used within the useful size distribution range.
Figure I B is a cross-section elevation of the semiconductor package substrate 101 depicted in Figure 1A after further processing according to an embodiment. The semiconductor package substrate 102 has been processed to pattern the resist 114, seen in Figure 1 A to become the patterned resist 115. The patterned resist 115 includes a free surface 116 and a copper-interface surface 1 18. The paterned resist 1 15 also has a tapered resist etch-entrant profile 120 that is narrower at a copper- interface surface 118 than at a free surface 116. Accordingly, neither a re-entrant profile, nor a substantially vertical entrant profile is created according to an embodiment. In an embodiment, the tapered profile 120 is achieved by laser drilling a polymerized acrylic that contains inorganic filler embodiments and additive embodiments as disclosed.
Figure 1C is a cross-section elevation of the semiconductor package substrate 102 depicted in Figure I B after further processing according to an embodiment. The semiconductor package substrate 103 is being processed by a directional wet etch that is creating a forming void 121 between two adjacently forming traces 123 and 125. The forming void 121 is indicated by touching a contoured sidewall of the forming trace 125. As illustrated, the forming void 121 can be dimensioned by width Xn-1 (a width before the final width Xn) and depth Zn-1 (the actual Z-direction thickness of the Cu film 112, minus an intermediate void depth). In some embodiments, the dimension Xn-1 is less than the intermediate depth Zn-1. Accordingly and due to the tapered resist etch- entrant profile 120, the composition of the resist 115, both as to the polymer chemistry and filler composition and particle distribution, the wet etch achieves an anisotropic profile where Zn-1 is greater than Xn-1, until the wet etch has broken through the Cu film 112 to isolate the forming traces 123 and 125.
Where Zn is greater than Xn as achieved by several disclosed embodiments, the void between the traces 124 and 126 may be referred to as a tall void. Etching according to disclosed embodiments results in the trace sidewall having a profile that is characteristic of anisotropic wet etching.
Figure ID is a cross-section elevation of the semiconductor package substrate 103 depicted in Figure 1C after further processing according to an embodiment. The directional wet etch on the semiconductor package substrate 104 has been completed and the forming void 121 depicted in Figure ID to become the void 122 that is touching the contoured sidewall of the trace 126 that was the forming trace 125 depicted in Figure 1C. As illustrated, the void 122 is dimensioned by width Xn and depth Zn which is the Cu film 112 thickness.
Figure 2 is a computer-enhanced and redrawn photomicrograph 200 of a contoured trace during processing according to an embodiment. A directional wet is creating a forming void 221 within a Cu film 212, and between two forming contoured traces 223 and 225. The directional wet etch is not completed as illustrated, as a portion of the Cu film 212 still bridges between the two forming contoured traces 223 and 225.
A patterned resist 215 has formed an angle a with respect to the copper- interface surface 118. The angle a is acute in every embodiment such that neither a re-entrant profile (obtuse angle a) not a straight profile (right angle) is formed. As illustrated the forming void 221 can be dimensioned by width Xn-1 (a width before the final width X) and depth Zn-1, which is less than the final Z- height of the forming contoured traces 223 and 225.
In an embodiment, a copper film 212 has a thickness of 25 pm. Etching is done through a tapered-profile patterned resist 215, and a previous resolution of 50 pm (and a resolution/thicknes ratio of 2), is changed to a resolution of 43 pm and a resolution/thickness ratio of 1.72. In an embodiment, a copper film 212 has a thickness of about 32-35 pm. Etching is done through a tapered- profile patterned resist 215, and a previous resolution of 67.5 pm (and a resolution/thickness ratio of 1 93), is changed to a resolution of 59 pm and a resolution/thickness ratio of 1.84. In an embodiment, a 25 pm thick Cu film is etched to achieve a 40/40 resolution and trace spacing. In an embodiment, a 35 pm thick Cu film is etched to achieve a 50/50 resolution and trace spacing.
Figure IE is a cross-section elevation of the semiconductor package substrate 104 depicted in Figure I D after further processing according to an embodiment. The directional wet etch on the semiconductor package substrate 105 has been completed to create useful-dimension adjacent traces upon the core 110 and the void 121 depicted in Figure ID is now the void 122. The void 122 also has opened the Cu film 112 to expose the core 110 and thereby to create discrete adjacent contoured traces, e.g. 124 and 126, respectively. As illustrated, the void 122 is dimensioned by width Xn and depth Zn, which is the Cu film 112 thickness.
After a wet rinse process to remove the patterned resist 115 depicted in Figure ID, an interlayer dielectric layer (ILD) 128 is applied to both fill the void 122 between the first trace 124 and the subsequent trace 126, and it is also applied to a useful height to facilitate formation of a filled via (see Figure IF).
Figure IF is a cross-section elevation of the semiconductor package substrate 105 depicted in Figure IE after further processing according to an embodiment. The semiconductor package 106 has been processed with a first level of filled vias. After the directional wet etch and the ILD 128 application, the I LD has been patterned and via filled to form corresponding filled vias 130 and 132 on the semiconductor package substrate 106 to respective contoured traces 124 and 126.
Figure 3 is a cross- section elevation of a computer re-drawn
photomicrograph of a semiconductor package 300 according to an embodiment.
The semiconductor package substrate 300 includes a semiconductor package core 310 that was mated to a conductive film 312 such as a Cu film 312, and that has been patterned to form a first contoured trace 234 and a subsequent contoured trace 326 that is adjacent to the first contoured trace 324. Each contoured trace exhibits a neck minimum 350 (indicated on the first trace 324) at a Z-direction position that is closer to an upper surface than to the surface that contacts the package core 310.
Processing on the semiconductor package substrate 300 is similar to the process depicted in Figures 1A through IF such that the contoured traces 324 and 326 have been formed by subtractive etching through a tapered-entrant profile resist such as the patterned resist 115 depicted in at least figures IB 1C, ID, and Figure 2.
Further processing is indicated by the presence of an ILD 328 that has filled the void 322 as well as provided a depth above the first contoured trace 324 to form a filled via 330. Other processing is indicated by two layers of traces. Where the contoured first trace 324 may be referred to as IF, the trace layer indicated at 332 may be referred to as 2F, and the trace 336 depicted contacted by the filled via 334 may be referred to as 3F. Other trace le vels may be built above the contoured traces 324 and 326, and the next trace may be referred to as 4F.
Figure lDxc is a close-up view of a portion of the structure depicted in Figure ID after stripping the patterned resist 115. The first contoured trace 124 exhibits a characteristic profile on the trace sidewall. The characteristic profile exhibits a neck minimum that is indicated by a bisecting line 150. The characteristic profile neck minimum 150 is located close to the trace top surface 124t than to the trace bottom surface 124b. Further to define the contoured sidewall of the first trace 124, a first curvilinearity 129 is found between the trace top surface 1241 and the neck minimum level 150. Further, a second curviiinearity 127 is found between the trace bottom surface 124b and the neck minimum level 150. In an embodiment, the first curviiinearity 129 is greater than the second curviiinearity 127. The combined curved portions 127 and 129 make up the curved sidewall of the trace 124. In most disclosed etching conditions, the neck minimum 150 is formed below the top surface 124t such that at least a portion of an hourglass shape is detected. Curviiinearity is quantified by measuring the arc length of the shortest arc, divided by the straight line across the beginning and end of the arc. For the longer arc, curviiinearity is quantified by the arc length of the longer arc, divided by the same straight line from the shortest arc.
Although no specific processing theory is asserted it is observed that a directional wet etch allows an etching effect to penetrate deep (in the Z- direction) at a faster rate than incidental lateral etching (in the X-direction). It is observed under directional wet-etch processing conditions, that an etch endpoint and usefully rapid stopping of the etch-chemistry presence is observed once the Cu foil 112 has been breached. In a useful wet-etch endpoint processing embodiment, once the Cu foil 112 has been breached to create the first trace 124, the trace height (which is always the etch depth Zn, is greater than the trace width Xn as measured where the trace 124 necks at 150.
Figure 3xc is a close-up view of a portion of the structure depicted in Figure 3 before stripping a patterned resist 315. The first contoured trace 324 exhibits a characteristic profile on the trace sidewall. The characteristic profile exhibits a neck minimum that is indicated by a bisecting line 350. The characteristic profile neck minimum is located close to the trace top surface 324t than to the trace bottom surface 324b. Further to define the contoured sidewall of the first trace 324 a first curviiinearity 329 is found between the trace top surface 324t and the neck minimum level 350. Further, a second curviiinearity 327 is found between the trace bottom surface 324b and the neck minimum level 350. In an embodiment, the first curviiinearity 329 is greater than the second curviiinearity 327. The combined curved portions 327 and 329 make up the curved sidewall of the trace 324.
Although no specific processing theory is asserted, it is observed that a directional wet etch allows an etching effect to penetrate deep (in the Z- direction) at a faster rate than incidental lateral etching (in the X-direction). It is observed under directional wet-etch processing conditions that an etch endpoint and usefully rapid stopping of the etch-chemistry presence is observed once the Cu foil 312 has been breached. In a useful wet-etch endpoint processing embodiment, once the Cu foil 312 has been breached to create the first trace 324, the trace height (which is always the etch depth Zn, is greater than the trace width Xn as measured where the trace 324 necks at 350
As illustrated, spacing between contoured traces is substantially the same as the trace thickness at the necking feature 350. Accordingly w'here the trace thickness is Xn, the spacing is ~Xn within about 96% or smaller deviation. This deviation is measured by dividing the trace thickness Xn with the inter-trace spacing -Xn.
Figure 4 is a cross-section elevation of a semiconductor package 400 according to an embodiment.
The semiconductor package substrate 400 includes a semiconductor package core 410 that was mated to a conductive film 412 such as a Cu film 412, and that has been patterned to form a first contoured trace 434 and a subsequent contoured trace 426 that is adjacent to the first contoured trace 424.
Processing on the semiconductor package 400 is similar· to the process depicted in Figures 1A through IF such that the contoured traces 424 and 426 have been formed by subtractive etching through a tapered-entrant profile resist such as the patterned resist 115 depicted in at least figures IB, 1C, ID, and Figure 2.
Further processing is indicated by the presence of an ILD 428 that has filled a void 428 as well as provided a depth above the first contoured trace 424 to form a filled via 430. Other processing is indicated by two layers of traces. Where the contoured first trace 424 may be referred to as IF, the trace layer indicated at 432 may be referred to as 2F, and the trace 436 may be referred to as 3F. Other trace levels may be built above the contoured traces 424 and 426, and the next trace may be referred to as 4F.
As illustrated, the semiconductor package 400 includes a semiconductive device package 452 according to an embodiment. In an embodiment, the semiconductor package 400 is bumped 454 for further attachment such as to a motherboard. In an embodiment, a motherboard 40 or some other mounting substrate 40 is provided to attach the semiconductor device package 452 and the contoured-trace containing semiconductor package substrate. In an embodiment, an outer shell 411 provides at least one of physical and electrically insu!ative protection for the contoured-trace containing semiconductor package substrate.
Figure 5 is a process flow diagram 500 according to an embodiment.
At 510, the process includes forming a patterned resist above a copper film that is on a semiconductor package substrate.
At 520, the process includes directionally wet etching through the patterned resist to form a tall void in the copper film, and a first trace and an adjacent subsequent trace. The traces exhibit contoured sidewalls with a neck minimum.
At 530, the process includes removing the patterned resist.
At 540, the process includes forming an ILD layer in the void and above the first and subsequent traces.
At 550, the process includes filling a via into the ILD that contacts the top of the contoured first trace.
At 560, the process includes completing a semiconductor package that contains the first and subsequent traces.
At 570, the process includes assembling the contoured-trace containing semiconductor package substrate to a computing system.
Figure 6 is included to show an example of a higher-level device application for the disclosed embodiments. The contoured-trace embodiments are part of an apparatus that may be found in several parts of a computing system. In an embodiment, a computing system 600 includes, but is not limited to, a desktop computer. In an embodiment, a system 600 includes, but is not limited to a laptop computer. In an embodiment, a system 600 includes, but is not limited to a netbook. In an embodiment a system 600 includes but is not limited to a tablet. In an embodiment, a system 600 includes, but is not limited to a notebook computer. In an embodiment, a system 600 includes, but is not limited to a personal digital assistant (PDA). In an embodiment, a system 600 includes, but is not limited to a server. In an embodiment, a system 600 includes, but is not limited to a workstation. In an embodiment, a system 600 includes, but is not limited to a cellular telephone. In an embodiment, a system 600 includes, but is not limited to a mobile computing device. In an embodiment, a system 600 includes, but is not limited to a smart phone. In an embodiment, a system 600 includes, but is not limited to an internet appliance. Other types of computing devices may he configured with the microelectronic device that includes contoured-trace embodiments.
In an embodiment, the processor 610 has one or more processing cores 612 and 612N, where 612N represents the Nth processor core inside processor 610 where N is a positive integer. In an embodiment, the electronic device system 600 using a contoured-trace embodiment that includes multiple processors including 610 and 605 where the processor 605 has logic similar or identical to the logic of the processor 610. In an embodiment, the processing core 612 includes, but is not limited to, pre-fetch logic to fetch instructions, decode logic to decode the instructions, execution logic to execute instructions and the like. In an embodiment, the processor 610 has a cache memory 616 to cache at least one of instructions and data for the MAA apparatus in the system 600. The cache memory 616 may be organized into a hierarchal structure including one or more levels of cache memory.
In an embodiment, the processor 610 includes a memory controller 614, which is operable to perform functions that enable the processor 610 to access and communicate with memory 630 that includes at least one of a volatile memory 632 and a non-volatile memory 634. In an embodiment, the processor 610 is coupled with memory 630 and chipset 620. The processor 610 may also be coupled to a wireless antenna 678 to communicate with any device configured to at least one of transmit and receive wireless signals. In an embodiment, the wireless antenna interface 678 operates in accordance with, but is not limited to, the IEEE 802.11 standard and its related family, Home Plug AV (HPAY), Ultra Wide Band (UWB), Bluetooth, WiMax, or any form of wireless communication protocol.
In an embodiment, the volatile memory 632 includes, but is not limited to, Synchronous Dynamic Random Access Memory (SDRAM), Dynamic Random Access Memory (DRAM), RAMBUS Dynamic Random Access Memory (RDRAM), and/or any other type of random access memory device. The non-volatile memory 634 includes, but is not limited to, flash memory, phase change memory (PCM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), or any other type of non-volatile memory device.
The memory 630 stores information and instructions to be executed by the processor 610. In an embodiment, the memory 630 may also store temporary variables or other intermediate information while the processor 610 is executing instructions. In the illustrated embodiment, the chipset 620 connects with processor 610 via Point- to- Point (PtP or P-P) interfaces 617 and 622.
Either of these PtP embodiments may be achieved using a contoured-trace package embodiment as set forth in this disclosure. The chipset 620 enables the processor 610 to connect to other elements in the contoured-trace package embodiments in a system 600. In an embodiment, interfaces 617 and 622 operate in accordance with a PtP communication protocol such as the Intel® QuickPath Interconnect (QPI) or the like. In other embodiments, a different interconnect may be used.
In an embodiment, the chipset 620 is operable to communicate with the processor 610, 605N, the display device 640, and other devices 672, 676, 674, 660, 662, 664, 666, 677, etc. The chipset 620 may also be coupled to a wireless antenna 678 to communicate with any device configured to at least do one of transmit and receive wireless signals.
The chipset 620 connects to the display device 640 via the interface 626. The display 640 may be, for example, a liquid crystal display (LCD), a plasma display, cathode ray tube (CRT) display, or any other form of visual display device. In and embodiment, the processor 610 and the chipset 620 are merged into a contoured-trace package in a system. Additionally, the chipset 620 connects to one or more buses 650 and 655 that interconnect various elements 674, 660, 662, 664, and 666. Buses 650 and 655 may be interconnected together via a bus bridge 672 such as at least one contoured-trace package embodiment.
In one embodiment, the chipset 620, via interface 624, couples with a non volatile memory 660, a mass storage device(s) 662, a keyboard/mouse 664, a network interface 666, smart TV 676, and the consumer electronics 677, etc.
In an embodiment, the mass storage device 662 includes, but is not limited to, a solid state drive, a hard disk drive, a universal serial bus flash memory drive, or any other form of computer data storage medium. In one embodiment, the net work interface 666 is implemented by any type of well- known network interface standard including, but not limited to, an Ethernet interface, a universal serial bus (USB) interface, a Peripheral Component Interconnect (PCI) Express interface, a wireless interface and/or any other suitable type of interface. In one embodiment, the wireless interface operates in accordance with, but is not limited to, the IEEE 802.11 standard and its related family. Home Plug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMax, or any form of wireless communication protocol.
While the modules shown in Figure 6 are depicted as separate blocks within the contoured-trace package embodiment in a computing system 600, the functions performed by some of these blocks may be integrated within a single semiconductor circuit or may be implemented using two or more separate integrated circuits. For example, although cache memory 616 is depicted as a separate block within processor 610, cache memory 616 (or selected aspects of 616) can be incorporated into the processor core 612.
Where useful, the computing system 600 may have a broadcasting structure interface such as for affixing the contoured-trace package to a cellular tower.
To illustrate the contoured-trace package embodiments and methods disclosed herein, a non- limiting list of examples is provided herein:
Example 1 is a semiconductor device package, comprising: a package substrate supporting a contoured trace layer, wherein a trace within the contoured trace layer includes: a trace top surface at a trace height; a trace bottom surface disposed on the package substrate; and a trace sidewall communicating between the trace bottom surface and the trace top surface, wherein the trace sidewall includes a characteristic profile, wherein the characteristic profile exhibits a neck minimum located closer to the trace top surface than to the trace bottom surface.
In Example 2, the subject matter of Example 1 optionally includes wherein the trace sidewall characteristic profile is characteristic of anisotropic wet etching.
In Example 3, the subject matter of any one or more of Examples 1-2 optionally include wherein the characteristic profile exhibits a first curvilinearity between the trace top surface and the neck minimum and a second curvilinearity between the neck minimum and the trace bottom surface. In Example 4, the subject matter of any one or more of Examples 1-3 optionally include wherein the characteristic profile exhibits a first curvilinearity between the trace top surface and the neck minimum and a second curvilinearity between the neck minimum and the trace bottom surface, and wherein the first curvilinearity is greater than the second curvilinearity.
In Example 5, the subject matter of any one or more of Examples 1-4 optionally include wherein the trace is a first trace further including a subsequent trace disposed adjacent the first trace, wherein the subsequent trace includes: a subsequent trace top surface at the trace height; a subsequent trace bottom surface disposed on the package substrate; and a subsequent trace sidewall communicating between the subsequent trace bottom surface and the subsequent trace top surface, wherein the subsequent trace sidewall includes a characteristic profile, wherein the characteristic profile exhibits a neck minimum located closer to the subsequent trace top surface than to the subsequent trace bottom surface.
In Example 6 the subject matter of any one or more of Examples 1-5 optionally include wherein the trace is a first trace, further including a subsequent trace disposed adjacent the first trace wherein the subsequent trace includes: a subsequent trace top surface at the trace height; a subsequent trace bottom surface disposed on the package substrate; a subsequent trace sidewall communicating between the subsequent trace bottom surface and the subsequent trace top surface, wherein the subsequent trace sidewall includes a characteristic profile, wherein the characteristic profile exhibits a neck minimum located closer to the subsequent trace top surface than to the subsequent trace bottom surface; and wherein the first trace and subsequent trace are spaced apart by a distance that matches each trace width at the neck minimum within about 96 percent.
In Example 7, the subject matter of any one or more of Examples 1-6 optionally include wherein the trace is a first trace, further including a subsequent trace disposed adjacent the first trace, wherein the subsequent trace includes: a subsequent trace top surface at the trace height; a subsequent trace bottom surface disposed on the package substrate; a subsequent trace sidewall communicating between the subsequent trace bottom surface and the subsequent trace top surface, wherein the subsequent trace sidewall includes a characteristic profile, wherein the characteristic profile exhibits a neck minimum located closer to the subsequent trace top surface than to the subsequent trace bottom surface; and wherein the first trace and subsequent trace are spaced apart by a distance that matches each trace width at the neck minimum within about 96 percent, and wherein distance and the neck minimum are selected from the group consisting of 30micrometer (pm) (30/30), 40/40 and 50/50.
In Example 8, the subject matter of any one or more of Examples 1-7 optionally include wherein the trace is a first trace, further including a subsequent trace disposed adjacent the first trace, wherein the subsequent trace includes: a subsequent trace top surface at the trace height; a subsequent trace bottom surface disposed on the package substrate; a subsequent trace sidewall communicating between the subsequent trace bottom surface and the subsequent trace top surface, wherein the subsequent trace sidewall includes a characteristic profile, wherein the characteristic profile exhibits a neck minimum located closer to the subsequent trace top surface than to the subsequent trace bottom surface; and wherein a tall void is formed by the first trace and the adjacent subsequent trace by respective adjacent trace sidewalls.
In Example 9, the subject matter of any one or more of Examples 1-8 optionally include wherein the package substrate is a package core, further including: a through-core via that contacts the trace, wherein the trace is a first trace, further including a subsequent trace disposed adjacent the first trace, wherein the subsequent trace includes: a subsequent trace top surface at the trace height; a subsequent trace bottom surface disposed on the package substrate; a subsequent trace sidewall communicating between the subsequent trace bottom surface and the subsequent trace top surface, wherein the subsequent trace sidewall includes a characteristic profile, wherein the characteristic profile exhibits a neck minimum located closer to the subsequent trace top surface than to the subsequent trace bottom surface; and wherein the first trace and subsequent trace are spaced apart by a distance that matches each trace width at the neck minimum within about 96 percent.
Example 10 is a semiconductor device package, comprising: a package substrate supporting a contoured trace layer, wherein a first trace and a subsequent trace are configured within the contoured trace layer, wherein the first trace is adjacent the subsequent trace, and wherein each trace includes: a trace top surface at a trace height; a trace bottom surface disposed on the package substrate; and a contoured trace sidewall communicating between the trace bottom surface and the trace top surface, wherein the first trace width and the subsequent trace width are substantially equal, and wherein adjacent contoured trace sidewalls of the first trace and the subsequent trace, form a tall void.
In Example 11, the subject matter of Example 10 optionally include the first and subsequent contoured traces are spaced apart by about 40, are about 40 micrometer thick at the narrowest dimension, and wherein each trace height is about 25 micrometer.
In Example 12, the subject matter of any one or more of Examples 10-11 optionally include the first and subsequent contoured traces are spaced apart by about 40 micrometer thick at the narrowest dimension, and wherein each trace height is about 35 micrometer.
In Example 13, the subject matter of any one or more of Examples 10-12 optionally include wherein each contoured trace sidewall characteristic profile is characteristic of anisotropic wet etching.
Example 14 is a process of forming a trace for a semiconductor package, comprising: patterning a resist disposed above a copper film, the resist including: an organic film; and a filler dispersed in the organic film; wherein the resist includes a free surface and a copper-interface surface, wherein the resist is patterned with a tapered profile, and wherein the tapered profile is narrower at the copper-interface surface than at the tree surface; wet etching through the tapered profile under conditions to contour the copper film to create a trace sidewall between the free surface and the copper- surface, and wherein the trace sidewall includes a characteristic profile, wherein the characteristic profile exhibits a neck minimum located closer to the trace top surface than to the trace bottom surface; and removing the resist.
In Example 15, the subject matter of Example 14 optionally includes the trace is a first trace, and wherein the process forms a subsequent trace adjacent the first trace including a characteristic trace sidewall contour, further including wherein wet etching results in a first trace thickness and a subsequent trace thickness measured at each neck minimum, and wherein the first trace and the subsequent trace are spaced apart by a distance at least 96 percent of each trace thickness
In Example 16, the subject matter of any one or more of Examples 14—15 optionally include wherein the polymer is an acrylic material including an inorganic filler, and wherein etching through the patterned resist include etching through a tapered entrant profile of an acute angle.
In Example 17, the subject matter of any one or more of Examples 14-16 optionally include the polymer is present in a range from 30% to 80%, and wherein the inorganic filler is present in a range from 70% to 20%.
In Example 18, the subject matter of any one or more of Examples 14-17 optionally include the polymer is present in a range from 30% to 80%, wherein the inorganic filler is present in a range from 70% to 20% and wherein the inorganic filler has a particle size distribution of maximum 5 micrometer, 87% passing 1 micrometer, and 99 % of the particles passing 1 micrometer are larger than 0.01 micrometer.
In Example 19, the subject matter of any one or more of Examples 14-18 optionally include the polymer is an acrylic in a range from 30% to 80%, and wherein the inorganic filler is one of an oxide and a sulphate of a metal, and present in a range from 70% to 20%%.
In Example, 20, the subject matter of any one or more of Examples 14-19 optionally include the polymer is a siloxane acrylic in a range from 30% to 80%, and wherein the inorganic filler is selected from silica and barium sulphate and present in a range from 70% to 20%.
In Example 21, the subject matter of any one or more of Examples 14-20 optionally include removing the patterned resist; forming an interlayer dielectric (ILD) layer above the first trace; and filling a via in the ILD to contact the first trace.
Example 22 is a computing system, comprising: a semiconduetive device; a semiconductor device package comprising: a package substrate supporting a contoured trace layer, including a first contoured trace and a subsequent contoured trace adjacent the first contoured trace, wherein each contoured trace includes: a trace top surface at a trace height; a trace bottom surface disposed on the package substrate; and a trace sidewall communicating between the trace bottom surface and the trace top surface, wherein the trace sidewall includes a characteristic profile, wherein the characteristic profile exhibits a neck minimum located closer to the trace top surface than to the trace bottom surface; wherein a tall void is formed by the first trace and the adjacent subsequent trace by respective adjacent trace sidewalls; and an outer shell supporting the semiconductor device package.
In Example 23, the subject matter of Example 22 optionally includes wherein the characteristic profile exhibits a first curvilinearity between the trace top surface and the neck minimum and a second curvilinearity between the neck minimum and the trace bottom surface.
In Example 24, the subject matter of any one or more of Examples 22-23 optionally include wherein the characteristic profile exhibits a first curvilinearity between the trace top surface and the neck minimum and a second curvilinearity between the neck minimum and the trace bottom surface, and wherein the first curvilinearity is greater than the second curvilinearity.
The above detailed description includes references to the accompanying drawings, which form a part of the detailed description. The drawings showy by way of illustration, specific embodiments in which the invention can be practiced. These embodiments are also referred to herein as“examples.” Such examples can include elements in addition to those shown or described.
However, the present inventors also contemplate examples in which only those elements shown or described are provided. Moreover, the present inventors also contemplate examples using any combination or permutation of those elements shown or described (or one or more aspects thereof), either with respect to a particular· example (or one or more aspects thereof), or with respect to other examples (or one or more aspects thereof) shown or described herein.
In the event of inconsistent usages between this document and any documents so incorporated by reference the usage in this document controls.
In this document, the terms“a” or“an” are used, as is common in patent documents, to include one or more than one, independent of any other instances or usages of“at least one” or“one or more.” In this document, the term“or” is used to refer to a nonexclusive or, such that“A or B” includes“A but not B,”“B but not A,” and“A and B,” unless otherwise indicated. In this document, the terms“including” and“in which” are used as the plain-English equivalents of the respective terms“comprising” and“wherein.” Also, in the following claims, the terms“including” and“comprising” are open-ended, that is, a system, device, article, composition, formulation, or process that includes elements in addition to those listed after such a term in a clai are still deemed to fall within the scope of that claim. Moreover, in the following claims, the terms“first,” “second,” and“third,” etc. are used merely as labels and are not intended to impose numerical requirements on their objects.
Method examples described herein can be machine or computer- implemented at least in part. Some examples can include a computer-readable medium or machine-readable medium encoded with instructions operable to configure an electrical device to perform methods as described in the above examples. An implementation of such methods can include code, such as microcode, assembly language code, a higher- level language code or the like. Such code can include computer readable instructions for performing various methods. The code may form portions of computer program products. Further in an example, the code can be tangibly stored on one or more volatile, non- transitory, or non-volatile tangible computer-readable media, such as during execution or at other times. Examples of these tangible computer-readable media can include, but are not limited to, hard disks, removable magnetic disks removable optical disks (e.g., compact disks and digital video disks), magnetic cassettes, memory cards or sticks, random access memories (RAMs), read only memories (ROMs), and the like.
The above description is intended to be illustrative, and not restrictive. For example, the above-described examples (or one or more aspects thereof) may be used in combination with each other. Other embodiments can be used, such as by one of ordinary skill in the art upon reviewing the above description. The Abstract is provided to comply with 37 C.F.R. § 1.72(b), to allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Also, in the above Detailed Description, various features may be grouped together to streamline the disclosure. This should not be interpreted as intending that an unclaimed disclosed feature is essential to any claim. Rather, inventive subject matter may lie in less than all features of a particular· disclosed embodiment. Thus, the following claims are hereby incorporated into the Detailed Description as examples or embodiments with each claim standing on its own as a separate embodiment, and it is contemplated that such embodiments can be combined with each other in various
combinations or permutations. The scope of the disclosed embodiments should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

Claims

LA semiconductor device package, comprising:
a package substrate supporting a contoured trace layer, wherein a trace within the contoured trace layer includes:
a trace top surface at a trace height;
a trace bottom surface disposed on the package substrate; and
a trace sidewall communicating between the trace bottom surface and the trace top surface, wherein the trace sidewall includes a characteristic profile, wherein the characteristic profile exhibits a neck minimum located closer to the trace top surface than to the trace bottom surface.
2 The semiconductor device package of claim 1, wherein the trace sidewall characteristic profi le is characteristic of anisotropic wet etching.
3. The semiconductor device package of claim 1, wherein the characteristic profile exhibits a first curvilinearity between the trace top surface and the neck minimum and a second curvilinearity between the neck minimum and the trace bottom surface.
4. The semiconductor device package of claim 1, wherein the characteristic profile exhibits a first curvilinearity between the trace top surface and the neck minimum and a second curvilinearity between the neck minimum and the trace bottom surface, and wherein the first curvilinearity is greater than the second curvilinearity.
5. The semiconductor device package of clai 1, wherein the trace is a first trace, further including a subsequent trace disposed adjacent the first trace, wherein the subsequent trace includes:
a subsequent trace top surface at the trace height;
a subsequent trace bottom surface disposed on the package substrate; and a subsequent trace sidewall communicating between the subsequent trace bottom surface and the subsequent trace top surface, wherein the subsequent trace sidewall includes a characteristic profile, wherein the characteristic profile exhibits a neck minimum located closer to the subsequent trace top surface than to the subsequent trace bottom surface.
6. The semiconductor device package of claim 1, wherein the trace is a first trace, further including a subsequent trace disposed adjacent the first trace, wherein the subsequent trace includes:
a subsequent trace top surface at the trace height;
a subsequent trace bottom surface disposed on the package substrate;
a subsequent trace sidewall communicating between the subsequent trace bottom surface and the subsequent trace top surface, wherein the subsequent trace sidewall includes a characteristic profile, wherein the characteristic profile exhibits a neck minimum located closer to the subsequent trace top surface than to the subsequent trace bottom surface; and
wherein the first trace and subsequent trace are spaced apart by a distance that matches each trace width at the neck minimum within about 96 percent.
7. The semiconductor device package of claim 1, wherein the trace is a first trace, further including a subsequent trace disposed adjacent the first trace, wherein the subsequent trace includes:
a subsequent trace top surface at the trace height;
a subsequent trace bottom surface disposed on the package substrate;
a subsequent trace sidewall communicating between the subsequent trace bottom surface and the subsequent trace top surface, wherein the subsequent trace sidewall includes a characteristic profile, wherein the characteristic profile exhibits a neck minimum located closer to the subsequent trace top surface than to the subsequent trace bottom surface; and
wherein the first trace and subsequent trace are spaced apart by a distance that matches each trace width at the neck minimum within about 96 percent, and wherein distance and the neck minimum are selected from the group consisting of 30 micrometer (pm) (30/30), 40/40 and 50/50.
8. The semiconductor device package of claim 1, wherein the trace is a first trace, further including a subsequent trace disposed adjacent the first trace, wherein the subsequent trace includes:
a subsequent trace top surface at the trace height;
a subsequent trace bottom surface disposed on the package substrate;
a subsequent trace sidewall communicating between the subsequent trace bottom surface and the subsequent trace top surface, wherein the subsequent trace sidewall includes a characteristic profile, wherein the characteristic profile exhibits a neck minimum located closer to the subsequent trace top surface than to the subsequent trace bottom surface; and
wherein a tall void is formed by the first trace and the adjacent subsequent trace by respective adjacent trace sidewalls
9. The semiconductor device package of claim 1, wherein the package substrate is a package core, further including:
a through-core via that contacts the trace, wherein the trace is a first trace, further including a subsequent trace disposed adjacent the first trace, wherein the subsequent trace includes:
a subsequent trace top surface at the trace height;
a subsequent trace bottom surface disposed on the package substrate;
a subsequent trace sidewall communicating between the subsequent trace bottom surface and the subsequent trace top surface, wherein the subsequent trace sidewall includes a characteristic profile, wherein the characteristic profile exhibits a neck minimum located closer to the subsequent trace top surface than to the subsequent trace bottom surface; and
wherein the first trace and subsequent trace are spaced apart by a distance that matches each trace width at the neck minimum within about 96 percent.
10. A semiconductor device package, comprising:
a package substrate supporting a contoured trace layer, wherein a first trace and a subsequent trace are configured within the contoured trace layer, wherein the first trace is adjacent the subsequent trace, and wherein each trace includes:
a trace top surface at a trace height;
a trace bottom surface disposed on the package substrate; and
a contoured trace sidewall communicating between the trace bottom surface and the trace top surface, wherein the first trace width and the subsequent trace width are substantially equal, and wherein adjacent contoured trace sidewalls of the first trace and the subsequent trace, form a tall void.
1 1. The semiconductor device package of claim 10, wherein the first and
subsequent contoured traces are spaced apart by about 40 micrometer, are about 40 micrometer thick at a narrowest dimension, and wherein each trace height is about 25 micrometer.
12. The semiconductor device package of claim 10, wherein the first and
subsequent contoured traces are spaced apart by about 50 micrometer, are about 50 micrometer thick at a narrowest dimension, and wherein each trace height is about 35 micrometer.
13. The semiconductor device package of claim 10, wherein each contoured trace sidewall characteristic profile is characteristic of anisotropic wet etching.
14. A process of forming a trace for a semiconductor package, comprising: patterning a resist disposed above a copper film, the resist including:
an organic film; and
a filler dispersed in the organic film;
wherein the resist includes a free surface and a copper-interface surface, wherein the resist is patterned with a tapered profi le, and wherein the tapered profile is narrower at the copper- interface surface than at the free surface;
wet etching through the tapered profile under conditions to contour the copper film to create a trace sidewall between the free surface and the copper- surface, and wherein the trace sidewall includes a characteristic profile, wherein the characteristic profile exhibits a neck minimum located closer to the trace top surface than to the trace bottom surface; and removing the resist.
15. The process of claim 14, wherein the trace is a first trace, and wherein the process forms a subsequent trace adjacent the first trace including a characteristic trace sidewall contour, further including wherein wet etching results in a first trace thickness and a subsequent trace thickness measured at each neck minimum, and wherein the first trace and the subsequent trace are spaced apart by a distance at least 96 percent of each trace thickness.
16. The process of claim 14, wherein the polymer is an acrylic material
including an inorganic filler, and wherein etching through the patterned resist include etching through a tapered entrant profile of an acute angle.
17. The process of claim 14, wherein the polymer is present in a range from 30% to 80%, and wherein the inorganic filler is present in a range from 70% to 20%.
18. The process of claim 14, wherein the polymer is present in a range from 309¾ to 80%, wherein the inorganic filler is present in a range from 70% to 20% and wherein the inorganic filler has a particle size distribution of maximum 5 micrometer, 87% passing 1 micrometer, and 99 % of the particles passing 1 micrometer are larger than 0.01 micrometer.
19. The process of claim 14, wherein the polymer is an acrylic in a range from 30% to 80%, and wherein the inorganic filler is one of an oxide and a sulphate of a metal, and present in a range from 70% to 20%.
20. The process of claim 14, wherein the polymer is a siloxane acrylic in a range from 30% to 80%, and wherein the inorganic filler is selected from silica and barium sulphate and present in a range from 70% to 20%.
21. The process of claim 14, further including:
removing the patterned resist;
forming an interlayer dielectric (ILD) layer above the first trace; and
filling a via in the ILD to contact the first trace.
22. A computing system, comprising:
a semiconduetive device;
a semiconductor device package, comprising:
a package substrate supporting a contoured trace layer, including a first contoured trace and a subsequent contoured trace adjacent the first contoured trace, wherein each contoured trace includes:
a trace top surface at a trace height;
a trace bottom surface disposed on the package substrate; and
a trace sidewall communicating between the trace bottom surface and the trace top surface, wherein the trace sidewall includes a characteristic profile wherein the characteristic profile exhibits a neck minimum located closer to the trace top surface than to the trace bottom surface; wherein a tall void is formed by the first trace and the adjacent subsequent trace by respective adjacent trace sidewalls; and
an outer shell supporting the semiconductor device package
23. The computing system of claim 22, wherein the characteristic profile exhibits a first curvilinearity between the trace top surface and the neck minimum and a second curvilinearity between the neck minimum and the trace bottom surface.
24. The computing system of claim 22, wherein the characteristic profile exhibits a first curvilinearity between the trace top surface and the neck minimum and a second curvilinearity between the neck minimum and the trace bottom surface, and wherein the first curvilinearity is greater than the second curvilinearity.
PCT/US2017/065822 2017-12-12 2017-12-12 Contoured traces in package substrates, and methods of forming same WO2019117870A1 (en)

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CN104137257A (en) * 2011-12-21 2014-11-05 英特尔公司 Packaged semiconductor die and cte-engineering die pair
KR20150069376A (en) * 2013-12-13 2015-06-23 삼성전기주식회사 Resist film and methods of forming a pattern
US20150318235A1 (en) * 2014-05-05 2015-11-05 Advanced Semiconductor Engineering, Inc. Substrate, semiconductor package thereof and process of making same
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Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001250884A (en) * 2000-03-08 2001-09-14 Sanyo Electric Co Ltd Manufacturing method of circuit device
CN104137257A (en) * 2011-12-21 2014-11-05 英特尔公司 Packaged semiconductor die and cte-engineering die pair
KR20150069376A (en) * 2013-12-13 2015-06-23 삼성전기주식회사 Resist film and methods of forming a pattern
US20150318235A1 (en) * 2014-05-05 2015-11-05 Advanced Semiconductor Engineering, Inc. Substrate, semiconductor package thereof and process of making same
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