WO2019114088A1

WO2019114088A1 - Novel superconducting cyclotron tuning system

Info

Publication number: WO2019114088A1
Application number: PCT/CN2018/073257
Authority: WO
Inventors: 宋云涛; 陈根; 彭振; 赵燕平; 陈永华; 杨庆喜
Original assignee: 合肥中科离子医学技术装备有限公司
Priority date: 2017-12-13
Filing date: 2018-01-18
Publication date: 2019-06-20
Also published as: JP2020514941A; CN107864548A; JP6670010B1; CN107864548B

Abstract

Disclosed is a novel superconducting cyclotron tuning system, wherein an analog IQ phase discrimination module is used for modulating the sine (I) and cosine (Q) of a phase difference between an LO signal and an RF signal, and using same as an input signal of an analog IQ phase discrimination calibration module; and the analog IQ phase discrimination calibration module is used for calibrating a measurement error of the analog IQ phase discrimination module and detecting the analog IQ phase discrimination module in real time, and automatically shuts off when the calibration of the analog IQ phase discrimination module is completed, avoiding the influence of the calibration module on an analog IQ phase discrimination result. In the system of the present invention, using the technique of combining an analog signal processing system and a digital signal processing system increases the precision of system tuning and the noise resistance performance, and reduces the delay time of a feedback system increased due to signal processing; and the analog IQ phase discrimination calibration module carried in the tuning system itself improves the self-adjustment capability of the analog IQ phase discrimination module and expands the range of application thereof.

Description

A Novel Superconducting Cyclotron Tuning System

Technical field

The invention belongs to the technical field of cyclotrons, and in particular relates to a novel superconducting cyclotron tuning system.

Background technique

Superconducting cyclotrons are increasingly used in medical fields such as PET (positron emission tomography) diagnosis, isotope production, and proton therapy because of their unique compact characteristics and low power consumption. Among them, the resonant cavity is one of the important components of the superconducting cyclotron, and the resonant cavity mainly provides an electric field for ion acceleration. The working state of the resonant cavity directly affects the beam quality. However, due to electromagnetic heating effect, mechanical vibration, beam load effect and other factors during the operation of the resonant cavity, the resonant cavity cannot be stably operated under the specified working state, resulting in excessive power reflection of the power source, damaging the transmission system and power. Source, and more importantly, the detuning of the cavity results in a decrease in beam quality and beam loss. In order to solve such problems, the low-level control system of the superconducting cyclotron is generally divided into two categories, one of which uses a self-excited method to drive the resonant cavity. Such a method can well solve the problem of cavity detuning, but such a system The principle and debugging are more complicated, and are generally applied to a control system of a high quality factor resonant cavity, such as a superconducting resonant cavity. There is also a class that uses its excitation drive method to drive the resonant cavity. This kind of system principle is relatively simple, and has been widely used in the control system of the accelerator cavity. The disadvantage is that when the cavity is detuned, the amplitude and phase are coupled, so In order to decouple the amplitude and phase loops, it is necessary to ensure that the cavity operates stably in a resonant state. In the accelerator low-level control system, the tuning system loop is generally used to ensure that the cavity is stabilized in real time in the working state to ensure better beam quality. The analog tuning system was first used in the tuning system control of the accelerator cavity. However, due to the non-ideal factors of the analog device, the system has DC offset, phase imbalance and amplitude imbalance, so the pure analog tuning system is difficult. Meet high control needs and precision. As DSP and FPGA have been widely used in control systems, more and more tuning control systems use digital signal processing systems. Digital signal processing systems can solve the problems of analog systems well, but the delay of digital systems. In the tuning control system with high control precision and low delay, the digital system can not meet the requirements, so there is a semi-digital and semi-analog tuning system, which can reduce the delay of the digital system and overcome the analog system. It is vulnerable to noise and other shortcomings. The existing semi-digital and semi-analog tuning system can greatly improve the DC offset and phase imbalance of the analog tuning system, as well as the amplitude imbalance, to a certain extent, but the low delay and resistance of the superconducting cyclotron Due to the demanding requirements of noise, high precision, wide dynamic range, the traditional calibration method can not meet the requirements.

Summary of the invention

The object of the present invention is to provide a novel superconducting cyclotron tuning system, which combines the advantages of an analog signal and a digital signal organically, wherein the novel IQ tuning module can be used for both a signal modulation module of a superconducting cyclotron and a signal modulation module. The tuning system of the noise-resistant, low-latency superconducting cavity can also be used for mobile broadband communication base stations.

The object of the present invention can be achieved by the following technical solutions:

A novel superconducting cyclotron tuning system, comprising a servo motor, a cavity ignition detection device, an analog IQ phase discrimination calibration module, an analog IQ phase discrimination module, a power divider, and a dual directional coupler;

The analog IQ phase detector module is configured to modulate the sine I and cosine Q of the phase difference between the LO signal and the RF signal, and the analog IQ phase detector module provides an I signal and a Q signal feedback signal for the analog IQ phase discrimination calibration module as the analog IQ. The input signal of the phase calibration module;

The analog IQ phase detecting module comprises a split power splitter, a hybrid splitter, a first adjustable phase shifter, a second adjustable phase shifter, a first double balanced mixer, and a second double balanced mixer. , a first low pass filter, a second low pass filter, a first zero DC bias adjustable gain amplifier, a second zero DC bias adjustable gain amplifier;

The analog IQ phase discrimination calibration module is configured to calibrate a measurement error of the analog IQ phase detection module;

The analog IQ phase discrimination calibration module detects the analog IQ phase detection module in real time. When the analog IQ phase detection module is calibrated, it is automatically turned off to avoid the influence of the calibration module on the analog IQ phase detection result;

The analog IQ phase discrimination calibration module comprises a digital signal processor, a first variable phase shifter, a second variable phase shifter, a first DC offset bias variable gain amplifier circuit, and a second DC offset bias variable Gain amplification circuit.

Further, the dual directional coupler is configured to transmit a coupled RF source incident signal, adjust a level of the coupled signal to 0 dBm through a signal conditioning circuit, and input the coupled signal into an analog IQ phase detecting module as an LO input signal;

The power splitter is configured to send the cavity sampling signal to the analog IQ phase detecting module as an RF signal, and the power splitter is further configured to send the cavity sampling signal to the input signal to the cavity firing detecting device;

The servo motor is used to detect the tuning position and control the speed and direction of the tuning rod movement.

Further, the cavity firing detection device includes a detector and a digital signal processor;

The digital signal processor controls the motor to complete the tuning function by converting the I signal and the Q signal output by the analog IQ phase detector module into a control signal of the motor;

The detector differentiates the detection result by envelope detection. When the energy released by the cavity unit time is greater than the release energy per unit time during normal operation, the cavity is judged to be in a fire state, and the signal processor issues an instruction to disconnect the radio frequency. switch;

Further, the measurement error includes a DC offset, an amplitude imbalance, and a phase imbalance.

Further, the one-two splitters are respectively connected to the RF port and the phase shifter of the mixer, and the phase shifter is connected to the RF port of the mixer M219, and the one-two splitter will RF The signals are respectively transmitted to the mixer and the mixer M219, and the shunt power is attenuated by 3 db;

The hybrid power splitter is respectively connected to the LO port of the phase shifter and the mixer, the phase shifter is connected to the LO port of the mixer, the LO signal is divided into two paths, and the phase difference of the two signals is 90°, the shunt power is attenuated by 3db;

The first tunable phase shifter and the second tunable phase shifter are configured to dynamically adjust a phase difference, the phase difference including an RF signal of the M1 mixer and a 0° phase difference of the LO signal and an RF of the M2 mixer 90° phase difference between the signal and the LO signal;

The first double balanced mixer and the second double balanced mixer are configured to extract phase information of the RF signal by using the LO signal;

The first low pass filter and the second low pass filter are configured to output an upconverted signal and a downconverted signal on the mixer, and retain the down converted signal to filter out the upconverted signal, the first low pass filter And the bandpass range of the second low pass filter is 0-1.9 MHz;

The first zero DC bias adjustable gain amplifier and the second zero DC bias adjustable gain amplifier are configured to transmit a radio frequency circuit signal, the first zero DC bias adjustable gain amplifier and a second zero DC offset The adjustable gain amplifier is also used to eliminate the dc bias of the amplifier.

Further, the analog IQ phase discrimination calibration module generates an analog RF signal and inputs it to the analog IQ phase detection module, continuously changes the phase difference between the RF signal and the LO signal, and samples the I signal and the Q signal through the analog to digital converter through the LM. The fitting algorithm fits the trigonometric function curve of the channel signal to obtain the amplitude and DC offset in the channel and the phase difference between the I signal and the Q signal. The analog IQ phase discrimination calibration module is also used to adjust the analog IQ through the PI feedback control. The phase detector module calibrates the analog IQ phase detector module.

Further, the first variable phase shifter and the second variable phase shifter are used to simulate an IQ phase discrimination calibration module to calibrate a phase imbalance caused by a power divider, and the digital signal processor compares the set phase and I, The phase of the Q signal is delayed by the phase of the I signal and the Q signal, and the delayed signal is transmitted to the first variable phase shifter and the second variable phase shifter;

The first variable phase shifter and the second variable phase shifter reduce the phase delay of the I signal and the Q signal by adjusting the resistance until the delay is 0;

The first DC offset bias gain amplifier circuit and the second DC offset bias gain amplifier circuit are configured to calibrate DC offset and gain imbalance caused by the amplifier circuit; the digital signal processor compares settings The amplitude and the amplitude of the I and Q signals obtain the amplitude error of the I signal and the Q signal, and the first DC offset bias gain amplifier circuit and the second DC offset bias gain amplifier circuit adjust the DC offset. A variable gain amplifier circuit is provided to reduce the DC offset and gain imbalance of the I and Q signals.

Further, the first variable phase shifter and the second variable phase shifter are advanced variable phase shifters, and the phase shift range is 0-180°, including a DC blocking capacitor, a first resistor, a second resistor, The first variable resistor and the first operational amplifier.

Further, the DC offset bias circuit includes a first symmetric fixed value resistor R3, a second symmetric fixed value resistor R4, a second variable resistor R5, a voltage follower, and a fixed value resistor R6, and the amplifier is eliminated by adjusting the resistance of R5. The resulting DC offset.

Further, the variable gain amplifying circuit includes a decoupling capacitor, a second operational amplifier, a third resistor, a third variable resistor, and a fourth resistor and a decoupling capacitor, and the gain of the amplifying circuit is changed by adjusting the variable resistor R8, thereby eliminating the cause The gain imbalance caused by the amplifying circuit.

The beneficial effects of the invention:

The system of the invention adopts a combination of an analog signal processing system and a digital signal system to improve system tuning precision and noise resistance performance, and reduce the delay time of the feedback system due to signal processing, and the analog IQ phase calibration module carried by the tuning system itself is improved. The self-adjusting capability of the analog IQ phase-sensing module is extended and its application range is extended. At the same time, the invention has the capability of real-time detection for abnormalities such as detection of cavity sparking, tuning range of tuning rod, and running state of the motor, thereby protecting the entire system. Safe operation, to avoid the occurrence of accidents; the detection cavity of the invention uses an envelope detector, mainly because the response time of the envelope detector is significantly shorter than other detection methods, and the implementation scheme is simple and easy.

DRAWINGS

In order to facilitate the understanding of those skilled in the art, the present invention will be further described below in conjunction with the accompanying drawings.

1 is a schematic block diagram of a superconducting cyclotron tuning system of the present invention.

2 is a schematic block diagram of a novel analog IQ phase discrimination module of the present invention.

FIG. 3 is a schematic block diagram of a novel analog IQ phase-advanced phase shifter according to the present invention.

4 is a schematic block diagram of a novel analog IQ phase-collecting DC compensation amplifying circuit of the present invention.

FIG. 5 is a signal flow diagram of a novel analog IQ phase discrimination module and calibration module of the present invention.

6 is a flow chart of calibration of a novel analog IQ phase detector module of the present invention.

7 is a flow chart of real-time detection of a novel tuning system of a superconducting cyclotron according to the present invention.

Figure 8 is a three-dimensional view of a driving device for a novel tuning system of a superconducting cyclotron according to the present invention.

Preferred embodiment of the invention

The technical solutions of the present invention will be described clearly and completely hereinafter with reference to the embodiments. It is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts are within the scope of the present invention.

A novel superconducting cyclotron tuning system, comprising a servo motor 1, a cavity ignition detection device, an analog IQ phase discrimination calibration module 3, an analog IQ phase discrimination module 4, a power divider 5, and a dual directional coupler 8 1;

The dual directional coupler 8 is configured to transmit a coupled RF source incident signal, adjust the level of the coupled signal to 0 dBm through a signal conditioning circuit, and input the coupled signal to the analog IQ phase detecting module 4 as an LO input signal;

The power splitter 5 is configured to send a cavity sampling signal to the analog IQ phase detecting module 4 as an RF signal, and the power splitter 5 is further configured to send the cavity sampling signal to the cavity firing detecting device;

The analog IQ phase detector module 4 is used to modulate the sine I and cosine Q of the phase difference between the LO signal and the RF signal;

The analog IQ phase discrimination calibration module 3 is configured to calibrate measurement errors of the analog IQ phase discrimination module 4, the measurement errors including DC offset, amplitude imbalance, and phase imbalance;

The servo motor 1 is used for detecting a tuning position and controlling a speed and direction of movement of the tuning rod;

The cavity ignition detecting device comprises a detector 6 and a digital signal processor 2;

The digital signal processor 2 controls the motor 1 to complete the tuning function by converting the I signal and the Q signal output by the analog IQ phase detector module 4 into control signals of the motor;

The detector 6 differentiates the detection result by envelope detection. When the energy released by the cavity unit time is greater than the release energy per unit time during normal operation, that is, the ratio of the cavity pressure to the cavity time constant, the cavity is judged to be playing. In the fire state, the signal processor 2 issues an instruction to disconnect the RF switch 7 to protect the security of the entire system;

In this embodiment, the dual directional coupler 8 uses the capacitive coupling cavity signal as the RF signal of the analog IQ phase discrimination module, and the cavity incident signal of the 0dbm is coupled by the directional coupler as the LO signal of the analog IQ phase detection module, the RF signal and The LO signal is modulated by the analog IQ phase detector module 4 to obtain the synchronization signal I and the quadrature signal Q, and then the IQ signal is converted into a digital signal by ADC sampling, and the cavity is obtained by the digital signal processing algorithm in the digital signal processor 2 (DSP). The detuning angle and the type of detuning, and finally converting the detuning angle and type into a pulse signal and a direction signal for driving the servo motor;

As shown in FIG. 7, a specific embodiment of the present invention is as follows:

S1, low power verification;

S2, whether the control signal in the system is normal, wherein the control signal comprises a motor running signal, a radio frequency switch working signal, and an analog IQ phase detecting module 3 calibration signal;

S3, the system is safely operated by the hardware program;

Preferably, the system detects the signal by the envelope detector detecting cavity, and when the rate of energy release in the cavity is greater than the cavity firing criterion, the RF power supply is immediately disconnected to avoid an accident;

The analog IQ phase detecting module comprises a split power splitter 14, a hybrid splitter 15, a first adjustable phase shifter 16, a second adjustable phase shifter 17, a first double balanced mixer 18, a first Two double balanced mixers 19, a first low pass filter 20, a second low pass filter 21, a first zero DC bias adjustable gain amplifier 22, a second zero DC bias adjustable gain amplifier 23, as shown in the figure 2;

The one-two splitters 14 are respectively connected to the RF port of the mixer 18 and the phase shifter 16, the phase shifter 16 is connected to the RF port of the mixer M219, and the split-to-two splitter 14 is to RF. The signals are respectively transmitted to the mixer 18 and the mixer M219, and the shunt power is attenuated by 3 db. The initial state of the phase shifter 16 is 0° by default. After the splitter D114, the RF signal is divided into RF ₁ and RF ₂ . The relation is expressed as:

Where A is the amplitude of the RF signal, a is the phase of the line connecting the power divider 14 and the mixer 18, and b is the phase of the line connecting the power divider 14 and the mixer M219;

The hybrid power divider 15 is respectively connected to the LO port of the phase shifter 17 and the mixer 19, the phase shifter 17 is connected to the LO port of the mixer 18, and the LO signal is divided into two paths, and two paths are The phase difference of the signal is 90°, and the shunt power is attenuated by 3db. After passing through the power divider 15, the LO signal is divided into LO ₁ and LO ₂ , and its expression is expressed as:

Where c is the LO signal phase, d is the LO signal phase, and e is the LO signal phase.

The first adjustable phase shifter 16 and the second adjustable phase shifter 17 are used for dynamically adjusting the phase difference, the phase difference including the RF signal of the M1 mixer 18 and the LO signal amount of 0° phase difference and M2 mixing a 90° phase difference between the RF signal of the frequency converter 19 and the LO signal;

The first double balanced mixer 18 and the second double balanced mixer 19 are configured to extract phase information of an RF signal by using an LO signal;

The first low pass filter 20 and the second low pass filter 21 are configured to output an up-converted signal and a down-converted signal on the mixer, and retain the down-converted signal, and filter out the up-converted signal, the first low-pass filter 20 And the band pass range of the second low-pass filter 21 is 0-1.9 MHz, so that the up-converted signal can be filtered out and the down-converted DC signal is retained;

The first zero DC bias adjustable gain amplifier 22 and the second zero DC bias adjustable gain amplifier 23 are used to transmit RF circuit signals, which are beneficial for ADC sampling, the first zero DC bias adjustable gain amplifier 22 and the first The 20 DC offset adjustable gain amplifier 23 is also used to eliminate the DC offset phenomenon of the amplifier and improve the accuracy of the analog IQ phase discrimination;

In this embodiment, the in-phase output terminals of the one-two power splitter 14 and the Hybrid power splitter 15 are mounted with a first adjustable phase shifter 16 and a second adjustable phase shifter 17 for fine-tuning the phase due to the power splitter. Signal modulation error caused by imbalance;

In this embodiment, it adopts a real-time adjustable DC offset network and an amplifier gain to compensate for the amplitude imbalance caused by the power splitter and the mixer caused by the DC offset of the amplifier.

The analog IQ phase discrimination calibration module 3 detects the analog IQ phase detection module 4 in real time. When the analog IQ phase detection module 4 is calibrated, it is automatically turned off to avoid the influence of the calibration module on the analog IQ phase discrimination result. The analog IQ phase detector module 4 mainly provides an I signal and a Q signal feedback signal for the analog IQ phase discrimination module 3 as an input signal of the analog IQ phase discrimination calibration module 3.

The analog IQ phase discrimination calibration module 3 generates an analog RF signal and inputs it to the analog IQ phase detector module 4, continuously changes the phase difference between the RF signal and the LO signal, and samples the I signal and the Q signal through the analog to digital converter, and then utilizes the LM. The fitting algorithm fits the trigonometric function curve of the channel signal to obtain the amplitude and DC offset in the channel and the phase difference between the I signal and the Q signal. The analog IQ phase discrimination calibration module 3 is also used to adjust the analog IQ meter through the PI feedback control. Phase module 4, calibration analog IQ phase detection module 4; analog IQ phase discrimination calibration module 3 includes a digital signal processor 2, a first variable phase shifter, a second variable phase shifter, and a first DC cancellation bias a gain amplifying circuit and a second DC offset bias variable gain amplifying circuit;

Preferably, the functions of the analog IQ phase discrimination calibration module 3 mainly include: generating an analog RF signal and an LO signal, accepting an analog IQ signal, analog-to-digital conversion (ADC) and digital-to-analog conversion (DAC), and digital signal processing, and feedback signals. Output

The digital signal processor 2 is used for analog digital signal processing of the IQ phase discrimination calibration module 3, and the digital signal processor 2 implements I signal and Q signal amplitude, phase difference, and DC offset calculation by an LM fitting algorithm, wherein The LM fitting algorithm mainly constructs the objective function by observing the change trend of the sampling points, setting the fitting function, and using the least squares method:

F(x)=(f(a _i ,x,y)-f(a _i-1 ,x,y)) ²

Where f(a _i , x, y) represents the function value of the fitting function at the sampling point (x, y) after passing i iterations. Through constant iterative calculation, the error minimum is found; the algorithm is adaptable, easy to implement, and the nonlinear fitting error is small;

The first variable phase shifter and the second variable phase shifter are used to simulate the phase discrimination calibration module 3 to calibrate the phase imbalance caused by the power divider, and the digital signal processor 2 compares the set phase and I, Q. The phase of the signal is delayed by the phase of the I signal and the Q signal, and the delayed signal is transmitted to the first variable phase shifter and the second variable phase shifter;

Preferably, the first variable phase shifter and the second variable phase shifter reduce the phase delay of the I signal and the Q signal by adjusting the resistance until the delay is 0;

In this embodiment, the first variable phase shifter and the second variable phase shifter are advanced variable phase shifters, and the phase shift range is 0-180°, including a DC blocking capacitor 29, a first resistor 27, and a second The resistor 28, the first variable resistor 25 and the first operational amplifier 26, as shown in FIG. 3, have an expression expressed as:

The first DC offset bias gain amplifier circuit and the second DC offset bias gain amplifier circuit are used to calibrate DC offset and gain imbalance caused by the amplifier circuit; the digital signal processor 2 compares the set The amplitude and the amplitude of the I and Q signals obtain the amplitude error of the I signal and the Q signal, and the first DC offset bias gain amplifier circuit and the second DC offset bias gain amplifier circuit adjust the DC offset Variable gain amplifier circuit to reduce DC offset and gain imbalance of I and Q signals;

In this embodiment, the DC offset bias circuit includes a first symmetric fixed value resistor R3, a second symmetric fixed value resistor R4, a second variable resistor R5, a voltage follower 33, and a fixed value resistor R6, by adjusting the resistance of the R5. Eliminate the DC offset caused by the amplifier, as shown in Figure 4;

The variable gain amplifying circuit includes a decoupling capacitor 38, a second operational amplifier 37, a third resistor 35, a third variable resistor 36, and a fourth resistor 39 and a decoupling capacitor 40. The gain of the amplifying circuit is changed by adjusting the variable resistor R8. Thereby eliminating the gain imbalance caused by the amplifying circuit;

As shown in FIG. 5, the system adopts TTL level communication and radio frequency cable, and the output signal of the new analog IQ phase detector module 3 is converted into a digital signal by an analog-to-digital converter, and is transmitted to the analog IQ phase discrimination calibration module through a communication line. 4. The analog IQ phase discrimination calibration module 4 returns the feedback signal to the new analog IQ phase detector module 3 through the digital-to-analog converter to realize the closed-loop operation of the system and complete the calibration of the analog IQ phase detector;

Preferably, the analog IQ phase discrimination calibration module 3 calibration logic includes phase imbalance calibration, DC offset calibration, and amplitude imbalance calibration;

Preferably, the first variable phase shifter and the second variable phase shifter are used to calibrate the phase imbalance caused by the power splitter 5;

Preferably, the first DC offset bias gain amplifier circuit and the second DC offset bias gain amplifier circuit are used for calibrating DC offset and amplitude imbalance;

In this embodiment, the calibration process of the analog IQ phase discrimination module 4 includes the following steps:

S1, the calibration signal is sent to the analog IQ phase discrimination calibration module 4, and the analog IQ phase discrimination module 4 generates the LO signal and the RF signal through the direct digital frequency synthesizer according to the user setting value;

S2, determining whether the phase of the IQ phase detector is orthogonal, if the phase of the IQ phase detector is not orthogonal, adjusting the first variable phase shifter and the second variable phase shifter to make the phase and phase setting of the IQ channel The value is zero;

S3, the digital signal processor 2 calculates the DC offset and amplitude of the analog IQ phase detector, and the PI controller controls the DC offset and gain of the post amplifier to eliminate DC offset and amplitude imbalance;

Preferably, in order to further improve the phase discrimination accuracy of the new analog IQ phase detector, it is generally necessary to increase the number of new analog IQ phase detectors by 2 to 3 times.

The superconducting cyclotron novel tuning system driving device comprises a chassis 101, an intermediate disk 104 and a top plate 109, and between the chassis 101 and the intermediate disk 104, between the intermediate disk 104 and the top plate 109 are connected by an optical axis 102, wherein the optical axis 102 The linear bearing 103 is installed through the surface of the intermediate disk 104, and the optical axis 102 is fixed to the peripheral side of the limiting plate 117;

The surface of the intermediate plate 104 is fixed with a ball screw fixing base 105, the surface of the intermediate plate 104 is fixed with a limit switch fixing plate 118 and a limit switch 119;

a top surface of the top plate 109 is mounted with a ball screw 106 and a synchronous wheel 115 and is fixed with a potentiometer 107, wherein the ball screw 106 and the ball screw mount 105, the ball screw 106 is fixed with a timing pulley 108 on the circumferential side;

Preferably, the ball screw 106 is fixed to the surface of the top plate 109 through the screw nut fixing shaft 111 and the lock nut 112;

Preferably, the potentiometer 107 is fixed to the surface of the top plate 109 by the potentiometer fixing plate 110;

The other surface of the top plate 109 is mounted with a planetary gear reducer 114, and the other surface of the planetary gear reducer 114 is mounted with a servo motor 113;

The analog IQ phase detector 3 drives the servo motor 113 according to the detuning angle and direction. The servo motor 113 drives the intermediate disk 104 through the timing pulley 108. The orientation bar mainly ensures the directionality of the displacement of the intermediate disk 104.

The preferred embodiments of the invention disclosed above are merely illustrative of the invention. The preferred embodiments are not to be considered in all detail, and the invention is not limited to the specific embodiments. Obviously, many modifications and variations are possible in light of the teachings herein. The present invention has been chosen and described in detail to explain the embodiments of the invention and the invention. The invention is to be limited only by the scope of the appended claims and the appended claims.

Industrial applicability

The specific working principle of the present invention is: using a combination of an analog signal processing system and a digital signal system to improve system tuning accuracy and noise resistance, and reducing the delay time of the feedback system due to signal processing, and the analog IQ meter carried by the tuning system itself. The phase calibration module improves the self-adjusting ability of the analog IQ phase-sensing module and expands its application range. At the same time, the invention has the capability of real-time detection for abnormalities such as cavity ignition detection, tuning rod tuning range, and motor running condition. To protect the entire system from safe operation and avoid accidents.

Claims

A novel superconducting cyclotron tuning system, comprising: servo motor (1), cavity ignition detection device, analog IQ phase discrimination calibration module (3), analog IQ phase detection module (4), power divider (5), dual directional coupler (8);

The analog IQ phase detector module (4) is for modulating the sine I and cosine Q of the phase difference between the LO signal and the RF signal, and the analog IQ phase detector module (4) provides an I signal for the analog IQ phase discrimination module (3) And Q signal feedback signal as an input signal of the analog IQ phase discrimination calibration module (3);

The analog IQ phase detecting module comprises a split power splitter (14), a hybrid splitter (15), a first adjustable phase shifter (16), a second adjustable phase shifter (17), and a first Double balanced mixer (18), second double balanced mixer (19), first low pass filter (20), second low pass filter (21), first zero DC bias adjustable gain amplifier (22), a second zero DC bias adjustable gain amplifier (23);

The analog IQ phase discrimination calibration module (3) is used to calibrate the measurement error of the analog IQ phase detector module (4);

The analog IQ phase discrimination calibration module (3) performs real-time detection on the analog IQ phase detection module (4). When the analog IQ phase detection module (4) is calibrated, it is automatically turned off to avoid the influence of the calibration module on the analog IQ phase detection result;

The analog IQ phase discrimination calibration module (3) includes a digital signal processor (2), a first variable phase shifter, a second variable phase shifter, a first DC offset bias variable gain amplifying circuit, and a second DC offset variable gain amplifier circuit.
A novel superconducting cyclotron tuning system according to claim 1, wherein said dual directional coupler (8) is configured to transmit a coupled RF source incident signal, and the level of the coupled signal is adjusted by a signal conditioning circuit 0dbm, and input the coupled signal into the analog IQ phase detector module (4) as the LO input signal;

The power splitter (5) is configured to send a cavity sampling signal to the analog IQ phase detector module (4) as an RF signal, and the power splitter (5) is further configured to send the cavity sampling signal to the input signal to the cavity Body ignition detection device;

The servo motor (1) is used to detect the tuning position and control the speed and direction of the tuning rod movement.
A novel superconducting cyclotron tuning system according to claim 1, wherein said cavity firing detecting means comprises a detector (6) and a digital signal processor (2);

The digital signal processor (2) controls the motor (1) to complete the tuning function by converting the I signal and the Q signal output by the analog IQ phase detecting module (4) into a control signal of the motor;

The detector (6) differentiates the detection result by envelope detection. When the energy released by the cavity unit time is greater than the release energy per unit time during normal operation, the cavity is judged to be in a sparking state, and the signal processor (2) ) Issue an instruction to disconnect the RF switch (7).
A novel superconducting cyclotron tuning system according to claim 1 wherein:

The measurement errors include DC offset, amplitude imbalance, and phase imbalance.
A novel superconducting cyclotron tuning system according to claim 1, wherein said one-two splitter (14) and the RF port and phase shifter (16) of the mixer (18), respectively Connected, the phase shifter (16) is connected to the RF port of the mixer M219, and the one-two splitter (14) transmits the RF signal to the mixer (18) and the mixer M219, respectively. The road power is attenuated by 3db;

The hybrid power divider (15) is respectively connected to the LO port of the phase shifter (17) and the mixer (19), and the phase shifter (17) is connected to the LO port of the mixer (18), LO The signal is divided into two paths, and the phase difference between the two signals is 90°, and the shunt power is attenuated by 3db;

The first adjustable phase shifter (16) and the second adjustable phase shifter (17) are for dynamically adjusting a phase difference, the phase difference including an RF signal of the M1 mixer (18) and an LO signal amount of 0. ° phase difference and 90° phase difference between the RF signal and the LO signal of the M2 mixer (19);

The first double balanced mixer (18) and the second double balanced mixer (19) are configured to extract phase information of the RF signal by the LO signal;

The first low pass filter (20) and the second low pass filter (21) are configured to output an up-converted signal and a down-converted signal on the mixer, and retain the down-converted signal to filter out the up-converted signal. The bandpass range of the first low pass filter (20) and the second low pass filter (21) is 0-1.9 MHz;

The first zero DC bias adjustable gain amplifier (22) and the second zero DC bias adjustable gain amplifier (23) are configured to transmit a radio frequency circuit signal, the first zero DC bias adjustable gain amplifier The (22) and second zero DC bias adjustable gain amplifiers (23) are also used to eliminate the amplifier's DC offset.
A novel superconducting cyclotron tuning system according to claim 1, wherein said analog IQ phase discrimination module (3) generates an analog RF signal and inputs it to an analog IQ phase detector module (4) for continuous change. The phase difference between the RF signal and the LO signal, and the I signal and the Q signal are sampled by an analog-to-digital converter, and the trigonometric function curve of the channel signal is fitted by the LM fitting algorithm to obtain the amplitude and DC offset and the I signal in the channel. The phase difference of the Q signal, the analog IQ phase discrimination calibration module (3) is also used to adjust the analog IQ phase detector module (4) through the PI feedback control, and calibrate the analog IQ phase detector module (4).
A novel superconducting cyclotron tuning system according to claim 1, wherein said first variable phase shifter and said second variable phase shifter are used for simulating an IQ phase discrimination calibration module (3) calibration factor The phase imbalance caused by the power divider, the digital signal processor (2) compares the set phase and the phase of the I and Q signals to obtain the phase delay of the I signal and the Q signal, and transmits the delayed signal to the first variable phase shift. And a second variable phase shifter;

The first variable phase shifter and the second variable phase shifter reduce the phase delay of the I signal and the Q signal by adjusting the resistance until the delay is 0;

The first DC offset bias gain amplifier circuit and the second DC offset bias gain amplifier circuit are used to calibrate DC offset and gain imbalance caused by the amplifier circuit; the digital signal processor (2) Comparing the set amplitude and the amplitude of the I and Q signals to obtain the amplitude error of the I signal and the Q signal, the first DC offset bias gain amplifier circuit and the second DC offset bias gain amplifier circuit are adjusted The DC offset variable gain amplifier circuit reduces the DC offset and gain imbalance of the I and Q signals.
A novel superconducting cyclotron tuning system according to claim 7, wherein said first variable phase shifter and said second variable phase shifter are advanced variable phase shifters, and the phase shift range is 0-180°, comprising a DC blocking capacitor (29), a first resistor (27), a second resistor (28), a first variable resistor (25), and a first operational amplifier (26).
A novel superconducting cyclotron tuning system according to claim 7, wherein the DC-DC biasing circuit comprises a first symmetric fixed value resistor R3, a second symmetric fixed value resistor R4, and a second variable resistor R5. The voltage follower (33) and the fixed value resistor R6 eliminate the DC offset caused by the amplifier by adjusting the resistance of R5.
A novel superconducting cyclotron tuning system according to claim 7, wherein the variable gain amplifying circuit comprises a decoupling capacitor (38), a second operational amplifier (37), a third resistor (35), and a The three variable resistors (36) and the fourth resistors (39) and the decoupling capacitors (40) change the gain of the amplifying circuit by adjusting the variable resistor R8, thereby eliminating the gain imbalance caused by the amplifying circuit.