WO2019103168A1 - Method for manufacturing thin film having layered structure, thin film having layered structure and manufactured thereby, and method for manufacturing semiconductor device by using same - Google Patents

Method for manufacturing thin film having layered structure, thin film having layered structure and manufactured thereby, and method for manufacturing semiconductor device by using same Download PDF

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Publication number
WO2019103168A1
WO2019103168A1 PCT/KR2017/013292 KR2017013292W WO2019103168A1 WO 2019103168 A1 WO2019103168 A1 WO 2019103168A1 KR 2017013292 W KR2017013292 W KR 2017013292W WO 2019103168 A1 WO2019103168 A1 WO 2019103168A1
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layer
thin film
epitaxial layer
porous silicon
silicon substrate
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PCT/KR2017/013292
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French (fr)
Korean (ko)
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김가현
송희은
김동석
조임현
오준호
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한국에너지기술연구원
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics

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  • the present invention relates to a method of manufacturing a laminated structure thin film, a laminated structure thin film produced thereby, and a method of manufacturing a semiconductor device using the same, and more particularly, to a laminated structure thin film which is used for manufacturing a semiconductor device such as a solar cell, A thin film of a laminated structure manufactured by the method, and a method of manufacturing a semiconductor device using the thin film.
  • the deposition process is a method of forming a thin film by vaporizing or sublimating a substance to be synthesized in a vacuum and attaching it on the surface of a crystalline silicon substrate in atomic or molecular units.
  • a crystalline silicon substrate is subjected to wire sawing (cutting) as shown in Fig. 1 (b) ) (3).
  • the cut crystalline silicon substrate 3 is identified in Fig. 1 (c).
  • a crystalline silicon substrate for a solar cell is mainly used for a substrate having a thickness of 200 mu m, and a thickness of 100 mu m or less is difficult to be processed by a cutting process.
  • the crystalline silicon substrate produced by the cutting method requires a step of etching a surface of the damage layer (contaminated layer).
  • a porous silicon 7 is formed on the surface of the crystalline silicon substrate 5 by a wet process, and then a chemical vapor deposition (CVD) process is performed on the surface of the porous silicon 7, The epitaxy layer 9 is grown.
  • CVD chemical vapor deposition
  • the above-described method is effective for depositing a crystalline film, but the porous silicon 7 must be formed by a wet process and forming gas annealing using hydrogen gas at an elevated temperature of about 1100 ° C. must be performed. And the growth of the epitaxial layer is also required to be performed at a high temperature of about 1300 DEG C by a thermal chemical vapor deposition process, which makes commercialization difficult.
  • An object of the present invention is to provide a method of manufacturing a laminated structure thin film of a novel method capable of lowering the process temperature without requiring a wet process, a laminated structure thin film produced thereby, and a semiconductor device using the same Method.
  • a method of manufacturing a semiconductor device including: depositing a porous silicon layer on one surface of a crystalline silicon substrate; depositing an epitaxial layer on the surface of the porous silicon layer; And a step of laminating at least one selected from a metal electrode, a protective film and an adhesion promoting layer on the upper surface of the taxi layer.
  • the deposition is performed by a capacitively coupled plasma (CCP) reaction.
  • CCP capacitively coupled plasma
  • the epitaxial layer may be a single layer of a silicon thin film, or may be grown as a single layer containing impurities in the thin silicon film or may be grown in a laminated structure containing impurities.
  • the single layer containing the impurity or the laminate structure including the impurity may be made of an alloy structure containing at least one selected from the group consisting of C and Ge as the impurity,
  • the dielectric constant of the dielectric layer is controlled by controlling the electric conductivity including the species or more, or adding at least one selected from O and N as the impurities.
  • the density of the porous silicon layer and the epitaxial layer is controlled by controlling the temperature of the crystalline silicon substrate and the ratio of the precursor gas.
  • At least one selected from SiH 4 , Si 2 H 6 , SiCl 4 , SiHCl 3 and SiF 4 is diluted with H 2 or He gas.
  • hydrogen plasma treatment is further performed at a temperature of 1100 ° C or less to readjust the porosity of the porous silicon layer.
  • the crystalline silicon substrate on which the laminated structure thin film is peeled off is recycled to the next process for forming the laminated structure thin film.
  • the laminated structure thin film includes a porous silicon layer, an epitaxial layer stacked on one surface of the porous silicon layer, and an additional layer stacked on the upper surface of the epitaxial layer and composed of at least one selected from a metal electrode, a protective film, do.
  • the additional layer is an adhesion promoting layer, and the dissimilar substrate is bonded to the upper surface of the adhesion promoting layer.
  • the epitaxial layer is a laminate structure comprising a single layer or an impurity.
  • the impurities are one or more selected from among C, Ge, B, P, Al, As, O,
  • the laminated thin film including the epitaxial layer is formed on the crystalline silicon substrate by plasma deposition and then peeled off from the crystalline silicon substrate, the laminated thin film having a thickness of 100 ⁇ or less There is an effect that a high-quality silicon substrate can be manufactured.
  • the thin film of the laminated structure is produced by the plasma deposition, the wet process is eliminated and the process step can be shortened, and the process temperature can be lowered to several hundreds of degrees Celsius at a high temperature of about 1300 ° C conventionally, So that it can be commercialized.
  • the present invention is advantageous in that it is used in the manufacture of solar cell semiconductor devices, thereby greatly reducing the manufacturing cost of solar cells.
  • FIG. 1 is a view showing a method of manufacturing a crystalline silicon substrate by cutting.
  • FIG. 2 is a view showing a process of forming a crystalline film on a crystalline silicon substrate by a conventional method of manufacturing a crystalline silicon substrate.
  • FIG 3 is a view showing an embodiment of a method of manufacturing a laminated structure thin film according to the present invention.
  • FIG. 4 is a view showing another embodiment of the method for manufacturing a laminated structure thin film according to the present invention.
  • FIG. 5 is a view showing an example of a plasma reactor for producing a laminated thin film of the present invention.
  • FIG. 3 shows an embodiment of a method for manufacturing a laminated structure thin film according to the present invention.
  • the laminated structure thin film manufacturing method of one embodiment is a laminated structure thin film manufacturing method for forming a laminated structure thin film on a crystalline silicon substrate.
  • the crystalline silicon substrate 11 can be prepared by cutting the grown ingot or block by a wire cutting method. That is, the crystalline silicon substrate 11 can be prepared by the same method as that shown in FIG.
  • the step a) may include a step of cleaning the surface of the crystalline silicon substrate 11 by etching or polishing the crystalline silicon substrate 11, and the etching may proceed with a wet or vacuum process.
  • Step b) and step c) are performed by forming a porous silicon layer 13 and an epitaxial layer 15 by vapor deposition and then performing a plasma process.
  • the plasma process is performed by using a plasma reactor having a capacitively coupled plasma (CCP) plasma structure.
  • CCP capacitively coupled plasma
  • the plasma reaction apparatus of the CCP plasma structure includes an upper electrode 31 to which the crystalline silicon substrate 11 is attached and a lower electrode 33 positioned to have a predetermined electrode distance from the upper electrode 31 in the chamber 30
  • the lower electrode 33 is grounded and the voltage 35 is applied directly to the upper electrode 31 only.
  • the plasma reaction apparatus of the CCP plasma structure can change the process conditions by adjusting the distance between the upper electrode 31 and the lower electrode 33 to control the distance between the crystalline silicon substrate 11 and the plasma electrode.
  • Plasma frequencies of 13.56 MHz, 27.12 MHz, 40.68 MHz, 54.24 MHz and 60 MHz are available.
  • porous silicon layer 13 and the epitaxial layer 15 can be deposited all over one surface of the crystalline silicon substrate 11.
  • a porous silicon layer and an epitaxial layer may be sequentially deposited on one surface of a crystalline silicon substrate, or a porous silicon layer and an epitaxial layer may be sequentially deposited on both surfaces of the crystalline silicon substrate.
  • both the porous silicon layer 13 and the epitaxial layer 15 are deposited on both surfaces of the crystalline silicon substrate 11, they can be simultaneously deposited on both surfaces or sequentially deposited one by one.
  • the density of the porous silicon layer 13 and the epitaxial layer 15 can be adjusted by controlling the crystalline silicon substrate temperature, the precursor gas ratio, and the like.
  • the crystalline silicon substrate temperature can be controlled in the range of 100 to 1100 ° C.
  • the temperature of the crystalline silicon substrate is controlled in the range of 200 to 950 ⁇ ⁇ .
  • the precursor gas may be at least one selected from the group consisting of SiH 4 , Si 2 H 6 , SiCl 4 , SiHCl 3 and SiF 4 to be diluted with H 2 or He gas.
  • the porous silicon layer and the epitaxial layer can be artificially formed to have a low density by controlling process conditions such as a thin film growth initial gas flow rate ratio, a plasma power, and the like.
  • the porosity of the porous silicon layer can be readjusted by further performing a hydrogen plasma treatment at a temperature of 1100 DEG C or less.
  • the epitaxial layer may grow as a single layer or grow into a laminate structure containing impurities.
  • the impurity may be a Group 4 element such as C or Ge, a dopant such as B, P, Al, As, or an impurity such as O, N or the like.
  • a laminate structure including an impurity may be formed by adding a Group 4 element such as C or Ge together with a precursor gas to an alloy structure, or by adding a dopant such as B, P, Al, or As to control electric conductivity, O, N, or the like can be added to fabricate a dielectric layer.
  • Step d) is a step of, after growth of the epitaxial layer, laminating an additional layer on the upper surface of the epitaxial layer 15, which is a selected one of a metal electrode, a protective film, and an adhesion promoting layer for bonding with the dissimilar substrate.
  • the step further comprises peeling (separating) the laminated thin film formed on the crystalline silicon substrate 11 from the crystalline silicon substrate.
  • the peeling can apply heat or mechanical stress to peel the laminated thin film from the crystalline silicon substrate.
  • the laminated structure thin film is easily peeled off from the crystalline silicon substrate by the porous silicon layer.
  • the crystalline silicon substrate 11 from which the laminated structure thin film has been peeled can be recycled for the next process for forming the same laminated structure thin film.
  • the laminated structure thin film produced by the above-described method is formed by stacking a porous silicon layer 13, an epitaxial layer 15 stacked on one surface of the porous silicon layer 13, an upper surface of the epitaxial layer 15, An additional layer 17 composed of at least one selected from a protective film and an adhesion promoting layer.
  • the porous silicon layer 13 and the epitaxial layer 15 are uniformly deposited to a thickness of 50 to 100 nm.
  • the porous silicon layer 13 may be deposited as a pure silicon thin film or contain some impurities.
  • the impurities contained in the porous silicon layer may be one or two selected from C, Ge, B, P, Al, As, Or more.
  • the density of the porous silicon layer may range from 1.1 to 2.33 g / cm < 3 >.
  • the porous silicon layer 13 is a single crystal silicon thin film layer.
  • the epitaxial layer 15 to be described later may also be a single crystal silicon thin film layer if it is formed as a single layer.
  • the epitaxial layer is grown on the top surface of the porous silicon layer.
  • the epitaxial layer is a laminate structure comprising a single layer or an impurity.
  • the epitaxial layer may contain a pure silicon film or some impurities.
  • the impurities contained in the epitaxial layer may be one or more selected from among C, Ge, B, P, Al, As, O,
  • the metal electrode may be laminated by a screen printing process using a metal paste.
  • the protective layer is laminated to prevent oxidation of the laminated thin film.
  • the additional layer 17 is an adhesion promoting layer
  • the dissimilar substrate 19 is laminated on the upper surface of the adhesion promoting layer.
  • the laminated structure thin film including the above-described epitaxial layer can be fabricated with a pn junction structure of heterogeneous junction or homogeneous junction.
  • FIG. 4 is a view showing another embodiment of the method for manufacturing a laminated structure thin film according to the present invention.
  • the step of peeling the laminated structure thin film formed on the crystalline silicon substrate 11 from the crystalline silicon substrate 11 is followed by the step of peeling the thin film on the additional layer 17 It is possible to bond the different substrates 19 to each other. Materials such as silicon, quartz, sapphire, glass, plastic, and metal foil can be used for the different substrate 19.
  • the crystalline silicon substrate is prepared by pre-etching or polishing the surface.
  • the etching can proceed by wet or vacuum processes.
  • the cleaned crystalline silicon substrate adheres to the upper electrode in the chamber of the plasma reactor of the CCP plasma structure.
  • a precursor gas, an impurity, or the like is injected into the chamber while applying a voltage to the upper electrode to generate a plasma to deposit a porous silicon layer on one surface of the crystalline silicon substrate, and after the deposition of the porous silicon layer, Layer.
  • the precursor gas may be one in which at least one selected from the group consisting of SiH 4 , Si 2 H 6 , SiCl 4 , SiHCl 3 and SiF 4 is diluted with H 2 or He gas, and the impurities are C, Ge, B, P, Al , As, O, and N can be injected.
  • Precursor gases are SiH may be 4, it is possible to adjust the dilution ratio of H 2 / SiH 4 from 1 to 1000 range.
  • the temperature of the silicon substrate can be maintained in the range of 200 to 950 ° C to synthesize a material having a low defect density.
  • the porous silicon layer having a low density can be formed by controlling the gas flow rate ratio and the plasma power during the deposition of the porous silicon layer.
  • a hydrogen plasma treatment may be further performed to readjust the porosity of the porous silicon layer.
  • a precursor gas and a Group 4 element such as C and Ge may be added as an impurity to form an alloy structure.
  • a dopant such as B, P, Al or As may be added to control the electric conductivity, Or the like can be added to fabricate the dielectric layer.
  • One or more gases selected from B 2 H 6 , B (CH 3 ) 3 , BF 3 , PH 3 , AsH 3 and Al 2 (CH 3 ) 6 may be added to control the impurity content.
  • at least one gas selected from N 2 O, CO 2 , O 2 , NH 3 and N 2 can be further added.
  • the laminated thin plate produced by the above-described method is subjected to thermal and mechanical stress to peel off from the crystalline silicon substrate.
  • the above-described method for manufacturing a laminated structure thin film can realize a laminated structure thin film having a thickness of 100 ⁇ or less by controlling the deposition thickness, and thus a high-quality silicon substrate can be formed.
  • the process step can be shortened and the thin film can be formed at a temperature of the silicon substrate below 1100 ° C, which is advantageous in that the process cost can be reduced and commercialized.
  • the above-described laminated structure thin film manufacturing method can be applied to the manufacture of semiconductor devices such as solar cells.

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Abstract

A method for manufacturing a thin film having a layered structure is disclosed. The method for manufacturing a thin film having a layered structure comprises the steps of: depositing a porous silicon layer on one surface of a crystalline silicon substrate; depositing an epitaxial layer on an upper surface of the porous silicon layer; and layering, on an upper surface of the epitaxial layer, an additional layer formed of at least one selected from a metal electrode, a protective film, and an adhesion promoting layer.

Description

적층구조 박막 제조방법, 이에 의해 제조된 적층구조 박막 및 이를 이용한 반도체 소자 제조방법Laminated thin film manufacturing method, laminated structure thin film produced thereby, and semiconductor device manufacturing method using the same
본 발명은 적층구조 박막 제조방법, 이에 의해 제조된 적층구조 박막 및 이를 이용한 반도체 소자 제조방법에 관한 것으로, 더욱 상세하게는 태양전지 등의 반도체 소자 제조에 이용되며 하나 이상의 단결정 실리콘 박막층을 포함하는 적층구조 박막 제조방법, 이에 의해 제조된 적층구조 박막 및 이를 이용한 반도체 소자 제조방법에 관한 것이다.The present invention relates to a method of manufacturing a laminated structure thin film, a laminated structure thin film produced thereby, and a method of manufacturing a semiconductor device using the same, and more particularly, to a laminated structure thin film which is used for manufacturing a semiconductor device such as a solar cell, A thin film of a laminated structure manufactured by the method, and a method of manufacturing a semiconductor device using the thin film.
반도체 소자 제조는 많은 종류의 박막(Thin film) 증착공정을 수반한다. 증착공정은 진공 중에서 합성하고자 하는 물질을 기화 또는 승화시켜서 원자 또는 분자 단위로 결정질 실리콘 기판 표면 위에 부착되도록 함으로써 박막을 형성시키는 방법이다.Semiconductor device fabrication involves many types of thin film deposition processes. The deposition process is a method of forming a thin film by vaporizing or sublimating a substance to be synthesized in a vacuum and attaching it on the surface of a crystalline silicon substrate in atomic or molecular units.
일반적으로 결정질 실리콘 기판은 도 1의 (a)에 도시된 바와 같이, 인상(Czochralski)법으로 결정 성장한 잉곳 또는 블록(1)을 도 1의 (b)에 도시된 바와 같이, 와이어 절단(wire sawing)(3) 방법으로 절단 가공하여 제작된다. 절단 가공된 결정질 실리콘 기판(3)은 도 1의 (c)에서 확인된다.Generally, as shown in Fig. 1 (a), a crystalline silicon substrate is subjected to wire sawing (cutting) as shown in Fig. 1 (b) ) (3). The cut crystalline silicon substrate 3 is identified in Fig. 1 (c).
그런데 와이어 절단 방법으로 절단 가공한 결정질 실리콘 기판은 절단 손실(kerf-loss)이 발생하여 낭비가 심하고, 가공할 수 있는 기판 두께에 한계가 있다. 현재 태양광용 결정질 실리콘 기판은 200㎛ 두께의 기판이 주로 사용되며, 100㎛ 이하의 두께는 절단 가공으로는 가공이 어렵다.However, in a crystalline silicon substrate cut by a wire cutting method, kerf-loss is generated, which is wasteful, and there is a limit to the thickness of the substrate that can be processed. At present, a crystalline silicon substrate for a solar cell is mainly used for a substrate having a thickness of 200 mu m, and a thickness of 100 mu m or less is difficult to be processed by a cutting process.
또한, 절단 가공 방법으로 제작한 결정질 실리콘 기판은 표면에 데미지층(오염층)이 존재하여 이를 식각하는 공정이 추가로 요구된다.Further, the crystalline silicon substrate produced by the cutting method requires a step of etching a surface of the damage layer (contaminated layer).
한편, 기존의 반도체 소자는 상술한 결정질 실리콘 기판(5)의 표면에 습식 공정으로 다공성 실리콘(7)을 형성한 후, 다공성 실리콘(7)의 상면에 화학기상증착(CVD) 공정을 수행하여 고온에서 에피택시(epitaxy)층(9)을 성장시킨다.In the conventional semiconductor device, a porous silicon 7 is formed on the surface of the crystalline silicon substrate 5 by a wet process, and then a chemical vapor deposition (CVD) process is performed on the surface of the porous silicon 7, The epitaxy layer 9 is grown.
그런데 상술한 방식은 결정질 막을 증착하는데 효과적이나, 다공성 실리콘(7)을 습식 공정으로 형성해야 하며 1100℃ 정도의 고온에서 추가적으로 수소 가스를 이용한 포밍 가스 어닐링(forming gas annealing)을 실시해야 하므로 비용상승을 유발하고, 에피택시층의 성장 또한 열 화학기상증착 공정으로 1300℃ 정도의 고온에서 실시되어야 하므로 상용화를 어렵게 하는 문제점이 있다.However, the above-described method is effective for depositing a crystalline film, but the porous silicon 7 must be formed by a wet process and forming gas annealing using hydrogen gas at an elevated temperature of about 1100 ° C. must be performed. And the growth of the epitaxial layer is also required to be performed at a high temperature of about 1300 DEG C by a thermal chemical vapor deposition process, which makes commercialization difficult.
본 발명의 목적은 반도체 소자 제조에 이용하는 적층구조 박막 제조방법이며, 습식공정이 필요 없고 공정온도를 낮출 수 있는 새로운 방법의 적층구조 박막 제조방법, 이에 의해 제조된 적층구조 박막 및 이를 이용한 반도체 소자 제조방법을 제공하는 것이다.An object of the present invention is to provide a method of manufacturing a laminated structure thin film of a novel method capable of lowering the process temperature without requiring a wet process, a laminated structure thin film produced thereby, and a semiconductor device using the same Method.
상기한 바와 같은 목적을 달성하기 위한 본 발명의 특징에 따르면, 본 발명은 결정질 실리콘 기판의 일면에 다공성 실리콘층을 증착하는 단계와 상기 다공성 실리콘층의 상면에 에피택시층을 증착하는 단계와 상기 에피택시층의 상면에 금속전극, 보호막, 접착촉진층 중 선택된 1종 이상을 적층하는 단계를 포함한다.According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, including: depositing a porous silicon layer on one surface of a crystalline silicon substrate; depositing an epitaxial layer on the surface of the porous silicon layer; And a step of laminating at least one selected from a metal electrode, a protective film and an adhesion promoting layer on the upper surface of the taxi layer.
상기 증착은 CCP(Capacitively Coupled Plasma) 반응에 의해 수행된다.The deposition is performed by a capacitively coupled plasma (CCP) reaction.
상기 다공성 실리콘층의 상면에 에피택시층을 증착하는 단계에서, 상기 에피택시층은 실리콘 박막의 단일층이거나 상기 실리콘 박막에 불순물을 포함하는 단일층으로 성장하거나 불순물을 포함하는 적층구조로 성장한다.In the step of depositing an epitaxial layer on the upper surface of the porous silicon layer, the epitaxial layer may be a single layer of a silicon thin film, or may be grown as a single layer containing impurities in the thin silicon film or may be grown in a laminated structure containing impurities.
상기 불순물을 포함하는 단일층 또는 상기 불순물을 포함하는 적층구조는, 상기 불순물로 C, Ge 중 선택된 1종 이상을 포함하여 합금 구조로 제작하거나, 상기 불순물로 B, P, Al, As 중 선택된 1종 이상을 포함하여 전기전도도를 통제하거나, 상기 불순물로 O, N 중 선택된 1종 이상을 추가하여 유전체층을 제작한다.The single layer containing the impurity or the laminate structure including the impurity may be made of an alloy structure containing at least one selected from the group consisting of C and Ge as the impurity, The dielectric constant of the dielectric layer is controlled by controlling the electric conductivity including the species or more, or adding at least one selected from O and N as the impurities.
상기 플라즈마 공정 수행시, 상기 결정질 실리콘 기판 온도, 전구체 가스 비율을 조절하여 상기 다공성 실리콘층과 상기 에피택시층의 밀도를 조절한다;.In the plasma process, the density of the porous silicon layer and the epitaxial layer is controlled by controlling the temperature of the crystalline silicon substrate and the ratio of the precursor gas.
상기 전구체 가스는 SiH4, Si2H6, SiCl4, SiHCl3, SiF4 중 선택된 1종 이상을 H2 또는 He 가스에 희석시킨 것을 사용한다.As the precursor gas, at least one selected from SiH 4 , Si 2 H 6 , SiCl 4 , SiHCl 3 and SiF 4 is diluted with H 2 or He gas.
상기 플라즈마 공정 수행 후, 1100℃ 이하의 온도에서 수소 플라즈마 처리를 추가로 수행하여 상기 다공성 실리콘층의 공극률을 재조정한다.After the plasma process is performed, hydrogen plasma treatment is further performed at a temperature of 1100 ° C or less to readjust the porosity of the porous silicon layer.
상기 에피택시층의 상면에 금속전극, 보호막, 접착촉진층 중 선택된 1종을 적층하는 단계 후, 상기 결정질 실리콘 기판에 형성된 적층구조 박막을 상기 결정질 실리콘 기판으로부터 박리하는 단계를 더 포함한다.Further comprising the step of laminating a selected one of a metal electrode, a protective film and an adhesion promoting layer on the upper surface of the epitaxial layer, and then peeling the laminated structure thin film formed on the crystalline silicon substrate from the crystalline silicon substrate.
상기 적층구조 박막이 박리된 상기 결정질 실리콘 기판은 상기 적층구조 박막 형성을 위한 다음번 공정에 재활용한다.The crystalline silicon substrate on which the laminated structure thin film is peeled off is recycled to the next process for forming the laminated structure thin film.
상기 금속전극, 보호막, 접착촉진층 중 선택된 1종의 상면에 이종기판을 적층하는 단계를 더 포함한다.And laminating the dissimilar substrate on the upper surface of the selected one of the metal electrode, the protective film, and the adhesion promoting layer.
적층구조 박막은 다공성 실리콘층, 상기 다공성 실리콘층의 일면에 적층되는 에피택시층, 상기 에피택시층의 상면에 적층되며 금속전극, 보호막, 접착촉진층 중 선택된 1종 이상으로 구성되는 추가층을 포함한다.The laminated structure thin film includes a porous silicon layer, an epitaxial layer stacked on one surface of the porous silicon layer, and an additional layer stacked on the upper surface of the epitaxial layer and composed of at least one selected from a metal electrode, a protective film, do.
상기 추가층은 접착촉진층이고, 상기 접착촉진층의 상면에 이종기판을 접합한다.The additional layer is an adhesion promoting layer, and the dissimilar substrate is bonded to the upper surface of the adhesion promoting layer.
상기 에피택시층은 단일층 또는 불순물을 포함하는 적층구조이다.The epitaxial layer is a laminate structure comprising a single layer or an impurity.
상기 불순물은 C, Ge, B, P, Al, As, O, N 중 선택된 1종 또는 2종 이상이다.The impurities are one or more selected from among C, Ge, B, P, Al, As, O,
본 발명은 결정형 실리콘 기판상에 에피택시층을 포함하는 적층구조 박막을 플라즈마 증착에 의해 형성한 후, 결정형 실리콘 기판으로부터 박리시켜 제조하므로, 임의의 두께 조절 조절로 두께 100㎛ 이하의 적층구조 박막 구현이 가능하고 고품질의 실리콘 기판을 제조할 수 있는 효과가 있다.Since the laminated thin film including the epitaxial layer is formed on the crystalline silicon substrate by plasma deposition and then peeled off from the crystalline silicon substrate, the laminated thin film having a thickness of 100 탆 or less There is an effect that a high-quality silicon substrate can be manufactured.
또한, 본 발명은 플라즈마 증착에 의해 적층구조 박막을 제조하므로 습식공정이 없어져 공정 단계를 단축할 수 있고, 공정 온도를 종래 1300℃ 정도의 고온에서 수백℃ 수준으로 낮출 수 있어 공정 비용을 대폭 절감할 수 있고 이로 인해 상용화가 가능한 효과가 있다. In addition, since the thin film of the laminated structure is produced by the plasma deposition, the wet process is eliminated and the process step can be shortened, and the process temperature can be lowered to several hundreds of degrees Celsius at a high temperature of about 1300 ° C conventionally, So that it can be commercialized.
또한, 본 발명은 태양전지 반도체 소자 제조에 이용되어 태양전지 제조 비용을 대폭 절감할 수 있는 효과가 있다.In addition, the present invention is advantageous in that it is used in the manufacture of solar cell semiconductor devices, thereby greatly reducing the manufacturing cost of solar cells.
도 1은 결정질 실리콘 기판을 절단 가공하여 제작하는 방법을 보인 도면. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a view showing a method of manufacturing a crystalline silicon substrate by cutting. FIG.
도 2는 종래의 결정질 실리콘 기판 제조방법으로 결정질 실리콘 기판에 결정질 막을 형성하는 공정을 보인 도면.2 is a view showing a process of forming a crystalline film on a crystalline silicon substrate by a conventional method of manufacturing a crystalline silicon substrate.
도 3은 본 발명에 의한 적층구조 박막 제조방법의 일 실시예를 보인 도면. 3 is a view showing an embodiment of a method of manufacturing a laminated structure thin film according to the present invention.
도 4는 본 발명에 의한 적층구조 박막 제조방법의 다른 실시예를 보인 도면.4 is a view showing another embodiment of the method for manufacturing a laminated structure thin film according to the present invention.
도 5는 본 발명의 적층구조 박막을 제조하기 위한 플라즈마 반응장치의 예를 보인 구성도.5 is a view showing an example of a plasma reactor for producing a laminated thin film of the present invention.
이하 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세하게 설명한다. Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 3에는 본 발명에 의한 적층구조 박막 제조방법의 일 실시예가 도시되어 있다.FIG. 3 shows an embodiment of a method for manufacturing a laminated structure thin film according to the present invention.
일 실시예의 적층구조 박막 제조방법은, 결정질 실리콘 기판에 적층구조 박막을 형성하는 적층구조 박막 제조방법이며, 도 3에 도시된 바와 같이, 결정질 실리콘 기판(11)을 준비하는 단계(a)와, 결정질 실리콘 기판(11)의 일면에 다공성 실리콘층(13)을 증착하는 단계(b)와, 다공성 실리콘층(13)의 상면에 에피택시층(15)을 증착하는 단계(c)와, 에피택시층(15)의 상면에 금속전극, 보호막, 접착촉진층 중 선택된 1종 이상으로 구성되는 추가층(17)을 적층하는 단계(d)를 포함한다.The laminated structure thin film manufacturing method of one embodiment is a laminated structure thin film manufacturing method for forming a laminated structure thin film on a crystalline silicon substrate. As shown in FIG. 3, a step (a) of preparing a crystalline silicon substrate 11, (B) depositing a porous silicon layer (13) on one side of a crystalline silicon substrate (11), (c) depositing an epitaxial layer (15) on the upper surface of the porous silicon layer (13) (D) laminating an additional layer (17) composed of at least one selected from a metal electrode, a protective film and an adhesion promoting layer on the upper surface of the layer (15).
a) 단계에서, 결정질 실리콘 기판(11)은 성장한 잉곳 또는 블록을 와이어 절단방법으로 절단 가공하여 제작한 것을 준비할 수 있다. 즉, 결정질 실리콘 기판(11)은 도 1에서 제시하고 있는 방법과 동일한 방법으로 제작된 것을 준비할 수 있다.In the step a), the crystalline silicon substrate 11 can be prepared by cutting the grown ingot or block by a wire cutting method. That is, the crystalline silicon substrate 11 can be prepared by the same method as that shown in FIG.
a) 단계는 결정질 실리콘 기판(11)을 식각 또는 연마하여 결정질 실리콘 기판(11)의 표면을 세정하는 단계를 포함할 수 있으며, 식각은 습식 또는 진공 공정으로 진행할 수 있다.The step a) may include a step of cleaning the surface of the crystalline silicon substrate 11 by etching or polishing the crystalline silicon substrate 11, and the etching may proceed with a wet or vacuum process.
b) 단계 및 c) 단계는 다공성 실리콘층(13)과 에피택시층(15)을 증착에 의해 형성하는 단계로 플라즈마 공정을 수행하여 형성한다. Step b) and step c) are performed by forming a porous silicon layer 13 and an epitaxial layer 15 by vapor deposition and then performing a plasma process.
플라즈마 공정은 CCP(Capacitively Coupled Plasma) 플라즈마 구조의 플라즈마 반응장치를 이용하여 수행한다. The plasma process is performed by using a plasma reactor having a capacitively coupled plasma (CCP) plasma structure.
설명의 편의를 위해, 도 5를 참조하여 CCP 플라즈마 구조의 플라즈마 반응장치에 대해 간단히 설명한다. For convenience of explanation, a plasma reaction device of a CCP plasma structure will be briefly described with reference to FIG.
CCP 플라즈마 구조의 플라즈마 반응장치는 결정질 실리콘 기판(11)이 부착되는 상부 전극(31)과 상부 전극(31)과 소정의 전극 거리를 가지도록 위치되는 하부 전극(33)을 챔버(30) 내에 포함하며, 하부 전극(33)은 그라운드(ground) 되어 있고 상부 전극(31)만 전압(35)이 직접 인가되도록 된다. The plasma reaction apparatus of the CCP plasma structure includes an upper electrode 31 to which the crystalline silicon substrate 11 is attached and a lower electrode 33 positioned to have a predetermined electrode distance from the upper electrode 31 in the chamber 30 The lower electrode 33 is grounded and the voltage 35 is applied directly to the upper electrode 31 only.
이러한 CCP 플라즈마 구조의 플라즈마 반응장치는 챔버(30) 내부로 가스를 주입하면서 상부 전극(31)에 전압(35)을 인가하면 전극 표면에 분포되는 전하에 의해 발생하는 축전 자기장에 의해 플라즈마가 발생하고 유지되며 플라즈마가 가스를 이온화시켜 결정질 실리콘 기판(11)에 증착시킨다.When a voltage 35 is applied to the upper electrode 31 while injecting gas into the chamber 30, a plasma is generated by a charge-accumulating magnetic field generated by charges distributed on the surface of the electrode, And the plasma ionizes the gas to deposit the crystalline silicon substrate 11.
CCP 플라즈마 구조의 플라즈마 반응장치는 상부 전극(31)과 하부 전극(33) 사이의 거리를 조절하여 결정질 실리콘 기판(11)과 플라즈마 전극 거리를 조절함으로써 공정 조건을 변화시킬 수 있다. The plasma reaction apparatus of the CCP plasma structure can change the process conditions by adjusting the distance between the upper electrode 31 and the lower electrode 33 to control the distance between the crystalline silicon substrate 11 and the plasma electrode.
플라즈마 주파수는 13.56MHz, 27.12MHz, 40.68MHz, 54.24MHz 및 60MHz 등이 사용 가능하다.Plasma frequencies of 13.56 MHz, 27.12 MHz, 40.68 MHz, 54.24 MHz and 60 MHz are available.
다공성 실리콘층(13) 및 에피택시층(15)은 결정질 실리콘 기판(11)의 일면에 모두 증착할 수 있다. The porous silicon layer 13 and the epitaxial layer 15 can be deposited all over one surface of the crystalline silicon substrate 11. [
예를 들어, 결정질 실리콘 기판의 일면에 다공성 실리콘층, 에피택시층을 순차적으로 증착하거나, 결정질 실리콘 기판의 양면에 각각 다공성 실리콘층, 에피택시층을 순차적으로 증착할 수 있다.For example, a porous silicon layer and an epitaxial layer may be sequentially deposited on one surface of a crystalline silicon substrate, or a porous silicon layer and an epitaxial layer may be sequentially deposited on both surfaces of the crystalline silicon substrate.
결정질 실리콘 기판(11)의 양면에 다공성 실리콘층(13) 및 에피택시층(15)을 모두 증착할 경우 양면에 동시에 증착하거나 일면씩 순차적으로 증착할 수 있다.When both the porous silicon layer 13 and the epitaxial layer 15 are deposited on both surfaces of the crystalline silicon substrate 11, they can be simultaneously deposited on both surfaces or sequentially deposited one by one.
결정질 실리콘 기판 온도, 전구체 가스 비율 등을 조절하여 다공성 실리콘층(13)과 에피택시층(15)의 밀도를 조절할 수 있다.The density of the porous silicon layer 13 and the epitaxial layer 15 can be adjusted by controlling the crystalline silicon substrate temperature, the precursor gas ratio, and the like.
결정질 실리콘 기판 온도는 100~1100℃ 범위에서 조절할 수 있다. 바람직하게는, 결정질 실리콘 기판 온도는 200~950℃ 범위로 조절한다.The crystalline silicon substrate temperature can be controlled in the range of 100 to 1100 ° C. Preferably, the temperature of the crystalline silicon substrate is controlled in the range of 200 to 950 占 폚.
전구체 가스는 SiH4, Si2H6, SiCl4, SiHCl3, SiF4 중 선택된 1종 이상을 H2 또는 He 가스에 희석시켜 사용할 수 있다. The precursor gas may be at least one selected from the group consisting of SiH 4 , Si 2 H 6 , SiCl 4 , SiHCl 3 and SiF 4 to be diluted with H 2 or He gas.
다공성 실리콘층과 에피택시층은 박막 성장 초반 가스 유량비, 플라즈마 파워 등의 공정 조건을 제어하여 인위적으로 밀도가 낮게 형성할 수 있다. The porous silicon layer and the epitaxial layer can be artificially formed to have a low density by controlling process conditions such as a thin film growth initial gas flow rate ratio, a plasma power, and the like.
다공성 실리콘층 증착 후, 1100℃ 이하의 온도에서 수소 플라즈마 처리를 추가로 수행하여 다공성 실리콘층의 공극률을 재조정할 수 있다. After deposition of the porous silicon layer, the porosity of the porous silicon layer can be readjusted by further performing a hydrogen plasma treatment at a temperature of 1100 DEG C or less.
에피택시층은 단일층으로 성장하거나 불순물을 포함하는 적층구조로 성장할 수 있다.The epitaxial layer may grow as a single layer or grow into a laminate structure containing impurities.
불순물은 C, Ge 등의 4족 원소이거나 B, P, Al, As 등의 도펀트이거나 O, N 등의 불순물일 수 있다. The impurity may be a Group 4 element such as C or Ge, a dopant such as B, P, Al, As, or an impurity such as O, N or the like.
구체적으로, 불순물을 포함하는 적층구조는 전구체 가스와 함께 C, Ge 등의 4족 원소를 추가하여 합금 구조로 제작하거나, B, P, Al, As 등의 도펀트를 추가하여 전기전도도를 통제하거나, O, N 등의 불순물을 추가하여 유전체층을 제작할 수 있다.Specifically, a laminate structure including an impurity may be formed by adding a Group 4 element such as C or Ge together with a precursor gas to an alloy structure, or by adding a dopant such as B, P, Al, or As to control electric conductivity, O, N, or the like can be added to fabricate a dielectric layer.
d) 단계는, 에피택시층의 성장 후, 에피택시층(15)의 상면에 금속전극, 보호막, 이종기판과 결합하기 위한 접착촉진층 중 선택된 1종인 추가층을 적층하는 단계이다.Step d) is a step of, after growth of the epitaxial layer, laminating an additional layer on the upper surface of the epitaxial layer 15, which is a selected one of a metal electrode, a protective film, and an adhesion promoting layer for bonding with the dissimilar substrate.
d) 단계 후, 결정질 실리콘 기판(11)에 형성된 적층구조 박막을 결정질 실리콘 기판으로부터 박리(분리)하는 단계를 더 포함한다. 박리는 열 또는 기계적 응력을 가하여 결정질 실리콘 기판으로부터 적층구조 박막을 박리할 수 있다. 적층구조 박막은 다공질 실리콘층에 의해 결정질 실리콘 기판으로부터 박리가 용이하다.After the step d), the step further comprises peeling (separating) the laminated thin film formed on the crystalline silicon substrate 11 from the crystalline silicon substrate. The peeling can apply heat or mechanical stress to peel the laminated thin film from the crystalline silicon substrate. The laminated structure thin film is easily peeled off from the crystalline silicon substrate by the porous silicon layer.
적층구조 박막이 박리된 결정질 실리콘 기판(11)은 동일한 적층구조 박막 형성을 위한 다음번 공정에 재활용할 수 있다. The crystalline silicon substrate 11 from which the laminated structure thin film has been peeled can be recycled for the next process for forming the same laminated structure thin film.
상술한 방법에 의해 제조된 적층구조 박막은 다공성 실리콘층(13), 다공성 실리콘층(13)의 일면에 적층되는 에피택시층(15), 에피택시층(15)의 상면에 적층되며 금속전극, 보호막, 접착촉진층 중 선택된 1종 이상으로 구성되는 추가층(17)을 포함할 수 있다.The laminated structure thin film produced by the above-described method is formed by stacking a porous silicon layer 13, an epitaxial layer 15 stacked on one surface of the porous silicon layer 13, an upper surface of the epitaxial layer 15, An additional layer 17 composed of at least one selected from a protective film and an adhesion promoting layer.
다공성 실리콘층(13) 및 에피택시층(15)은 50~100nm의 두께로 균일하게 증착된다. 다공성 실리콘층(13)은 순수한 실리콘 박막으로 증착하거나 일부 불순물을 함유할 수 있다 다공성 실리콘층에 포함되는 불순물은 C, Ge, B, P, Al, As, O, N 중 선택된 1종 또는 2종 이상일 수 있다.The porous silicon layer 13 and the epitaxial layer 15 are uniformly deposited to a thickness of 50 to 100 nm. The porous silicon layer 13 may be deposited as a pure silicon thin film or contain some impurities. The impurities contained in the porous silicon layer may be one or two selected from C, Ge, B, P, Al, As, Or more.
다공성 실리콘층의 밀도는 1.1~ 2.33g/㎤ 범위일 수 있다.The density of the porous silicon layer may range from 1.1 to 2.33 g / cm < 3 >.
다공성 실리콘층(13)은 단결정 실리콘 박막층이다. 후술할 에피택시층(15)도 단일층으로 형성되는 경우 단결정 실리콘 박막층일 수 있다.The porous silicon layer 13 is a single crystal silicon thin film layer. The epitaxial layer 15 to be described later may also be a single crystal silicon thin film layer if it is formed as a single layer.
에피택시층은 다공성 실리콘층의 상면에 성장된다. 에피택시층은 단일층 또는 불순물을 포함하는 적층구조이다. An epitaxial layer is grown on the top surface of the porous silicon layer. The epitaxial layer is a laminate structure comprising a single layer or an impurity.
에피택시층은 순수한 실리콘 박막 또는 일부 불순물을 함유할 수 있다. 에피택시층에 포함되는 불순물은 C, Ge, B, P, Al, As, O, N 중 선택된 1종 또는 2종 이상일 수 있다.The epitaxial layer may contain a pure silicon film or some impurities. The impurities contained in the epitaxial layer may be one or more selected from among C, Ge, B, P, Al, As, O,
금속전극은 금속페이스트를 이용한 스크린 프린팅 공정에 의해 적층될 수 있다. 보호층은 적층구조 박막의 산화를 방지하기 위해 적층된다. 추가층(17)이 접착촉진층인 경우, 접착촉진층의 상면에 이종기판(19)이 적층된다.The metal electrode may be laminated by a screen printing process using a metal paste. The protective layer is laminated to prevent oxidation of the laminated thin film. When the additional layer 17 is an adhesion promoting layer, the dissimilar substrate 19 is laminated on the upper surface of the adhesion promoting layer.
상술한 에피택시층을 포함하는 적층구조 박막은 이종접합 또는 동종접합의 pn접합 구조로 제작할 수 있다.The laminated structure thin film including the above-described epitaxial layer can be fabricated with a pn junction structure of heterogeneous junction or homogeneous junction.
도 4에는 본 발명에 의한 적층구조 박막 제조방법의 다른 실시예를 보인 도면이 도시되어 있다.FIG. 4 is a view showing another embodiment of the method for manufacturing a laminated structure thin film according to the present invention.
다른 실시예의 적층구조 박막 제조방법은, 도 4에 도시된 바와 같이, 결정질 실리콘 기판(11)에 형성된 적층구조 박막을 결정질 실리콘 기판(11)으로부터 박리하는 단계 후, 추가층(17)에 박막 지지용 이종기판(19)을 접합할 수 있다. 이종기판(19)은 실리콘, 석영, 사파이어, 유리, 플라스틱, 금속호일 등의 재료를 사용할 수 있다.4, the step of peeling the laminated structure thin film formed on the crystalline silicon substrate 11 from the crystalline silicon substrate 11 is followed by the step of peeling the thin film on the additional layer 17 It is possible to bond the different substrates 19 to each other. Materials such as silicon, quartz, sapphire, glass, plastic, and metal foil can be used for the different substrate 19.
이하 본 발명의 적층구조 박막 제조방법의 과정을 더욱 상세하게 설명한다. Hereinafter, the process of the laminated structure thin film manufacturing method of the present invention will be described in more detail.
결정형 실리콘 기판은 사전에 식각 또는 연마 방법으로 표면을 세정한 것을 준비한다. 식각은 습식 또는 진공 공정으로 진행할 수 있다. The crystalline silicon substrate is prepared by pre-etching or polishing the surface. The etching can proceed by wet or vacuum processes.
세정한 결정형 실리콘 기판은 CCP 플라즈마 구조의 플라즈마 반응장치의 챔버 내 상부 전극에 부착한다. The cleaned crystalline silicon substrate adheres to the upper electrode in the chamber of the plasma reactor of the CCP plasma structure.
이때, 상부 전극과 하부 전극 사이의 간격을 조절하거나 가스 유량비, 플라즈마 파워 등을 제어하고자 하는 공정 조건으로 설정할 수 있다.At this time, it is possible to set the process conditions for controlling the interval between the upper electrode and the lower electrode, controlling the gas flow rate ratio, plasma power, and the like.
다음으로, 상부 전극에 전압을 가하여 플라즈마를 발생시키면서 챔버 내로 전구체 가스, 불순물 등을 주입하여 결정형 실리콘 기판의 일면에 다공성 실리콘층을 증착하고 다공성 실리콘층의 증착 후, 다공성 실리콘층의 상면에 에피택시층을 증착한다.Next, a precursor gas, an impurity, or the like is injected into the chamber while applying a voltage to the upper electrode to generate a plasma to deposit a porous silicon layer on one surface of the crystalline silicon substrate, and after the deposition of the porous silicon layer, Layer.
전구체 가스는 SiH4, Si2H6, SiCl4, SiHCl3, SiF4 중 선택된 1종 이상을 H2 또는 He 가스에 희석시킨 것을 주입할 수 있으며, 불순물은 C, Ge, B, P, Al, As, O, N 중 선택된 1종 또는 2종 이상을 주입할 수 있다.The precursor gas may be one in which at least one selected from the group consisting of SiH 4 , Si 2 H 6 , SiCl 4 , SiHCl 3 and SiF 4 is diluted with H 2 or He gas, and the impurities are C, Ge, B, P, Al , As, O, and N can be injected.
전구체 가스는 SiH4 일 수 있으며, H2/SiH4의 희석비를 1~1000 범위에서 조절할 수 있다.Precursor gases are SiH may be 4, it is possible to adjust the dilution ratio of H 2 / SiH 4 from 1 to 1000 range.
다공성 실리콘층과 에피택시층의 증착시 실리콘 기판 온도를 200~950℃ 범위로 유지하여 결함 밀도가 낮은 재료를 합성할 수 있다.When the porous silicon layer and the epitaxial layer are deposited, the temperature of the silicon substrate can be maintained in the range of 200 to 950 ° C to synthesize a material having a low defect density.
다공성 실리콘층 증착시 가스 유량비 및 플라즈마 파워를 제어하여 밀도가 낮은 다공성 실리콘층을 형성할 수 있다.The porous silicon layer having a low density can be formed by controlling the gas flow rate ratio and the plasma power during the deposition of the porous silicon layer.
다공성 실리콘층 증착 후, 수소 플라즈마 처리를 더 수행하여 다공성 실리콘층의 공극률을 재조정할 수 있다. After deposition of the porous silicon layer, a hydrogen plasma treatment may be further performed to readjust the porosity of the porous silicon layer.
에피택시층 증착시 전구체 가스와 함께 불순물로 C, Ge 등의 4족 원소를 추가하여 합금 구조로 제작하거나, B, P, Al, As 등의 도펀트를 추가하여 전기전도도를 통제하거나, O, N 등의 불순물을 추가하여 유전체층을 제작할 수 있다.When the epitaxial layer is deposited, a precursor gas and a Group 4 element such as C and Ge may be added as an impurity to form an alloy structure. Alternatively, a dopant such as B, P, Al or As may be added to control the electric conductivity, Or the like can be added to fabricate the dielectric layer.
불순물 함량을 조절하기 위해 B2H6, B(CH3)3, BF3, PH3, AsH3, Al2(CH3)6 중 선택된 1종 이상의 가스를 첨가할 수 있다. 유전체층 제작을 위해서는 N2O, CO2, O2, NH3, N2 중 선택된 1종 이상의 가스를 더 첨가할 수 있다.One or more gases selected from B 2 H 6 , B (CH 3 ) 3 , BF 3 , PH 3 , AsH 3 and Al 2 (CH 3 ) 6 may be added to control the impurity content. For producing the dielectric layer, at least one gas selected from N 2 O, CO 2 , O 2 , NH 3 and N 2 can be further added.
상술한 방법에 의해 제조된 적층구조 박판을 열적, 기계적 응력을 가하여 결정형 실리콘 기판으로부터 박리한다.The laminated thin plate produced by the above-described method is subjected to thermal and mechanical stress to peel off from the crystalline silicon substrate.
상술한 적층구조 박판 제조방법은 증착 두께를 조절하여 100㎛ 이하 두께의 적층구조 박막 구현이 가능하므로 고품질의 실리콘 기판을 형성할 수 있다. 또한, 실리콘 기판에 박막을 직접 증착하므로 공정 단계를 단축할 수 있으며, 실리콘 기판 온도 1100℃ 이하에서 박막 형성이 가능하므로 공정 비용을 절감하여 상용화를 가능하게 하는 이점이 있다.The above-described method for manufacturing a laminated structure thin film can realize a laminated structure thin film having a thickness of 100 탆 or less by controlling the deposition thickness, and thus a high-quality silicon substrate can be formed. In addition, since the thin film is directly deposited on the silicon substrate, the process step can be shortened and the thin film can be formed at a temperature of the silicon substrate below 1100 ° C, which is advantageous in that the process cost can be reduced and commercialized.
상술한 적층구조 박막 제조방법은 태양전지 등의 반도체 소자 제조에 적용할 수 있다.The above-described laminated structure thin film manufacturing method can be applied to the manufacture of semiconductor devices such as solar cells.
본 발명은 도면과 명세서에 최적의 실시예들이 개시되었다. 여기서, 특정한 용어들이 사용되었으나, 이는 단지 본 발명을 설명하기 위한 목적에서 사용된 것이지 의미 한정이나 특허청구범위에 기재된 본 발명의 범위를 제한하기 위하여 사용된 것은 아니다. 그러므로 본 발명 기술분야의 통상의 지식을 가진 자라면, 이로부터 다양한 변형 및 균등한 타 실시예가 가능하다는 점을 이해할 것이다. 따라서, 본 발명의 진정한 기술적 권리범위는 첨부된 특허청구범위의 기술적 사상에 의해 정해져야 할 것이다. Best Mode for Carrying Out the Invention The present invention has been described with reference to the drawings and the specification. Although specific terms are used herein, they are used for the purpose of describing the present invention only and are not used to limit the scope of the present invention described in the meaning of the claims or the claims. Therefore, those skilled in the art will appreciate that various modifications and equivalent embodiments are possible without departing from the scope of the present invention. Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

Claims (15)

  1. 결정질 실리콘 기판의 일면에 다공성 실리콘층을 증착하는 단계;Depositing a porous silicon layer on one side of the crystalline silicon substrate;
    상기 다공성 실리콘층의 상면에 에피택시층을 증착하는 단계; 및Depositing an epitaxial layer on top of the porous silicon layer; And
    상기 에피택시층의 상면에 금속전극, 보호막, 접착촉진층 중 선택된 1종 이상으로 구성된 추가층을 적층하는 단계;를 포함하는 것을 특징으로 하는 적층구조 박막 제조방법.And laminating an additional layer comprising at least one selected from the group consisting of a metal electrode, a protective film and an adhesion promoting layer on the upper surface of the epitaxial layer.
  2. 청구항 1에 있어서, The method according to claim 1,
    상기 증착은 CCP(Capacitively Coupled Plasma) 반응에 의해 수행되는 것을 특징으로 하는 적층구조 박막 제조방법.Wherein the deposition is performed by a CCP (Capacitively Coupled Plasma) reaction.
  3. 청구항 1에 있어서, The method according to claim 1,
    상기 다공성 실리콘층의 상면에 에피택시층을 증착하는 단계에서,In the step of depositing an epitaxial layer on the upper surface of the porous silicon layer,
    상기 에피택시층은 실리콘 박막의 단일층이거나 상기 실리콘 박막에 불순물을 포함하는 단일층으로 성장하거나 불순물을 포함하는 적층구조로 성장하는 것을 특징으로 하는 적층구조 박막 제조방법.Wherein the epitaxial layer is a single layer of a silicon thin film or grown as a single layer containing an impurity in the silicon thin film or grown in a laminated structure containing impurities.
  4. 청구항 3에 있어서, The method of claim 3,
    상기 불순물을 포함하는 단일층 또는 상기 불순물을 포함하는 적층구조는,A single layer containing the impurity or a laminated structure including the impurity may be formed by,
    상기 불순물로 C, Ge 중 선택된 1종 이상을 포함하여 합금 구조로 제작하거나, The impurities may be made of an alloy structure including at least one selected from C and Ge,
    상기 불순물로 B, P, Al, As 중 선택된 1종 이상을 포함하여 전기전도도를 통제하거나, The impurities may include at least one selected from the group consisting of B, P, Al and As to control electric conductivity,
    상기 불순물로 O, N 중 선택된 1종 이상을 추가하여 유전체층을 제작하는 것을 특징으로 하는 적층구조 박막 제조방법.Wherein at least one selected from the group consisting of O and N is added as the impurity to form a dielectric layer.
  5. 청구항 2에 있어서, The method of claim 2,
    상기 플라즈마 공정 수행시,During the plasma process,
    상기 결정질 실리콘 기판 온도, 전구체 가스 비율, 공정압력 및 플라즈마 파워 중 선택된 1종 이상을 조절하여 상기 다공성 실리콘층과 상기 에피택시층의 밀도를 조절하는 것을 특징으로 하는 박막 제조 방법.Wherein the density of the porous silicon layer and the epitaxial layer is controlled by controlling at least one selected from the group consisting of the crystalline silicon substrate temperature, the precursor gas ratio, the process pressure, and the plasma power.
  6. 청구항 5에 있어서, The method of claim 5,
    상기 전구체 가스는 SiH4, Si2H6, SiCl4, SiHCl3, SiF4 중 선택된 1종 이상을 H2 또는 He 가스에 희석시킨 것을 사용하는 것을 특징으로 하는 박막 제조 방법.Wherein the precursor gas is one in which at least one selected from SiH 4 , Si 2 H 6 , SiCl 4 , SiHCl 3 and SiF 4 is diluted with H 2 or He gas.
  7. 청구항 5에 있어서, The method of claim 5,
    상기 플라즈마 공정 수행 후, 1100℃ 이하의 온도에서 수소 플라즈마 처리를 추가로 수행하여 상기 다공성 실리콘층의 공극률을 재조정하는 것을 특징으로 하는 박막 제조 방법.After the plasma process is performed, a hydrogen plasma treatment is further performed at a temperature of 1100 ° C or less to readjust the porosity of the porous silicon layer.
  8. 청구항 1에 있어서, The method according to claim 1,
    상기 에피택시층의 상면에 금속전극, 보호막, 접착촉진층 중 선택된 1종을 적층하는 단계 후,A step of laminating a selected one of a metal electrode, a protective film and an adhesion promoting layer on the upper surface of the epitaxial layer,
    상기 결정질 실리콘 기판에 형성된 적층구조 박막을 상기 결정질 실리콘 기판으로부터 박리하는 단계를 더 포함하는 것을 특징으로 하는 적층구조 박막 제조 방법.And peeling the laminated structure thin film formed on the crystalline silicon substrate from the crystalline silicon substrate.
  9. 청구항 8에 있어서, The method of claim 8,
    상기 적층구조 박막이 박리된 상기 결정질 실리콘 기판은 상기 적층구조 박막 형성을 위한 다음번 공정에 재활용하는 것을 특징으로 하는 적층구조 박막 제조 방법.Wherein the crystalline silicon substrate on which the laminated structure thin film is peeled is recycled in the next process for forming the laminated structure thin film.
  10. 청구항 1에 있어서, The method according to claim 1,
    상기 금속전극, 보호막, 접착촉진층 중 선택된 1종 이상으로 구성된 추가층의 상면에 실리콘, 석영, 사파이어, 유리, 플라스틱, 금속호일 중 선택된 1종 이상의 재료로 만들어진 이종기판을 접합하는 단계를 더 포함하는 것을 특징으로 하는 적층구조 박막 제조 방법.Further comprising the step of bonding a heterogeneous substrate made of at least one selected from the group consisting of silicon, quartz, sapphire, glass, plastic and metal foil on the upper surface of the additional layer composed of at least one selected from the metal electrode, the protective film and the adhesion promoting layer Wherein the thin film has a thickness of 100 nm or less.
  11. 청구항 1 내지 청구항 10 중 어느 한 항의 방법으로 제조된 것이며,Claims 1. A process for the preparation of a compound of formula < RTI ID = 0.0 > (I) < / RTI &
    다공성 실리콘층;A porous silicon layer;
    상기 다공성 실리콘층의 일면에 적층되는 에피택시층; 및An epitaxial layer deposited on one surface of the porous silicon layer; And
    상기 에피택시층의 상면에 적층되며 금속전극, 보호막, 접착촉진층 중 선택된 1종 이상으로 구성되는 추가층을 포함하는 것을 특징으로 하는 적층구조 박막.And an additional layer stacked on the upper surface of the epitaxial layer and composed of at least one selected from a metal electrode, a protective layer, and an adhesion promoting layer.
  12. 청구항 11에 있어서, The method of claim 11,
    상기 추가층은 접착촉진층이고, Said additional layer being an adhesion promoting layer,
    상기 접착촉진층의 상면에 이종기판이 접합되는 것을 특징으로 하는 적층구조 박막.Wherein a different substrate is bonded to the upper surface of the adhesion promoting layer.
  13. 청구항 11에 있어서, The method of claim 11,
    상기 에피택시층은 단일층 또는 불순물을 포함하는 적층구조인 것을 특징으로 하는 적층구조 박막.Wherein the epitaxial layer is a laminate structure including a single layer or an impurity.
  14. 청구항 13에 있어서, 14. The method of claim 13,
    상기 불순물은 C, Ge, B, P, Al, As, O, N 중 선택된 1종 또는 2종 이상인 것을 특징으로 하는 적층구조 박막.Wherein the impurities are one or more selected from the group consisting of C, Ge, B, P, Al, As, O and N.
  15. 청구항 1 내지 청구항 10 중 어느 한 항의 방법을 이용하여 적층구조 박막을 제조하고 기판으로 사용하는 것을 특징으로 하는 반도체 소자 제조방법.A method for fabricating a semiconductor device, wherein a laminated thin film is manufactured and used as a substrate by using the method of any one of claims 1 to 10.
PCT/KR2017/013292 2017-11-21 2017-11-21 Method for manufacturing thin film having layered structure, thin film having layered structure and manufactured thereby, and method for manufacturing semiconductor device by using same WO2019103168A1 (en)

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JPH10135500A (en) * 1996-03-18 1998-05-22 Sony Corp Manufacture of thin film semiconductor, solar cell and light emission element
JPH1131828A (en) * 1997-07-11 1999-02-02 Sony Corp Manufacture of semiconductor substrate
JP2000082643A (en) * 1999-07-30 2000-03-21 Canon Inc Semiconductor substrate and manufacture thereof
US20090001416A1 (en) * 2007-06-28 2009-01-01 National University Of Singapore Growth of indium gallium nitride (InGaN) on porous gallium nitride (GaN) template by metal-organic chemical vapor deposition (MOCVD)
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