WO2019088354A1

WO2019088354A1 - Insulated gate drive device

Info

Publication number: WO2019088354A1
Application number: PCT/KR2017/014851
Authority: WO
Inventors: 장성록; 김종수; 김형석; 유찬훈; 배정수
Original assignee: 한국전기연구원
Priority date: 2017-10-31
Filing date: 2017-12-15
Publication date: 2019-05-09
Also published as: KR20190048636A

Abstract

An insulated gate drive device is disclosed. The present invention provides an insulated gate drive device which, in driving a full bridge power supply circuit, transmits a driving signal and driving power to a driving circuit for driving respective semiconductor switching devices through a transformer, wherein the driving signal is chopped so as to repeatedly transmit signals with a short pulse width. As such, it is possible to provide an insulated gate driving device for driving a power supply capable of supplying DC to 8 KHz power while effectively reducing the size of the transformer by overcoming the limitations of transformers which are incapable of transmitting DC.

Description

Insulated gate drive

The present invention relates to an insulated gate drive apparatus, and more particularly, to an insulated gate drive apparatus used in a power supply apparatus for strategic mineral exploration.

Various examples of typical pulsed power supplies are well known in the art. For example, applicants of the present invention have disclosed techniques related to various pulse power devices such as Korean Patents 10-0820171, 10-1444734, 10-1739882, and the like.

Recently, a pulse power supply optimized for a specific field and a driving circuit thereof have been actively studied. Among them, a representative field is a pulsed power source using a strategic mineral resource probe.

Strategy Mineral resource exploitation Pulse power supply needs to supply variable output power of DC ~ 8Khz. However, in general, there is a problem that DC operation can not be performed in the case of a transformer used for outputting AC power.

The present applicant has considered a method of supplying a separate insulated power supply to a gate drive circuit for controlling a semiconductor switching device included in a pulse power supply device and transmitting a driving signal through an optical signal. In this case, however, a pulse power supply device There is a problem in that the circuit for oversizing becomes excessively complicated and thus the cost increases greatly.

A problem to be solved by the present invention is to provide an insulated gate drive device capable of driving a power supply device supplying a DC to 8 KHz power source with a relatively simple circuit configuration and low cost so that it can be used for strategic mineral exploration.

An insulated gate driving apparatus according to a preferred embodiment of the present invention for solving the above problems is an insulated gate driving apparatus for driving the gates of a plurality of semiconductor switching elements constituting a full bridge power supply circuit, A gate signal generator; A signal chopper for chopping the gate signal to generate a plurality of pulse signals; A first transformer and a second transformer having a primary side connected to the signal chopper and transferring the plurality of pulse signals to a secondary side; And a plurality of gate drive circuits respectively connected to the plurality of semiconductor switching elements for respectively driving semiconductor switching elements connected thereto according to the pulse voltage signal transmitted from the first transformer or the second transformer, The gate drive circuits connected to the same transformer among the gate drive circuits of the plurality of gate drive circuits alternately turn on and off the semiconductor switching elements by receiving pulse voltage signals of different polarities.

The plurality of gate drive circuits may be configured to receive the first pulse voltage signal from the secondary side of the first transformer and to drive the gate of the first semiconductor switching element connected between the first node of the power input stage and the first node of the power output stage A first gate drive circuit; A third gate for driving a gate of a third semiconductor switching element connected between a second node of the power input terminal and a first node of the power output terminal, receiving the pulse voltage signal of the opposite polarity from the first voltage signal from the secondary side of the first transformer, A drive circuit; A second gate drive circuit receiving a second pulse voltage signal from a secondary side of the second transformer and driving a gate of a second semiconductor switching element connected between a first node of the power input stage and a second node of the power output stage; And a fourth transistor for driving the gate of the fourth semiconductor switching element connected between the second node of the power input terminal and the second node of the power output terminal, receiving the voltage signal of the opposite polarity from the second pulse voltage signal from the secondary side of the second transformer, Gate drive circuit.

The gate signal generator adjusts the phase difference between the gate signal to be output to the first transformer and the gate signal to be output to the second transformer to control the width of the AC pulse output through the power output terminal of the full bridge power supply circuit .

The gate signal to be output to the first transformer and the gate signal to be output to the second transformer may have the same magnitude and pulse width.

The gate signal generator may have a polarity opposite to that of the gate signal to be output to the first transformer and the gate signal to be output to the second transformer so that the DC power is output through the power output terminal of the full- And the like.

Each of the plurality of gate drive circuits may further include: a first resistor and a second resistor connected in series across the secondary winding of the first transformer or the second transformer connected thereto to distribute the voltage; A first capacitor connected in parallel to both ends of the first resistor; A gate connected between the first resistor and the second resistor and connected between one end of the secondary side of the first transformer or the second transformer and a gate of the semiconductor switching element connected thereto, A first switching element which is turned on when a positive voltage signal is applied from the secondary side of the second transformer to turn on the semiconductor switching element and is turned off when a negative voltage signal is applied; A gate connected between the first resistor and the second resistor and connected between the other end of the secondary side of the first transformer or the second transformer and a source of the semiconductor switching element connected thereto, A second switching element which is turned off when a positive voltage signal is applied from the secondary side of the second transformer and is turned on when a negative voltage signal is applied; And a second capacitor connected between a gate and a source of the semiconductor switching device.

Each of the plurality of gate drive circuits may further include a first resistor and a second resistor connected in series across the secondary winding of the first transformer or the second transformer to distribute the voltage; A first capacitor connected in parallel to both ends of the first resistor; A first PMOS having a gate connected between the first resistor and the second resistor, a source connected to one end of the secondary winding, and a drain connected to a gate of the semiconductor switching element connected to the drain; A second PMOS having a gate connected between the first resistor and the second resistor, a source connected to the other end of the secondary winding, and a drain connected to a source of the semiconductor switching element connected to the drain; And a second capacitor coupled between a drain of the first PMOS and a drain of the second PMOS.

According to another aspect of the present invention, there is provided a power supply apparatus including: a gate signal generator for generating a gate signal; A signal chopper for chopping the gate signal to generate a plurality of pulse signals; A first transformer and a second transformer whose primary side is connected to the signal chopper to transfer the plurality of pulse signals to a secondary side, a plurality of semiconductor switching elements constituting a full bridge circuit, and a plurality of semiconductor switching elements And a plurality of gate drive circuits respectively connected to the first and second transformers and driving the semiconductor switching elements connected to the first and second transformers in accordance with a pulse voltage signal transmitted from the first transformer or the second transformer, The gate drive circuits connected to the same transformer among the circuits receive pulse voltage signals of different polarities and alternately turn on and off the semiconductor switching elements.

The plurality of power modules may be connected in series or in parallel, and the first transformer and the second transformer may be included in the power module based on a power input terminal of the full bridge circuit. Gate drive circuits for driving the semiconductor switching elements on one side of the semiconductor switching elements are connected to the secondary side of the first transformer and gate drive circuits for driving the semiconductor switching elements on the other side are connected to the second Can be connected to the vehicle side.

The gate signal generator may be configured such that a gate signal to be output to the first transformer and a gate signal to be output to the second transformer have a polarity opposite to that of the gate signal to be output to the second transformer so that DC power is output through a power output terminal of the full bridge circuit Can be generated as a DC signal.

In driving a full bridge power supply circuit, a driving signal and a driving power are transmitted to a driving circuit for driving each semiconductor switching device through a transformer. The driving signal is chopped to generate a short pulse width signal It is possible to provide an insulated gate driving apparatus for driving a power supply capable of supplying a DC power of 8 KHz while effectively reducing the size of a transformer by overcoming the limitations of a transformer that can not deliver DC .

FIG. 1 is a diagram showing a configuration of an insulated gate driving apparatus according to a preferred embodiment of the present invention.

2 is a view illustrating a process of operating an insulated gate driving apparatus according to a preferred embodiment of the present invention so as to output a positive DC power in a full bridge power supply circuit.

3 is a view illustrating a process of operating an insulated gate driving apparatus according to a preferred embodiment of the present invention so as to output negative DC power in a full bridge power supply circuit.

4 is a diagram illustrating an example of a gate drive circuit according to a preferred embodiment of the present invention.

5A and 5B are views illustrating an example of connecting the full bridge power supply circuit of the present invention in a serial or parallel manner according to a preferred embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

1, the insulated gate driving apparatus of the present invention includes a gate signal generator 10, a signal chopper (not shown) The first transformer 31, the second transformer 32 and the plurality of gate drive circuits 41 to 44, that is, the first gate drive circuits 41 to 44, 4 gate drive circuit 44 as shown in FIG. Here, each of the first gate drive circuit 41 to the fourth gate drive circuit 44 is connected so as to correspond to the first semiconductor switching element S1 to the fourth semiconductor switching element S4 constituting the full bridge power supply circuit .

The gate signal generator 10 generates a gate signal and outputs the gate signal to a signal chopper 20. The gate signal output from the gate signal generator 10 may be an alternating current pulse signal as shown in FIG. 1 or a direct current signal as shown in FIG. 2 and FIG. In the preferred embodiment of the present invention, the gate signal generator 10 includes a first gate signal for controlling the first semiconductor switching element S1 and the third semiconductor switching element S3, a second semiconductor switching element S2, And simultaneously generates and outputs a second gate signal for controlling the fourth semiconductor switching element S4.

The signal chopper 20 chops the gate signals inputted from the gate signal generator 10 in a short time period to generate a plurality of pulse signals as shown in FIGS. 1 to 3, And outputs the pulse signals to the first transformer 31 and the second transformer 32. The signal chopper 20 chops the first gate signal, outputs the first gate signal to the first transformer 31, chops the second gate signal, and outputs the chopped signal to the second transformer 32.

The first transformer 31 is connected to the signal chopper 20 on the primary side and the secondary side is connected to the first gate drive circuit 41 and the third gate drive circuit 43 so that the signal chopper 20 to the first gate drive circuit 41 and the third gate drive circuit 43 connected to the secondary side.

At this time, the first gate drive circuit 41 and the third gate drive circuit 43 generate a voltage signal having the same magnitude and opposite polarity by the pulse signal applied to the primary side of the first transformer 31, To the secondary side of the first transformer (31).

Likewise, the second transformer 32 is connected to the signal chopper 20 on the primary side and to the second gate drive circuit 42 and the fourth gate drive circuit 44 on the secondary side, And receives a plurality of pulse signals from the chopper 20 and transfers them to the second gate drive circuit 42 and the fourth gate drive circuit 44 connected to the secondary side.

At this time, the second gate drive circuit 42 and the fourth gate drive circuit 44 generate a voltage signal having the same magnitude and opposite polarity by the pulse signal applied to the primary side of the second transformer 32, To the secondary side of the second transformer (32).

The first to fourth gate drive circuits 41 to 44 are connected to the first to fourth semiconductor switching elements S1 to S4 constituting the full bridge power supply device, And turns on or off the semiconductor switching element connected thereto according to the signal.

In the preferred embodiment of the present invention shown in FIGS. 1 to 3, the first to fourth semiconductor switching elements S1 to S4 are implemented as NMOS FETs, and each of the gate drive circuits 41 to 44 is a semiconductor switching element To the gate and source of the transistor.

In the full bridge power supply apparatus to which the gate drive circuit of the present invention is applied, +1/2 Vdc is applied to the first input node 51 and -1/2 Vdc is applied to the second input node 52, Is input. In addition, the power supply unit outputs a voltage between the output-side first node 61 and the output-side second node 62.

1 to 3, the first semiconductor switching element S1 is connected between the power input terminal first node 51 and the power output terminal first node 61, and the third semiconductor switching element S1 S3 are connected between the power input terminal second node 52 and the power output terminal first node 61. [

The second semiconductor switching element S2 is connected between the first power supply input node 51 and the second power supply output node 62 and the fourth semiconductor switching element S4 is connected to the second power supply input node 52, And the second output node 62 of the power output stage.

First, referring to FIG. 1, the operation of the insulated gate driving apparatus according to the preferred embodiment of the present invention, in which the full bridge power supply receives DC power and outputs an AC power pulse, will be described. 10 outputs a gate signal in the form of an AC pulse to the signal chopper 20, as shown in Fig. 1 (b). The gate signal generator 10 includes a first gate signal Vgate1 for outputting to the first transformer 31 to control the semiconductor switching elements S1 and S3 and a second gate signal Vgate2 for controlling the semiconductor switching elements S2 and S4. The two gate signals are generated as AC pulse signals having the same magnitude and pulse width as each other, and the first gate signal Vgate1 and the second gate signal Vgate2 The width of the power pulse output through the first power supply output stage first node 61 and the power supply output stage second node 62, which will be described later, is adjusted.

1, the signal chopper 20 generates a plurality of pulse signals by chopping the gate signal for the first transformer 31 and the gate signal for the second transformer 32 in a short time period, Signals to the first transformer 31 and the second transformer 32, respectively. It is a matter of course that the chopping period of the signal chopper 20 can be changed according to a design specification required by the power supply device.

The pulse signals outputted from the signal chopper 20 are transmitted to the first gate drive circuit 41 to the fourth gate drive circuit 44 connected to the secondary side through the first transformer 31 and the second transformer 32 . As shown in Fig. 1, the first gate drive circuit 41 and the third gate drive circuit 43 are connected to the core of the first transformer 31 so that a voltage pulse signal having the opposite polarity of the same magnitude is transmitted. . Thus, the first gate drive circuit 41 and the third gate drive circuit 43 operate in opposite directions, and accordingly, the semiconductor switching elements S1 and S3 are alternately turned on and off.

Likewise, the second gate drive circuit 42 and the fourth gate drive circuit 44 are wound on the core of the second transformer 32 so that a voltage pulse signal having the same magnitude and opposite polarity is transmitted. Accordingly, the second gate drive circuit 42 and the fourth gate drive operate in opposite directions, and accordingly, the semiconductor switching elements S2 and S4 are alternately turned on and off.

First, in the time period T1, positive voltage pulses are transmitted to the first gate drive circuit 41 and the second gate drive circuit 42 so that the first semiconductor switching element and the third semiconductor switching element S3 are turned on do. On the other hand, negative voltage pulses are transmitted to the second gate drive circuit 42 and the fourth gate drive circuit 44 so that the second semiconductor switching element S2 and the fourth semiconductor switching element S4 are turned off . The operation of turning on and off the semiconductor switching elements S1 to S4 in the respective gate drive circuits 41 to 44 will be described later with reference to Fig. In this case, since there is no voltage difference between the power source output stage first node 61 and the power source output stage second node 62, the full bridge power source device outputs 0V.

Thereafter, in the time period T2, the voltage pulse transmitted to the first gate drive circuit 41 and the third gate drive circuit 43 through the first transformer 31 is the same as the time interval T1, The element S1 and the third semiconductor switching element S3 maintain the turn-on and turn-off states, respectively.

On the other hand, in the case of the second transformer 32, the gate pulse signals input from the signal chopper 20 to the primary side are changed from positive pulses to negative pulses, and accordingly, the secondary side of the second transformer 32 The voltage signal received by the second gate drive circuit 42 and the fourth gate drive connected to the second gate drive circuit 42 is also changed to a negative pulse voltage and a positive pulse voltage so that the second semiconductor switching element S2 is turned off, The semiconductor switching element S4 is turned on. Accordingly, the voltage difference between the power source output stage first node 61 and the power source output stage second node 62 becomes + Vdc, and the full bridge power source device outputs the power source pulse having the magnitude of + Vdc (Vout).

Thereafter, in the time period T3, since the voltage signals transmitted to the second gate drive circuit 42 and the fourth gate drive through the second transformer 32 are the same, the second semiconductor switching element S2 is turned off And the turn-on state of the fourth semiconductor switching element S4 remain unchanged

On the other hand, in the case of the first transformer 31, the gate pulse signals input from the signal chopper 20 to the primary side are changed from positive pulses to negative pulses, and accordingly, the secondary side of the first transformer 31 The voltage signal received by the first gate drive circuit 41 and the third gate drive connected to the first gate drive circuit 41 is also changed to a negative pulse voltage and a positive pulse voltage so that the first semiconductor switching element S1 is turned off, The semiconductor switching element S3 is turned on. Accordingly, since there is no voltage difference between the power supply output stage first node 61 and the power output stage second node 62, the full bridge power supply device outputs OV.

Thereafter, in the time period T4, the voltage signal transmitted through the first transformer 31 is kept equal to the time interval T3, so that the first semiconductor switching device S1 maintains the turn-off state, The switching element S3 maintains the turn-on state.

On the other hand, in the case of the second transformer 32, the gate pulse signals input to the primary side in the signal chopper 20 are changed from a negative pulse to a positive pulse, and accordingly, the secondary side of the second transformer 32 The voltage signal received by the second gate drive circuit 42 and the fourth gate drive circuit 44 connected to the second semiconductor switching element S2 is also changed to the positive pulse voltage and the negative pulse voltage, And the fourth semiconductor switching element S4 is turned off. Accordingly, the voltage difference between the power source output stage first node 61 and the power source output stage second node 62 becomes -Vdc, and the full bridge power source device outputs the power source pulse having the magnitude of -Vdc (Vout).

Thereafter, since the process after the time interval T5 is a repetition of the process after the time interval T1, redundant description will be omitted. The pulse width and the phase difference of the first gate signal and the second gate signal output from the gate signal generator 10 are adjusted to adjust the pulse width and the period of the pulse power supply Vout output from the full bridge power supply circuit It will be appreciated by those skilled in the art.

2, in order to continuously output positive DC power from the full bridge power supply circuit, the gate signal generator 10 generates a constant positive DC voltage as the gate signal Vgate1 output to the first transformer 31 And outputs a constant negative DC voltage as the gate signal Vgate2 to be output to the second transformer 32. [

The signal chopper 20 chops the gate signals inputted from the gate signal generator 10 and outputs the chopped signals to the first transformer 31 and the second transformer 32, respectively. As shown in FIG. 2, the signal chopper 20 continuously outputs positive pulse signals to the first transformer 31 and continuously outputs negative pulse signals to the second transformer 32.

The first transformer 31 receives the positive pulses and transfers them to the first gate drive circuit 41 and the third gate drive circuit 43. The first gate drive circuit 41 receives the positive voltage pulse The first semiconductor switching element S1 is turned on and the third gate drive circuit 43 receives the negative voltage pulse to turn off the third semiconductor switching element S3.

The first transformer 31 receives the negative pulses and transfers them to the second gate drive circuit 42 and the fourth gate drive circuit 44 and the second gate drive circuit 42 receives the negative voltage pulses The second semiconductor switching element S2 is turned off and the fourth gate drive circuit 44 receives the positive voltage pulse to turn on the fourth semiconductor switching element S4.

As a result, only the first semiconductor switching element S1 and the fourth semiconductor switching element S4 are maintained in the turned-on state as in the time period T2 of FIG. 1, and the

output terminals

61 and 62 of the full bridge power supply circuit + Vdc voltage is continuously output.

3, in order to continuously output negative DC power from the full bridge power supply circuit, the gate signal generator 10 generates a constant negative DC voltage as the gate signal Vgate1 output to the first transformer 31 And outputs a constant positive DC voltage as the gate signal Vgate2 to be output to the second transformer 32. [

The signal chopper 20 chops the gate signals inputted from the gate signal generator 10 and outputs the chopped signals to the first transformer 31 and the second transformer 32, respectively. As shown in FIG. 3, the signal chopper 20 continuously outputs negative pulse signals to the first transformer 31 and continuously outputs positive pulse signals to the second transformer 32.

The first transformer 31 receives the negative pulses and transfers them to the first gate drive circuit 41 and the third gate drive circuit 43. The first gate drive circuit 41 receives the negative voltage pulses The first semiconductor switching element S1 is turned off and the third gate drive circuit 43 receives the positive voltage pulse to turn on the third semiconductor switching element S3.

The second transformer 32 receives positive pulses and transfers them to the second gate drive circuit 42 and the fourth gate drive circuit 44 which receives a positive voltage pulse The second semiconductor switching element S2 is turned on and the fourth gate drive circuit 44 receives the negative voltage pulse to turn off the fourth semiconductor switching element S4.

As a result, only the second semiconductor switching element S2 and the third semiconductor switching element S3 are maintained in the turned-on state as in the time period T4 of FIG. 1, and the

output terminals

61 and 62 of the full bridge power supply circuit The voltage of -Vdc is continuously output (Vout).

4 is a diagram showing an example of gate drive circuits 41 to 44 according to a preferred embodiment of the present invention.

4, each of the gate drive circuits 41 to 44 according to the preferred embodiment of the present invention is connected in series to both ends of the secondary winding of the first transformer 31 or the second transformer 32, A first resistor R1 and a second resistor R2 for dividing the first and second resistors R1 and R2, a first capacitor C1 connected in parallel at both ends of the first resistor R1, A first PMOS M1 connected to one end of the secondary side winding and connected to a gate of the semiconductor switching element whose drain is connected to the first PMOS M1, a gate connected to the first resistor R1 and a second resistor R2 A second PMOS M2 connected to the source of the semiconductor switching device having a source connected to the other end of the secondary winding and a drain connected to the drain of the first PMOS M1 and a drain of the second PMOS And a second capacitor C2 connected between the drains of the transistors M2 and M2.

Referring to FIG. 4, the operation of the gate drive circuits 41 to 44 according to the preferred embodiment of the present invention will be described. First, a positive voltage pulse is applied through the first transformer 31 or the second transformer 32 The current flows from the first resistor R1 to the second resistor R2 and the voltage of the first resistor R1 and the second resistor R2 causes the gate of the second PMOS M2 The second PMOS M2 is turned off because a high voltage is applied. In the case of the first PMOS (M1), a voltage higher than the gate is applied to the source, which turns on. At this time, the first capacitor C1 makes a time delay between the time when the second PMOS M2 is turned off and the time when the first PMOS M1 is turned on. That is, the first PMOS M1 is turned on after the second PMOS M2 is turned off.

When the first PMOS M1 is turned on, a voltage is applied to the gate of the semiconductor switching element connected to the gate drive circuits 41 to 44 simultaneously with the charging of the second capacitor C2 to turn on the semiconductor switching element implemented by the NMOS .

Thereafter, even if the positive voltage pulse disappears, the gate voltage can be maintained for a predetermined time through the voltage charged in the second capacitor C2. By applying the repetitive positive voltage pulse, the gate drive circuits 41 to 44 are connected The gate voltage of the semiconductor switching element can be maintained.

On the other hand, when a negative voltage pulse is applied, the second PMOS M2 is turned on and the first PMOS M1 is turned off, thereby turning off the semiconductor switching elements to which the gate drive circuits 41 to 44 are connected.

5A and 5B, the full bridge power supply circuits shown in FIGS. 1 to 3 are each modularized, and the + terminal and the - terminal of each power output terminal are connected and connected in series (see FIG. 5A) Terminals of the output terminal and the terminals of the output terminal can be connected and connected in parallel (see FIG. 5B).

That is, the first and second transformers, the plurality of semiconductor switching elements connected in the form of a full bridge, and the plurality of semiconductor switching elements are connected to the first and second transformers, respectively, And a plurality of gate drive circuits for driving the switching elements, respectively. The plurality of power modules may be connected in series or in parallel.

At this time, only one gate signal generator 10 and one signal chopper 20 are provided in the entire power supply, and the pulse signals output from the signal chopper 20 are simultaneously supplied to the primary side of the transformers included in the respective power supply modules The entire module can be controlled at once.

The present invention has been described with reference to the preferred embodiments. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. Therefore, the disclosed embodiments should be considered in an illustrative rather than a restrictive sense. The scope of the present invention is defined by the appended claims rather than by the foregoing description, and all differences within the scope of equivalents thereof should be construed as being included in the present invention.

Claims

An insulated gate drive apparatus for driving gates of a plurality of semiconductor switching elements constituting a full bridge power supply circuit,

A gate signal generator for generating a gate signal;

A signal chopper for chopping the gate signal to generate a plurality of pulse signals;

A first transformer and a second transformer having a primary side connected to the signal chopper and transferring the plurality of pulse signals to a secondary side; And

And a plurality of gate drive circuits respectively connected to the plurality of semiconductor switching elements and each driving a semiconductor switching element connected thereto according to a pulse voltage signal transmitted from the first transformer or the second transformer,

Wherein the gate drive circuits connected to the same transformer among the plurality of gate drive circuits alternately turn on and off the semiconductor switching elements by receiving pulse voltage signals of different polarities.
The semiconductor memory device according to claim 1, wherein the plurality of gate drive circuits

A first gate drive circuit receiving a first pulse voltage signal from a secondary side of the first transformer and driving a gate of a first semiconductor switching element connected between a first node of a power input terminal and a first node of a power output terminal;

A third gate for driving a gate of a third semiconductor switching element connected between a second node of the power input terminal and a first node of the power output terminal, receiving the pulse voltage signal of the opposite polarity from the first voltage signal from the secondary side of the first transformer, A drive circuit;

A second gate drive circuit receiving a second pulse voltage signal from a secondary side of the second transformer and driving a gate of a second semiconductor switching element connected between a first node of the power input stage and a second node of the power output stage; And

And a fourth gate for driving the gate of the fourth semiconductor switching element connected between the second node of the power input terminal and the second node of the power output terminal, receiving the voltage signal of the opposite polarity from the second pulse voltage signal from the secondary side of the second transformer, And a drive circuit.
3. The apparatus as claimed in claim 1 or 2, wherein the gate signal generator

Wherein the control circuit adjusts the phase difference between the gate signal to be output to the first transformer and the gate signal to be output to the second transformer to control the width of the AC pulse output through the power output terminal of the full bridge power supply circuit. drive.
The method of claim 3,

Wherein the gate signal to be output to the first transformer and the gate signal to be output to the second transformer have the same magnitude and pulse width.
3. The apparatus as claimed in claim 1 or 2, wherein the gate signal generator

And a direct-current power source is connected to a power output terminal of the full-

Wherein the gate signal to be outputted to the first transformer and the gate signal to be outputted to the second transformer are generated as a DC signal having polarities opposite to each other.
3. The method according to claim 1 or 2,

Wherein each of the plurality of gate drive circuits includes:

A first resistor and a second resistor connected in series to both ends of the secondary winding of the first transformer or the second transformer connected thereto to distribute the voltage;

A first capacitor connected in parallel to both ends of the first resistor;

A gate connected between the first resistor and the second resistor and connected between one end of the secondary side of the first transformer or the second transformer and a gate of the semiconductor switching element connected thereto, A first switching element which is turned on when a positive voltage signal is applied from the secondary side of the second transformer to turn on the semiconductor switching element and is turned off when a negative voltage signal is applied;

A gate connected between the first resistor and the second resistor and connected between the other end of the secondary side of the first transformer or the second transformer and a source of the semiconductor switching element connected thereto, A second switching element which is turned off when a positive voltage signal is applied from the secondary side of the second transformer and is turned on when a negative voltage signal is applied; And

And a second capacitor connected between a gate and a source of the semiconductor switching device.
3. The method according to claim 1 or 2,

Wherein each of the plurality of gate drive circuits includes:

A first resistor and a second resistor connected in series across the secondary winding of the first transformer or the second transformer to distribute the voltage;

A first capacitor connected in parallel to both ends of the first resistor;

A first PMOS having a gate connected between the first resistor and the second resistor, a source connected to one end of the secondary winding, and a drain connected to a gate of the semiconductor switching element connected to the drain;

A second PMOS having a gate connected between the first resistor and the second resistor, a source connected to the other end of the secondary winding, and a drain connected to a source of the semiconductor switching element connected to the drain; And

And a second capacitor coupled between a drain of the first PMOS and a drain of the second PMOS.
A gate signal generator for generating a gate signal;

A signal chopper for chopping the gate signal to generate a plurality of pulse signals; And

A first transformer and a second transformer, the primary side of which is connected to the signal chopper to transfer the plurality of pulse signals to the secondary side,

A plurality of semiconductor switching elements constituting a full bridge circuit, and

And a plurality of gate drive circuits respectively connected to the plurality of semiconductor switching elements and driving the semiconductor switching elements connected to the plurality of semiconductor switching elements in accordance with the pulse voltage signal transmitted from the first transformer or the second transformer and,

Wherein the gate drive circuits connected to the same transformer among the plurality of gate drive circuits alternately turn on and off the semiconductor switching elements by receiving pulse voltage signals of different polarities.
9. The method of claim 8,

A plurality of power modules are provided, a plurality of power modules are connected to each other in series or in parallel,

Wherein the first transformer and the second transformer comprise:

Gate drive circuits for driving semiconductor switching elements on one side of the semiconductor switching elements included in the power supply module are connected to the secondary side of the first transformer with reference to the power input terminal of the full bridge circuit, And the gate drive circuits driving the switching elements are connected to the secondary side of the second transformer.
10. The apparatus of claim 8 or 9, wherein the gate signal generator

And adjusts a width of an AC pulse output through a power output terminal of the full bridge power circuit by adjusting a phase difference between a gate signal to be output to the first transformer and a gate signal to be output to the second transformer.
11. The method of claim 10,

Wherein the gate signal to be output to the first transformer and the gate signal to be output to the second transformer have the same magnitude and pulse width.
10. The apparatus of claim 8 or 9, wherein the gate signal generator

And a DC power supply is connected to the power supply output terminal of the full bridge circuit,

Wherein the gate signal to be output to the first transformer and the gate signal to be output to the second transformer are generated as a DC signal having polarities opposite to each other.
10. The method according to claim 8 or 9,

Wherein each of the plurality of gate drive circuits includes:

A first resistor and a second resistor connected in series to both ends of the secondary winding of the first transformer or the second transformer connected thereto to distribute the voltage;

A first capacitor connected in parallel to both ends of the first resistor;

A gate connected between the first resistor and the second resistor and connected between one end of the secondary side of the first transformer or the second transformer and a gate of the semiconductor switching element connected thereto, A first switching element which is turned on when a positive voltage signal is applied from the secondary side of the second transformer to turn on the semiconductor switching element and is turned off when a negative voltage signal is applied;

A gate connected between the first resistor and the second resistor and connected between the other end of the secondary side of the first transformer or the second transformer and a source of the semiconductor switching element connected thereto, A second switching element which is turned off when a positive voltage signal is applied from the secondary side of the second transformer and is turned on when a negative voltage signal is applied; And

And a second capacitor connected between a gate and a source of the semiconductor switching element.
10. The method according to claim 8 or 9,

Wherein each of the plurality of gate drive circuits includes:

A first resistor and a second resistor connected in series across the secondary winding of the first transformer or the second transformer to distribute the voltage;

A first capacitor connected in parallel to both ends of the first resistor;

A first PMOS having a gate connected between the first resistor and the second resistor, a source connected to one end of the secondary winding, and a drain connected to a gate of the semiconductor switching element connected to the drain;

A second PMOS having a gate connected between the first resistor and the second resistor, a source connected to the other end of the secondary winding, and a drain connected to a source of the semiconductor switching element connected to the drain; And

And a second capacitor coupled between a drain of the first PMOS and a drain of the second PMOS.