WO2019085919A1 - Depression region treatment method for shallow trench isolation structure, and semiconductor device - Google Patents

Depression region treatment method for shallow trench isolation structure, and semiconductor device Download PDF

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WO2019085919A1
WO2019085919A1 PCT/CN2018/112839 CN2018112839W WO2019085919A1 WO 2019085919 A1 WO2019085919 A1 WO 2019085919A1 CN 2018112839 W CN2018112839 W CN 2018112839W WO 2019085919 A1 WO2019085919 A1 WO 2019085919A1
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silicon oxide
shallow trench
trench isolation
isolation structure
region
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PCT/CN2018/112839
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French (fr)
Chinese (zh)
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张松
梁志彬
刘涛
金炎
王德进
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无锡华润上华科技有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers

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  • the present invention relates to the field of semiconductor manufacturing, and in particular to a method for processing a recessed region of a Shallow Trench Isolation (STI) structure, and to a semiconductor component.
  • STI Shallow Trench Isolation
  • Factors affecting the rounding of the apex angle include the angle of the bevel of the trench, the film thickness of the pad oxide layer (Line Oxide) and the temperature of the oxidation step of the bottom oxide layer. It is also affected by the quality of the SiO 2 filled with STI, the most important being the wet etch rate of SiO 2 by HF. The lower the rate at which the SiO 2 layer is etched by HF, the less the divot phenomenon will be.
  • Quality factors SiO 2 layer mainly affect the selective deposition process SiO 2 layer, and subsequent tempering SiO (Anneal) 2 layers conditions, such as temperature, time and environment. Similarly, the CMP of the STI SiO 2 layer does not appear to be concave, which would otherwise worsen the problem of SiO 2 divot.
  • the current deep sub-micron integrated circuit process has formed a complex process in this respect.
  • a new process will carefully select and pass many experiments to reduce the influence of divot until it can be The extent of acceptance. For example, from the rounding of the top corner of the STI, the quality of the STI-filled SiO 2 , the CMP thickness control of the SiO 2 layer, the amount of wet etching in the process, and the like, the steps are carefully controlled to reduce the divot, often requiring multiple experiments. Even if it is learned, it still can't completely solve the problem of divot, but it also takes a lot of time and cost, and may bring other unpredictable side effects.
  • a method of processing a recessed region of a shallow trench isolation structure and a semiconductor component are provided.
  • a method for processing a recessed region of a shallow trench isolation structure includes: providing a wafer having a shallow trench isolation structure formed on a substrate, and forming a recessed region at an interface with the active region on an upper surface of the shallow trench isolation structure Depositing silicon oxide on the surface of the wafer, and the silicon oxide fills the recessed region; dry etching the deposited silicon oxide to control the etching depth to expose the substrate The surface of the region can again retain the silicon oxide filled in the recessed region; the gate oxide layer is thermally oxidized on the surface of the active region.
  • a semiconductor component comprising a substrate, a shallow trench isolation structure on the substrate, a gate oxide layer on a surface of the active region of the substrate, and a polysilicon gate on the gate oxide layer, the shallow trench isolation structure
  • the surface is formed with a recessed region at the interface with the active region, and the recessed region is filled with silicon oxide.
  • FIG. 1 is a flow chart of a method for processing a recessed region of a shallow trench isolation structure in an embodiment
  • FIG. 2 is a schematic cross-sectional view of the wafer when the step S110 of FIG. 1 is completed;
  • FIG. 3 is a schematic cross-sectional view of the wafer when the step S120 of FIG. 1 is completed;
  • FIG. 4 is a schematic cross-sectional view of the wafer when the step S140 of FIG. 1 is completed;
  • FIG. 5 is a schematic cross-sectional structural view of a wafer after depositing polysilicon
  • FIG. 6 is a schematic diagram of a conventional technique in which gate polysilicon is filled into a Divot to form a parasitic transistor.
  • the vocabulary of the semiconductor field used in the present specification is a technical vocabulary commonly used by those skilled in the art.
  • the P+ type represents a P-type of a heavily doped concentration
  • the P-type represents P-type with medium doping concentration
  • P-type represents P type with light doping concentration
  • N+ type represents N type with heavy doping concentration
  • N type represents N type with medium doping concentration
  • N-type represents light doping concentration N type.
  • FIG. 1 is a flow chart of a method for processing a recessed area of a shallow trench isolation structure in an embodiment, comprising the following steps:
  • a shallow trench isolation structure 20 is formed on the substrate 10. Due to the limitation of the process level, the upper surface of the shallow trench isolation structure 20 forms a recess 21 at the interface with the active region A.
  • the formed components are laterally structured, and the recessed regions 21 are formed on both sides in the X-axis direction of FIG. 2, and the source and drain of the components are connected.
  • the line direction is the Y axis in FIG. 2, that is, the line direction between the recessed areas 21 is perpendicular to the line direction between the source and the drain.
  • a suitable thickness of silicon oxide is deposited such that recessed regions 21 (not labeled in Figure 3) are filled with silicon oxide 30.
  • a dry etching process is employed. By controlling the etching depth so that the silicon oxide 30 is etched, both the surface of the active region A of the substrate 10 is exposed, and the silicon oxide 30 filled in the recessed region 21 is retained as much as possible.
  • the etch depth is controlled by controlling the etch time of the dry etch.
  • the gate oxide layer 40 when the gate oxide layer 40 is thermally oxidized, the sidewalls on both sides of the active region A do not grow the gate oxide layer due to the presence of the silicon oxide 30.
  • the recessed region processing method of the shallow trench isolation structure fills the recessed region 21 formed at the boundary on the upper surface of the shallow trench isolation structure 20 by depositing silicon oxide, so that no large space is left to cause the polysilicon to fill the recessed region. 21; and when the gate oxide layer 40 is thermally oxidized, the sidewall of the active region A is covered by the deposited silicon oxide 30 and is not exposed to the air, so that the sidewall does not grow the gate oxide layer, and the recess region 21 In other words, parasitic transistors are not formed, and leakage due to the parasitic transistor can be avoided.
  • step S140 further includes the step of depositing polysilicon on the surface of the wafer.
  • the recessed region 21 (not shown in FIG. 5) is filled with the silicon oxide 30. It can be understood that in the actual production, the middle portion of the surface of the silicon oxide 30 may not completely fill and form a gap, and a small amount of polysilicon 50 will be filled into the gap. However, because the gap is small, it will not have a significant impact on the components.
  • the step of etching the polysilicon to form a polysilicon gate is further included.
  • step S120 is to deposit a high temperature oxide film (HTO).
  • HTO high temperature oxide film
  • Many semiconductor devices include HTO steps in the front stage of the manufacturing process, so the HTO process is easy to be compatible with existing manufacturing processes and cost-effective. Moreover, the HTO is generated for the furnace tube, and the defect is less, which also makes the compatibility of the HTO with most processes better.
  • step S120 may also employ other deposition processes, such as deposition using TEOS (orthosilicate) as a gas source.
  • TEOS orthosilicate
  • the thickness h of the silicon oxide 30 deposited in step S120 is more than 40% of the depth of the recessed region 21.
  • the thickness h is 40% to 60% of the depth of the recessed portion 21, and is usually set to about half of the depth of the recessed portion 21.
  • the present invention also provides a semiconductor component including a substrate, a shallow trench isolation structure on the substrate, a gate oxide layer on the surface of the active region of the substrate, and a polysilicon gate on the gate oxide layer, shallow trench
  • the upper surface of the isolation structure is formed with a recessed portion (Divot) at a boundary with the active region, and the recessed region is filled with silicon oxide.
  • the divot formed on the upper surface of the shallow trench isolation structure is filled with silicon oxide, so that a large amount of polysilicon is not filled in the recessed region, so that parasitic transistors are not formed in the recessed region. The leakage caused by the parasitic transistor can be avoided.
  • the silicon oxide in the recessed regions is formed by a deposition process.
  • the deposition process is to deposit a high temperature oxide film.

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Abstract

A depression region treatment method for a shallow trench isolation structure, and a semiconductor device. The method comprises: providing a wafer having a shallow trench isolation structure formed on a substrate, wherein a depression region is formed at the junction of the upper surface of the shallow trench isolation structure and an active region; depositing silicon oxide on the surface of the wafer, and fully filling the depression region with silicon oxide; dry etching the deposited silicon oxide, and controlling the etch depth to not only expose the surface of the active region of the substrate, but also retain as much as possible the silicon oxide with which the depression region is filled; and performing thermal oxidation on the surface of the active region to grow a gate oxide layer.

Description

浅沟槽隔离结构的凹陷区处理方法及半导体元器件Method for processing depressed area of shallow trench isolation structure and semiconductor component 技术领域Technical field
本发明涉及半导体制造领域，特别是涉及一种浅沟槽隔离(Shallow Trench Isolation,STI)结构的凹陷区处理方法，还涉及一种半导体元器件。The present invention relates to the field of semiconductor manufacturing, and in particular to a method for processing a recessed region of a Shallow Trench Isolation (STI) structure, and to a semiconductor component.
背景技术Background technique
在当前的亚微米工艺中，浅沟槽隔离技术被普遍应用。STI技术明显缩减了隔离区域的面积，提供了极小的有源区侵入及更平坦的表面。但由于局部应力集中，很容易会在STI界面处(SiO 2接近硅的有源区域)的角边缘过度腐蚀填充的氧化层而形成一凹陷区，一般称为“Divot”。这种“Divot”现象导致晶体管栅极在跨越STI与有源区域时，组成栅极的多晶硅会填入STI SiO 2表面divot的区域，而在该处产生一个寄生器件(Parasitic device)，参见图6。因为这个寄生晶体管的开启电压Vt比原来设计的正常晶体管Vt低很多，在正常晶体管操作时会产生额外的漏电。这种“Divot”现象也会造成晶体管栅极腐蚀时更容易出现residue(残留物)缺陷等。 In the current sub-micron process, shallow trench isolation technology is commonly used. STI technology significantly reduces the area of the isolated area, providing minimal active area intrusion and a flatter surface. However, due to local stress concentration, it is easy to excessively etch the filled oxide layer at the corner edge of the STI interface (SiO 2 close to the active region of silicon) to form a recessed region, generally referred to as "Divot". This "Divot" phenomenon causes the transistor gate to span the STI and the active region, and the polysilicon that makes up the gate fills the surface of the STI SiO 2 surface divot, where a parasitic device is created, see figure 6. Since the turn-on voltage Vt of this parasitic transistor is much lower than the original designed transistor Vt, additional leakage occurs during normal transistor operation. This "Divot" phenomenon can also cause residue defects in the transistor gate corrosion.
基本上，当STI的顶角圆化效果越好时，divot的现象就越轻微。影响顶角圆化的因素包括沟渠的斜角角度、垫氧化层(Pad Oxide)及亲底氧化层(Liner Oxide)的膜厚度和亲底氧化层氧化步骤的温度等。还会受STI填充的SiO 2的品质影响，最重要的是HF对该SiO 2的湿蚀刻速率。该SiO 2层被HF蚀刻的速率越低，则divot现象会越轻微。影响SiO 2层品质的因素主要有该SiO 2层淀积工艺的选择，及后续SiO 2层的回火(Anneal)条件，如温度、时间及环境等。同样，STI SiO 2层的CMP，也不能出现盘凹的现象，否则也会让SiO 2divot的问题恶化。 Basically, the better the divot is when the rounding effect of the STI is better. Factors affecting the rounding of the apex angle include the angle of the bevel of the trench, the film thickness of the pad oxide layer (Line Oxide) and the temperature of the oxidation step of the bottom oxide layer. It is also affected by the quality of the SiO 2 filled with STI, the most important being the wet etch rate of SiO 2 by HF. The lower the rate at which the SiO 2 layer is etched by HF, the less the divot phenomenon will be. Quality factors SiO 2 layer mainly affect the selective deposition process SiO 2 layer, and subsequent tempering SiO (Anneal) 2 layers conditions, such as temperature, time and environment. Similarly, the CMP of the STI SiO 2 layer does not appear to be concave, which would otherwise worsen the problem of SiO 2 divot.
当前的深亚微米集成电路工艺在这方面已经形成一套复杂的工艺方法， 一个新的工艺会在已有的多种方法中仔细的选择并通过多次的实验来减少divot的影响、直到可接受的程度。例如从STI的顶角圆化、STI填充的SiO 2的品质、SiO 2层的CMP厚度控制，工艺中湿法腐蚀的量等多个步骤小心地控制来减少divot，常常需要通过多次的实验甚至推倒重来，但往往仍不能完全解决divot的问题，同时又需要花费大量的时间与成本，并可能带来其它不可预测的副作用。 The current deep sub-micron integrated circuit process has formed a complex process in this respect. A new process will carefully select and pass many experiments to reduce the influence of divot until it can be The extent of acceptance. For example, from the rounding of the top corner of the STI, the quality of the STI-filled SiO 2 , the CMP thickness control of the SiO 2 layer, the amount of wet etching in the process, and the like, the steps are carefully controlled to reduce the divot, often requiring multiple experiments. Even if it is reinvented, it still can't completely solve the problem of divot, but it also takes a lot of time and cost, and may bring other unpredictable side effects.
发明内容Summary of the invention
根据本申请的各实施例，提供一种浅沟槽隔离结构的凹陷区处理方法和一种半导体元器件。According to various embodiments of the present application, a method of processing a recessed region of a shallow trench isolation structure and a semiconductor component are provided.
一种浅沟槽隔离结构的凹陷区处理方法，包括：提供在衬底上形成有浅沟槽隔离结构的晶圆，且浅沟槽隔离结构上表面在与有源区交界处形成有凹陷区；在所述晶圆表面淀积氧化硅，且所述氧化硅填满所述凹陷区；干法刻蚀淀积的所述氧化硅，通过控制刻蚀深度使得既能露出衬底的有源区表面、又能尽量保留所述凹陷区内填充的氧化硅；在所述有源区表面热氧化生长栅氧化层。A method for processing a recessed region of a shallow trench isolation structure includes: providing a wafer having a shallow trench isolation structure formed on a substrate, and forming a recessed region at an interface with the active region on an upper surface of the shallow trench isolation structure Depositing silicon oxide on the surface of the wafer, and the silicon oxide fills the recessed region; dry etching the deposited silicon oxide to control the etching depth to expose the substrate The surface of the region can again retain the silicon oxide filled in the recessed region; the gate oxide layer is thermally oxidized on the surface of the active region.
一种半导体元器件，包括衬底、衬底上的浅沟槽隔离结构、衬底的有源区表面上的栅氧化层、以及栅氧化层上的多晶硅栅，所述浅沟槽隔离结构上表面在与有源区交界处形成有凹陷区，所述凹陷区内被氧化硅填充。A semiconductor component comprising a substrate, a shallow trench isolation structure on the substrate, a gate oxide layer on a surface of the active region of the substrate, and a polysilicon gate on the gate oxide layer, the shallow trench isolation structure The surface is formed with a recessed region at the interface with the active region, and the recessed region is filled with silicon oxide.
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其它特征、目的和优点将从说明书、附图以及权利要求书变得明显。Details of one or more embodiments of the present application are set forth in the accompanying drawings and description below. Other features, objects, and advantages of the invention will be apparent from the description and appended claims.
附图说明DRAWINGS
图1是一实施例中浅沟槽隔离结构的凹陷区处理方法的流程图；1 is a flow chart of a method for processing a recessed region of a shallow trench isolation structure in an embodiment;
图2为图1步骤S110完成时晶圆的剖面结构示意图；2 is a schematic cross-sectional view of the wafer when the step S110 of FIG. 1 is completed;
图3为图1步骤S120完成时晶圆的剖面结构示意图；3 is a schematic cross-sectional view of the wafer when the step S120 of FIG. 1 is completed;
图4为图1步骤S140完成时晶圆的剖面结构示意图；4 is a schematic cross-sectional view of the wafer when the step S140 of FIG. 1 is completed;
图5为淀积多晶硅后晶圆的剖面结构示意图；5 is a schematic cross-sectional structural view of a wafer after depositing polysilicon;
图6为传统技术中栅极多晶硅填入Divot形成寄生晶体管的示意图。FIG. 6 is a schematic diagram of a conventional technique in which gate polysilicon is filled into a Divot to form a parasitic transistor.
具体实施方式Detailed ways
为了便于理解本发明，下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的首选实施例。但是，本发明可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本发明的公开内容更加透彻全面。In order to facilitate the understanding of the present invention, the present invention will be described more fully hereinafter with reference to the accompanying drawings. Preferred embodiments of the invention are given in the drawings. However, the invention may be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and comprehensive.
除非另有定义，本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本发明。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。All technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs, unless otherwise defined. The terminology used in the description of the present invention is for the purpose of describing particular embodiments and is not intended to limit the invention. The term "and/or" used herein includes any and all combinations of one or more of the associated listed items.
本说明书所使用的半导体领域词汇为本领域技术人员常用的技术词汇，例如对于P型和N型杂质，为区分掺杂浓度，简易的将P+型代表重掺杂浓度的P型，P型代表中掺杂浓度的P型，P-型代表轻掺杂浓度的P型，N+型代表重掺杂浓度的N型，N型代表中掺杂浓度的N型，N-型代表轻掺杂浓度的N型。The vocabulary of the semiconductor field used in the present specification is a technical vocabulary commonly used by those skilled in the art. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, the P+ type represents a P-type of a heavily doped concentration, and the P-type represents P-type with medium doping concentration, P-type represents P type with light doping concentration, N+ type represents N type with heavy doping concentration, N type represents N type with medium doping concentration, and N-type represents light doping concentration N type.
图1是一实施例中浅沟槽隔离结构的凹陷区处理方法的流程图，包括下列步骤：1 is a flow chart of a method for processing a recessed area of a shallow trench isolation structure in an embodiment, comprising the following steps:
S110，提供在衬底上形成有STI及Divot的晶圆。S110, providing a wafer on which STI and Divot are formed on a substrate.
参见图2，衬底10上形成有浅沟槽隔离结构20。因工艺水平的限制，浅沟槽隔离结构20上表面在与有源区A的交界处形成了凹陷区(Divot)21。在一个实施例中，与图6中的结构一样，形成的元器件是横向结构的，凹陷区21是形成于图2中X轴方向的两侧，而元器件的源极和漏极的连线方向是图2中Y轴，即凹陷区21之间的连线方向垂直于源漏之间的连线方向。Referring to FIG. 2, a shallow trench isolation structure 20 is formed on the substrate 10. Due to the limitation of the process level, the upper surface of the shallow trench isolation structure 20 forms a recess 21 at the interface with the active region A. In one embodiment, as in the structure of FIG. 6, the formed components are laterally structured, and the recessed regions 21 are formed on both sides in the X-axis direction of FIG. 2, and the source and drain of the components are connected. The line direction is the Y axis in FIG. 2, that is, the line direction between the recessed areas 21 is perpendicular to the line direction between the source and the drain.
S120，在晶圆表面淀积氧化硅，且氧化硅填满凹陷区。S120, depositing silicon oxide on the surface of the wafer, and the silicon oxide fills the recessed region.
参见图3，淀积合适厚度的氧化硅，使得凹陷区21(图3中未标示)被 氧化硅30填满。Referring to Figure 3, a suitable thickness of silicon oxide is deposited such that recessed regions 21 (not labeled in Figure 3) are filled with silicon oxide 30.
S130，干法刻蚀淀积的氧化硅，露出衬底的有源区表面且尽量保留凹陷区内填充的氧化硅。S130, dry etching the deposited silicon oxide to expose the surface of the active region of the substrate and to retain as much as possible of the filled silicon oxide in the recessed region.
为了尽量保证凹陷区21内填充的氧化硅30不被刻蚀掉，采用干法刻蚀工艺。通过控制刻蚀深度使得氧化硅30被刻蚀后，既能保证衬底10的有源区A表面露出，又能尽量保留凹陷区21内填充的氧化硅30。In order to ensure that the silicon oxide 30 filled in the recessed region 21 is not etched as much as possible, a dry etching process is employed. By controlling the etching depth so that the silicon oxide 30 is etched, both the surface of the active region A of the substrate 10 is exposed, and the silicon oxide 30 filled in the recessed region 21 is retained as much as possible.
在一个实施例中，通过控制干法刻蚀的刻蚀时间，来控制刻蚀深度。In one embodiment, the etch depth is controlled by controlling the etch time of the dry etch.
S140，在有源区表面热氧化生长栅氧化层。S140, thermally oxidizing the gate oxide layer on the surface of the active region.
参见图4，热氧化生长栅氧化层40时，有源区A两边的侧壁由于氧化硅30的存在，不会生长栅氧化层。Referring to FIG. 4, when the gate oxide layer 40 is thermally oxidized, the sidewalls on both sides of the active region A do not grow the gate oxide layer due to the presence of the silicon oxide 30.
上述浅沟槽隔离结构的凹陷区处理方法，通过淀积氧化硅填充浅沟槽隔离结构20上表面在边界处形成的凹陷区21，因此不会留出较大的空间导致多晶硅填入凹陷区21内；且热氧化生长栅氧化层40时，有源区A的侧壁由于被淀积的氧化硅30覆盖，不会暴露在空气中，因此侧壁不会生长栅氧化层，凹陷区21也就不会形成寄生晶体管，能够避免该寄生晶体管导致的漏电。The recessed region processing method of the shallow trench isolation structure fills the recessed region 21 formed at the boundary on the upper surface of the shallow trench isolation structure 20 by depositing silicon oxide, so that no large space is left to cause the polysilicon to fill the recessed region. 21; and when the gate oxide layer 40 is thermally oxidized, the sidewall of the active region A is covered by the deposited silicon oxide 30 and is not exposed to the air, so that the sidewall does not grow the gate oxide layer, and the recess region 21 In other words, parasitic transistors are not formed, and leakage due to the parasitic transistor can be avoided.
在一个实施例中，步骤S140之后还包括在晶圆表面淀积多晶硅的步骤。参见图5，凹陷区21(图5中未标示)被氧化硅30填充。可以理解的，实际生产中氧化硅30表面靠中间的部分可能没办法完全填满、形成缝隙，少量的多晶硅50会填入该缝隙中。但由于缝隙很小，不会对元器件造成明显影响。淀积多晶硅之后，还包括刻蚀多晶硅形成多晶硅栅的步骤。In one embodiment, step S140 further includes the step of depositing polysilicon on the surface of the wafer. Referring to FIG. 5, the recessed region 21 (not shown in FIG. 5) is filled with the silicon oxide 30. It can be understood that in the actual production, the middle portion of the surface of the silicon oxide 30 may not completely fill and form a gap, and a small amount of polysilicon 50 will be filled into the gap. However, because the gap is small, it will not have a significant impact on the components. After depositing the polysilicon, the step of etching the polysilicon to form a polysilicon gate is further included.
在一个实施例中，步骤S120是淀积高温氧化膜(HTO)。很多半导体器件在制造工艺的前段包括HTO的步骤，因此采用HTO工艺容易与现有的制造工艺兼容、节约成本。而且HTO为炉管生成，缺陷(defect)较少，这也使得采用HTO与多数工艺的兼容性较好。在另一个实施例中，步骤S120也可以采用其他淀积工艺，例如采用TEOS(正硅酸乙酯)做气体源进行淀积。In one embodiment, step S120 is to deposit a high temperature oxide film (HTO). Many semiconductor devices include HTO steps in the front stage of the manufacturing process, so the HTO process is easy to be compatible with existing manufacturing processes and cost-effective. Moreover, the HTO is generated for the furnace tube, and the defect is less, which also makes the compatibility of the HTO with most processes better. In another embodiment, step S120 may also employ other deposition processes, such as deposition using TEOS (orthosilicate) as a gas source.
参见图3，在一个实施例中，步骤S120淀积的氧化硅30的厚度h为凹陷区21深度的40％以上。优选的，厚度h为凹陷区21深度的40％～60％，通 常设置为凹陷区21深度的一半左右。Referring to FIG. 3, in one embodiment, the thickness h of the silicon oxide 30 deposited in step S120 is more than 40% of the depth of the recessed region 21. Preferably, the thickness h is 40% to 60% of the depth of the recessed portion 21, and is usually set to about half of the depth of the recessed portion 21.
本发明还相应提供一种半导体元器件，包括衬底、衬底上的浅沟槽隔离结构、衬底的有源区表面上的栅氧化层、以及栅氧化层上的多晶硅栅，浅沟槽隔离结构上表面在与有源区交界处形成有凹陷区(Divot)，凹陷区内被氧化硅填充。The present invention also provides a semiconductor component including a substrate, a shallow trench isolation structure on the substrate, a gate oxide layer on the surface of the active region of the substrate, and a polysilicon gate on the gate oxide layer, shallow trench The upper surface of the isolation structure is formed with a recessed portion (Divot) at a boundary with the active region, and the recessed region is filled with silicon oxide.
上述半导体元器件，浅沟槽隔离结构上表面在边界处形成的凹陷区(divot)内填充有氧化硅，因此凹陷区内不会有大量的多晶硅填入，从而不会在凹陷区形成寄生晶体管，能够避免该寄生晶体管导致的漏电。In the above semiconductor component, the divot formed on the upper surface of the shallow trench isolation structure is filled with silicon oxide, so that a large amount of polysilicon is not filled in the recessed region, so that parasitic transistors are not formed in the recessed region. The leakage caused by the parasitic transistor can be avoided.
在一个实施例中，凹陷区内的氧化硅是通过淀积工艺形成。在一个实施例中，该淀积工艺是淀积高温氧化膜。In one embodiment, the silicon oxide in the recessed regions is formed by a deposition process. In one embodiment, the deposition process is to deposit a high temperature oxide film.
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。The above-described embodiments are merely illustrative of several embodiments of the present invention, and the description thereof is more specific and detailed, but is not to be construed as limiting the scope of the invention. It should be noted that a number of variations and modifications may be made by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of the invention should be determined by the appended claims.

Claims (11)

  1. 一种浅沟槽隔离结构的凹陷区处理方法，包括：A method for processing a depressed area of a shallow trench isolation structure, comprising:
    提供在衬底上形成有浅沟槽隔离结构的晶圆，且浅沟槽隔离结构上表面在与有源区交界处形成有凹陷区；Providing a wafer having a shallow trench isolation structure formed on the substrate, and the upper surface of the shallow trench isolation structure is formed with a recessed region at a boundary with the active region;
    在所述晶圆表面淀积氧化硅，且所述氧化硅填满所述凹陷区；Depositing silicon oxide on the surface of the wafer, and the silicon oxide fills the recessed region;
    干法刻蚀淀积的所述氧化硅，通过控制刻蚀深度使得既能露出衬底的有源区表面、又能尽量保留所述凹陷区内填充的氧化硅；及Dry etching the deposited silicon oxide by controlling the etching depth so as to expose the active region surface of the substrate while retaining the silicon oxide filled in the recess region as much as possible;
    在所述有源区表面热氧化生长栅氧化层。A gate oxide layer is thermally oxidized on the surface of the active region.
  2. 根据权利要求1所述的方法，其中，所述在所述有源区表面热氧化生长栅氧化层的步骤之后，还包括在所述晶圆表面淀积多晶硅的步骤。The method of claim 1 wherein said step of thermally oxidizing a growth gate oxide layer on said active region surface further comprises the step of depositing polysilicon on said wafer surface.
  3. 根据权利要求2所述的方法，其中，还包括刻蚀所述多晶硅形成多晶硅栅的步骤。The method of claim 2 further comprising the step of etching said polysilicon to form a polysilicon gate.
  4. 根据权利要求1所述的方法，其中，所述在所述晶圆表面淀积氧化硅的步骤，是淀积高温氧化膜。The method of claim 1 wherein said step of depositing silicon oxide on said wafer surface is to deposit a high temperature oxide film.
  5. 根据权利要求1-4中任意一项所述的方法，其中，所述在所述晶圆表面淀积氧化硅的步骤中，淀积的氧化硅厚度为所述凹陷区深度的40％以上。The method according to any one of claims 1 to 4, wherein in the step of depositing silicon oxide on the surface of the wafer, the deposited silicon oxide has a thickness of more than 40% of the depth of the recessed region.
  6. 根据权利要求5所述的方法，其中，所述厚度为所述凹陷区深度的40％～60％。The method of claim 5 wherein said thickness is between 40% and 60% of the depth of said recessed region.
  7. 根据权利要求5所述的方法，其中，所述厚度为所述凹陷区深度的一半。The method of claim 5 wherein said thickness is half the depth of said recessed region.
  8. 根据权利要求4所述的方法，其中，所述淀积高温氧化膜是采用炉管生成。The method according to claim 4, wherein said depositing a high temperature oxide film is carried out using a furnace tube.
  9. 一种半导体元器件，包括：A semiconductor component comprising:
    衬底；Substrate
    浅沟槽隔离结构，设于所述衬底上；a shallow trench isolation structure disposed on the substrate;
    栅氧化层，设于所述衬底的有源区表面上；及a gate oxide layer disposed on a surface of the active region of the substrate;
    多晶硅栅，设于所述；a polysilicon gate, disposed in the
    其中，所述浅沟槽隔离结构的上表面在与有源区交界处形成有凹陷区，所述凹陷区内被氧化硅填充。Wherein, the upper surface of the shallow trench isolation structure is formed with a recessed region at a boundary with the active region, and the recessed region is filled with silicon oxide.
  10. 根据权利要9所述的半导体元器件，其中，所述氧化硅是通过淀积工艺形成。The semiconductor component according to claim 9, wherein said silicon oxide is formed by a deposition process.
  11. 根据权利要10所述的半导体元器件，其中，所述淀积工艺是淀积高温氧化膜。The semiconductor component according to claim 10, wherein said deposition process is a deposition of a high temperature oxide film.
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