WO2019083338A1 - Oxide semiconductor thin-film transistor and method for manufacturing same - Google Patents

Oxide semiconductor thin-film transistor and method for manufacturing same

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Publication number
WO2019083338A1
WO2019083338A1 PCT/KR2018/012903 KR2018012903W WO2019083338A1 WO 2019083338 A1 WO2019083338 A1 WO 2019083338A1 KR 2018012903 W KR2018012903 W KR 2018012903W WO 2019083338 A1 WO2019083338 A1 WO 2019083338A1
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WIPO (PCT)
Prior art keywords
oxide semiconductor
film transistor
thin film
semiconductor thin
gate electrode
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PCT/KR2018/012903
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French (fr)
Korean (ko)
Inventor
장진
이수희
Original Assignee
경희대학교산학협력단
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Application filed by 경희대학교산학협력단 filed Critical 경희대학교산학협력단
Priority to US16/759,562 priority Critical patent/US11296232B2/en
Publication of WO2019083338A1 publication Critical patent/WO2019083338A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment

Definitions

  • the present invention relates to an oxide semiconductor thin film transistor and a manufacturing method thereof, and more particularly, to an oxide semiconductor thin film transistor for a flexible display device that improves the lifetime and reliability of the device and a manufacturing method thereof.
  • a display device driven by a thin film transistor (TFT) using an a-IGZO Indium Gallium Zinc Oxide
  • TFT thin film transistor
  • a-IGZO Indium Gallium Zinc Oxide
  • considerable research is being conducted on a ring oscillator and a driving circuit using not only an inverter necessary for driving a display device but a driving circuit.
  • a parasitic capacitance is generated between a gate electrode and a source electrode or a drain electrode. This is because characteristics of an oxide semiconductor thin film transistor having high- There was a disadvantage that it deteriorated.
  • a flexible display device is a device that adds flexibility by forming a display portion on a flexible substrate, and has a very useful advantage of being able to bend or flex its shape when necessary.
  • Various applications such as the flexible display mobile communication device, the wearable smart device, the foldable device, the automobile display, the digital signage, the electronic newspaper, the electronic book, the electronic board, It is expected to lead to next generation display development.
  • the display performance should be maintained even when bending occurs, the display performance is defective depending on the degree of bending.
  • a thin film transistor is formed on a flexible substrate.
  • a stress due to bending is transmitted to the thin film transistor to generate a crack, .
  • Embodiments of the present invention are intended to provide an oxide semiconductor thin film transistor and a manufacturing method thereof that improve the lifetime and reliability of the device.
  • Embodiments of the present invention reduce the parasitic capacitance between the gate electrode (first or second) and the source electrode or the drain electrode by reducing the area of the source / drain electrode, An oxide semiconductor thin film transistor used as a device, and a manufacturing method thereof.
  • An oxide semiconductor thin film transistor includes a substrate; A first gate electrode formed on the substrate; A gate insulating layer formed on the first gate electrode; An oxide semiconductor layer formed on the gate insulating layer to correspond to the first gate electrode; A source / drain electrode formed on the oxide semiconductor layer so as to be spaced apart from the source electrode and the drain electrode, the source / drain electrode being formed in a plurality of island patterns; And a passivation layer formed on the source / drain electrode.
  • the source / drain electrode includes a first region formed in a direction of the first gate electrode and a second region formed in a direction opposite to the first region with respect to a horizontal plane of the substrate. Wherein the plurality of island patterns have a resistance to external stress by separating the first regions from each other.
  • the plurality of island patterns may be a plurality of line patterns in which a plurality of line patterns are repeatedly formed.
  • the width of each of the plurality of line patterns may be from 1 ⁇ to 10 ⁇ .
  • the spacing between the plurality of line patterns may be between 1 ⁇ and 16 ⁇ .
  • the plurality of island patterns may have a lattice shape in which a plurality of line patterns intersect vertically.
  • the first gate electrode may be formed to be spaced apart from the source / drain electrode formed on the oxide semiconductor layer by a distance of -1 ⁇ to 3 ⁇ in the horizontal direction.
  • the oxide semiconductor thin film transistor may further include a second gate electrode on the passivation layer formed on the source / drain electrode.
  • the second gate electrode may be formed to be spaced apart from the source / drain electrode formed on the oxide semiconductor layer by a distance of -1 mu m to 3 mu m in a horizontal direction.
  • connection electrode electrically connecting the first gate electrode and the second gate electrode.
  • the first gate electrode and the second gate electrode may be electrically connected to receive the same voltage.
  • An oxide semiconductor thin film transistor includes an oxide semiconductor layer formed on a substrate, a first gate electrode formed on the oxide semiconductor layer, and a source / drain electrode formed of a plurality of island patterns, Drain electrode includes a first region formed in a direction of the first gate electrode and a second region formed in a direction opposite to a first region with respect to a horizontal plane of the substrate, In the plurality of island patterns, the first regions are separated from each other and are resistant to external stress.
  • a display device includes a substrate; An oxide semiconductor thin film transistor according to any one of claims 1 to 11 formed on the substrate; And a display device electrically connected to the oxide semiconductor thin film transistor.
  • the display device may be an organic light emitting device.
  • a method of fabricating an oxide semiconductor thin film transistor includes: forming a first gate electrode on a substrate; Forming a gate insulating layer on the first gate electrode; Forming an oxide semiconductor layer on the gate insulating layer corresponding to the first gate electrode; Forming source / drain electrodes on the oxide semiconductor layer by patterning the source / drain electrodes in a plurality of island patterns spaced apart from each other; And forming a passivation layer on the source / drain electrode.
  • the first gate electrode or the second gate electrode may be formed to be spaced apart from the source / drain electrode formed on the oxide semiconductor layer by a distance of -1 mu m to 3 mu m in the horizontal direction.
  • the source / drain electrode is formed by a plurality of island patterns separated from the first region to generate a diffusion current between the source electrode and the drain electrode, thereby generating a parasitic capacitance .
  • the oxide semiconductor thin film transistor according to the embodiments of the present invention has a plurality of island patterns formed in a source / drain electrode to reduce a cross-sectional area, thereby preventing damages, particularly cracks, caused by external stresses such as bending or bending, It is possible to improve the electrical characteristics, life span and reliability of the device.
  • the oxide semiconductor thin film transistor having high performance electrical characteristics can be used as a pixel element of a flexible display device such as a liquid crystal display device (LCD) or an organic light emitting display device (AMOLED).
  • a flexible display device such as a liquid crystal display device (LCD) or an organic light emitting display device (AMOLED).
  • FIGS. 1A to 1H illustrate cross-sectional views of an oxide semiconductor thin film transistor illustrating an overall flow of a method of manufacturing an oxide semiconductor thin film transistor according to an embodiment of the present invention.
  • 2A to 2C are plan views of a plurality of island patterns formed in various shapes in an oxide semiconductor thin film transistor according to an embodiment of the present invention.
  • FIG. 3A is a plan view of a conventional oxide semiconductor thin film transistor
  • FIG. 3B is a plan view of an oxide semiconductor thin film transistor according to an embodiment of the present invention.
  • 4A to 4H illustrate characteristics of an oxide semiconductor thin film transistor according to an exemplary embodiment of the present invention in accordance with a width of a plurality of line patterns.
  • FIG. 5A is a graph showing a drain current-gate voltage characteristic according to a width of a plurality of line patterns when the interval between a plurality of line patterns of the oxide semiconductor thin film transistor according to an embodiment of the present invention is 1.5 mu m
  • FIG. 5B is a graph showing the drain current-drain voltage characteristics according to the width of a plurality of line patterns when the interval between the plurality of line patterns is 1.5 .mu.m.
  • FIG. 5C is a graph showing drain current-gate voltage characteristics according to a width of a plurality of line patterns when the interval between a plurality of line patterns of an oxide semiconductor thin film transistor according to an embodiment of the present invention is 3 mu m
  • FIG. 5D is a graph showing the drain current-drain voltage characteristics according to the width of a plurality of line patterns when the interval between the plurality of line patterns is 3 ⁇ m.
  • FIG. 5E is a cross-sectional view of the oxide semiconductor thin film transistor according to an embodiment of the present invention when the interval between a plurality of line patterns of the oxide semiconductor thin film transistor is 1.5 mu m or 3 mu m
  • FIG. 5 is a graph showing a drain current characteristic according to a change in width.
  • 6A to 6H illustrate characteristics of an oxide semiconductor thin film transistor according to an embodiment of the present invention in accordance with the interval between a plurality of line patterns.
  • FIG. 7A is a graph showing drain current-gate voltage characteristics according to a change in the interval between a plurality of line patterns when a width of a plurality of line patterns of an oxide semiconductor thin film transistor according to an embodiment of the present invention is 5 ⁇ m
  • FIG. 7B is a graph showing drain current-drain voltage characteristics according to a change in the interval between a plurality of line patterns when the width of a plurality of line patterns of the oxide semiconductor thin film transistor according to an embodiment of the present invention is 5 ⁇ m. to be.
  • FIG. 8 is a graph showing a capacitance-gate voltage characteristic according to a change in spacing between a plurality of line patterns of an oxide semiconductor thin film transistor according to an embodiment of the present invention.
  • FIG. 9A is a graph showing inverter characteristics of an oxide semiconductor thin film transistor according to an embodiment of the present invention in accordance with a change in the interval between a plurality of line patterns
  • FIG. 9B is a graph showing frequency characteristics
  • FIG. 9C is a graph showing the drain current and capacitance of an oxide semiconductor thin film transistor according to an embodiment of the present invention in accordance with a change in the interval between a plurality of line patterns
  • FIGS. 9D and 9E are cross- FIG. 2 is a schematic view showing a diffusion current of an oxide semiconductor thin film transistor according to one embodiment of the present invention.
  • FIG. 10A is a graph showing a positive bias temperature stress (PBTS) of an oxide semiconductor thin film transistor having a general structure other than a plurality of island patterns
  • FIG. 10B is a graph showing a positive bias temperature (PBTS) of an oxide semiconductor thin film transistor according to an embodiment of the present invention, temperature stress.
  • PBTS positive bias temperature stress
  • FIG. 10C is a graph showing the HCTS (high current temperature stress) of an oxide semiconductor thin film transistor having a general structure other than a plurality of island patterns, FIG. temperature stress.
  • 11A to 11C show a bending test equipment and a reliability test equipment of a flexible display device to which an oxide semiconductor thin film transistor is applied according to an embodiment of the present invention.
  • FIG. 11D is a graph showing drain current-gate voltage characteristics measured after bending test of a flexible display device having oxide semiconductor thin film transistors of a general structure other than a plurality of island patterns
  • FIG. 11E is a graph Gate voltage characteristics measured after a bending test of a flexible display device including an oxide semiconductor thin film transistor according to the present invention.
  • FIG. 11F is an optical microscope image showing an oxide semiconductor thin film transistor having a general structure other than a plurality of island patterns on which a bending test is performed
  • FIG. 11G shows an oxide semiconductor thin film transistor according to an embodiment of the present invention in which a bending test is performed It is an optical microscope image.
  • FIG. 12A to 12D illustrate an oxide semiconductor thin film transistor according to an embodiment of the present invention, in which a first region is formed by a plurality of island patterns and an optical microscope image of an oxide semiconductor layer and source / )to be.
  • FIGS. 13A to 13H are graphs showing transfer and output characteristics of an oxide semiconductor thin film transistor according to an embodiment of the present invention, according to a channel length.
  • FIG. 13A to 13H are graphs showing transfer and output characteristics of an oxide semiconductor thin film transistor according to an embodiment of the present invention, according to a channel length.
  • FIG. 14A is an optical microscope image showing an oxide semiconductor thin film transistor having a general structure not a plurality of island patterns used in a ring oscillator
  • FIG. 14B is a cross- Is an optical microscope image showing an oxide semiconductor transistor according to one embodiment of the present invention.
  • FIG. 15A and 15B are optical microscope images showing thermal analysis of a metal-over-active (MOA) of an oxide semiconductor transistor according to an embodiment of the present invention
  • Figs. 15C and 15D are cross- FIG. 2 is a light microscope image showing an active-over-metal (AOM) thermal analysis of an oxide semiconductor transistor according to the present invention.
  • MOA metal-over-active
  • AOM active-over-metal
  • 16A to 16F illustrate voltage-time characteristics of a ring oscillator including an oxide semiconductor transistor according to an embodiment of the present invention, according to the interval between a plurality of island patterns.
  • FIGS. 17A to 17H are cross-sectional views illustrating an oxide semiconductor thin film transistor showing an overall flow of a method of manufacturing an oxide semiconductor thin film transistor (dual gate structure) according to another embodiment of the present invention.
  • FIG. 18A is a plan view of a conventional oxide semiconductor thin film transistor
  • FIG. 18B is a plan view of an oxide semiconductor thin film transistor according to another embodiment of the present invention.
  • 19A to 19C are cross-sectional views illustrating different gate driving in an oxide semiconductor thin film transistor (dual gate structure) according to another embodiment of the present invention.
  • FIGS. 20A to 20F show the characteristics of an oxide semiconductor thin film transistor according to another embodiment of the present invention in accordance with the width of a plurality of line patterns.
  • FIGS. 21A to 21F show characteristics of an oxide semiconductor thin film transistor according to another embodiment of the present invention in accordance with the interval between a plurality of line patterns.
  • 22A to 22C are graphs showing transmission characteristics according to different gate driving in an oxide semiconductor thin film transistor according to another embodiment of the present invention in which the first gate electrode and the second gate electrode have the same size .
  • 22D to 22F are graphs showing output characteristics according to different gate driving in an oxide semiconductor thin film transistor according to another embodiment of the present invention in which the first gate electrode and the second gate electrode have the same size .
  • FIG. 22G is a graph showing output characteristics according to a change in spacing between a plurality of island patterns in a lower sweep in an oxide semiconductor thin film transistor according to another embodiment of the present invention in FIG. 22I
  • FIG. 22H is a graph
  • FIG. 22I is a graph showing output characteristics of the oxide semiconductor thin film transistor according to another embodiment when the upper gap sweeps between a plurality of island patterns
  • FIG. 22I is a graph showing the output characteristics of the oxide semiconductor thin film transistor
  • FIG. 5 is a graph showing output characteristics according to a change in interval between a plurality of island patterns in a dual sweep.
  • FIGS. 23A to 23C are diagrams for explaining the gate driving method according to another embodiment of the present invention having an offset structure in which the distance between the source / drain electrode and the second gate is -1 mu m, And Fig.
  • 23D to 23F are diagrams for explaining the gate driving method according to another embodiment of the present invention having an offset structure in which the distance between the source / drain electrode and the second gate is -1 mu m, Fig.
  • FIG. 23G is a graph showing output characteristics according to a change in interval between a plurality of island patterns in a lower sweep in the oxide semiconductor thin film transistor according to another embodiment of the present invention in FIG. 23D
  • FIG. 23H is a graph
  • FIG. 23I is a graph showing output characteristics according to a change in interval between a plurality of island patterns in an upper sweep in an oxide semiconductor thin film transistor according to another embodiment
  • FIG. 23I is a graph showing the output characteristics of the oxide semiconductor thin film transistor
  • FIG. 5 is a graph showing output characteristics according to a change in interval between a plurality of island patterns in a dual sweep.
  • FIGS. 24A and 24B are graphs comparing values obtained by dividing a drain current value in a dual sweep by a drain current value in a bottom sweep in an oxide semiconductor thin film transistor according to another embodiment of the present invention.
  • FIG. 24A is a graph comparing values obtained by dividing a drain current value in a dual sweep by a drain current value in a bottom sweep in an oxide semiconductor thin film transistor according to another embodiment of the present invention.
  • FIG. 25B is a graph showing an oxide semiconductor thin film transistor according to another embodiment of the present invention having an offset structure in which the distance between the source / drain electrode and the second gate electrode is -1 mu m
  • FIG. 5 is a graph showing a capacitance-gate contact characteristic according to a change in pattern interval.
  • FIG. 26A is a circuit diagram of a display device having a pixel element including one oxide semiconductor thin film transistor according to another embodiment of the present invention
  • FIG. 26B is a cross-sectional view illustrating an oxide semiconductor thin film transistor according to another embodiment of the present invention.
  • 2 shows a circuit diagram of a display device having a pixel element including two pixel elements.
  • FIGS. 27A to 27G show cross-sectional views of an oxide semiconductor thin film transistor showing an overall flow of a method of manufacturing an oxide semiconductor thin film transistor (Coplanar structure) according to still another embodiment of the present invention.
  • FIG. 28 shows a cross-sectional view of a dual gate structure of an oxide semiconductor thin film transistor (Coplanar structure) according to another embodiment of the present invention.
  • 29A and 29B are cross-sectional views illustrating an overlap and an offset of an oxide semiconductor thin film transistor according to embodiments of the present invention.
  • the term 'or' implies an inclusive or 'inclusive' rather than an exclusive or 'exclusive'. That is, unless expressly stated otherwise or clear from the context, the expression 'x uses a or b' means any of the natural inclusive permutations.
  • FIGS. 1A to 1H an oxide semiconductor thin film transistor and a method of manufacturing the same according to an embodiment of the present invention will be described in detail with reference to FIGS. 1A to 1H.
  • An oxide semiconductor thin film transistor 100 includes a substrate 103, a first gate electrode 105, a gate insulating layer 106, an oxide semiconductor layer 107, source / drain electrodes 108, 109 and a passivation layer 110.
  • the oxide semiconductor thin film transistor 100 may further include a support layer 102, a buffer layer 104, and a pixel electrode 111. In this case,
  • the source / drain electrodes 108 and 109 of the oxide semiconductor thin film transistor 100 are formed in a first region formed in the direction of the first gate electrode 105 with respect to the horizontal plane of the substrate 103 (P1) and a second region (P2) formed in a direction opposite to the first region (P1), and the plurality of island patterns have a resistance to external stress by separating the first regions (P1) from each other.
  • the oxide semiconductor thin film transistor 100 reduces the area of the source / drain electrodes 108 and 109 so that the first gate electrode 105 and the source / drain electrodes 108 and 109, The occurrence of parasitic capacitance can be reduced.
  • FIGS. 1A to 1H illustrate cross-sectional views of an oxide semiconductor thin film transistor illustrating an overall flow of a method of manufacturing an oxide semiconductor thin film transistor according to an embodiment of the present invention.
  • a method of manufacturing an oxide semiconductor thin film transistor 100 includes forming a support layer 102 and a substrate 103 on a carrier substrate 101.
  • a support layer 102 is formed on the carrier substrate 101.
  • the supporting layer 102 is not necessarily required.
  • the support layer 102 may be formed to have transparency using a carbon nanotube-graphene oxide (CNT-GO).
  • CNT-GO carbon nanotube-graphene oxide
  • the carbon nanotube-graphene oxide support layer 102 has a bending property and is suitable for application to a flexible display device.
  • a substrate 103 is formed on the support layer 102.
  • the substrate 103 may be a flexible substrate having flexibility, as a substrate for supporting various components of the oxide semiconductor thin film transistor.
  • the flexible substrate can be bended or folded in a specific direction.
  • the flexible substrate may be folded in the transverse direction, the longitudinal direction, or the diagonal direction.
  • the flexible substrate may be formed, for example, by coating a polyimide-based solution on the carrier substrate 101 on which the support layer 102 is formed, and may be in the form of a film.
  • the substrate 103 may be made of any one material selected from the group consisting of glass, a polyimide-based polymer, a polyester-based polymer, a silicon-based polymer, an acrylic polymer, a polyolefin-based polymer, or a copolymer thereof.
  • a flexible substrate such as a polyester, a polyvinyl, a polycarbonate, a polyethylene, a polyacetate, a polyimide, , Polyethylene terephthalate (PES), polyacrylate (PAR), polyethylene naphthalate (PEN), and polyethylene ether phthalate (PET).
  • a flexible substrate such as a polyester, a polyvinyl, a polycarbonate, a polyethylene, a polyacetate, a polyimide, , Polyethylene terephthalate (PES), polyacrylate (PAR), polyethylene naphthalate (PEN), and polyethylene ether phthalate (PET).
  • the substrate 103 may be made of a transparent flexible material.
  • the substrate 103 may include at least one or more thin film transistor regions.
  • the thin film transistor (TFT) may be disposed in the thin film transistor region, and the thin film transistor region may be disposed in the matrix on the substrate 103.
  • the substrate 103 may have a thickness within a range of 1 ⁇ ⁇ to 30 ⁇ ⁇ , and preferably within a range of 1 ⁇ ⁇ to 10 ⁇ ⁇ .
  • a method of fabricating an oxide semiconductor thin film transistor 100 includes forming a buffer layer 104 on a substrate 103.
  • the buffer layer 104 may be formed on the substrate 103.
  • the buffer layer 104 prevents penetration of external impurities such as moisture or oxygen through the substrate 103 and can flatten the surface of the substrate 103.
  • the buffer layer 104 is not necessarily required and may be adopted or omitted depending on the type of the substrate 103.
  • the buffer layer 104 when the buffer layer 104 is used, the buffer layer 104 may be formed of an inorganic material such as silicon oxide (SiOx), silicon nitride (SiNx), aluminum oxide (AlOx), or an inorganic material such as acrylic or polyimide And the like.
  • an inorganic material such as silicon oxide (SiOx), silicon nitride (SiNx), aluminum oxide (AlOx), or an inorganic material such as acrylic or polyimide And the like.
  • a method of manufacturing an oxide semiconductor thin film transistor 100 includes forming a first gate electrode 105 on a substrate 103 on which a buffer layer 104 is formed.
  • the first gate electrode 105 may be formed on the buffer layer 104, and the first gate electrode 105 may be a bottom gate electrode.
  • the first gate electrode 105 is formed by depositing a gate conductive film (not shown) on the buffer layer 104, forming a photoresist pattern on the gate conductive film, selectively etching the gate conductive film using the photoresist pattern as a mask For example, by etching, i.e., patterning.
  • the first gate electrode 105 is spaced from the source / drain electrodes 108 and 109 formed on the oxide semiconductor layer 107 in the horizontal direction by 1 ⁇ ⁇ to 3 ⁇ ⁇ (offset and overlap) .
  • FIGS. 29A and 29B A technique in which the first gate electrode 105 is spaced apart from the source / drain electrodes 108 and 109 formed on the oxide semiconductor layer 107 will be described with reference to FIGS. 29A and 29B.
  • 29A and 29B are cross-sectional views showing overlap and offset of an oxide semiconductor thin film transistor according to embodiments of the present invention.
  • the offset and the overlap may be at least one of a width between one end of the first gate electrode 105 and the source electrode 108 and a width between the other end of the first gate electrode 105 and the drain electrode 109 .
  • the overlapped portion overlaps the first gate electrode 105 and the source electrode 108 .
  • the overlap means a width from 0 mu m to 3 mu m.
  • Offset refers to the distance between the first gate electrode 105 and the source electrode 108 in the horizontal direction when viewing the first gate electrode 105 and the source electrode 108 in a direction perpendicular to the substrate it means. Therefore, the offset means the width from -1 mu m to 0 mu m.
  • the offset of the first gate electrode 105 of the oxide semiconductor thin film transistor reduces the defect region formed at the lower interface of the oxide semiconductor layer 107,
  • the threshold voltage change in the positive bias stress (PBS) can be reduced to improve the electrical characteristics of the oxide semiconductor transistor.
  • the first gate electrode 105 may be formed of a metal material such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or combinations thereof, but may be made of various materials. Also, the first gate electrode 105 may be formed as a single layer or a multi-layer structure including the above-described material.
  • Mo molybdenum
  • Al aluminum
  • Cr chromium
  • Au gold
  • Ti titanium Ti
  • Ni nickel
  • Nd neodymium
  • Cu copper
  • the first gate electrode 105 may be formed as a single layer or a multi-layer structure including the above-described material.
  • the first gate electrode 105 may be formed by any one of a vacuum deposition method, a chemical vapor deposition method, a physical vapor deposition method, an atomic layer deposition method, a metal organic chemical vapor deposition method Vapor deposition, plasma-enhanced chemical vapor deposition, molecular beam epitaxy, hydride vapor phase epitaxy, sputtering, spin coating, dip coating, Coating may be formed using at least one of dip coating and zone casting.
  • a method of manufacturing an oxide semiconductor thin film transistor 100 includes forming a gate insulating layer 106 and an oxide semiconductor film 107a on a first gate electrode 105 do.
  • a gate insulator 106 is formed on the first gate electrode 105.
  • the gate insulating layer 106 is formed on the buffer layer 104 on which the first gate electrode 105 is formed to insulate the first gate electrode 105 and the oxide semiconductor layer 107 (see FIG. 1E). That is, the first gate electrode 105 and the oxide semiconductor layer 107 are insulated by the gate insulating layer 106.
  • the gate insulating layer 106 may be formed to cover the entire surface of the buffer layer 104 including the first gate electrode 105, as shown in FIG.
  • the gate insulating layer 106 may be formed by a method such as vacuum deposition, chemical vapor deposition, physical vapor deposition, atomic layer deposition, metalorganic chemical vapor deposition Deposition, Plasma-Enhanced Chemical Vapor Deposition, Molecular Beam Epitaxy, Hydride Vapor Phase Epitaxy, Sputtering, Spin Coating, Dip Coating, a dip coating method and a zone casting method.
  • the gate insulating layer 106 may be formed by spin coating using a solution for forming a gate insulating layer, and spin coating may be performed by using a solution for forming the gate insulating layer 106 on the substrate 103
  • the substrate 103 is rotated at a high speed and coated with a centrifugal force applied to a solution for forming the gate insulating layer 106.
  • spin coating the production cost can be reduced as compared with the deposition process, Simplification of technology can reduce process cost and process time.
  • the gate insulating layer 106 may be formed of an inorganic material such as a silicon oxide (SiOx), a silicon nitride (SiNx), a titanium oxide (TiOx), a hafnium oxide (HfOx), or a polyvinyl alcohol (PVP), polymethyl methacrylate (PMMA), and the like.
  • the gate insulating layer 106 may be formed of a single layer or a multi-layer structure including the above-described materials, but is not limited thereto, and may be formed of various materials.
  • An oxide semiconductor film 107a is formed on the gate insulating layer 106.
  • the oxide semiconductor film 107a is formed so as to cover the entire surface of the gate insulating layer 106 on the gate insulating layer 106, as a film for forming the oxide semiconductor layer 107.
  • a photoresist pattern is formed on the oxide semiconductor film 107a, and the oxide semiconductor film 107a is patterned to correspond to the first gate electrode 105 in the thin film transistor region using the photoresist pattern as a mask, (See FIG. 1E) may be formed.
  • a method of fabricating an oxide semiconductor thin film transistor 100 according to an embodiment of the present invention includes forming an oxide semiconductor layer 107 and source / drain electrodes 108 and 109 on a first gate electrode 105, ).
  • the oxide semiconductor layer 107 is formed to correspond to the first gate electrode 105 on the gate insulating layer 106, as shown in FIG.
  • the oxide semiconductor layer 107 may be formed by a vacuum deposition method, a chemical vapor deposition method, a physical vapor deposition method, an atomic layer deposition method, a metal organic chemical vapor deposition method Deposition, Plasma-Enhanced Chemical Vapor Deposition, Molecular Beam Epitaxy, Hydride Vapor Phase Epitaxy, Sputtering, Spin Coating, Dip Coating, dip coating, and zone casting, and may be formed of various oxide semiconductor materials.
  • the oxide semiconductor layer 107 may be formed of, for example, indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium zinc oxide (IZO), indium tin oxide (ITO), zinc tin oxide (ZTO), gallium zinc oxide (ZZO), hafnium indium zinc oxide (HIZO), zinc indium tin oxide (ZITO), and aluminum zinc oxide (AZTO).
  • IGZO indium gallium zinc oxide
  • ZnO zinc oxide
  • IZO indium zinc oxide
  • ITO indium tin oxide
  • ZTO zinc tin oxide
  • ZZO gallium zinc oxide
  • ZITO zinc indium tin oxide
  • AZTO aluminum zinc oxide
  • the oxide semiconductor layer 107 may be formed of an amorphous or polycrystalline material including the above-described material.
  • the oxide semiconductor thin film transistor 100 may further include an etch stopper layer (not shown) on the oxide semiconductor layer 107.
  • the etch stopper layer may be provided for protecting the upper surface of the oxide semiconductor layer 107 from the etchant to secure the stability of the oxide semiconductor layer 107. That is, the etch stopper layer can protect the oxide semiconductor layer 107 from the etchant flowing in the etching process of the source / drain electrodes 108 and 109.
  • the etch stopper layer may be made of, for example, silicon oxide (SiOx).
  • the oxide semiconductor layer 107 may include a channel region where a channel is formed and source / drain regions connected to the source / drain electrodes 108 and 109, respectively.
  • the source / drain electrodes 108 and 109 are formed on the oxide semiconductor layer 107 so as to be spaced apart from each other.
  • the source / drain electrodes 108 and 109 refer to the source electrode 108 and the drain electrode 109, and the source electrode 108 and the drain electrode 109 refer to the gate insulating film 107 formed with the oxide semiconductor layer 107 And are formed to be electrically connected to the oxide semiconductor layer 107, respectively.
  • the source / drain electrodes 108 and 109 are formed by depositing a source / drain conductive film (not shown) on the gate insulating layer 106 including the oxide semiconductor layer 107 and forming a photoresist pattern And then patterning the source / drain conductive film using the photoresist pattern as a mask. By forming the photoresist pattern in various shapes, the source / drain electrodes 108, 109 can be formed.
  • the source / drain electrodes 108 and 109 are formed by depositing a source / drain conductive film through a sputtering method, and then patterning the substrate using a photoresist pattern mask having a predetermined island pattern through a photolithography process .
  • the source / drain electrodes 108 and 109 of the oxide semiconductor thin film transistor according to an embodiment of the present invention may include a plurality of island patterns.
  • the source / drain electrodes 108 and 109 of the oxide semiconductor thin film transistor may include a first region P1 formed in the direction of the first gate electrode 105 with respect to a horizontal plane of the substrate 103, And a second region P2 formed in a direction opposite to the first region P1 and the plurality of island patterns are formed so that the first regions P1 are separated from each other and the source / drain electrodes 108 and 109
  • parasitic capacitance generated between the first gate electrode 105 and the source / drain electrodes 108 and 109 can be reduced, and resistance to external stresses such as bending or bending can be improved, It is possible to prevent damage from being caused.
  • the first region P1 includes the source / drain electrodes 108 and 109 that are not separated (e.g., ⁇ , ⁇ , ⁇ , or ⁇ )
  • parasitic capacitances And is not suitable for use in a display device due to a non-constant current value.
  • cracks are easily generated by a large area of the source / drain electrodes 108 and 109 .
  • the source / drain electrodes 108 and 109 which are separated (e.g.,? Or #) in the first region P1 included in the oxide semiconductor thin film transistor 100 according to an embodiment of the present invention, P1 are separated so that the parasitic capacitance can be reduced and device stability by a constant current value and crack occurrence in the flexible design can be prevented.
  • the parasitic capacitance is generated in a portion where the first gate electrode 105 and the source / drain electrodes 108 and 109 overlap each other.
  • the source / drain electrodes 108 and 109 are used to separate the first region P1 where the source / drain electrodes 108 and 109 are overlapped with each other, thereby reducing the parasitic capacitance, The area of the drain electrodes 108 and 109 can be reduced to prevent the occurrence of cracks.
  • the oxide semiconductor thin film transistor includes a plurality of island pattern source / drain electrodes 108 and 109 having a first region P1 separated from the source electrode 108, So that spreading currents can be generated between the electrodes 109.
  • the first gate electrode 105 is distributed over the entire surface of the oxide semiconductor layer 107, so that the channel region of the entire oxide semiconductor layer 107 is formed by the field of the first gate electrode 105 At this time, a current flows through the field between the source / drain electrodes 108 and 109.
  • the source / drain electrodes 108 and 109 are separated from each other by a first region P1 and are divided into a plurality of island patterns, Lt; / RTI >
  • a diffusion current can be further generated.
  • the oxide semiconductor thin film transistor according to an embodiment of the present invention has many additional processes to be performed at the upper interface of the oxide semiconductor layer 107 after the oxide semiconductor layer 107 is formed,
  • the upper interface of the lower layer 107 contains a relatively larger number of defects than the lower interface.
  • the oxide semiconductor thin film transistor 100 is formed so that the first regions P1 of the island patterns are separated from each other, thereby forming the oxide semiconductor layer 107 at the upper interface And reduce the threshold voltage at the positive bias temperature stress (PBTS) or the high current temperature stress (HCTS) to improve the electrical characteristics of the oxide semiconductor transistor.
  • PBTS positive bias temperature stress
  • HCTS high current temperature stress
  • the positive bias temperature stress is a stress that biases the first gate electrode 105, and the source / drain electrodes 108 and 109 are connected to a plurality of first regions P1 separated from each other Shaped irregular pattern, the generated heat not only reduces the heat but also the heat is easily dispersed to reduce the stress and to exhibit the stabilization characteristic.
  • the high current temperature stress is a current stress applied to a channel region which gives a bias between the first gate electrode 105 and the drain electrode 109, and the source / drain electrodes 108 and 109
  • HCTS high current temperature stress
  • the oxide semiconductor thin film transistor 100 not only can increase the amount of current passing through the source electrode 108 and the drain electrode 109, It can exhibit stabilization characteristics in reliability test for negative voltage and temperature.
  • the source / drain electrodes 108 and 109 may be formed of a metal material such as molybdenum (Mo), aluminum (Al), chrome (Cr), gold (Au), titanium (Ti) ), Neodymium (Nd), and copper (Cu), or combinations thereof, but may be made of various materials. Further, the source / drain electrodes 108 and 109 may be formed as a single layer or a multi-layer structure including the above-described materials.
  • the source / drain electrodes 108 and 109 may be formed by a known method such as a vacuum deposition method, a chemical vapor deposition method, a physical vapor deposition method, an atomic layer deposition method, Organic chemical vapor deposition, plasma-enhanced chemical vapor deposition, molecular beam epitaxy, hydride vapor phase epitaxy, sputtering, spin coating, , Dip coating, and zone casting, as described above.
  • a vacuum deposition method such as a vacuum deposition method, a chemical vapor deposition method, a physical vapor deposition method, an atomic layer deposition method, Organic chemical vapor deposition, plasma-enhanced chemical vapor deposition, molecular beam epitaxy, hydride vapor phase epitaxy, sputtering, spin coating, , Dip coating, and zone casting, as described above.
  • a method of manufacturing an oxide semiconductor thin film transistor 100 includes forming a passivation layer 110 on source / drain electrodes 108 and 109.
  • the oxide semiconductor thin film transistor 100 may include a passivation layer 110.
  • a passivation layer 110 is formed on the source / drain electrodes 108 and 109. Specifically, the passivation layer 110 is formed to cover (cover) both the gate insulating layer 106, the oxide semiconductor layer 107, and the source / drain electrodes 108 and 109.
  • the passivation layer 110 may be formed of the same material as the gate insulating layer 106 as a protective layer.
  • the passivation layer 110 may be formed of a single layer composed of any one of materials such as silicon oxide and silicon nitride, or a multi-layer structure thereof, but is not limited thereto and may be formed of various materials.
  • the passivation layer 110 may be formed by any suitable process such as vacuum deposition, chemical vapor deposition, physical vapor deposition, atomic layer deposition, Metal Organic Chemical Vapor Deposition ), Plasma-enhanced chemical vapor deposition (MOCVD), molecular beam epitaxy, hydride vapor phase epitaxy, sputtering, spin coating, dip coating dip coating, and zone casting.
  • a suitable process such as vacuum deposition, chemical vapor deposition, physical vapor deposition, atomic layer deposition, Metal Organic Chemical Vapor Deposition ), Plasma-enhanced chemical vapor deposition (MOCVD), molecular beam epitaxy, hydride vapor phase epitaxy, sputtering, spin coating, dip coating dip coating, and zone casting.
  • the oxide semiconductor thin film transistor 100 may further include a pixel electrode.
  • a pixel electrode is formed on the passivation layer 110.
  • the pixel electrode is electrically connected to the source / drain electrodes 108 and 109 and electrically connects the source / drain electrodes 108 and 109 to other components outside the oxide semiconductor thin film transistor 100 .
  • the pixel electrode 118 may also be formed of a metal material, for example, molybdenum (Mo).
  • a method of manufacturing an oxide semiconductor thin film transistor according to an embodiment of the present invention removes a carrier substrate 101.
  • the carrier substrate 101 may be removed from the support layer 102.
  • the carrier substrate 101 can be physically removed.
  • an oxide semiconductor thin film transistor according to an embodiment of the present invention which is manufactured through a method of manufacturing an oxide semiconductor thin film transistor according to an embodiment of the present invention, is illustrated.
  • An oxide semiconductor thin film transistor 100 includes a substrate 103, a first gate electrode 105, a gate insulating layer 106, an oxide semiconductor layer 107, source / drain electrodes 108, 109 and a passivation layer 110.
  • the oxide semiconductor thin film transistor 100 may further include a support layer 102, a buffer layer 104, and a pixel electrode 111. In this case,
  • the source / drain electrodes 108 and 109 of the oxide semiconductor thin film transistor 100 are formed in a first region formed in the direction of the first gate electrode 105 with respect to the horizontal plane of the substrate 103 (P1) and a second region (P2) formed in a direction opposite to the first region (P1), and the plurality of island patterns have a resistance to external stress by separating the first regions (P1) from each other.
  • the oxide semiconductor thin film transistor 100 reduces the area of the source / drain electrodes 108 and 109 so that the first gate electrode 105 and the source / drain electrodes 108 and 109, It is possible to reduce the occurrence of parasitic capacitance generated between the electrodes.
  • the oxide semiconductor thin film transistor having high performance electrical characteristics can be used as a pixel element of a flexible display device such as a liquid crystal display device (LCD) or an organic light emitting display device (AMOLED).
  • a flexible display device such as a liquid crystal display device (LCD) or an organic light emitting display device (AMOLED).
  • the oxide semiconductor thin film transistor according to an embodiment of the present invention can be used as a pixel element of a flexible display device such as a liquid crystal display device (LCD) or an organic light emitting display device (AMOLED). More specifically, after the oxide semiconductor thin film transistor is manufactured using the above-described method, a pixel electrode 111 electrically connected to one of the source / drain electrodes 108 and 109 is formed, Can be produced.
  • a pixel electrode 111 electrically connected to one of the source / drain electrodes 108 and 109 is formed, Can be produced.
  • a passivation layer 110 is formed to cover the source / drain electrodes 108 and 109, and the drain electrode 109 is formed through the through hole of the covering passivation layer 110.
  • An intermediate layer (not shown) including a light emitting layer (not shown) is formed on the pixel electrode 111 and an opposite electrode (not shown) is formed thereon, A display device can be manufactured.
  • 2A to 2C are plan views of a plurality of island patterns formed in various shapes in an oxide semiconductor thin film transistor according to an embodiment of the present invention.
  • the source / drain electrodes 108 and 109 may be formed in a plurality of island patterns.
  • the plurality of island patterns may be formed in various shapes such as a line shape, a zigzag line shape, or a lattice shape.
  • a plurality of island patterns may be formed in a plurality of line patterns in which a plurality of line patterns are repeatedly formed, as shown in FIG. 2A,
  • the line pattern may be formed in a plurality of zigzag line shapes extending in the zigzag direction, or may be formed in a lattice shape in which a plurality of line patterns are vertically crossed, as shown in Fig. 2C.
  • the width Lw of the plurality of line patterns constituting the plurality of island patterns may be 1 ⁇ ⁇ to 10 ⁇ ⁇ , preferably 1 ⁇ ⁇ to 5 ⁇ ⁇ , and more preferably 4 ⁇ ⁇ to 5 ⁇ ⁇ have.
  • the width Lw of the plurality of line patterns is less than 4 ⁇ ⁇ , there is a problem that the current value is reduced. If the width Lw is more than 5 ⁇ ⁇ , the width is too wide and parasitic capacitance can not be effectively reduced.
  • the interval Lg between the plurality of line patterns may be 1 to 16 mu m, and preferably 1 to 5 mu m. At this time, the intervals Lg between the plurality of line patterns may be the same or different from each other.
  • interval Lg between the plurality of line patterns is less than 1 ⁇ , the interval becomes too narrow to effectively reduce the parasitic capacitance. If the interval Lg exceeds 5 ⁇ , the current value is reduced.
  • FIG. 3A is a plan view of a conventional oxide semiconductor thin film transistor
  • FIG. 3B is a plan view of an oxide semiconductor thin film transistor according to an embodiment of the present invention.
  • a conventional oxide semiconductor thin film transistor has source / drain electrodes 80 and 90 formed on a gate electrode 50 and an oxide semiconductor layer 70, which are spaced apart from each other.
  • the source / drain electrodes 80 and 90 are not formed in a plurality of island patterns.
  • the oxide semiconductor thin film transistor according to an embodiment of the present invention includes source / drain electrodes 108 and 109 separated from each other on a first gate electrode 105 and an oxide semiconductor layer 107, A second gate electrode 112 is formed, and the source / drain electrodes 108 and 109 are formed in a plurality of island patterns. Furthermore, a plurality of island patterns of the source / drain electrodes 108 and 109 are formed by a plurality of island patterns in which the first regions P1 are separated from each other.
  • the oxide semiconductor thin film transistor according to an embodiment of the present invention reduces the area of the source / drain electrodes 108 and 109 compared to the conventional oxide semiconductor thin film transistor, thereby reducing the area of the first gate electrode 105 and the source / 108, and 109 can be reduced, and resistance to external stress can be improved.
  • 4A to 4H illustrate characteristics of an oxide semiconductor thin film transistor according to an exemplary embodiment of the present invention in accordance with a width of a plurality of line patterns.
  • the oxide semiconductor thin film transistor includes a plurality of island patterns having different widths of patterns. Microscope.
  • 4A is an optical microscope image of a general oxide semiconductor thin film transistor having a structure in which a first region of a source electrode S and a drain electrode D are not separated.
  • the source electrode S and the drain electrode D of the general oxide semiconductor thin film transistor exhibit a structure in which the first region is not separated.
  • 4B to 4H are diagrams showing a state in which the source electrode S and the drain electrode D are formed in a plurality of island patterns having a lattice shape and the first region is separated by the optical microscope of the oxide semiconductor thin film transistor according to the embodiment of the present invention Image.
  • the source electrode S and the drain electrode D of the oxide semiconductor thin film transistor according to the exemplary embodiment of the present invention are formed in a plurality of island patterns having the first region divided into a grid shape can confirm.
  • the width of a plurality of lattice-shaped line patterns of the source electrode S and the drain electrode D of the oxide semiconductor thin film transistor according to the embodiment of the present invention is well formed .
  • FIG. 5A is a graph showing a drain current-gate voltage characteristic according to a width of a plurality of line patterns when the interval between a plurality of line patterns of the oxide semiconductor thin film transistor according to an embodiment of the present invention is 1.5 mu m
  • FIG. 5B is a graph showing the drain current-drain voltage characteristics according to the width of a plurality of line patterns when the interval between the plurality of line patterns is 1.5 .mu.m.
  • FIG. 5C is a graph showing drain current-gate voltage characteristics according to a width of a plurality of line patterns when the interval between a plurality of line patterns of an oxide semiconductor thin film transistor according to an embodiment of the present invention is 3 mu m
  • FIG. 5D is a graph showing the drain current-drain voltage characteristics according to the width of a plurality of line patterns when the interval between the plurality of line patterns is 3 ⁇ m.
  • FIG. 5E is a cross-sectional view of the oxide semiconductor thin film transistor according to an embodiment of the present invention when the interval between a plurality of line patterns of the oxide semiconductor thin film transistor is 1.5 mu m or 3 mu m
  • FIG. 5 is a graph showing a drain current characteristic according to a change in width.
  • the drain current increases as the width of a plurality of line patterns increases, when the interval between the plurality of line patterns is 1.5 mu m or 3 mu m. Therefore, it can be seen that diffusion currents exist in the oxide semiconductor thin film transistor according to an embodiment of the present invention.
  • the width of a plurality of line patterns is 5 m
  • the reference oxide semiconductor thin film transistor STD Similar things can be seen.
  • 6A to 6H illustrate characteristics of an oxide semiconductor thin film transistor according to an embodiment of the present invention in accordance with the interval between a plurality of line patterns.
  • the oxide semiconductor thin film transistor includes a plurality of island patterns having a plurality of line patterns, 1 shows an optical microscope image.
  • 6A is an optical microscope image of an oxide semiconductor thin film transistor having a structure in which the first regions of the source electrode S and the drain electrode D are not branched.
  • the source electrode S and the drain electrode D of the general oxide semiconductor thin film transistor are not branched in the first region.
  • 6B to 6F are optical microscope images of an oxide semiconductor thin film transistor according to an embodiment of the present invention in which the drain electrode D is formed of a plurality of island patterns having a lattice shape and the first region is separated.
  • the source electrode S and the drain electrode D of the oxide semiconductor thin film transistor according to the embodiment of the present invention are formed into a plurality of island patterns having the first region separated into a grid shape can confirm.
  • the lattice shapes of the source electrode S and the drain electrode D of the oxide semiconductor thin film transistor according to the embodiment of the present invention are such that a plurality of line patterns are well formed at various intervals Can be confirmed.
  • FIG. 7A is a graph showing drain current-gate voltage characteristics according to a change in the interval between a plurality of line patterns when a width of a plurality of line patterns of an oxide semiconductor thin film transistor according to an embodiment of the present invention is 5 ⁇ m
  • FIG. 7B is a graph showing drain current-drain voltage characteristics according to a change in the interval between a plurality of line patterns when the width of a plurality of line patterns of the oxide semiconductor thin film transistor according to an embodiment of the present invention is 5 ⁇ m. to be.
  • Table 1 is a table showing the characteristics of Figs. 7A and 7B.
  • the drain current characteristic is relatively reduced compared to the reference oxide semiconductor thin film transistor when the interval between the plurality of line patterns is 12 mu m.
  • FIG. 8 is a graph showing a capacitance-gate voltage characteristic according to a change in spacing between a plurality of line patterns of an oxide semiconductor thin film transistor according to an embodiment of the present invention.
  • the capacitance measured at the negative gate voltage VGS is the sum of the depletion and the overlap capacitance between the gate electrode and the source / drain electrode, and as the spacing between the plurality of line patterns increases It can be seen that the capacitance is reduced because the parasitic capacitance is reduced.
  • the oxide semiconductor thin film transistor according to an embodiment of the present invention includes a plurality of isolated island patterns in the first region, thereby greatly reducing the parasitic capacitance.
  • FIG. 9A is a graph showing inverter characteristics of an oxide semiconductor thin film transistor according to an embodiment of the present invention in accordance with a change in the interval between a plurality of line patterns
  • FIG. 9B is a graph showing frequency characteristics
  • FIG. 9C is a graph showing the drain current and capacitance of an oxide semiconductor thin film transistor according to an embodiment of the present invention in accordance with a change in the interval between a plurality of line patterns
  • FIGS. 9D and 9E are cross- FIG. 2 is a schematic view showing a diffusion current of an oxide semiconductor thin film transistor according to one embodiment of the present invention.
  • the interval between the plurality of line patterns is 5 mu m, and the width of the plurality of line patterns is 5 mu m.
  • the oxide semiconductor thin film transistor according to the embodiment of the present invention exhibits stable driving characteristics in a range of a width between a plurality of line patterns ranging from 0 ⁇ to 10 ⁇ . It can be seen that it is suitable for application to
  • FIG. 9B shows characteristics of a ring oscillator (circuit) inverting a plurality of inverters.
  • a ring oscillator characteristics that are highly frequency-influenced can be confirmed by the influence of parasitic capacitance . It can be seen that a plurality of line patterns have the same current value in both 0 ⁇ ⁇ to 10 ⁇ ⁇ and the parasitic capacitance is reduced to have a high precision value.
  • the drain current characteristics of the oxide thin film transistor are similar to those of the reference oxide semiconductor thin film transistor STD up to a distance of 10 mu m between the plurality of line patterns, It can be seen that the drain current characteristics are relatively reduced compared to the reference oxide semiconductor thin film transistor.
  • the capacitance of the oxide semiconductor thin film transistor according to an embodiment of the present invention is 0.18 pF
  • the reference oxide semiconductor thin film transistor STD is 0.45 pF
  • the oxide semiconductor thin film transistor according to an embodiment of the present invention differs from the reference oxide semiconductor thin film transistor (STD) source / .
  • the reference oxide semiconductor thin film transistor (STD) and the oxide semiconductor thin film transistor according to an embodiment of the present invention exhibit substantially similar drain current characteristics (the drain current is not reduced), and the parasitic capacitance As shown in FIG.
  • FIG. 10A is a graph showing a positive bias temperature stress (PBTS) of an oxide semiconductor thin film transistor having a general structure other than a plurality of island patterns
  • FIG. 10B is a graph showing a positive bias temperature (PBTS) of an oxide semiconductor thin film transistor according to an embodiment of the present invention, temperature stress.
  • PBTS positive bias temperature stress
  • FIG. 10C is a graph showing the HCTS (high current temperature stress) of an oxide semiconductor thin film transistor having a general structure other than a plurality of island patterns, FIG. temperature stress.
  • 10B and 10D are oxide semiconductor thin film transistors according to an embodiment of the present invention in which the interval between a plurality of line patterns is 10 mu m and the width of a plurality of line patterns is 5 mu m.
  • an oxide semiconductor thin film transistor having a general structure other than a plurality of island patterns and an oxide semiconductor thin film transistor according to an embodiment of the present invention all increase in threshold voltage each time the PBST stress time increases , And PBTS is caused by electronic trapping at the interface of the oxide semiconductor layer / gate insulating film.
  • the oxide semiconductor thin film transistor according to an embodiment of the present invention has a smaller area of the source / drain electrode than a general structure of the oxide semiconductor thin film transistor not of a plurality of island patterns, so that there is no change in the transfer curve, It can be seen that the oxide semiconductor thin film transistor having a general structure other than the island pattern has more heat than that of the oxide semiconductor thin film transistor according to an embodiment of the present invention.
  • the heat dissipation performance is excellent by reducing the area of the source / drain electrodes.
  • 11A to 11C show a bending test equipment and a reliability test equipment of a flexible display device to which an oxide semiconductor thin film transistor is applied according to an embodiment of the present invention.
  • FIG. 11A is a sectional view of the bending test equipment (reliability test equipment)
  • FIG. 11B is an actual view of the bending test equipment
  • FIG. 11C is a plan view of the bending test equipment (reliability test equipment).
  • the bending test equipment used in accordance with an embodiment of the present invention has a bending angle &thetas; To ⁇ 90 ° and a flexible display device including an oxide semiconductor thin film transistor may be disposed between two clamps to perform a reliability test for bending stress.
  • FIG. 11D is a graph showing drain current-gate voltage characteristics measured after bending test of a flexible display device having oxide semiconductor thin film transistors of a general structure other than a plurality of island patterns
  • FIG. 11E is a graph Gate voltage characteristics measured after a bending test of a flexible display device including an oxide semiconductor thin film transistor according to the present invention.
  • the bending time (s) (number of bending) was changed to 0, 100, 500, 1,000, 2000, 3000 and 5,000, and the bending radius The radius was fixed to 0.32 mm so that the bending angle was 90 °.
  • FIG. 11F is an optical microscope image showing an oxide semiconductor thin film transistor having a general structure other than a plurality of island patterns on which a bending test is performed
  • FIG. 11G shows an oxide semiconductor thin film transistor according to an embodiment of the present invention in which a bending test is performed It is an optical microscope image.
  • the oxide semiconductor thin film transistor according to an embodiment of the present invention is characterized in that cracks are not generated in the source / drain electrodes even after the bending test is performed by the source / drain electrodes formed by a plurality of isolated island patterns in the first region .
  • FIG. 12A to 12D illustrate an oxide semiconductor thin film transistor according to an embodiment of the present invention, in which a first region is formed by a plurality of island patterns and an optical microscope image of an oxide semiconductor layer and source / ) to be.
  • a source electrode S and a drain electrode D of an oxide semiconductor thin film transistor according to an embodiment of the present invention are formed in a plurality of island patterns having a first lattice shape You can see the figure.
  • the oxide semiconductor thin film transistor according to an embodiment of the present invention well forms an oxide semiconductor layer having various widths (having a channel length).
  • FIGS. 13A to 13H are graphs showing transfer and output characteristics of an oxide semiconductor thin film transistor according to an embodiment of the present invention, according to a channel length.
  • FIG. 13A to 13H are graphs showing transfer and output characteristics of an oxide semiconductor thin film transistor according to an embodiment of the present invention, according to a channel length.
  • FIG. 13A and 13B are graphs showing transfer and output characteristics of an oxide semiconductor thin film transistor according to an embodiment of the present invention with a channel length of 10 mu m
  • FIG. 5 is a graph showing transfer and output characteristics of an oxide semiconductor thin film transistor according to an embodiment of the present invention.
  • FIG. 13E and 13F are graphs showing transfer and output characteristics of an oxide semiconductor thin film transistor according to an embodiment of the present invention with a channel length of 30 mu m
  • FIG. 5 is a graph illustrating transfer and output characteristics of an oxide semiconductor thin film transistor according to an embodiment of the present invention.
  • the width of a plurality of line patterns is 5 mu m, and the interval between a plurality of line patterns is 10 mu m.
  • FIGS. 13A to 13H show the characteristics according to the channel length, showing stable characteristics of the oxide semiconductor thin film transistor up to a maximum channel length of 50 ⁇ m.
  • the oxide semiconductor thin film transistor according to the embodiment of the present invention does not decrease the drain current but decreases the parasitic capacitance.
  • FIG. 14A is an optical microscope image showing an oxide semiconductor thin film transistor having a general structure not a plurality of island patterns used in a ring oscillator
  • FIG. 14B is a cross- Is an optical microscope image showing an oxide semiconductor transistor according to one embodiment of the present invention.
  • the source / drain electrodes of the oxide semiconductor transistor according to an embodiment of the present invention are formed in a plurality of island patterns, and the first regions of the plurality of island patterns are separated .
  • FIG. 15A and 15B are optical microscope images showing thermal analysis of a metal-over-active (MOA) of an oxide semiconductor transistor according to an embodiment of the present invention
  • Figs. 15C and 15D are cross- FIG. 2 is a light microscope image showing an active-over-metal (AOM) thermal analysis of an oxide semiconductor transistor according to the present invention.
  • MOA metal-over-active
  • AOM active-over-metal
  • FIG. 15A is an optical image in a structure in which a source / drain electrode is larger in area than an oxide semiconductor layer
  • 15B is an optical image when the area is smaller than that of the semiconductor layer
  • 15A to 15D have a channel length of 5 mu m and a total width of the oxide semiconductor layer of 20 mu m.
  • 16A to 16F illustrate voltage-time characteristics of a ring oscillator including an oxide semiconductor transistor according to an embodiment of the present invention, according to the interval between a plurality of island patterns.
  • Fig. 16A shows the interval between a plurality of island patterns is 0 mu m
  • Fig. 16B is 6 mu m
  • Fig. 16C is 8 mu m
  • Fig. 16D is 10 mu m
  • Fig. 22E is 12 mu m
  • the total oxide semiconductor layer width in Figs. 16A to 16F is 240 mu m, and the power supply voltage V DD is 15V.
  • FIGS. 17A to 17H are cross-sectional views illustrating an oxide semiconductor thin film transistor showing an overall flow of a method of manufacturing an oxide semiconductor thin film transistor (dual gate structure) according to another embodiment of the present invention.
  • the oxide semiconductor thin film transistor includes a substrate 103, a first gate electrode 105, a gate insulating layer 106, an oxide semiconductor layer 107, a source / Drain electrodes 108 and 109, a passivation layer 110 and a second gate electrode 112 and may further include a support layer 102, a buffer layer 104 and a connection electrode (not shown).
  • the elements of the oxide semiconductor thin film transistor according to another embodiment of the present invention may include the same technical elements as those of the oxide semiconductor thin film transistor according to an embodiment of the present invention, It will be omitted.
  • a method for fabricating an oxide semiconductor thin film transistor according to another embodiment of the present invention includes forming a support layer 102 and a substrate 103 on a carrier substrate 101.
  • a support layer 102 is formed on the carrier substrate 101.
  • the supporting layer 102 is not necessarily required.
  • the substrate 103 is a substrate for supporting various components of the oxide semiconductor thin film transistor, and may be a substrate having flexibility.
  • a method of fabricating an oxide semiconductor thin film transistor according to another embodiment of the present invention includes forming a buffer layer 104 on a substrate 103.
  • the buffer layer 104 may be formed on the substrate 103.
  • the buffer layer 104 prevents penetration of external impurities such as moisture or oxygen through the substrate 103 and can flatten the surface of the substrate 103.
  • the buffer layer 104 is not necessarily required and may be adopted or omitted depending on the type of the substrate 103.
  • a method for fabricating an oxide semiconductor thin film transistor according to another embodiment of the present invention includes forming a first gate electrode 105 on a substrate 103 on which a buffer layer 104 is formed.
  • a first gate electrode 105 is formed on the buffer layer 104.
  • the first gate electrode 105 may be a bottom gate electrode.
  • a method for fabricating an oxide semiconductor thin film transistor includes forming a gate insulating layer 106 and an oxide semiconductor film 107a on a first gate electrode 105.
  • a gate insulator 106 is formed on the first gate electrode 105.
  • an oxide semiconductor film 107a is formed on the gate insulating layer 106.
  • the oxide semiconductor film 107a is formed so as to cover the entire surface of the gate insulating layer 106 on the gate insulating layer 106, as a film for forming the oxide semiconductor layer 107.
  • a photoresist pattern is formed on the oxide semiconductor film 107a, and the oxide semiconductor film 107a is patterned to correspond to the first gate electrode 105 in the thin film transistor region using the photoresist pattern as a mask, (See Fig. 14E) can be formed.
  • a method of manufacturing an oxide semiconductor thin film transistor according to another embodiment of the present invention includes forming an oxide semiconductor layer 107 and source / drain electrodes 108 and 109 on a first gate electrode 105 do.
  • the oxide semiconductor layer 107 is formed to correspond to the first gate electrode 105 on the gate insulating layer 106.
  • source / drain electrodes 108 and 109 are formed on the oxide semiconductor layer 107 so as to be spaced apart from each other.
  • the source / drain electrodes 108 and 109 may be formed of a plurality of island patterns in which the first regions P1 are separated.
  • the source / drain electrodes 108 and 109 are formed by a plurality of island patterns in which the first regions P1 are separated, so that they are resistant to external stresses such as bending or bending, Damage can be prevented.
  • a method for fabricating an oxide semiconductor thin film transistor according to another embodiment of the present invention includes forming a passivation layer 110 on source / drain electrodes 108 and 109.
  • the oxide semiconductor thin film transistor 100 may further include a passivation layer 110.
  • a method for fabricating an oxide semiconductor thin film transistor according to another embodiment of the present invention includes forming a second gate electrode 112 on a passivation layer 110.
  • the oxide semiconductor thin film transistor according to another embodiment of the present invention further includes a second gate electrode 112 as shown in FIG. 17G.
  • a second gate electrode 112 is formed on the passivation layer 110.
  • the second gate electrode 112 may be a top gate electrode and may have a dual gate structure together with the first gate electrode 105.
  • the second gate electrode 112 is formed by depositing a gate conductive film (not shown) on the passivation layer 110, forming a photoresist pattern on the gate conductive film, and then using the photoresist pattern as a mask, That is, by patterning.
  • the second gate electrode 112 may be formed of a metal material such as Mo, Al, Cr, Au, Ti, Ni, Neodymium (Nd), and copper (Cu), or a combination thereof, but is not limited thereto, and may be made of various materials. Further, the second gate electrode 112 may be formed as a single layer or a multi-layer structure including the above-described material.
  • the second gate electrode 112 is spaced from the source / drain electrodes 108 and 109 formed on the oxide semiconductor layer 107 in the horizontal direction by 1 ⁇ ⁇ to 3 ⁇ ⁇ (offset and overlap) .
  • the offset and the overlap mean at least one of a width between one end of the second gate electrode 112 and the source electrode 108 and a width between the other end of the second gate electrode 112 and the drain electrode 109.
  • the overlap is a portion where the second gate electrode 112 and the source electrode 108 are overlapped with each other .
  • the overlap means a width from 0 mu m to 3 mu m.
  • the offset is the distance between the second gate electrode 112 and the source electrode 108 in the horizontal direction when viewing the second gate electrode 112 and the source electrode 108 in a direction perpendicular to the substrate it means. Therefore, the offset means the width from -1 mu m to 0 mu m.
  • the oxide semiconductor thin film transistor according to another embodiment of the present invention has many additional processes to be performed at the upper interface of the oxide semiconductor layer 107 after the oxide semiconductor layer 107 is formed, Has a relatively higher defect than an interface at the bottom.
  • the offset of the second gate electrode 112 of the oxide semiconductor thin film transistor reduces the defect region formed at the upper interface of the oxide semiconductor layer 107,
  • the threshold voltage change in the positive bias stress (PBS) can be reduced to improve the electrical characteristics of the oxide semiconductor transistor.
  • the oxide semiconductor thin film transistor 100 may further include a connection electrode (not shown) electrically connecting the first gate electrode 105 and the second gate electrode 112.
  • connection electrode is an electrode for electrically connecting the first gate electrode 105 and the second gate electrode 112, and the first gate electrode 105 and the second gate electrode 112 are electrically connected to the connection electrode The same voltage can be applied through the resistor Rs.
  • the width of the channel formed in the oxide semiconductor layer 107 not only can increase the amount of current passing through the source electrode 108 and the drain electrode 109 but also exhibits stabilization characteristics in a reliability test for positive voltage, negative voltage and temperature .
  • the oxide semiconductor thin film transistor 100 may further form a passivation layer on the second gate electrode 112.
  • the passivation layer may include at least one material selected from inorganic insulators such as silicon nitride (SiNx) or silicon oxide (SiOx), organic insulators and low dielectric constant insulators.
  • the passivation layer may protect the oxide semiconductor transistor according to another embodiment of the present invention from the outside.
  • a method for fabricating an oxide semiconductor thin film transistor according to another embodiment of the present invention removes a carrier substrate 101.
  • the carrier substrate 101 may be removed from the support layer 102.
  • the oxide semiconductor thin film transistor according to another embodiment of the present invention may have resistance to external stress by forming the source / drain electrodes 108 and 109 as a plurality of island patterns separated from the first region.
  • the oxide semiconductor thin film transistor according to another embodiment of the present invention can be used for driving a pixel element, for example, an organic light emitting element, of a display device, particularly a flexible display device.
  • FIG. 18A is a plan view of a conventional oxide semiconductor thin film transistor
  • FIG. 18B is a plan view of an oxide semiconductor thin film transistor according to another embodiment of the present invention.
  • a conventional oxide semiconductor thin film transistor has source / drain electrodes 80 and 90 formed on a gate electrode 50 and an oxide semiconductor layer 70, which are spaced apart from each other.
  • the source / drain electrodes 80 and 90 are not formed in a plurality of island patterns.
  • source / drain electrodes 108 and 109 which are separated from each other on the first gate electrode 105 and the oxide semiconductor layer 107 of the oxide semiconductor thin film transistor according to another embodiment of the present invention, Two gate electrodes 112 are formed, and the source / drain electrodes 108 and 109 are formed in a plurality of island patterns. Furthermore, a plurality of island patterns of the source / drain electrodes 108 and 109 are formed by a plurality of island patterns in which the first regions P1 are separated from each other.
  • the oxide semiconductor thin film transistor according to another embodiment of the present invention reduces the area of the source / drain electrodes 108 and 109 compared to the conventional oxide semiconductor thin film transistor, thereby reducing the area of the first gate electrode 105 or the second gate electrode 112 and the source / drain electrodes 108, 109 can be reduced and the immunity against external stress can be improved.
  • 19A to 19C are cross-sectional views illustrating different gate driving in an oxide semiconductor thin film transistor (dual gate structure) according to another embodiment of the present invention.
  • FIG. 19A shows the distribution and current flow of electrons when the first gate electrode is sweeped (-15 to 15V) and the second gate electrode is grounded.
  • FIG. 19C shows the distribution and current flow of electrons when the first gate electrode is grounded with a sweep (upper sweep) of -15 to 15 V, and
  • FIG. 19C shows the first gate electrode and the second gate electrode Electrically or physically connected and sweep (dual sweep) at -15 to 15V at the same time.
  • FIGS. 20A to 20F show the characteristics of an oxide semiconductor thin film transistor according to another embodiment of the present invention in accordance with the width of a plurality of line patterns.
  • FIGS. 20A to 20F are cross-sectional views illustrating an oxide semiconductor thin film transistor according to another embodiment of the present invention.
  • FIGS. 20A to 20F are cross-sectional views illustrating an oxide semiconductor thin film transistor according to another embodiment of the present invention. Microscope.
  • 20A is an optical microscope image of a general oxide semiconductor thin film transistor having a structure in which a first region of a source electrode S and a drain electrode D are not separated.
  • the source electrode S and the drain electrode D of the general oxide semiconductor thin film transistor exhibit a structure in which the first region is not separated.
  • 20B to 20F are cross-sectional views of an oxide semiconductor thin film transistor according to another embodiment of the present invention in which the source electrode S and the drain electrode D are formed in a plurality of island patterns having a lattice shape, Image.
  • a source electrode S and a drain electrode D of an oxide semiconductor thin film transistor according to another embodiment of the present invention are formed in a plurality of island patterns having a first lattice-like lattice shape can confirm.
  • the width of a plurality of lattice-shaped island patterns of the source electrode S and the drain electrode D of the oxide semiconductor thin film transistor according to another embodiment of the present invention is well formed .
  • FIGS. 21A to 21F show characteristics of an oxide semiconductor thin film transistor according to another embodiment of the present invention in accordance with the interval between a plurality of line patterns.
  • FIGS. 21A to 21F are cross-sectional views illustrating an oxide semiconductor thin film transistor according to another embodiment of the present invention.
  • the oxide semiconductor thin film transistor includes a plurality of island patterns, 1 shows an optical microscope image.
  • 21A is an optical microscope image of an oxide semiconductor thin film transistor having a structure in which the first region of the source electrode S and the drain electrode D are not branched.
  • the source electrode S and the drain electrode D of the general oxide semiconductor thin film transistor show a state in which the first region is not branched.
  • 21B to 21F are optical microscope images of an oxide semiconductor thin film transistor according to another embodiment of the present invention in which the drain electrode D is formed of a plurality of island patterns having a lattice shape and the first region is separated.
  • a source electrode S and a drain electrode D of an oxide semiconductor thin film transistor according to another embodiment of the present invention are formed in a plurality of island patterns having a first lattice-like lattice shape can confirm.
  • the lattice shape of the source electrode S and the drain electrode D of the oxide semiconductor thin film transistor according to another embodiment of the present invention is such that a plurality of line patterns are well formed at various intervals Can be confirmed.
  • 22A to 22C are graphs showing transmission characteristics according to different gate driving in an oxide semiconductor thin film transistor according to another embodiment of the present invention in which the first gate electrode and the second gate electrode have the same size .
  • FIG. 22A is a graph illustrating transmission characteristics according to a distance between a plurality of island patterns in a bottom sweep in an oxide semiconductor thin film transistor according to another embodiment of the present invention
  • FIG. 22C shows a transmission characteristic according to the interval between a plurality of island patterns in the top sweep of an oxide semiconductor thin film transistor
  • FIG. 22C is a graph showing the transmission characteristics according to the dual sweep in the oxide semiconductor thin film transistor according to another embodiment of the present invention.
  • FIG. 5B shows transmission characteristics according to the interval between a plurality of island patterns.
  • an oxide semiconductor thin film transistor according to another embodiment of the present invention including a source electrode and a drain electrode of a plurality of island patterns including an isolated first region includes a reference oxide semiconductor thin film transistor 0 Mu] m.
  • 22D to 22F are graphs showing output characteristics according to different gate driving in an oxide semiconductor thin film transistor according to another embodiment of the present invention in which the first gate electrode and the second gate electrode have the same size .
  • FIG. 22D is a graph illustrating an output characteristic according to a distance between a plurality of island patterns in a bottom sweep in an oxide semiconductor thin film transistor according to another embodiment of the present invention
  • FIG. 22E is a graph illustrating an output characteristic according to another embodiment of the present invention
  • FIG. 22F illustrates an output characteristic according to a distance between a plurality of island patterns in a top sweep of an oxide semiconductor thin film transistor.
  • FIG. 22F illustrates a dual sweep in the oxide semiconductor thin film transistor according to another embodiment of the present invention.
  • FIG. 5B shows output characteristics according to an interval between a plurality of island patterns.
  • the output characteristics of the oxide semiconductor thin film transistor having the dual gate structure including the source electrode and the drain electrode of the plurality of island patterns including the separated first region are improved.
  • FIG. 22G is a graph showing output characteristics according to a change in spacing between a plurality of island patterns in a lower sweep in an oxide semiconductor thin film transistor according to another embodiment of the present invention in FIG. 22I
  • FIG. 22H is a graph
  • FIG. 22I is a graph showing output characteristics of the oxide semiconductor thin film transistor according to another embodiment when the upper gap sweeps between a plurality of island patterns
  • FIG. 22I is a graph showing the output characteristics of the oxide semiconductor thin film transistor
  • FIG. 5 is a graph showing output characteristics according to a change in interval between a plurality of island patterns in a dual sweep.
  • the oxide semiconductor thin film transistor according to another embodiment of the present invention exhibits a drain characteristic similar to that of the reference oxide semiconductor thin film transistor (0 mu m).
  • 22A to 22C are graphs showing transmission characteristics according to different gate driving in an oxide semiconductor thin film transistor according to another embodiment of the present invention in which the first gate electrode and the second gate electrode have the same size .
  • FIGS. 23A to 23C are diagrams for explaining the case where an oxide semiconductor thin film transistor according to another embodiment of the present invention having an offset structure (second gate electrode) having a distance between a source / drain electrode and a second gate is -1 mu m
  • FIG. 2 is a graph illustrating transmission characteristics according to gate driving.
  • FIG. 23A is a graph illustrating transmission characteristics according to a distance between a plurality of island patterns in a bottom sweep in an oxide semiconductor thin film transistor according to another embodiment of the present invention
  • FIG. 23B is a graph illustrating transmission characteristics according to another embodiment of the present invention
  • FIG. 23C shows a transmission characteristic according to the interval between a plurality of island patterns in the top sweep of an oxide semiconductor thin film transistor
  • FIG. 23C shows a transfer characteristic in a dual sweep mode in the oxide semiconductor thin film transistor according to another embodiment of the present invention.
  • FIG. 5B shows transmission characteristics according to the interval between a plurality of island patterns.
  • 23A to 23C show that the oxide semiconductor thin film transistor according to another embodiment of the present invention exhibits a drain characteristic similar to that of the reference oxide semiconductor thin film transistor (0 mu m).
  • FIG. 23D to 23F illustrate an oxide semiconductor thin film transistor according to another embodiment of the present invention having an offset structure (second gate electrode) with a distance between a source / drain electrode and a second gate of -1 mu m
  • FIG. 2 is a graph showing output characteristics according to gate driving.
  • FIG. 23D is a graph illustrating an output characteristic according to a distance between a plurality of island patterns in a bottom sweep in an oxide semiconductor thin film transistor according to another embodiment of the present invention
  • FIG. 23E is a graph illustrating an output characteristic according to another embodiment of the present invention
  • FIG. 23F is a graph illustrating an output characteristic according to a distance between a plurality of island patterns during top sweep in an oxide semiconductor thin film transistor.
  • FIG. 23F is a graph illustrating the output characteristics of the oxide semiconductor thin film transistor according to another embodiment of the present invention when performing a dual sweep And shows an output characteristic according to the interval between a plurality of island patterns.
  • FIG. 23G is a graph showing output characteristics according to a change in interval between a plurality of island patterns in a lower sweep in the oxide semiconductor thin film transistor according to another embodiment of the present invention in FIG. 23D
  • FIG. 23H is a graph
  • FIG. 23I is a graph showing output characteristics according to a change in interval between a plurality of island patterns in an upper sweep in an oxide semiconductor thin film transistor according to another embodiment
  • FIG. 23I is a graph showing the output characteristics of the oxide semiconductor thin film transistor
  • FIG. 5 is a graph showing output characteristics according to a change in interval between a plurality of island patterns in a dual sweep.
  • the oxide semiconductor thin film transistor according to another embodiment of the present invention exhibits a drain characteristic similar to that of the reference oxide semiconductor thin film transistor (0 mu m).
  • FIGS. 24A and 24B are graphs comparing values obtained by dividing a drain current value in a dual sweep by a drain current value in a bottom sweep in an oxide semiconductor thin film transistor according to another embodiment of the present invention.
  • FIG. 24A is a graph comparing values obtained by dividing a drain current value in a dual sweep by a drain current value in a bottom sweep in an oxide semiconductor thin film transistor according to another embodiment of the present invention.
  • FIG. 24A shows values in a structure in which the first gate electrode and the second gate electrode have the same size
  • FIG. 24B shows the offset structure (second gate electrode), the distance between the source / drain electrode and the second gate electrode Is 1 [micro] m.
  • FIG. 25B is a graph showing an oxide semiconductor thin film transistor according to another embodiment of the present invention having an offset structure (second gate electrode) in which the distance between the source / drain electrode and the second gate electrode is -1 mu m
  • FIG. 4 is a graph showing a capacitance-gate contact characteristic according to a variation of intervals of a plurality of island patterns in a dual sweep.
  • the parasitic capacitance is reduced by including the source / drain electrode having a plurality of island patterns including the separated first region.
  • FIG. 26A is a circuit diagram of a display device having a pixel element including one oxide semiconductor thin film transistor according to another embodiment of the present invention
  • FIG. 26B is a cross-sectional view illustrating an oxide semiconductor thin film transistor according to another embodiment of the present invention.
  • 2 shows a circuit diagram of a display device having a pixel element including two pixel elements.
  • the oxide semiconductor thin film transistor according to another embodiment of the present invention can be used as a pixel element of a display device.
  • FIGS. 27A to 27G an oxide semiconductor thin film transistor according to another embodiment of the present invention will be described with reference to FIGS. 27A to 27G.
  • FIGS. 27A to 27G show cross-sectional views of an oxide semiconductor thin film transistor showing an overall flow of a method of manufacturing an oxide semiconductor thin film transistor (Coplanar structure) according to still another embodiment of the present invention.
  • the oxide semiconductor thin film transistor according to another embodiment of the present invention includes a substrate 203, an oxide semiconductor layer 205, source / drain electrodes 206 and 207, a gate insulating layer 208, And a first gate electrode 209, and may further include a support layer 202 and a buffer layer 204.
  • the elements of the oxide semiconductor thin film transistor according to another embodiment of the present invention may include the same technical elements as those of the oxide semiconductor thin film transistor according to an embodiment of the present invention, Is omitted.
  • a method for fabricating an oxide semiconductor thin film transistor according to another embodiment of the present invention includes forming a support layer 202 and a substrate 203 on a carrier substrate 201.
  • a support layer 202 is formed on the carrier substrate 201.
  • the supporting layer 202 is not necessarily required.
  • the substrate 203 is formed on the support layer 202.
  • the substrate 203 is a substrate for supporting various components of the oxide semiconductor thin film transistor, and may be a substrate having flexibility.
  • a method of fabricating an oxide semiconductor thin film transistor according to another embodiment of the present invention includes forming a buffer layer 204 on a substrate 203.
  • a buffer layer 204 may be formed on the substrate 203.
  • the buffer layer 204 prevents penetration of external impurities such as moisture or oxygen through the substrate 203 and can flatten the surface of the substrate 203.
  • the buffer layer 204 is not necessarily required and may be adopted or omitted depending on the type of the substrate 203.
  • a method for fabricating an oxide semiconductor thin film transistor includes forming an oxide semiconductor layer 205 on a substrate 203 on which a buffer layer 204 is formed.
  • the buffer layer 204 is formed of the oxide semiconductor layer 205.
  • a method for fabricating an oxide semiconductor thin film transistor includes forming a source / drain electrode 206 and 207 on a buffer layer 204 and an oxide semiconductor layer 205.
  • the source and drain electrodes 206 and 207 are spaced apart from each other to be electrically connected to the buffer layer 204 and the oxide semiconductor layer 205 on the oxide semiconductor layer 205, respectively.
  • a method for fabricating an oxide semiconductor thin film transistor according to another embodiment of the present invention includes forming a gate insulating layer 208 on source / drain electrodes 206 and 207.
  • a gate insulating layer 208 is formed on the source / drain electrodes 206 and 207.
  • a method for fabricating an oxide semiconductor thin film transistor according to another embodiment of the present invention includes forming a first gate electrode 209 on a gate insulating layer 208.
  • the first gate electrode 209 is formed to correspond to the oxide semiconductor layer 205 on the gate insulating layer 208, as shown in Fig.
  • the first gate electrode 209 may be a top gate electrode.
  • a method of manufacturing an oxide semiconductor thin film transistor according to still another embodiment of the present invention removes a carrier substrate 201.
  • the carrier substrate 201 can be removed from the support layer 102.
  • the oxide semiconductor thin film transistor according to another embodiment of the present invention may have resistance to external stress by forming source / drain electrodes 206 and 207 in a plurality of island patterns separated from the first region.
  • the oxide semiconductor thin film transistor according to another embodiment of the present invention can be used for driving a pixel element, for example, an organic light emitting element, of a display device, in particular, a flexible display device.
  • the oxide semiconductor thin film transistor and the manufacturing method thereof have been described so far, the display device using the oxide semiconductor thin film transistor and the manufacturing method thereof are also within the scope of the present invention.
  • the oxide semiconductor thin film transistor according to embodiments of the present invention can be used as a pixel element of a flexible display device such as a liquid crystal display device (LCD) or an organic light emitting display device (AMOLED). More specifically, a display device can be manufactured through the steps of forming an oxide semiconductor thin film transistor using the above-described method, and then forming a pixel electrode electrically connected to one of the source / drain electrodes.
  • a display device can be manufactured through the steps of forming an oxide semiconductor thin film transistor using the above-described method, and then forming a pixel electrode electrically connected to one of the source / drain electrodes.
  • a passivation layer is formed to cover the source / drain electrodes 206 and 207, and a pixel electrode that contacts the drain electrode 207 through the through hole of the passivation layer
  • An intermediate layer (not shown) including a light emitting layer (not shown) is formed on the pixel electrode, and an opposite electrode (not shown) is formed thereon.
  • FIG. 28 shows a cross-sectional view of a dual gate structure of an oxide semiconductor thin film transistor (Coplanar structure) according to another embodiment of the present invention.
  • a dual gate structure of an oxide semiconductor thin film transistor includes a substrate 203, a second gate electrode 210 formed on the substrate, a second gate electrode 210
  • the gate insulating layer 208 and the first gate electrode 209 may be formed on the buffer layer 204 formed on the buffer layer 204, the oxide semiconductor layer 205 formed on the buffer layer, the source / drain electrodes 206 and 207, have.
  • the components of the dual gate structure of the oxide semiconductor thin film transistor (Coplanar structure) according to another embodiment of the present invention are the oxide semiconductor thin film transistor according to the above-described embodiment of the present invention and the other embodiment
  • the oxide semiconductor thin film transistor according to the present invention can include the same technical components as those of the oxide semiconductor thin film transistor according to the second embodiment.
  • the substrate 203 is a substrate for supporting various components of the oxide semiconductor thin film transistor, and may be a substrate having flexibility.
  • the second gate electrode 210 may be formed on the substrate 203 and the second gate electrode 210 may be a bottom gate electrode.
  • a buffer layer 204 is formed on the second gate electrode 210.
  • the buffer layer may serve as a gate insulating layer and a buffer layer may be formed under the second gate electrode 210, A gate insulating layer may be formed on the second gate electrode 210.
  • the buffer layer 204 prevents penetration of external impurities such as moisture or oxygen through the substrate 203 and can flatten the surface of the substrate 203.
  • the buffer layer 204 is not necessarily required and may be adopted or omitted depending on the type of the substrate 203.
  • the oxide semiconductor layer 205 is formed on the substrate 203 on which the buffer layer 204 is formed.
  • source / drain electrodes 206 and 207 are formed on the buffer layer 204 and the oxide semiconductor layer 205.
  • the dual gate structure of the oxide semiconductor thin film transistor includes source / drain electrodes 206 and 207 formed by a plurality of island patterns separated from the first region, It can tolerate stress.
  • the source / drain electrodes 206 and 207 are formed so as to be electrically connected to the buffer layer 204 and the oxide semiconductor layer 205 on the oxide semiconductor layer 205, respectively.
  • a gate insulating layer 208 is formed on the source / drain electrodes 206 and 207 and a first gate electrode 209 is formed on the gate insulating layer 208.
  • the first gate electrode 209 is formed to correspond to the oxide semiconductor layer 205 on the gate insulating layer 208.
  • the first gate electrode 209 may be a top gate electrode.
  • a dual gate structure of an oxide semiconductor thin film transistor (Coplanar structure) according to another embodiment of the present invention can be used for driving a pixel element of a display device, particularly a flexible display device, for example, an organic light emitting element .
  • the oxide semiconductor thin film transistor and the manufacturing method thereof have been described so far, the display device using the oxide semiconductor thin film transistor and the manufacturing method thereof are also within the scope of the present invention.
  • the oxide semiconductor thin film transistor according to embodiments of the present invention can be used as a pixel element of a flexible display device such as a liquid crystal display device (LCD) or an organic light emitting display device (AMOLED). More specifically, a display device can be manufactured through a step of forming an oxide semiconductor thin film transistor using the above-described method, and then forming a pixel electrode electrically connected to one of the source / drain electrodes.
  • a display device can be manufactured through a step of forming an oxide semiconductor thin film transistor using the above-described method, and then forming a pixel electrode electrically connected to one of the source / drain electrodes.
  • a passivation layer covering the source / drain electrodes is formed, and pixel electrodes for contacting the drain electrodes through the through holes of the covering passivation layer are formed.
  • An organic light emitting display device can be manufactured by forming an intermediate layer (not shown) on the substrate, and forming an opposite electrode thereon.

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Abstract

The present invention provides an oxide thin-film transistor and a method for manufacturing the same. An oxide thin-film transistor according to an embodiment of the present invention comprises: a substrate; a first gate electrode formed on the substrate; a gate insulating layer formed on the first gate electrode; an oxide semiconductor layer formed on the gate insulating layer so as to correspond to the first gate electrode; source/drain electrodes configured such that a source electrode and a drain electrode are formed on the oxide semiconductor layer so as to be spaced apart from each other, each of the source/drain electrodes being formed as multiple island patterns; and a passivation layer formed on the source/drain electrodes. The oxide thin-film transistor according to an embodiment of the present invention is characterized in that the source/drain electrodes comprise, with reference to the horizontal surface of the substrate, first areas formed in the direction of the first gate electrode and second areas formed in a direction opposite to the first areas, and the first areas of the multiple island patterns are separated from each other so as to have resistance against external stress.

Description

산화물 반도체 박막 트랜지스터 및 그 제조방법Oxide semiconductor thin film transistor and manufacturing method thereof
본 발명은 산화물 반도체 박막 트랜지스터 및 그 제조방법에 관한 것으로, 보다 상세하게는 장치의 수명 및 신뢰성을 향상시킨 플렉서블 디스플레이 장치용 산화물 반도체 박막 트랜지스터 및 그 제조방법에 관한 것이다.The present invention relates to an oxide semiconductor thin film transistor and a manufacturing method thereof, and more particularly, to an oxide semiconductor thin film transistor for a flexible display device that improves the lifetime and reliability of the device and a manufacturing method thereof.
최근 산화물 반도체(Oxide semiconductor)인 a-IGZO(Indium Gallium Zinc Oxide)를 이용한 박막 트랜지스터(Thin Film transistor; TFT)로 구동되는 디스플레이 장치의 개발이 빠르게 진행되고 있다. 이와 더불어, 디스플레이 장치의 구동에 기본적으로 필요한 인버터뿐만 아니라 이를 이용한 링 오실레이터 및 구동회로에 대해서도 상당 부분 연구가 진행되고 있다.Recently, a display device driven by a thin film transistor (TFT) using an a-IGZO (Indium Gallium Zinc Oxide), which is an oxide semiconductor, has been rapidly developed. In addition, considerable research is being conducted on a ring oscillator and a driving circuit using not only an inverter necessary for driving a display device but a driving circuit.
디스플레이 장치에 사용되는 산화물 반도체를 이용한 박막 트랜지스터(Thin Film transistor; TFT)는 게이트 전극과 소스 전극 또는 드레인 전극 사이에는 기생캐패시턴스가 발생하게 되는데, 이는 고성능의 전기적 특성을 가지는 산화물 반도체 박막 트랜지스터의 특성이 열화되는 단점이 있었다.In a thin film transistor (TFT) using an oxide semiconductor used in a display device, a parasitic capacitance is generated between a gate electrode and a source electrode or a drain electrode. This is because characteristics of an oxide semiconductor thin film transistor having high- There was a disadvantage that it deteriorated.
또한, 플렉서블(Flexible) 디스플레이에 사용되는 구동 소자에 대해서도 상당 부분 연구가 진행되고 있다.Further, much research has been made on a driving element used in a flexible display.
일반적으로 플렉서블 디스플레이 장치는 가요성 기판에 디스플레이부를 형성하여 유연성을 부가한 장치로서, 필요시 그 형태를 휘거나 구부려 사용할 수 있는 매우 유용한 장점을 가지고 있다. 이러한 플렉서블 디스플레이 이동통신기기, 웨어러블(Wearable) 스마트 기기, 폴더블(Foldable) 기기, 자동차용 디스플레이, 디지털 사이니지(Digital Signage), 전자신문, 전자책, 전자칠판, 게시판, 광고 등 각종 다양한 응용으로 차세대 디스플레이 발전을 이룰 것으로 예상된다.2. Description of the Related Art Generally, a flexible display device is a device that adds flexibility by forming a display portion on a flexible substrate, and has a very useful advantage of being able to bend or flex its shape when necessary. Various applications such as the flexible display mobile communication device, the wearable smart device, the foldable device, the automobile display, the digital signage, the electronic newspaper, the electronic book, the electronic board, It is expected to lead to next generation display development.
한편, 플렉서블 디스플레이 장치는 휨(Bending) 발생시에도 표시 성능을 그대로 유지해야 함에도 불구하고, 휨의 정도에 따라 표시 성능의 불량이 발생하는 문제점을 발생시킨다.On the other hand, in the flexible display device, although the display performance should be maintained even when bending occurs, the display performance is defective depending on the degree of bending.
특히, 플랙서블 디스플레이 장치는 플랙서블 기판 상에 박막 트랜지스터가 형성되는데, 플렉서블 디스플레이 장치의 휨이 크게 발생할 경우, 휨에 의한 스트레스(stress)가 박막 트랜지스터에 전달되어 크랙(crack)이 발생함으로써 박막 트랜지스터의 특성을 저하시킨다.In particular, in a flexible display device, a thin film transistor is formed on a flexible substrate. When a flexible display device is warped to a large extent, a stress due to bending is transmitted to the thin film transistor to generate a crack, .
이는 플렉서블 디스플레이 장치를 반복적으로 휘거나 구부릴 경우, 또는 플렉서블 디스플레이 장치가 대면적화될 경우 심화될 수 있으며, 결과적으로 플렉서블 디스플레이 장치의 수명 및 신뢰성을 떨어뜨린다.This may be exacerbated when the flexible display device is bent or bent repeatedly or when the flexible display device is large-sized, and as a result, the lifetime and reliability of the flexible display device are degraded.
본 발명의 실시예들은 장치의 수명 및 신뢰성을 향상시킨 산화물 반도체 박막 트랜지스터 및 그 제조방법을 제공하고자 한다.Embodiments of the present invention are intended to provide an oxide semiconductor thin film transistor and a manufacturing method thereof that improve the lifetime and reliability of the device.
본 발명의 실시예들은 소스/드레인 전극의 면적을 줄임으로써, 게이트 전극(제1 또는 제2)과 소스 전극 또는 드레인 전극 사이에 발생하는 기생캐패시턴스를 감소시켜 고성능의 전기적 특성을 가지는 디스플레이 장치의 화소 소자로 사용되는 산화물 반도체 박막 트랜지스터 및 그 제조방법을 제공하고자 한다.Embodiments of the present invention reduce the parasitic capacitance between the gate electrode (first or second) and the source electrode or the drain electrode by reducing the area of the source / drain electrode, An oxide semiconductor thin film transistor used as a device, and a manufacturing method thereof.
본 발명의 실시예에 따른 산화물 반도체 박막 트랜지스터는 기판; 상기 기판 상에 형성된 제1 게이트 전극; 상기 제1 게이트 전극 상에 형성된 게이트 절연층; 상기 제1 게이트 전극과 대응되도록 상기 게이트 절연층 상에 형성된 산화물 반도체층; 상기 산화물 반도체층 상에 소스 전극 및 드레인 전극이 서로 이격되어 형성되고, 각각 복수 개의 아일랜드 패턴으로 형성되는 소스/드레인 전극; 상기 소스/드레인 전극 상에 형성된 패시베이션층을 포함하고, 상기 소스/드레인 전극은 상기 기판의 수평면을 기준으로 상기 제1 게이트 전극 방향에 형성된 제1 영역 및 제1 영역과 반대 방향에 형성된 제2 영역을 포함하고, 상기 복수 개의 아일랜드 패턴은 상기 제1 영역이 서로 분리되어 외부 스트레스에 대한 내성을 가진다.An oxide semiconductor thin film transistor according to an embodiment of the present invention includes a substrate; A first gate electrode formed on the substrate; A gate insulating layer formed on the first gate electrode; An oxide semiconductor layer formed on the gate insulating layer to correspond to the first gate electrode; A source / drain electrode formed on the oxide semiconductor layer so as to be spaced apart from the source electrode and the drain electrode, the source / drain electrode being formed in a plurality of island patterns; And a passivation layer formed on the source / drain electrode. The source / drain electrode includes a first region formed in a direction of the first gate electrode and a second region formed in a direction opposite to the first region with respect to a horizontal plane of the substrate. Wherein the plurality of island patterns have a resistance to external stress by separating the first regions from each other.
상기 복수 개의 아일랜드 패턴은 복수 개의 라인 패턴이 반복되어 형성된 복수 개의 라인 형상일 수 있다.The plurality of island patterns may be a plurality of line patterns in which a plurality of line patterns are repeatedly formed.
상기 복수 개의 라인 패턴의 각각의 폭은 1 ㎛ 내지 10 ㎛일 수 있다.The width of each of the plurality of line patterns may be from 1 탆 to 10 탆.
상기 복수 개의 라인 패턴의 각각이 이격되는 간격은 1 ㎛ 내지 16 ㎛일 수 있다.The spacing between the plurality of line patterns may be between 1 탆 and 16 탆.
상기 복수 개의 아일랜드 패턴은 복수 개의 라인 패턴이 수직으로 교차하는 격자 형상일 수 있다.The plurality of island patterns may have a lattice shape in which a plurality of line patterns intersect vertically.
상기 제1 게이트 전극은 상기 산화물 반도체층 상에 형성된 상기 소스/드레인 전극으로부터 수평 방향으로 -1 ㎛ 내지 3 ㎛ 만큼 이격되도록 형성될 수 있다.The first gate electrode may be formed to be spaced apart from the source / drain electrode formed on the oxide semiconductor layer by a distance of -1 탆 to 3 탆 in the horizontal direction.
상기 산화물 반도체 박막 트랜지스터는, 상기 소스/드레인 전극 상에 형성된 패시베이션층 상에 제2 게이트 전극을 더 포함할 수 있다.The oxide semiconductor thin film transistor may further include a second gate electrode on the passivation layer formed on the source / drain electrode.
상기 제2 게이트 전극은 상기 산화물 반도체층 상에 형성된 상기 소스/드레인 전극으로부터 수평 방향으로 -1 ㎛ 내지 3 ㎛ 만큼 이격되도록 형성될 수 있다.The second gate electrode may be formed to be spaced apart from the source / drain electrode formed on the oxide semiconductor layer by a distance of -1 mu m to 3 mu m in a horizontal direction.
상기 제1 게이트 전극 및 상기 제2 게이트 전극을 전기적으로 연결하는 연결 전극을 더 포함할 수 있다.And a connection electrode electrically connecting the first gate electrode and the second gate electrode.
상기 제1 게이트 전극 및 상기 제2 게이트 전극은 전기적으로 연결되어 동일한 전압을 인가 받을 수 있다.The first gate electrode and the second gate electrode may be electrically connected to receive the same voltage.
본 발명의 실시예에 따른 산화물 반도체 박막 트랜지스터는 기판 상에 형성된 산화물 반도체층, 상기 산화물 반도체층 상에 형성된 제1 게이트 전극 및 각각 복수 개의 아일랜드 패턴으로 형성되는 소스/드레인 전극을 포함하는 코플라나(Coplanar)형 산화물 반도체 박막 트랜지스터에 있어서, 상기 소스/드레인 전극은 상기 기판의 수평면을 기준으로 상기 제1 게이트 전극 방향에 형성된 제1 영역 및 제1 영역과 반대 방향에 형성된 제2 영역을 포함하고, 상기 복수 개의 아일랜드 패턴은 상기 제1 영역이 서로 분리되어 외부 스트레스에 대한 내성을 가진다.An oxide semiconductor thin film transistor according to an embodiment of the present invention includes an oxide semiconductor layer formed on a substrate, a first gate electrode formed on the oxide semiconductor layer, and a source / drain electrode formed of a plurality of island patterns, Drain electrode includes a first region formed in a direction of the first gate electrode and a second region formed in a direction opposite to a first region with respect to a horizontal plane of the substrate, In the plurality of island patterns, the first regions are separated from each other and are resistant to external stress.
상기 산화물 반도체층 하부에 제2 게이트 전극을 더 포함할 수 있다.And a second gate electrode below the oxide semiconductor layer.
본 발명의 실시예에 따른 디스플레이 장치는 기판; 상기 기판 상에 형성된 제1항 내지 제11항 중 어느 한 항에 따른 산화물 반도체 박막 트랜지스터; 및 상기 산화물 반도체 박막 트랜지스터와 전기적으로 연결된 디스플레이 소자를 포함한다.A display device according to an embodiment of the present invention includes a substrate; An oxide semiconductor thin film transistor according to any one of claims 1 to 11 formed on the substrate; And a display device electrically connected to the oxide semiconductor thin film transistor.
본 발명의 실시예에 따른 디스플레이 장치에 있어서, 상기 디스플레이 소자는 유기 발광 소자일 수 있다.In the display device according to the embodiment of the present invention, the display device may be an organic light emitting device.
본 발명의 실시예에 따른 산화물 반도체 박막 트랜지스터의 제조방법은 기판 상에 제1 게이트 전극을 형성하는 단계; 상기 제1 게이트 전극 상에 게이트 절연층을 형성하는 단계; 상기 제1 게이트 전극과 대응되는 상기 게이트 절연층 상에 산화물 반도체층을 형성하는 단계; 상기 산화물 반도체층 상에 소스/드레인 전극을 서로 이격되되, 복수 개의 아일랜드 패턴으로 패턴화하여 형성하는 단계; 상기 소스/드레인 전극 상에 패시베이션층을 형성하는 단계를 포함한다.A method of fabricating an oxide semiconductor thin film transistor according to an embodiment of the present invention includes: forming a first gate electrode on a substrate; Forming a gate insulating layer on the first gate electrode; Forming an oxide semiconductor layer on the gate insulating layer corresponding to the first gate electrode; Forming source / drain electrodes on the oxide semiconductor layer by patterning the source / drain electrodes in a plurality of island patterns spaced apart from each other; And forming a passivation layer on the source / drain electrode.
상기 페시베이션층 상에 제2 게이트 전극을 형성하는 단계를 더 포함할 수 있다.And forming a second gate electrode on the passivation layer.
상기 제1 게이트 전극 또는 상기 제2 게이트 전극은 상기 산화물 반도체층 상에 형성된 상기 소스/드레인 전극으로부터 수평 방향으로 -1 ㎛ 내지 3 ㎛ 만큼 이격되도록 형성될 수 있다.The first gate electrode or the second gate electrode may be formed to be spaced apart from the source / drain electrode formed on the oxide semiconductor layer by a distance of -1 mu m to 3 mu m in the horizontal direction.
본 발명의 실시예들에 따른 산화물 반도체 박막 트랜지스터는 소스/드레인 전극을 제1 영역이 분리된 복수 개의 아일랜드 패턴으로 형성하여 소스 전극 및 드레인 전극 사이의 확산 전류를 생성하여 기생 캐패시턴스(parasitic capacitance)를 감소시킬 수 있다.In the oxide semiconductor thin film transistor according to the embodiments of the present invention, the source / drain electrode is formed by a plurality of island patterns separated from the first region to generate a diffusion current between the source electrode and the drain electrode, thereby generating a parasitic capacitance .
본 발명의 실시예들에 따른 산화물 반도체 박막 트랜지스터는 소스/드레인 전극을 복수 개의 아일랜드 패턴으로 형성하여 단면적을 줄임으로써 휨 또는 구부림 등의 외부 스트레스에 의한 손상, 특히 크랙(Crack) 발생을 방지하여 소자의 전기적 특성, 장치의 수명 및 신뢰성을 향상시킬 수 있다.The oxide semiconductor thin film transistor according to the embodiments of the present invention has a plurality of island patterns formed in a source / drain electrode to reduce a cross-sectional area, thereby preventing damages, particularly cracks, caused by external stresses such as bending or bending, It is possible to improve the electrical characteristics, life span and reliability of the device.
또한, 본 발명의 실시예들에 따른 고성능 전기적 특성을 가지는 산화물 반도체 박막 트랜지스터는 액정 디스플레이 장치(LCD) 또는 유기 발광 디스플레이 장치(AMOLED) 등의 플렉서블 디스플레이 장치의 화소 소자로 사용될 수 있다.In addition, the oxide semiconductor thin film transistor having high performance electrical characteristics according to embodiments of the present invention can be used as a pixel element of a flexible display device such as a liquid crystal display device (LCD) or an organic light emitting display device (AMOLED).
도 1a 내지 도 1h는 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터의 제조방법의 전체적인 흐름을 도시한 산화물 반도체 박막 트랜지스터의 단면도를 도시한 것이다.FIGS. 1A to 1H illustrate cross-sectional views of an oxide semiconductor thin film transistor illustrating an overall flow of a method of manufacturing an oxide semiconductor thin film transistor according to an embodiment of the present invention.
도 2a 내지 도 2c는 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터에 있어서, 다양한 형상으로 형성된 복수 개의 아일랜드 패턴의 평면도를 도시한 것이다.2A to 2C are plan views of a plurality of island patterns formed in various shapes in an oxide semiconductor thin film transistor according to an embodiment of the present invention.
도 3a는 종래의 산화물 반도체 박막 트랜지스터의 평면도를 도시한 것이고, 도 3b는 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터의 평면도를 도시한 것이다.FIG. 3A is a plan view of a conventional oxide semiconductor thin film transistor, and FIG. 3B is a plan view of an oxide semiconductor thin film transistor according to an embodiment of the present invention.
도 4a 내지 도 4h는 복수 개의 라인 패턴의 폭에 따른 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터의 특성을 도시한 것이다.4A to 4H illustrate characteristics of an oxide semiconductor thin film transistor according to an exemplary embodiment of the present invention in accordance with a width of a plurality of line patterns.
도 5a는 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터의 복수 개의 라인 패턴 사이의 간격이 1.5㎛일 경우, 복수 개의 라인 패턴의 폭의 변화에 따른 드레인 전류-게이트 전압 특성을 도시한 그래프이고, 도 5b는 복수 개의 라인 패턴 사이의 간격이 1.5㎛일 경우, 복수 개의 라인 패턴의 폭의 변화에 따른 드레인 전류-드레인 전압 특성을 도시한 그래프이다.5A is a graph showing a drain current-gate voltage characteristic according to a width of a plurality of line patterns when the interval between a plurality of line patterns of the oxide semiconductor thin film transistor according to an embodiment of the present invention is 1.5 mu m And FIG. 5B is a graph showing the drain current-drain voltage characteristics according to the width of a plurality of line patterns when the interval between the plurality of line patterns is 1.5 .mu.m.
도 5c는 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터의 복수 개의 라인 패턴 사이의 간격이 3㎛일 경우, 복수 개의 라인 패턴의 폭의 변화에 따른 드레인 전류-게이트 전압 특성을 도시한 그래프이고, 도 5d는 복수 개의 라인 패턴 사이의 간격이 3㎛일 경우, 복수 개의 라인 패턴의 폭의 변화에 따른 드레인 전류-드레인 전압 특성을 도시한 그래프이다.5C is a graph showing drain current-gate voltage characteristics according to a width of a plurality of line patterns when the interval between a plurality of line patterns of an oxide semiconductor thin film transistor according to an embodiment of the present invention is 3 mu m And FIG. 5D is a graph showing the drain current-drain voltage characteristics according to the width of a plurality of line patterns when the interval between the plurality of line patterns is 3 μm.
도 5e는 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터의 복수 개의 라인 패턴 사이의 간격이 1.5㎛ 또는 3㎛일 때, 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터의 복수 개의 라인 패턴의 폭의 변화에 따른 드레인 전류 특성을 도시한 그래프이다.5E is a cross-sectional view of the oxide semiconductor thin film transistor according to an embodiment of the present invention when the interval between a plurality of line patterns of the oxide semiconductor thin film transistor is 1.5 mu m or 3 mu m, FIG. 5 is a graph showing a drain current characteristic according to a change in width. FIG.
도 6a 내지 도 6h는 복수 개의 라인 패턴 사이의 간격에 따른 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터의 특성을 도시한 것이다.6A to 6H illustrate characteristics of an oxide semiconductor thin film transistor according to an embodiment of the present invention in accordance with the interval between a plurality of line patterns.
도 7a는 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터의 복수 개의 라인 패턴의 폭이 5㎛일 경우, 복수 개의 라인 패턴 사이의 간격의 변화에 따른 드레인 전류-게이트 전압 특성을 도시한 그래프이고, 도 7b는 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터의 복수 개의 라인 패턴의 폭이 5㎛일 경우, 복수 개의 라인 패턴 사이의 간격의 변화에 따른 드레인 전류-드레인 전압 특성을 도시한 그래프이다.FIG. 7A is a graph showing drain current-gate voltage characteristics according to a change in the interval between a plurality of line patterns when a width of a plurality of line patterns of an oxide semiconductor thin film transistor according to an embodiment of the present invention is 5 μm And FIG. 7B is a graph showing drain current-drain voltage characteristics according to a change in the interval between a plurality of line patterns when the width of a plurality of line patterns of the oxide semiconductor thin film transistor according to an embodiment of the present invention is 5 μm. to be.
도 8은 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터의 복수 개의 라인 패턴 사이의 간격의 변화에 따른 캐패시턴스-게이트 전압 특성을 도시한 그래프이다.FIG. 8 is a graph showing a capacitance-gate voltage characteristic according to a change in spacing between a plurality of line patterns of an oxide semiconductor thin film transistor according to an embodiment of the present invention.
도 9a는 복수 개의 라인 패턴 사이의 간격의 변화에 따른 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터의 인버터 특성을 도시한 그래프이고, 도 9b는 복수 개의 라인 패턴 사이의 간격의 변화에 따른 주파수를 도시한 그래프이며, 도 9c는 복수 개의 라인 패턴 사이의 간격의 변화에 따른 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터의 드레인 전류 및 캐패시턴스를 도시한 것이고, 도 9d 및 도 9e는 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터의 확산 전류를 도시한 개략도이다.FIG. 9A is a graph showing inverter characteristics of an oxide semiconductor thin film transistor according to an embodiment of the present invention in accordance with a change in the interval between a plurality of line patterns, FIG. 9B is a graph showing frequency characteristics FIG. 9C is a graph showing the drain current and capacitance of an oxide semiconductor thin film transistor according to an embodiment of the present invention in accordance with a change in the interval between a plurality of line patterns, and FIGS. 9D and 9E are cross- FIG. 2 is a schematic view showing a diffusion current of an oxide semiconductor thin film transistor according to one embodiment of the present invention.
도 10a는 복수 개의 아일랜드 패턴이 아닌 일반적인 구조의 산화물 반도체 박막 트랜지스터의 PBTS(positive bias temperature stress)를 도시한 그래프이고, 도 10b는 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터의 PBTS(positive bias temperature stress)를 도시한 그래프이다.10A is a graph showing a positive bias temperature stress (PBTS) of an oxide semiconductor thin film transistor having a general structure other than a plurality of island patterns, FIG. 10B is a graph showing a positive bias temperature (PBTS) of an oxide semiconductor thin film transistor according to an embodiment of the present invention, temperature stress.
도 10c는 복수 개의 아일랜드 패턴이 아닌 일반적인 구조의 산화물 반도체 박막 트랜지스터의 HCTS(high current temperature stress)를 도시한 그래프이고, 도 10d는 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터의 HCTS(high current temperature stress)를 도시한 그래프이다.FIG. 10C is a graph showing the HCTS (high current temperature stress) of an oxide semiconductor thin film transistor having a general structure other than a plurality of island patterns, FIG. temperature stress.
도 11a 내지 도 11c는 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터가 적용된 플렉서블 디스플레이 장치의 벤딩 테스트(Bending Test) 장비 및 신뢰성 테스트 장비를 도시한 것이다.11A to 11C show a bending test equipment and a reliability test equipment of a flexible display device to which an oxide semiconductor thin film transistor is applied according to an embodiment of the present invention.
도 11d는 복수 개의 아일랜드 패턴이 아닌 일반적인 구조의 산화물 반도체 박막 트랜지스터를 구비한 플렉서블 디스플레이 장치를 벤딩 테스트한 후에 측정한 드레인 전류-게이트 전압 특성을 나타낸 그래프이고, 도 11e는 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터를 구비한 플렉서블 디스플레이 장치를 벤딩 테스트한 후에 측정한 드레인 전류-게이트 전압 특성을 나타낸 그래프이다.11D is a graph showing drain current-gate voltage characteristics measured after bending test of a flexible display device having oxide semiconductor thin film transistors of a general structure other than a plurality of island patterns, and FIG. 11E is a graph Gate voltage characteristics measured after a bending test of a flexible display device including an oxide semiconductor thin film transistor according to the present invention.
도 11f는 벤딩 테스트가 진행된 복수 개의 아일랜드 패턴이 아닌 일반적인 구조의 산화물 반도체 박막 트랜지스터를 도시한 광학현미경 이미지이고, 도 11g는 벤딩 테스트가 진행된 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터를 도시한 광학현미경 이미지이다.11F is an optical microscope image showing an oxide semiconductor thin film transistor having a general structure other than a plurality of island patterns on which a bending test is performed, and FIG. 11G shows an oxide semiconductor thin film transistor according to an embodiment of the present invention in which a bending test is performed It is an optical microscope image.
도 12a 내지 도 12d는 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터에 있어서, 복수 개의 아일랜드 패턴으로 형성되고, 제1 영역이 분리된 소스/드레인 전극 및 산화물 반도체층의 광학현미경 이미지(Optical Microscope)이다.12A to 12D illustrate an oxide semiconductor thin film transistor according to an embodiment of the present invention, in which a first region is formed by a plurality of island patterns and an optical microscope image of an oxide semiconductor layer and source / )to be.
도 13a 내지 도 13h는 채널 길이에 따른 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터의 전송(transfer) 및 출력(output) 특성을 도시한 그래프이다.FIGS. 13A to 13H are graphs showing transfer and output characteristics of an oxide semiconductor thin film transistor according to an embodiment of the present invention, according to a channel length. FIG.
도 14a는 링 오실레이터(ring oscillator)에 사용되는 복수 개의 아일랜드 패턴이 아닌 일반적인 구조의 산화물 반도체 박막 트랜지스터를 도시한 광학 현미경 이미지이고, 도 14b는 링 오실레이터(ring oscillator)에 사용되는 본 발명의 본 발명의 일 실시예에 따른 산화물 반도체 트랜지스터를 도시한 광학 현미경 이미지이다.FIG. 14A is an optical microscope image showing an oxide semiconductor thin film transistor having a general structure not a plurality of island patterns used in a ring oscillator, and FIG. 14B is a cross- Is an optical microscope image showing an oxide semiconductor transistor according to one embodiment of the present invention.
도 15a 및 도 15b는 본 발명의 일 실시예에 따른 산화물 반도체 트랜지스터의 MOA(metal-over-active)의 열분석을 도시한 광학 현미경 이미지이고, 도 15c 및 도 15d는 본 발명의 일 실시예에 따른 산화물 반도체 트랜지스터의 AOM(active-over-metal)의 열분석을 도시한 광학 현미경 이미지이다.15A and 15B are optical microscope images showing thermal analysis of a metal-over-active (MOA) of an oxide semiconductor transistor according to an embodiment of the present invention, and Figs. 15C and 15D are cross- FIG. 2 is a light microscope image showing an active-over-metal (AOM) thermal analysis of an oxide semiconductor transistor according to the present invention.
도 16a 내지 도 16f는 복수 개의 아일랜드 패턴 사이의 간격에 따른 본 발명의 일 실시예에 따른 산화물 반도체 트랜지스터를 포함하는 링 오실레이터의 전압-시간 특성을 도시한 것이다.16A to 16F illustrate voltage-time characteristics of a ring oscillator including an oxide semiconductor transistor according to an embodiment of the present invention, according to the interval between a plurality of island patterns.
도 17a 내지 도 17h는 본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터(듀얼 게이트(Dual Gate) 구조)의 제조방법의 전체적인 흐름을 도시한 산화물 반도체 박막 트랜지스터의 단면도를 도시한 것이다.FIGS. 17A to 17H are cross-sectional views illustrating an oxide semiconductor thin film transistor showing an overall flow of a method of manufacturing an oxide semiconductor thin film transistor (dual gate structure) according to another embodiment of the present invention.
도 18a는 종래의 산화물 반도체 박막 트랜지스터의 평면도를 도시한 것이고, 도 18b는 본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터의 평면도를 도시한 것이다.FIG. 18A is a plan view of a conventional oxide semiconductor thin film transistor, and FIG. 18B is a plan view of an oxide semiconductor thin film transistor according to another embodiment of the present invention.
도 19a 내지 도 19c는 본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터(듀얼 게이트 구조)에서의 서로 다른 게이트 구동(gate driving)을 도시한 단면도이다.19A to 19C are cross-sectional views illustrating different gate driving in an oxide semiconductor thin film transistor (dual gate structure) according to another embodiment of the present invention.
도 20a 내지 도 20f는 복수 개의 라인 패턴의 폭에 따른 본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터의 특성을 도시한 것이다.FIGS. 20A to 20F show the characteristics of an oxide semiconductor thin film transistor according to another embodiment of the present invention in accordance with the width of a plurality of line patterns.
도 21a 내지 도 21f는 복수 개의 라인 패턴 사이의 간격에 따른 본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터의 특성을 도시한 것이다.FIGS. 21A to 21F show characteristics of an oxide semiconductor thin film transistor according to another embodiment of the present invention in accordance with the interval between a plurality of line patterns.
도 22a 내지 도 22c는 제1 게이트 전극과 제2 게이트 전극이 동일한 사이즈를 갖는 본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터에서 서로 다른 게이트 구동(gate driving)에 따른 전송 특성을 도시한 그래프이다.22A to 22C are graphs showing transmission characteristics according to different gate driving in an oxide semiconductor thin film transistor according to another embodiment of the present invention in which the first gate electrode and the second gate electrode have the same size .
도 22d 내지 도 22f는 제1 게이트 전극과 제2 게이트 전극이 동일한 사이즈를 갖는 본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터에서 서로 다른 게이트 구동(gate driving)에 따른 출력 특성을 도시한 그래프이다.22D to 22F are graphs showing output characteristics according to different gate driving in an oxide semiconductor thin film transistor according to another embodiment of the present invention in which the first gate electrode and the second gate electrode have the same size .
도 22g는 도 22i의 본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터에서 하부 스윕 시, 복수 개의 아일랜드 패턴 사이의 간격 변화에 따른 출력 특성을 도시한 그래프이고, 도 22h는 도 22e의 본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터에서 상부 스윕 시, 복수 개의 아일랜드 패턴 사이의 간격 변화에 따른 출력 특성을 도시한 그래프이며, 도 22i는 도 22f의 본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터에서 듀얼 스윕 시, 복수 개의 아일랜드 패턴 사이의 간격 변화에 따른 출력 특성을 도시한 그래프이다.FIG. 22G is a graph showing output characteristics according to a change in spacing between a plurality of island patterns in a lower sweep in an oxide semiconductor thin film transistor according to another embodiment of the present invention in FIG. 22I, FIG. 22H is a graph FIG. 22I is a graph showing output characteristics of the oxide semiconductor thin film transistor according to another embodiment when the upper gap sweeps between a plurality of island patterns, and FIG. 22I is a graph showing the output characteristics of the oxide semiconductor thin film transistor FIG. 5 is a graph showing output characteristics according to a change in interval between a plurality of island patterns in a dual sweep. FIG.
도 23a 내지 도 23c는 소스/드레인 전극과 제2 게이트 사이의 이격 거리가 -1㎛인 오프셋 구조를 갖는 본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터에서 서로 다른 게이트 구동(gate driving)에 따른 전송 특성을 도시한 그래프이다.FIGS. 23A to 23C are diagrams for explaining the gate driving method according to another embodiment of the present invention having an offset structure in which the distance between the source / drain electrode and the second gate is -1 mu m, And Fig.
도 23d 내지 도 23f는 소스/드레인 전극과 제2 게이트 사이의 이격 거리가 -1㎛인 오프셋 구조를 갖는 본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터에서 서로 다른 게이트 구동(gate driving)에 따른 출력 특성을 도시한 그래프이다.23D to 23F are diagrams for explaining the gate driving method according to another embodiment of the present invention having an offset structure in which the distance between the source / drain electrode and the second gate is -1 mu m, Fig.
도 23g는 도 23d의 본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터에서 하부 스윕 시, 복수 개의 아일랜드 패턴 사이의 간격 변화에 따른 출력 특성을 도시한 그래프이고, 도 23h는 도 23e의 본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터에서 상부 스윕 시, 복수 개의 아일랜드 패턴 사이의 간격 변화에 따른 출력 특성을 도시한 그래프이며, 도 23i는 도 23f의 본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터에서 듀얼 스윕 시, 복수 개의 아일랜드 패턴 사이의 간격 변화에 따른 출력 특성을 도시한 그래프이다.FIG. 23G is a graph showing output characteristics according to a change in interval between a plurality of island patterns in a lower sweep in the oxide semiconductor thin film transistor according to another embodiment of the present invention in FIG. 23D, and FIG. 23H is a graph FIG. 23I is a graph showing output characteristics according to a change in interval between a plurality of island patterns in an upper sweep in an oxide semiconductor thin film transistor according to another embodiment, and FIG. 23I is a graph showing the output characteristics of the oxide semiconductor thin film transistor FIG. 5 is a graph showing output characteristics according to a change in interval between a plurality of island patterns in a dual sweep. FIG.
도 24a 및 도 24b는 본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터에서 듀얼 스윕 시 드레인 전류(drain current) 값을 하부 스윕 시의 드레인 전류 값으로 나누었을 때의 값을 비교한 그래프이다.FIGS. 24A and 24B are graphs comparing values obtained by dividing a drain current value in a dual sweep by a drain current value in a bottom sweep in an oxide semiconductor thin film transistor according to another embodiment of the present invention. FIG.
도 25a은 제1 게이트 전극과 제2 게이트 전극이 같은 크기를 갖는 구조에서의 본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터가 듀얼 스윕 시 복수 개의 아일랜드 패턴의 간격의 변화에 따른 캐패시턴스-게이트 전압 특성을 도시한 그래프이고, 도 25b는 소스/드레인 전극과 제2 게이트 전극 사이의 이격 거리가 -1㎛인 오프셋 구조의 본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터가 듀얼 스윕 시 복수 개의 아일랜드 패턴의 간격의 변화에 따른 캐패시턴스-게이트 접압 특성을 도시한 그래프이다.25A is a graph showing the relationship between the capacitance-gate voltage < RTI ID = 0.0 > & tilde & FIG. 25B is a graph showing an oxide semiconductor thin film transistor according to another embodiment of the present invention having an offset structure in which the distance between the source / drain electrode and the second gate electrode is -1 mu m, FIG. 5 is a graph showing a capacitance-gate contact characteristic according to a change in pattern interval. FIG.
도 26a는 본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터를 1개 포함하는 화소 소자를 구비하는 디스플레이 장치의 회로도를 도시한 것이고, 도 26b는 본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터를 2개 포함하는 화소 소자를 구비하는 디스플레이 장치의 회로도를 도시한 것이다.FIG. 26A is a circuit diagram of a display device having a pixel element including one oxide semiconductor thin film transistor according to another embodiment of the present invention, and FIG. 26B is a cross-sectional view illustrating an oxide semiconductor thin film transistor according to another embodiment of the present invention. 2 shows a circuit diagram of a display device having a pixel element including two pixel elements.
도 27a 내지 도 27g는 본 발명의 또 다른 실시예에 따른 산화물 반도체 박막 트랜지스터(코플라나(Coplanar) 구조)의 제조방법의 전체적인 흐름을 도시한 산화물 반도체 박막 트랜지스터의 단면도를 도시한 것이다.FIGS. 27A to 27G show cross-sectional views of an oxide semiconductor thin film transistor showing an overall flow of a method of manufacturing an oxide semiconductor thin film transistor (Coplanar structure) according to still another embodiment of the present invention.
도 28은 본 발명의 또 다른 실시예에 따른 산화물 반도체 박막 트랜지스터(코플라나(Coplanar) 구조)의 듀얼 게이트 구조의 단면도를 도시한 것이다.28 shows a cross-sectional view of a dual gate structure of an oxide semiconductor thin film transistor (Coplanar structure) according to another embodiment of the present invention.
도 29a 및 도 29b는 본 발명의 실시예들에 따른 산화물 반도체 박막 트랜지스터의 오버랩 및 오프셋을 도시한 단면도이다.29A and 29B are cross-sectional views illustrating an overlap and an offset of an oxide semiconductor thin film transistor according to embodiments of the present invention.
이하 첨부 도면들 및 첨부 도면들에 기재된 내용들을 참조하여 본 발명의 실시예를 상세하게 설명하지만, 본 발명이 실시예에 의해 제한되거나 한정되는 것은 아니다.Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings and accompanying drawings, but the present invention is not limited to or limited by the embodiments.
본 명세서에서 사용된 용어는 실시예들을 설명하기 위한 것이며 본 발명을 제한하고자 하는 것은 아니다. 본 명세서에서, 단수형은 문구에서 특별히 언급하지 않는 한 복수형도 포함한다. 명세서에서 사용되는 "포함한다(comprises)" 및/또는 "포함하는(comprising)"은 언급된 구성요소, 단계, 동작 및/또는 소자는 하나 이상의 다른 구성요소, 단계, 동작 및/또는 소자의 존재 또는 추가를 배제하지 않는다.The terminology used herein is for the purpose of illustrating embodiments and is not intended to be limiting of the present invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. It is noted that the terms "comprises" and / or "comprising" used in the specification are intended to be inclusive in a manner similar to the components, steps, operations, and / Or additions.
본 명세서에서 사용되는 "실시예", "예", "측면", "예시" 등은 기술된 임의의 양상(aspect) 또는 설계가 다른 양상 또는 설계들보다 양호하다거나, 이점이 있는 것으로 해석되어야 하는 것은 아니다.As used herein, the terms "embodiment," "example," "side," "example," and the like should be construed as advantageous or advantageous over any other aspect or design It does not.
또한, '또는' 이라는 용어는 배타적 논리합 'exclusive or'이기보다는 포함적인 논리합 'inclusive or'를 의미한다. 즉, 달리 언급되지 않는 한 또는 문맥으로부터 명확하지 않는 한, 'x가 a 또는 b를 이용한다'라는 표현은 포함적인 자연 순열들(natural inclusive permutations) 중 어느 하나를 의미한다.Also, the term 'or' implies an inclusive or 'inclusive' rather than an exclusive or 'exclusive'. That is, unless expressly stated otherwise or clear from the context, the expression 'x uses a or b' means any of the natural inclusive permutations.
또한, 본 명세서 및 청구항들에서 사용되는 단수 표현("a" 또는 "an")은, 달리 언급하지 않는 한 또는 단수 형태에 관한 것이라고 문맥으로부터 명확하지 않는 한, 일반적으로 "하나 이상"을 의미하는 것으로 해석되어야 한다.Also, the phrase " a " or " an ", as used in the specification and claims, unless the context clearly dictates otherwise, or to the singular form, .
또한, 막, 층, 영역, 구성 요청 등의 부분이 다른 부분 "위에" 또는 "상에" 있다고 할 때, 다른 부분의 바로 위에 있는 경우뿐만 아니라, 그 중간에 다른 막, 층, 영역, 구성 요소 등이 개재되어 있는 경우도 포함한다.It will also be understood that when an element such as a film, layer, region, configuration request, etc. is referred to as being "on" or "on" another element, And the like are included.
본 발명은 다양한 변경을 가할 수 있고 여러 가지 실시예를 가질 수 있는 바, 특정 실시예들을 도면에 예시하고 상세한 설명에 상세하게 설명하고자 한다. 그러나 이는 본 발명을 특정한 실시 형태에 대해 한정하려는 것이 아니며, 본 발명의 사상 및 기술 범위에 포함되는 모든 변경, 균등물 내지 대체물을 포함하는 것으로 이해되어야 한다. 또한, 각 도면을 설명하면서 유사한 참조부호를 유사한 구성요소에 대해 사용하였다.While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It is to be understood, however, that the invention is not to be limited to the specific embodiments, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. Also, similar reference numerals have been used for like elements in describing each drawing.
이하, 도 1a 내지 도 1h를 참조하여 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터 및 이의 제조 방법에 대해 상세하게 설명하기로 한다.Hereinafter, an oxide semiconductor thin film transistor and a method of manufacturing the same according to an embodiment of the present invention will be described in detail with reference to FIGS. 1A to 1H.
본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터(100)는 기판(103), 제1 게이트 전극(105), 게이트 절연층(106), 산화물 반도체층(107), 소스/드레인 전극(108, 109) 및 패시베이션층(110)을 포함한다. 실시예에 따라, 산화물 반도체 박막 트랜지스터(100)는 지지층(102), 버퍼층(104) 및 화소 전극(111)을 더 포함할 수 있다.An oxide semiconductor thin film transistor 100 according to an embodiment of the present invention includes a substrate 103, a first gate electrode 105, a gate insulating layer 106, an oxide semiconductor layer 107, source / drain electrodes 108, 109 and a passivation layer 110. The oxide semiconductor thin film transistor 100 may further include a support layer 102, a buffer layer 104, and a pixel electrode 111. In this case,
또한, 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터(100)의 소스/드레인 전극(108, 109)은 기판(103)의 수평면을 기준으로 제1 게이트 전극(105) 방향에 형성된 제1 영역(P1) 및 제1 영역(P1)과 반대 방향에 형성된 제2 영역(P2)을 포함하고, 복수 개의 아일랜드 패턴은 제1 영역(P1)이 서로 분리되어 외부 스트레스에 대한 내성을 가진다.The source / drain electrodes 108 and 109 of the oxide semiconductor thin film transistor 100 according to an embodiment of the present invention are formed in a first region formed in the direction of the first gate electrode 105 with respect to the horizontal plane of the substrate 103 (P1) and a second region (P2) formed in a direction opposite to the first region (P1), and the plurality of island patterns have a resistance to external stress by separating the first regions (P1) from each other.
따라서, 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터(100)는 소스/드레인 전극(108, 109)의 면적을 감소시킴으로써, 제1 게이트 전극(105)과 소스/드레인 전극(108, 109) 사이에서 발생하는 기생 캐패시턴스(parasitic capacitance)이 발생을 줄일 수 있다.The oxide semiconductor thin film transistor 100 according to an embodiment of the present invention reduces the area of the source / drain electrodes 108 and 109 so that the first gate electrode 105 and the source / drain electrodes 108 and 109, The occurrence of parasitic capacitance can be reduced.
이하, 도 1a 내지 도 1h를 참조하여 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터의 각 구성 요소에 대해 보다 상세하게 설명하기로 한다.Hereinafter, each element of the oxide semiconductor thin film transistor according to one embodiment of the present invention will be described in detail with reference to FIGS. 1A to 1H.
도 1a 내지 도 1h는 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터의 제조 방법의 전체적인 흐름을 도시한 산화물 반도체 박막 트랜지스터의 단면도를 도시한 것이다.FIGS. 1A to 1H illustrate cross-sectional views of an oxide semiconductor thin film transistor illustrating an overall flow of a method of manufacturing an oxide semiconductor thin film transistor according to an embodiment of the present invention.
도 1a를 참조하면, 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터(100)의 제조방법은, 캐리어 기판(101) 상에 지지층(102)은 및 기판(103)을 형성한다.Referring to FIG. 1A, a method of manufacturing an oxide semiconductor thin film transistor 100 according to an embodiment of the present invention includes forming a support layer 102 and a substrate 103 on a carrier substrate 101.
도 1a에 도시된 바와 같이, 지지층(102)은 캐리어 기판(101) 상에 형성된다. 다만, 지지층(102)은 반드시 필요한 구성은 아니다.As shown in Fig. 1A, a support layer 102 is formed on the carrier substrate 101. Fig. However, the supporting layer 102 is not necessarily required.
일 실시예에 따라, 지지층(102)은 탄소나노튜브-그래핀 산화물(Carbon Nano Tube-Graphene Oxide, CNT-GO)을 이용하여 투명성을 갖도록 형성될 수 있다. 탄소나노튜브-그래핀 산화물 지지층(102)은 휘어지는 성질이 있어 플렉서블 디스플레이 장치에 적용하기에 적합하다.According to one embodiment, the support layer 102 may be formed to have transparency using a carbon nanotube-graphene oxide (CNT-GO). The carbon nanotube-graphene oxide support layer 102 has a bending property and is suitable for application to a flexible display device.
기판(103)은 지지층(102) 상에 형성된다. 기판(103)은 산화물 반도체 박막 트랜지스터의 여러 구성 요소들을 지지하기 위한 기판으로서, 가요성(flexibility)을 갖는 플렉서블 기판일 수 있다.A substrate 103 is formed on the support layer 102. The substrate 103 may be a flexible substrate having flexibility, as a substrate for supporting various components of the oxide semiconductor thin film transistor.
플렉서블 기판은 특정 방향으로 벤딩(bending) 또는 폴딩(folding)될 수 있다. 예를 들어, 플렉서블 기판은 가로 방향, 세로 방향 또는 사선 방향으로 폴딩될 수 있다.The flexible substrate can be bended or folded in a specific direction. For example, the flexible substrate may be folded in the transverse direction, the longitudinal direction, or the diagonal direction.
플렉서블 기판은 지지층(102)이 형성된 캐리어 기판(101) 상에 예를 들어 폴리이미드계 용액을 코팅함으로써 형성될 수 있고, 필름 형태일 수 있다.The flexible substrate may be formed, for example, by coating a polyimide-based solution on the carrier substrate 101 on which the support layer 102 is formed, and may be in the form of a film.
기판(103)은 유리, 폴리이미드계 고분자, 폴리에스터계 고분자, 실리콘계 고분자, 아크릴계 고분자, 폴리올레핀계 고분자 또는 이들의 공중합체로 이루어진 그룹으로부터 선택되는 어느 하나의 물질로 이루어질 수 있다.The substrate 103 may be made of any one material selected from the group consisting of glass, a polyimide-based polymer, a polyester-based polymer, a silicon-based polymer, an acrylic polymer, a polyolefin-based polymer, or a copolymer thereof.
기판(103)으로 플렉서블 기판이 사용되는 경우, 예를 들어, 폴리에스테르(Polyester), 폴리비닐(Polyvinyl), 폴리카보네이트(Polycarbonate), 폴리에틸렌(Polyethylene), 폴리아세테이트(Polyacetate), 폴리이미드(Polyimide), 폴리에테르술폰(Polyethersulphone; PES), 폴리아크릴레이트(Polyacrylate; PAR), 폴리에틸렌나프탈레이트(Polyethylenenaphthelate; PEN) 및 폴리에틸렌에테르프탈레이트(Polyethyleneterephehalate; PET)으로 이루어진 그룹으로부터 선택되는 어느 하나의 물질로 이루어질 수 있다.When a flexible substrate is used as the substrate 103, for example, a flexible substrate such as a polyester, a polyvinyl, a polycarbonate, a polyethylene, a polyacetate, a polyimide, , Polyethylene terephthalate (PES), polyacrylate (PAR), polyethylene naphthalate (PEN), and polyethylene ether phthalate (PET). .
일 실시예에 따라, 산화물 반도체 박막 트랜지스터(100)가 구비되는 디스플레이 장치가 투명 플렉서블 디스플레이 장치로 구현되는 경우, 기판(103)은 투명한 플렉서블의 물질로 이루어질 수 있다.According to one embodiment, when the display device including the oxide semiconductor thin film transistor 100 is implemented as a transparent flexible display device, the substrate 103 may be made of a transparent flexible material.
기판(103)은 적어도 하나 이상의 박막 트랜지스터 영역을 포함할 수 있다. 박막 트랜지스터(TFT)는 박막 트랜지스터 영역에 배치될 수 있고, 박막 트랜지스터 영역은 기판(103)에서 매트릭스 형태로 배치될 수 있다.The substrate 103 may include at least one or more thin film transistor regions. The thin film transistor (TFT) may be disposed in the thin film transistor region, and the thin film transistor region may be disposed in the matrix on the substrate 103.
기판(103)은 두께가 1 ㎛ 내지 30 ㎛ 범위 내에서 정해질 수 있으며, 바람직하게는 1 ㎛ 내지 10 ㎛ 범위 내에서 정해질 수 있다.The substrate 103 may have a thickness within a range of 1 占 퐉 to 30 占 퐉, and preferably within a range of 1 占 퐉 to 10 占 퐉.
도 1b를 참조하면, 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터(100)의 제조방법은, 기판(103) 상에 버퍼층(buffer layer)(104)을 형성한다.Referring to FIG. 1B, a method of fabricating an oxide semiconductor thin film transistor 100 according to an embodiment of the present invention includes forming a buffer layer 104 on a substrate 103.
도 1b에 도시된 바와 같이, 버퍼층(104)은 기판(103) 상에 형성될 수 있다.As shown in FIG. 1B, the buffer layer 104 may be formed on the substrate 103.
버퍼층(104)은 기판(103)을 통한 수분 또는 산소와 같은 외부 불순물의 침투를 방지하며, 기판(103)의 표면을 평탄화할 수 있다. 다만, 버퍼층(104)은 반드시 필요한 구성은 아니며, 기판(103)의 종류에 따라 채택되거나 생략될 수 있다.The buffer layer 104 prevents penetration of external impurities such as moisture or oxygen through the substrate 103 and can flatten the surface of the substrate 103. [ However, the buffer layer 104 is not necessarily required and may be adopted or omitted depending on the type of the substrate 103. [
또한, 도 1b에 도시된 바와 같이, 버퍼층(104)이 사용되는 경우, 버퍼층(104)은 실리콘옥사이드(SiOx), 실리콘나이트라이드(SiNx), 알루미늄옥사이드(AlOx) 등의 무기물 또는 아크릴 또는 폴리이미드 등의 유기물로 이루어질 수 있다. 1B, when the buffer layer 104 is used, the buffer layer 104 may be formed of an inorganic material such as silicon oxide (SiOx), silicon nitride (SiNx), aluminum oxide (AlOx), or an inorganic material such as acrylic or polyimide And the like.
도 1c를 참조하면, 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터(100)의 제조방법은, 버퍼층(104)이 형성된 기판(103) 상에 제1 게이트 전극(105)을 형성한다.Referring to FIG. 1C, a method of manufacturing an oxide semiconductor thin film transistor 100 according to an embodiment of the present invention includes forming a first gate electrode 105 on a substrate 103 on which a buffer layer 104 is formed.
도 1c에 도시된 바와 같이, 제1 게이트 전극(105)은 버퍼층(104) 상에 형성될 수 있고, 제1 게이트 전극(105)은 하부 게이트 전극(Bottom Gate)일 수 있다.1C, the first gate electrode 105 may be formed on the buffer layer 104, and the first gate electrode 105 may be a bottom gate electrode.
제1 게이트 전극(105)은 버퍼층(104) 상에 게이트 도전막(미도시)을 증착하고, 게이트 도전막 상에 포토레지스트 패턴을 형성한 후, 포토레지스트 패턴을 마스크로 하여 게이트 도전막을 선택적으로 식각, 즉, 패터닝함으로써 형성될 수 있다.The first gate electrode 105 is formed by depositing a gate conductive film (not shown) on the buffer layer 104, forming a photoresist pattern on the gate conductive film, selectively etching the gate conductive film using the photoresist pattern as a mask For example, by etching, i.e., patterning.
일 실시예에 따라, 제1 게이트 전극(105)은 산화물 반도체층(107) 상에 형성된 소스/드레인 전극(108, 109)으로부터 수평 방향으로 -1 ㎛ 내지 3 ㎛ 만큼 이격(오프셋 및 오버랩)되도록 형성될 수 있다.The first gate electrode 105 is spaced from the source / drain electrodes 108 and 109 formed on the oxide semiconductor layer 107 in the horizontal direction by 1 占 퐉 to 3 占 퐉 (offset and overlap) .
제1 게이트 전극(105)이 산화물 반도체층(107) 상에 형성된 소스/드레인 전극(108, 109)으로부터 이격되는 기술에 대해서는 도 29a 및 도 29b를 참고하여 설명하기로 한다.A technique in which the first gate electrode 105 is spaced apart from the source / drain electrodes 108 and 109 formed on the oxide semiconductor layer 107 will be described with reference to FIGS. 29A and 29B.
도 29a 및 도 29b는 도 29a 및 도 29b는 본 발명의 실시예들에 따른 산화물 반도체 박막 트랜지스터의 오버랩 및 오프셋을 도시한 단면도이다.29A and 29B are cross-sectional views showing overlap and offset of an oxide semiconductor thin film transistor according to embodiments of the present invention.
오프셋(Offset) 및 오버랩(Overlap)은 제1 게이트 전극(105)의 일단과 소스 전극(108) 사이의 폭 및 제1 게이트 전극(105)의 타단과 드레인 전극(109) 사이의 폭 중 적어도 하나를 의미한다.The offset and the overlap may be at least one of a width between one end of the first gate electrode 105 and the source electrode 108 and a width between the other end of the first gate electrode 105 and the drain electrode 109 .
예를 들면, 오버랩(Overlap)은 기판에서 수직한 방향으로 제1 게이트 전극(105) 및 소스 전극(108)을 바라보았을 때, 제1 게이트 전극(105)과 소스 전극(108)이 겹쳐지는 부분을 의미한다. 따라서, 오버랩은 0 ㎛ 내지 3 ㎛까지의 너비를 의미한다.For example, when the first gate electrode 105 and the source electrode 108 are viewed from the substrate in a direction perpendicular to the substrate, the overlapped portion overlaps the first gate electrode 105 and the source electrode 108 . Thus, the overlap means a width from 0 mu m to 3 mu m.
오프셋(Offset)은 기판에서 수직한 방향으로 제1 게이트 전극(105) 및 소스 전극(108)을 바라보았을 때, 제1 게이트 전극(105)과 소스 전극(108)이 수평방향으로 이격된 거리를 의미한다. 따라서, 오프셋은 -1 ㎛ 내지 0 ㎛까지의 너비를 의미한다.Offset refers to the distance between the first gate electrode 105 and the source electrode 108 in the horizontal direction when viewing the first gate electrode 105 and the source electrode 108 in a direction perpendicular to the substrate it means. Therefore, the offset means the width from -1 mu m to 0 mu m.
따라서, 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터의 제1 게이트 전극(105)의 오프셋은 산화물 반도체층(107)의 하단 계면(interface)에 형성되어 있는 결함(defect) 영역을 감소시켜, PBS(Positive Bias Stress)에서의 문턱전압 변화를 감소시켜 산화물 반도체 트랜지스터의 전기적 특성을 향상시킬 수 있다.Therefore, the offset of the first gate electrode 105 of the oxide semiconductor thin film transistor according to an embodiment of the present invention reduces the defect region formed at the lower interface of the oxide semiconductor layer 107, The threshold voltage change in the positive bias stress (PBS) can be reduced to improve the electrical characteristics of the oxide semiconductor transistor.
다시, 도 1c를 참조하면, 제1 게이트 전극(105)은 금속 물질로 형성될 수 있으며, 예를 들어, 몰리브덴(Mo), 알루미늄(Al), 크롬(Cr), 금(Au), 티타늄(Ti), 니켈(Ni), 네오디뮴(Nd) 및 구리(Cu) 중 어느 하나 또는 이들의 조합으로 이루어질 수 있으나, 이에 제한되지 않고, 다양한 물질로 이루어질 수 있다. 또한, 제1 게이트 전극(105)은 상술한 물질을 포함하는 단일층 또는 복층 구조로 형성될 수 있다.1C, the first gate electrode 105 may be formed of a metal material such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or combinations thereof, but may be made of various materials. Also, the first gate electrode 105 may be formed as a single layer or a multi-layer structure including the above-described material.
제1 게이트 전극(105)은 진공 증착법 (vacuum deposition), 화학 기상 증착법(chemical vapor deposition), 물리 기상 증착법(physical vapor deposition), 원자층 증착법(atomic layer deposition), 유기금속 화학 증착법(Metal Organic Chemical Vapor Deposition), 플라즈마 화학 증착법(Plasma-Enhanced Chemical Vapor Deposition), 분자선 성장법(Molecular Beam Epitaxy), 수소화물 기상 성장법(Hydride Vapor Phase Epitaxy), 스퍼터링(Sputtering), 스핀 코팅(spin coating), 딥 코팅(dip coating) 및 존 캐스팅(zone casting) 중 적어도 하나의 방법을 이용하여 형성될 수 있다.The first gate electrode 105 may be formed by any one of a vacuum deposition method, a chemical vapor deposition method, a physical vapor deposition method, an atomic layer deposition method, a metal organic chemical vapor deposition method Vapor deposition, plasma-enhanced chemical vapor deposition, molecular beam epitaxy, hydride vapor phase epitaxy, sputtering, spin coating, dip coating, Coating may be formed using at least one of dip coating and zone casting.
도 1d를 참조하면, 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터(100)의 제조방법은, 제1 게이트 전극(105) 상에 게이트 절연층(106) 및 산화물 반도체막(107a)을 형성한다.1D, a method of manufacturing an oxide semiconductor thin film transistor 100 according to an embodiment of the present invention includes forming a gate insulating layer 106 and an oxide semiconductor film 107a on a first gate electrode 105 do.
도 1d에 도시된 바와 같이, 게이트 절연층(Gate Insulator)(106)은 제1 게이트 전극(105) 상에 형성된다.As shown in FIG. 1D, a gate insulator 106 is formed on the first gate electrode 105.
구체적으로, 게이트 절연층(106)은 제1 게이트 전극(105)이 형성된 버퍼층(104) 상에 형성되어 제1 게이트 전극(105)과 산화물 반도체층(107)(도 1e 참조)을 절연시킨다. 즉, 제1 게이트 전극(105)과 산화물 반도체층(107)은 게이트 절연층(106)에 의하여 절연된다.Specifically, the gate insulating layer 106 is formed on the buffer layer 104 on which the first gate electrode 105 is formed to insulate the first gate electrode 105 and the oxide semiconductor layer 107 (see FIG. 1E). That is, the first gate electrode 105 and the oxide semiconductor layer 107 are insulated by the gate insulating layer 106.
게이트 절연층(106)은 도 1d에 도시된 바와 같이, 제1 게이트 전극(105)을 포함하는 버퍼층(104)의 전면을 덮도록 형성될 수 있다.The gate insulating layer 106 may be formed to cover the entire surface of the buffer layer 104 including the first gate electrode 105, as shown in FIG.
게이트 절연층(106)은 진공 증착법 (vacuum deposition), 화학 기상 증착법(chemical vapor deposition), 물리 기상 증착법(physical vapor deposition), 원자층 증착법(atomic layer deposition), 유기금속 화학 증착법(Metal Organic Chemical Vapor Deposition), 플라즈마 화학 증착법(Plasma-Enhanced Chemical Vapor Deposition), 분자선 성장법(Molecular Beam Epitaxy), 수소화물 기상 성장법(Hydride Vapor Phase Epitaxy), 스퍼터링(Sputtering), 스핀 코팅(spin coating), 딥 코팅(dip coating) 및 존 캐스팅(zone casting) 중 적어도 하나의 방법을 이용하여 형성될 수 있다.The gate insulating layer 106 may be formed by a method such as vacuum deposition, chemical vapor deposition, physical vapor deposition, atomic layer deposition, metalorganic chemical vapor deposition Deposition, Plasma-Enhanced Chemical Vapor Deposition, Molecular Beam Epitaxy, Hydride Vapor Phase Epitaxy, Sputtering, Spin Coating, Dip Coating, a dip coating method and a zone casting method.
바람직하게 게이트 절연층(106)은 게이트 절연층을 형성하기 위한 용액을 이용한 스핀 코팅에 의해 형성될 수 있고, 스핀 코팅은 기판(103) 상에 게이트 절연층(106)을 형성하기 위한 용액을 일정량 떨어뜨리고 기판(103)을 고속으로 회전시켜서 게이트 절연층(106)을 형성하기 위한 용액에 가해지는 원심력으로 코팅하는 방법으로, 스핀 코팅을 이용하면 증착 공정에 비하여 생산 비용을 절감시킬 수 있고, 공정 기술의 단순화를 통하여 공정 비용 및 공정 시간을 감소시킬 수 있다.Preferably, the gate insulating layer 106 may be formed by spin coating using a solution for forming a gate insulating layer, and spin coating may be performed by using a solution for forming the gate insulating layer 106 on the substrate 103 The substrate 103 is rotated at a high speed and coated with a centrifugal force applied to a solution for forming the gate insulating layer 106. By using spin coating, the production cost can be reduced as compared with the deposition process, Simplification of technology can reduce process cost and process time.
게이트 절연층(106)은 예를 들어, 실리콘옥사이드(SiOx), 실리콘나이트라이드(SiNx), 티타늄옥사이드(TiOx), 하프늄옥사이드(HfOx) 등의 무기물 또는 폴리비닐알코올(PVA), 폴리비닐피롤리돈(PVP), 폴리메틸메타크릴레이트(PMMA) 등의 유기물일 수 있다. 또한, 게이트 절연층(106)은 상술한 물질을 포함하는 단일층 또는 복층 구조로 형성될 수 있으나, 이에 제한되지 않고, 다양한 물질로 형성될 수 있다.The gate insulating layer 106 may be formed of an inorganic material such as a silicon oxide (SiOx), a silicon nitride (SiNx), a titanium oxide (TiOx), a hafnium oxide (HfOx), or a polyvinyl alcohol (PVP), polymethyl methacrylate (PMMA), and the like. In addition, the gate insulating layer 106 may be formed of a single layer or a multi-layer structure including the above-described materials, but is not limited thereto, and may be formed of various materials.
산화물 반도체막(107a)은 게이트 절연층(106) 상에 형성된다.An oxide semiconductor film 107a is formed on the gate insulating layer 106. [
구체적으로, 산화물 반도체막(107a)은 산화물 반도체층(107)의 형성을 위한 막으로서, 게이트 절연층(106) 상에서 게이트 절연층(106)의 전면을 덮도록 형성된다. 이후, 산화물 반도체막(107a) 상에 포토레지스트 패턴을 형성하고, 포토레지스트 패턴을 마스크로 하여 산화물 반도체막(107a)을 박막 트랜지스터 영역에서 제1 게이트 전극(105)과 대응되도록 패터닝함으로써 산화물 반도체층(107)(도 1e 참조)이 형성될 수 있다.Specifically, the oxide semiconductor film 107a is formed so as to cover the entire surface of the gate insulating layer 106 on the gate insulating layer 106, as a film for forming the oxide semiconductor layer 107. [ Thereafter, a photoresist pattern is formed on the oxide semiconductor film 107a, and the oxide semiconductor film 107a is patterned to correspond to the first gate electrode 105 in the thin film transistor region using the photoresist pattern as a mask, (See FIG. 1E) may be formed.
도 1e를 참조하면, 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터(100)의 제조방법은, 제1 게이트 전극(105) 상에 산화물 반도체층(107) 및 소스/드레인 전극(108, 109)을 형성한다.A method of fabricating an oxide semiconductor thin film transistor 100 according to an embodiment of the present invention includes forming an oxide semiconductor layer 107 and source / drain electrodes 108 and 109 on a first gate electrode 105, ).
도 1e에 도시된 바와 같이, 산화물 반도체층(107)은 게이트 절연층(106) 상에 제1 게이트 전극(105)과 대응되도록 형성된다.The oxide semiconductor layer 107 is formed to correspond to the first gate electrode 105 on the gate insulating layer 106, as shown in FIG.
산화물 반도체층(107)은 진공 증착법 (vacuum deposition), 화학 기상 증착법(chemical vapor deposition), 물리 기상 증착법(physical vapor deposition), 원자층 증착법(atomic layer deposition), 유기금속 화학 증착법(Metal Organic Chemical Vapor Deposition), 플라즈마 화학 증착법(Plasma-Enhanced Chemical Vapor Deposition), 분자선 성장법(Molecular Beam Epitaxy), 수소화물 기상 성장법(Hydride Vapor Phase Epitaxy), 스퍼터링(Sputtering), 스핀 코팅(spin coating), 딥 코팅(dip coating) 및 존 캐스팅(zone casting) 중 적어도 하나의 방법을 통하여 형성될 수 있으며, 다양한 산화물 반도체 물질로 형성될 수 있다.The oxide semiconductor layer 107 may be formed by a vacuum deposition method, a chemical vapor deposition method, a physical vapor deposition method, an atomic layer deposition method, a metal organic chemical vapor deposition method Deposition, Plasma-Enhanced Chemical Vapor Deposition, Molecular Beam Epitaxy, Hydride Vapor Phase Epitaxy, Sputtering, Spin Coating, Dip Coating, dip coating, and zone casting, and may be formed of various oxide semiconductor materials.
산화물 반도체층(107)은 예를 들어, 인듐갈륨징크옥사이드(IGZO), 징크옥사이드(ZnO), 인듐징크옥사이드(IZO), 인듐틴옥사이드(ITO), 징크틴옥사이드(ZTO), 갈륨징크옥사이드(GZO), 하프늄인듐징크옥사이드(HIZO), 징크인듐틴옥사이드(ZITO) 및 알루미늄징크옥사이드(AZTO)로 이루어진 그룹으로부터 선택되는 어느 하나를 포함하여 형성될 수 있으나, 이에 제한되지 않고, 다양한 물질로 형성될 수 있다.The oxide semiconductor layer 107 may be formed of, for example, indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium zinc oxide (IZO), indium tin oxide (ITO), zinc tin oxide (ZTO), gallium zinc oxide (ZZO), hafnium indium zinc oxide (HIZO), zinc indium tin oxide (ZITO), and aluminum zinc oxide (AZTO). However, it is not limited thereto. .
산화물 반도체층(107)은 상술한 물질을 포함하는 비정질 또는 다결정질로 형성될 수 있다.The oxide semiconductor layer 107 may be formed of an amorphous or polycrystalline material including the above-described material.
본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터(100)는 산화물 반도체층(107) 상에 에치스토퍼층(Etch Stopper Layer)(미도시)층을 더 포함할 수 있다.The oxide semiconductor thin film transistor 100 according to an embodiment of the present invention may further include an etch stopper layer (not shown) on the oxide semiconductor layer 107.
상기 에치스토퍼층은 산화물 반도체층(107)의 안정성을 확보하기 위하여 산화물 반도체층(107)의 상부 표면에서 식각액으로부터의 보호를 위해 구비될 수 있다. 즉, 상기 에치스토퍼층은 소스/드레인 전극(108, 109)의 식각 공정에서 유입되는 식각액으로부터 산화물 반도체층(107)을 보호할 수 있다. 상기 에치스토퍼층은 예를 들어, 실리콘옥사이드(SiOx)로 이루어질 수 있다.The etch stopper layer may be provided for protecting the upper surface of the oxide semiconductor layer 107 from the etchant to secure the stability of the oxide semiconductor layer 107. That is, the etch stopper layer can protect the oxide semiconductor layer 107 from the etchant flowing in the etching process of the source / drain electrodes 108 and 109. The etch stopper layer may be made of, for example, silicon oxide (SiOx).
산화물 반도체층(107)은 채널이 형성되는 채널 영역 및 소스/드레인 전극(108, 109)과 각각 연결되는 소스/드레인 영역을 포함할 수 있다.The oxide semiconductor layer 107 may include a channel region where a channel is formed and source / drain regions connected to the source / drain electrodes 108 and 109, respectively.
소스/드레인 전극(108, 109)은 산화물 반도체층(107) 상에 서로 이격되어 형성된다.The source / drain electrodes 108 and 109 are formed on the oxide semiconductor layer 107 so as to be spaced apart from each other.
구체적으로, 소스/드레인 전극(108, 109)은 소스 전극(108) 및 드레인 전극(109)을 의미하고, 소스 전극(108) 및 드레인 전극(109)은 산화물 반도체층(107)이 형성된 게이트 절연층(106) 상에서 서로 이격되되, 각각 산화물 반도체층(107)과 전기적으로 연결되도록 형성된다.More specifically, the source / drain electrodes 108 and 109 refer to the source electrode 108 and the drain electrode 109, and the source electrode 108 and the drain electrode 109 refer to the gate insulating film 107 formed with the oxide semiconductor layer 107 And are formed to be electrically connected to the oxide semiconductor layer 107, respectively.
소스/드레인 전극(108, 109)은 산화물 반도체층(107)을 포함하는 게이트 절연층(106) 상에 소스/드레인 도전막(미도시)을 증착하고, 소스/드레인 도전막 상에 포토레지스트 패턴을 형성한 후, 포토레지스트 패턴을 마스크로 하여 소스/드레인 도전막을 패터닝함으로써 형성될 수 있는데, 이때 포토레지스트 패턴을 다양한 형상으로 구현함으로써 다양한 형상을 가진 복수 개의 아일랜드 패턴으로 소스/드레인 전극(108, 109)을 형성할 수 있다.The source / drain electrodes 108 and 109 are formed by depositing a source / drain conductive film (not shown) on the gate insulating layer 106 including the oxide semiconductor layer 107 and forming a photoresist pattern And then patterning the source / drain conductive film using the photoresist pattern as a mask. By forming the photoresist pattern in various shapes, the source / drain electrodes 108, 109 can be formed.
보다 구체적으로, 소스/드레인 전극(108, 109)은 스퍼터링법을 통하여 소스/드레인 도전막을 증착한 후, 포토리소그래피(Photolithography) 공정을 통하여 소정의 아일랜드 패턴을 가지는 포토레지스트 패턴 마스크로 패터닝하여 형성할 수 있다.More specifically, the source / drain electrodes 108 and 109 are formed by depositing a source / drain conductive film through a sputtering method, and then patterning the substrate using a photoresist pattern mask having a predetermined island pattern through a photolithography process .
본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터의 소스/드레인 전극(108, 109)은 복수개의 아일랜드 패턴을 포함할 수 있다.The source / drain electrodes 108 and 109 of the oxide semiconductor thin film transistor according to an embodiment of the present invention may include a plurality of island patterns.
또한, 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터의 소스/드레인 전극(108, 109)은 기판(103)의 수평면을 기준으로 제1 게이트 전극(105) 방향에 형성된 제1 영역(P1) 및 제1 영역(P1)과 반대 방향에 형성된 제2 영역(P2)을 포함하고, 복수 개의 아일랜드 패턴은 제1 영역(P1)이 서로 분리되도록 형성하여, 소스/드레인 전극(108, 109)의 단면적을 감소시킴으로써, 제1 게이트 전극(105)과 소스/드레인 전극(108, 109) 사이에서 발생하는 기생 캐패시턴스가 발생을 줄일 수 있고, 휨 또는 구부림 등의 외부 스트레스에 대한 내성을 향상시켜 외부 스트레스에 의한 손상을 방지할 수 있다.The source / drain electrodes 108 and 109 of the oxide semiconductor thin film transistor according to an embodiment of the present invention may include a first region P1 formed in the direction of the first gate electrode 105 with respect to a horizontal plane of the substrate 103, And a second region P2 formed in a direction opposite to the first region P1 and the plurality of island patterns are formed so that the first regions P1 are separated from each other and the source / drain electrodes 108 and 109 By reducing the cross-sectional area, parasitic capacitance generated between the first gate electrode 105 and the source / drain electrodes 108 and 109 can be reduced, and resistance to external stresses such as bending or bending can be improved, It is possible to prevent damage from being caused.
보다 구체적으로, 제 1영역(P1)이 분리되지 않은 소스/드레인 전극(108, 109)을 포함(예; ▤, ▦, ▧ 또는 ▨)하는 종래의 산화물 반도체 박막 트랜지스터의 경우, 기생 캐패시턴가 발생하는 동시에 일정하지 않은 전류 값에 의해 디스플레이 장치에 사용하기에 적합하지 않고, 플렉서블 디자인에 적용 시, 넓은 면적의 소스/드레인 전극(108, 109)의 에 의해 쉽게 크랙 이 발생하는 문제점을 가지고 있다.More specifically, in the case of a conventional oxide semiconductor thin film transistor in which the first region P1 includes the source / drain electrodes 108 and 109 that are not separated (e.g., ▤, ▦, ▧, or ▨), parasitic capacitances And is not suitable for use in a display device due to a non-constant current value. When applied to a flexible design, cracks are easily generated by a large area of the source / drain electrodes 108 and 109 .
그러나, 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터(100)에 포함되는 제 1영역(P1)이 분리(예; ≡ 또는 ＃)된 소스/드레인 전극(108, 109)은 제 1영역(P1)이 분리되도록 형성됨으로써, 기생 캐패시턴스를 감소시키고, 일정한 전류 값에 의한 소자 안정화 및 플렉서블 디자인에서 크랙 발생을 방지할 수 있다.However, the source / drain electrodes 108 and 109, which are separated (e.g.,? Or #) in the first region P1 included in the oxide semiconductor thin film transistor 100 according to an embodiment of the present invention, P1 are separated so that the parasitic capacitance can be reduced and device stability by a constant current value and crack occurrence in the flexible design can be prevented.
특히, 기생 캐패시턴스는 제1 게이트 전극(105)과 소스/드레인 전극(108, 109)이 오버랩되는 부분에서 발생되나, 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터(100)는 제1 게이트 전극(105)과 소스/드레인 전극(108, 109)이 오버랩되는 부분인 제1 영역(P1)이 분리된 소스/드레인 전극(108, 109)을 사용함으로써, 기생 캐패시턴스를 감소시킬뿐만 아니라, 소스/드레인 전극(108, 109)의 면적을 줄여 크랙 발생을 방지할 수 있다.In particular, the parasitic capacitance is generated in a portion where the first gate electrode 105 and the source / drain electrodes 108 and 109 overlap each other. However, in the oxide semiconductor thin film transistor 100 according to the embodiment of the present invention, The source / drain electrodes 108 and 109 are used to separate the first region P1 where the source / drain electrodes 108 and 109 are overlapped with each other, thereby reducing the parasitic capacitance, The area of the drain electrodes 108 and 109 can be reduced to prevent the occurrence of cracks.
또한, 본 발명의 일 실시예에 따르면, 산화물 반도체 박막 트랜지스터는 제1 영역(P1)이 분리된 복수 개의 아일랜드 패턴의 소스/드레인 전극(108, 109)을 포함함으로써, 소스 전극(108) 및 드레인 전극(109) 사이에 확산 전류(spreading currents)를 발생시킬 수 있다.According to an embodiment of the present invention, the oxide semiconductor thin film transistor includes a plurality of island pattern source / drain electrodes 108 and 109 having a first region P1 separated from the source electrode 108, So that spreading currents can be generated between the electrodes 109. [
보다 구체적으로, 제1 게이트 전극(105)은 산화물 반도체층(107)의 전면에 분포하여 전체 산화물 반도체층(107)의 채널 영역이 제1 게이트 전극(105)의 필드(field)에 의해 전자가 축적되고, 이때, 소스/드레인 전극(108, 109) 사이의 필드에 의해 전류(current)가 흐르게 된다.More specifically, the first gate electrode 105 is distributed over the entire surface of the oxide semiconductor layer 107, so that the channel region of the entire oxide semiconductor layer 107 is formed by the field of the first gate electrode 105 At this time, a current flows through the field between the source / drain electrodes 108 and 109.
본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터는 소스/드레인 전극(108, 109)이 제1 영역(P1)이 분리되고, 복수 개의 아일랜드 패턴으로 나누어져 있어, 확산되는 필드에 의해 확산 전류가 발생될 수 있다.In the oxide semiconductor thin film transistor according to an embodiment of the present invention, the source / drain electrodes 108 and 109 are separated from each other by a first region P1 and are divided into a plurality of island patterns, Lt; / RTI >
더 나아가, 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터와 같이, 소스/드레인 전극(108, 109)이 제1 영역(P1)이 분리되고, 복수 개의 아일랜드 패턴으로 형성되는 경우, 확산되는 필드에 의해 확산 전류가 더욱 발생될 수 있다.In the case where the first region P1 is separated from the source / drain electrodes 108 and 109 and is formed of a plurality of island patterns, as in an oxide semiconductor thin film transistor according to an embodiment of the present invention, A diffusion current can be further generated.
또한, 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터는 산화물 반도체층(107)을 형성한 다음, 산화물 반도체층(107)의 상단 계면(interface)에서 진행되는 추가 공정이 많기 때문에, 산화물 반도체층(107)의 상단 계면(interface)이 하단 계면(interface)보다 상대적으로 많은 결함(defect)을 포함하고 있다.In addition, since the oxide semiconductor thin film transistor according to an embodiment of the present invention has many additional processes to be performed at the upper interface of the oxide semiconductor layer 107 after the oxide semiconductor layer 107 is formed, The upper interface of the lower layer 107 contains a relatively larger number of defects than the lower interface.
그러나, 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터(100)는 복수 개의 아일랜드 패턴의 제1 영역(P1)이 서로 분리되도록 형성함으로써, 산화물 반도체층(107)의 상단 계면(interface)에 형성되어 있는 결함(defect) 영역을 감소시켜, PBTS(positive bias temperature stress) 또는 HCTS(high current temperature stress)에서의 문턱전압 변화를 감소시켜 산화물 반도체 트랜지스터의 전기적 특성을 향상시킬 수 있다.However, the oxide semiconductor thin film transistor 100 according to an embodiment of the present invention is formed so that the first regions P1 of the island patterns are separated from each other, thereby forming the oxide semiconductor layer 107 at the upper interface And reduce the threshold voltage at the positive bias temperature stress (PBTS) or the high current temperature stress (HCTS) to improve the electrical characteristics of the oxide semiconductor transistor.
보다 구체적으로, PBTS(positive bias temperature stress)는 제1 게이트 전극(105)에 바이어스(bias)를 가하는 스트레스로, 소스/드레인 전극(108, 109)을 제1 영역(P1)이 서로 분리된 복수 개의 아일랜드 패턴으로 형성함으로써, 발생된는 열을 감소시킬 뿐만 아니라 열이 쉽게 분산되어 스트레스를 감소시켜 안정화 특성을 나타낼 수 있다.More specifically, the positive bias temperature stress (PBTS) is a stress that biases the first gate electrode 105, and the source / drain electrodes 108 and 109 are connected to a plurality of first regions P1 separated from each other Shaped irregular pattern, the generated heat not only reduces the heat but also the heat is easily dispersed to reduce the stress and to exhibit the stabilization characteristic.
HCTS(high current temperature stress)은 제1 게이트 전극(105)과 드레인 전극(109) 사이의 바이어스(bias)를 주는 채널 영역에 가해지는 전류 스트레스로, 소스/드레인 전극(108, 109)을 제1 영역(P1)이 서로 분리된 복수 개의 아일랜드 패턴으로 형성함으로써, 발생하는 열을 감소시킬 뿐만 아니라 열이 쉽게 분산되어 스트레스를 감소시켜 소자를 안정화시킬 수 있다.The high current temperature stress (HCTS) is a current stress applied to a channel region which gives a bias between the first gate electrode 105 and the drain electrode 109, and the source / drain electrodes 108 and 109 By forming the region P1 in a plurality of island patterns that are separated from each other, not only the generated heat is reduced but also the heat is easily dispersed to reduce stress and stabilize the device.
따라서, 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터(100)는 소스 전극(108) 및 드레인 전극(109)를 통과하는 통과하는 전류의 양을 증가시킬 수 있게 될 뿐 만 아니라 양의 전압, 음의 전압 및 온도에 대한 신뢰성 테스트에서 안정화 특성을 나타낼 수 있다.Accordingly, the oxide semiconductor thin film transistor 100 according to an embodiment of the present invention not only can increase the amount of current passing through the source electrode 108 and the drain electrode 109, It can exhibit stabilization characteristics in reliability test for negative voltage and temperature.
소스/드레인 전극(108, 109)은 금속 물질로 형성될 수 있으며, 예를 들어, 몰리브덴(Mo), 알루미늄(Al), 크롬(Cr), 금(Au), 티타늄(Ti), 니켈(Ni), 네오디뮴(Nd) 및 구리(Cu) 중 어느 하나 또는 이들의 조합으로 이루어질 수 있으나, 이에 제한되지 않고, 다양한 물질로 이루어질 수 있다. 또한, 소스/드레인 전극(108, 109)은 상술한 물질을 포함하는 단일층 또는 복층 구조로 형성될 수 있다.The source / drain electrodes 108 and 109 may be formed of a metal material such as molybdenum (Mo), aluminum (Al), chrome (Cr), gold (Au), titanium (Ti) ), Neodymium (Nd), and copper (Cu), or combinations thereof, but may be made of various materials. Further, the source / drain electrodes 108 and 109 may be formed as a single layer or a multi-layer structure including the above-described materials.
소스/드레인 전극(108, 109)은 진공 증착법 (vacuum deposition), 화학 기상 증착법(chemical vapor deposition), 물리 기상 증착법(physical vapor deposition), 원자층 증착법(atomic layer deposition), 유기금속 화학 증착법(Metal Organic Chemical Vapor Deposition), 플라즈마 화학 증착법(Plasma-Enhanced Chemical Vapor Deposition), 분자선 성장법(Molecular Beam Epitaxy), 수소화물 기상 성장법(Hydride Vapor Phase Epitaxy), 스퍼터링(Sputtering), 스핀 코팅(spin coating), 딥 코팅(dip coating) 및 존 캐스팅(zone casting) 중 적어도 하나의 방법을 이용하여 형성될 수 있다.The source / drain electrodes 108 and 109 may be formed by a known method such as a vacuum deposition method, a chemical vapor deposition method, a physical vapor deposition method, an atomic layer deposition method, Organic chemical vapor deposition, plasma-enhanced chemical vapor deposition, molecular beam epitaxy, hydride vapor phase epitaxy, sputtering, spin coating, , Dip coating, and zone casting, as described above.
도 1f를 참조하면, 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터(100)의 제조방법은, 소스/드레인 전극(108, 109) 상에 패시베이션층(Passivation Layer)(110)을 형성한다.Referring to FIG. 1F, a method of manufacturing an oxide semiconductor thin film transistor 100 according to an embodiment of the present invention includes forming a passivation layer 110 on source / drain electrodes 108 and 109.
도 1f에 도시된 바와 같이, 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터(100)는 패시베이션층(Passivation Layer)(110)을 포함할 수 있다.As shown in FIG. 1F, the oxide semiconductor thin film transistor 100 according to an embodiment of the present invention may include a passivation layer 110.
패시베이션층(110)은 소스/드레인 전극(108, 109) 상에 형성된다. 구체적으로, 패시베이션층(110)은 게이트 절연층(106), 산화물 반도체층(107) 및 소스/드레인 전극(108, 109)을 모두 덮도록(커버하도록) 형성된다.A passivation layer 110 is formed on the source / drain electrodes 108 and 109. Specifically, the passivation layer 110 is formed to cover (cover) both the gate insulating layer 106, the oxide semiconductor layer 107, and the source / drain electrodes 108 and 109.
패시베이션층(110)은 보호층으로서, 게이트 절연층(106)과 동일한 물질로 형성될 수 있다. 패시베이션층(110)은 예를 들어, 실리콘옥사이드, 실리콘나이트라이드 등의 물질 중 어느 하나로 구성된 단일층 또는 이들의 복층 구조로 형성될 수 있으나, 이에 제한되지 않고, 다양한 물질로 형성될 수 있다.The passivation layer 110 may be formed of the same material as the gate insulating layer 106 as a protective layer. The passivation layer 110 may be formed of a single layer composed of any one of materials such as silicon oxide and silicon nitride, or a multi-layer structure thereof, but is not limited thereto and may be formed of various materials.
패시베이션층(110)은 진공 증착법 (vacuum deposition), 화학 기상 증착법(chemical vapor deposition), 물리 기상 증착법(physical vapor deposition), 원자층 증착법(atomic layer deposition), 유기금속 화학 증착법(Metal Organic Chemical Vapor Deposition), 플라즈마 화학 증착법(Plasma-Enhanced Chemical Vapor Deposition), 분자선 성장법(Molecular Beam Epitaxy), 수소화물 기상 성장법(Hydride Vapor Phase Epitaxy), 스퍼터링(Sputtering), 스핀 코팅(spin coating), 딥 코팅(dip coating) 및 존 캐스팅(zone casting) 중 적어도 하나의 방법을 이용하여 형성될 수 있다.The passivation layer 110 may be formed by any suitable process such as vacuum deposition, chemical vapor deposition, physical vapor deposition, atomic layer deposition, Metal Organic Chemical Vapor Deposition ), Plasma-enhanced chemical vapor deposition (MOCVD), molecular beam epitaxy, hydride vapor phase epitaxy, sputtering, spin coating, dip coating dip coating, and zone casting.
본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터(100)는 화소 전극을 더 포함할 수 있다.The oxide semiconductor thin film transistor 100 according to an embodiment of the present invention may further include a pixel electrode.
화소 전극은 패시베이션층(110) 상에 형성된다. 화소 전극은 소스/드레인 전극(108, 109)과 각각 전기적으로 연결되며, 소스/드레인 전극(108, 109)을 산화물 반도체 박막 트랜지스터(100) 외부의 다른 구성 요소와 전기적으로 연결시키는 역할을 수행한다. 화소 전극(118) 또한 금속 재질, 일례로 몰리브덴(Mo)으로 형성될 수 있다.A pixel electrode is formed on the passivation layer 110. The pixel electrode is electrically connected to the source / drain electrodes 108 and 109 and electrically connects the source / drain electrodes 108 and 109 to other components outside the oxide semiconductor thin film transistor 100 . The pixel electrode 118 may also be formed of a metal material, for example, molybdenum (Mo).
도 1g를 참조하면, 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터의 제조방법은, 캐리어 기판(101)을 제거한다.Referring to FIG. 1G, a method of manufacturing an oxide semiconductor thin film transistor according to an embodiment of the present invention removes a carrier substrate 101.
도 1g에 도시된 바와 같이, 캐리어 기판(101)은 지지층(102)으로부터 제거될 수 있다.As shown in FIG. 1G, the carrier substrate 101 may be removed from the support layer 102.
구체적으로, 산화물 반도체 박막 트랜지스터(100)의 제조가 완료되거나 산화물 반도체 박막 트랜지스터(100) 상에 예를 들어, OLED와 같은 소자가 형성된 후, 별도의 장치를 통하여 지지층(102)으로부터 캐리어 기판(101)을 물리적으로 제거할 수 있다.Specifically, after the oxide semiconductor thin film transistor 100 is completed or an element such as an OLED is formed on the oxide semiconductor thin film transistor 100, the carrier substrate 101 Can be physically removed.
도 1h를 참조하면, 따라서, 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터의 제조방법을 통해 제조된 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터를 도시하였다.Referring to FIG. 1 H, an oxide semiconductor thin film transistor according to an embodiment of the present invention, which is manufactured through a method of manufacturing an oxide semiconductor thin film transistor according to an embodiment of the present invention, is illustrated.
본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터(100)는 기판(103), 제1 게이트 전극(105), 게이트 절연층(106), 산화물 반도체층(107), 소스/드레인 전극(108, 109) 및 패시베이션층(110)을 포함한다. 실시예에 따라, 산화물 반도체 박막 트랜지스터(100)는 지지층(102), 버퍼층(104) 및 화소 전극(111)을 더 포함할 수 있다.An oxide semiconductor thin film transistor 100 according to an embodiment of the present invention includes a substrate 103, a first gate electrode 105, a gate insulating layer 106, an oxide semiconductor layer 107, source / drain electrodes 108, 109 and a passivation layer 110. The oxide semiconductor thin film transistor 100 may further include a support layer 102, a buffer layer 104, and a pixel electrode 111. In this case,
또한, 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터(100)의 소스/드레인 전극(108, 109)은 기판(103)의 수평면을 기준으로 제1 게이트 전극(105) 방향에 형성된 제1 영역(P1) 및 제1 영역(P1)과 반대 방향에 형성된 제2 영역(P2)을 포함하고, 복수 개의 아일랜드 패턴은 제1 영역(P1)이 서로 분리되어 외부 스트레스에 대한 내성을 가진다.The source / drain electrodes 108 and 109 of the oxide semiconductor thin film transistor 100 according to an embodiment of the present invention are formed in a first region formed in the direction of the first gate electrode 105 with respect to the horizontal plane of the substrate 103 (P1) and a second region (P2) formed in a direction opposite to the first region (P1), and the plurality of island patterns have a resistance to external stress by separating the first regions (P1) from each other.
따라서, 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터(100)는 소스/드레인 전극(108, 109)의 면적을 감소시킴으로써, 제1 게이트 전극(105)과 소스/드레인 전극(108, 109) 사이에서 발생하는 기생 캐패시턴스의 발생을 감소시킬 수 있다.The oxide semiconductor thin film transistor 100 according to an embodiment of the present invention reduces the area of the source / drain electrodes 108 and 109 so that the first gate electrode 105 and the source / drain electrodes 108 and 109, It is possible to reduce the occurrence of parasitic capacitance generated between the electrodes.
본 발명의 일 실시예에 따른 고성능 전기적 특성을 가지는 산화물 반도체 박막 트랜지스터는 액정 디스플레이 장치(LCD) 또는 유기 발광 디스플레이 장치(AMOLED) 등의 플렉서블 디스플레이 장치의 화소 소자로 사용될 수 있다.The oxide semiconductor thin film transistor having high performance electrical characteristics according to an embodiment of the present invention can be used as a pixel element of a flexible display device such as a liquid crystal display device (LCD) or an organic light emitting display device (AMOLED).
본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터는 액정 디스플레이 장치(LCD) 또는 유기 발광 디스플레이 장치(AMOLED) 등의 플렉서블 디스플레이 장치의 화소 소자로 사용될 수 있다. 보다 구체적으로, 상술한 방법을 이용하여 산화물 반도체 박막 트랜지스터를 제조한 후, 소스/드레인 전극(108, 109) 중 어느 하나에 전기적으로 연결되는 화소 전극(111)을 형성하는 단계를 거쳐, 디스플레이 장치를 제조할 수 있다.The oxide semiconductor thin film transistor according to an embodiment of the present invention can be used as a pixel element of a flexible display device such as a liquid crystal display device (LCD) or an organic light emitting display device (AMOLED). More specifically, after the oxide semiconductor thin film transistor is manufactured using the above-described method, a pixel electrode 111 electrically connected to one of the source / drain electrodes 108 and 109 is formed, Can be produced.
예를 들어, 도 1a 내지 도 1h에 도시된 바와 같이, 소스/드레인 전극(108, 109) 덮는 패시베이션층(110)을 형성하고, 덮는 패시베이션층(110)의 관통홀을 통해 드레인 전극(109)에 컨택하는 화소 전극(111)을 형성하며, 화소 전극(111) 상에 발광층(미도시)을 포함하는 중간층(미도시)을 형성하고, 그 위에 대향전극(미도시)을 형성함으로써, 유기 발광 디스플레이 장치를 제조할 수 있다.For example, as shown in FIGS. 1A to 1H, a passivation layer 110 is formed to cover the source / drain electrodes 108 and 109, and the drain electrode 109 is formed through the through hole of the covering passivation layer 110. [ An intermediate layer (not shown) including a light emitting layer (not shown) is formed on the pixel electrode 111 and an opposite electrode (not shown) is formed thereon, A display device can be manufactured.
이하, 도 2a 내지 도 2c를 참조하여 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터의 복수 개의 아일랜드 패턴에 대해 보다 상세하게 설명하기로 한다.Hereinafter, a plurality of island patterns of the oxide semiconductor thin film transistor according to one embodiment of the present invention will be described in detail with reference to FIGS. 2A to 2C.
도 2a 내지 도 2c는 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터에 있어서, 다양한 형상으로 형성된 복수 개의 아일랜드 패턴의 평면도를 도시한 것이다.2A to 2C are plan views of a plurality of island patterns formed in various shapes in an oxide semiconductor thin film transistor according to an embodiment of the present invention.
본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터에 있어서, 소스/드레인 전극(108, 109)이 복수 개의 아일랜드 패턴으로 형성될 수 있다.In the oxide semiconductor thin film transistor according to an embodiment of the present invention, the source / drain electrodes 108 and 109 may be formed in a plurality of island patterns.
복수 개의 아일랜드 패턴은 라인 형상, 지그재그 라인 형상 또는 격자 형상 등의 다양한 형상으로 형성될 수 있다.The plurality of island patterns may be formed in various shapes such as a line shape, a zigzag line shape, or a lattice shape.
도 2a 내지 도 2c를 참조하면, 복수 개의 아일랜드 패턴은 도 2a에 도시된 바와 같이, 복수 개의 라인 패턴이 반복되어 형성된 복수 개의 라인 형상으로 형성될 수 있고, 도 2b에 도시된 바와 같이, 복수 개의 라인 패턴이 지그재그 방향으로 연장된 복수 개의 지그재그 라인 형상으로 형성될 수도 있으며, 도 2c에 도시된 바와 같이, 복수 개의 라인 패턴이 수직으로 교차하는 격자 형상으로 형성될 수도 있다.2A to 2C, a plurality of island patterns may be formed in a plurality of line patterns in which a plurality of line patterns are repeatedly formed, as shown in FIG. 2A, The line pattern may be formed in a plurality of zigzag line shapes extending in the zigzag direction, or may be formed in a lattice shape in which a plurality of line patterns are vertically crossed, as shown in Fig. 2C.
복수 개의 아일랜드 패턴을 구성하는 복수 개의 라인 패턴의 폭(Lw)은 각각 1 ㎛ 내지 10 ㎛일 수 있고, 바람직하게는 1 ㎛ 내지 5 ㎛일 수 있으며, 더욱 바람직하게는 4 ㎛ 내지 5 ㎛일 수 있다.The width Lw of the plurality of line patterns constituting the plurality of island patterns may be 1 占 퐉 to 10 占 퐉, preferably 1 占 퐉 to 5 占 퐉, and more preferably 4 占 퐉 to 5 占 퐉 have.
복수 개의 라인 패턴의 폭(Lw) 이 4 ㎛ 미만이면 전류 값이 줄어드는 문제가 있고, 5 ㎛를 초과하면 폭이 너무 넓어 기생 캐패시턴스를 효과적으로 감소시키지 못하는 문제가 있다.If the width Lw of the plurality of line patterns is less than 4 占 퐉, there is a problem that the current value is reduced. If the width Lw is more than 5 占 퐉, the width is too wide and parasitic capacitance can not be effectively reduced.
또한, 복수 개의 라인 패턴 사이의 간격(Lg), 즉 하나의 라인 패턴과 인접한 라인 패턴 사이의 간격(Lg)은 1 ㎛ 내지 16 ㎛일 수 있고, 바람직하게는 1 ㎛ 내지 5 ㎛일 수 있다. 이때, 복수 개의 라인 패턴 사이의 간격(Lg)은 모두 동일하거나, 서로 상이할 수 있다.The interval Lg between the plurality of line patterns, that is, the interval Lg between one line pattern and the adjacent line pattern may be 1 to 16 mu m, and preferably 1 to 5 mu m. At this time, the intervals Lg between the plurality of line patterns may be the same or different from each other.
복수 개의 라인 패턴 사이의 간격(Lg)이 1 ㎛ 미만이면 간격이 너무 좁아져 기생 캐패시턴스를 효과적으로 감소시키지 못하는 문제가 있고, 5 ㎛를 초과하면 전류 값이 줄어드는 문제가 있다.If the interval Lg between the plurality of line patterns is less than 1 탆, the interval becomes too narrow to effectively reduce the parasitic capacitance. If the interval Lg exceeds 5 탆, the current value is reduced.
도 3a는 종래의 산화물 반도체 박막 트랜지스터의 평면도를 도시한 것이고, 도 3b는 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터의 평면도를 도시한 것이다.FIG. 3A is a plan view of a conventional oxide semiconductor thin film transistor, and FIG. 3B is a plan view of an oxide semiconductor thin film transistor according to an embodiment of the present invention.
도 3a를 참조하면, 종래의 산화물 반도체 박막 트랜지스터는 게이트 전극(50) 및 산화물 반도체층(70) 상에 서로 이격되는 소스/드레인 전극(80, 90)이 형성되어 있다. 그러나, 종래의 산화물 반도체 박막 트랜지스터는 소스/드레인 전극(80, 90)이 복수 개의 아일랜드 패턴으로 형성되지 않는다.Referring to FIG. 3A, a conventional oxide semiconductor thin film transistor has source / drain electrodes 80 and 90 formed on a gate electrode 50 and an oxide semiconductor layer 70, which are spaced apart from each other. However, in the conventional oxide semiconductor thin film transistor, the source / drain electrodes 80 and 90 are not formed in a plurality of island patterns.
그러나, 도 3b를 참조하면, 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터는 제1 게이트 전극(105) 및 산화물 반도체층(107) 상에 서로 이격되는 소스/드레인 전극(108, 109) 및 제2 게이트 전극(112)이 형성되어 있고, 소스/드레인 전극(108, 109)이 복수 개의 아일랜드 패턴으로 형성되어 있다. 더욱이, 소스/드레인 전극(108, 109)의 복수 개의 아일랜드 패턴은 제1 영역(P1)이 서로 분리되어 있는 복수 개의 아일랜드 패턴으로 형성되어 있다.3B, the oxide semiconductor thin film transistor according to an embodiment of the present invention includes source / drain electrodes 108 and 109 separated from each other on a first gate electrode 105 and an oxide semiconductor layer 107, A second gate electrode 112 is formed, and the source / drain electrodes 108 and 109 are formed in a plurality of island patterns. Furthermore, a plurality of island patterns of the source / drain electrodes 108 and 109 are formed by a plurality of island patterns in which the first regions P1 are separated from each other.
따라서, 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터는 종래의 산화물 반도체 박막 트랜지스터 대비 소스/드레인 전극(108, 109)의 면적을 감소시킴으로써, 제1 게이트 전극(105)과 소스/드레인 전극(108, 109) 사이에서 발생하는 기생 캐패시턴스를 감소시킬 수 있고, 외부 스트레스에 대한 내성을 향상시킬 수 있다.Accordingly, the oxide semiconductor thin film transistor according to an embodiment of the present invention reduces the area of the source / drain electrodes 108 and 109 compared to the conventional oxide semiconductor thin film transistor, thereby reducing the area of the first gate electrode 105 and the source / 108, and 109 can be reduced, and resistance to external stress can be improved.
이하, 도 4a 내지 도 16f를 참조하여 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터의 전기적 및 광학적 특성에 대해 설명하기로 한다.Hereinafter, electrical and optical characteristics of the oxide semiconductor thin film transistor according to one embodiment of the present invention will be described with reference to FIGS. 4A to 16F.
도 4a 내지 도 4h는 복수 개의 라인 패턴의 폭에 따른 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터의 특성을 도시한 것이다.4A to 4H illustrate characteristics of an oxide semiconductor thin film transistor according to an exemplary embodiment of the present invention in accordance with a width of a plurality of line patterns.
도 4a 내지 도 4h는 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터에 있어서, 패턴의 폭이 상이한 복수 개의 아일랜드 패턴으로 형성되고, 제1 영역이 분리된 소스/드레인 전극의 광학현미경 이미지(Optical Microscope)를 도시한 것이다.4A to 4H illustrate an oxide semiconductor thin film transistor according to an embodiment of the present invention. The oxide semiconductor thin film transistor includes a plurality of island patterns having different widths of patterns. Microscope.
도 4a는 소스 전극(S) 및 드레인 전극(D)의 제1 영역이 분리되지 않은 구조를 가지는 일반적인 산화물 반도체 박막 트랜지스터의 광학현미경 이미지이다.4A is an optical microscope image of a general oxide semiconductor thin film transistor having a structure in which a first region of a source electrode S and a drain electrode D are not separated.
도 4a를 참조하면, 일반적인 산화물 반도체 박막 트랜지스터의 소스 전극(S) 및 드레인 전극(D)은 제1 영역이 분리되지 않은 구조 모습을 나타내는 것을 확인할 수 있다.Referring to FIG. 4A, it can be seen that the source electrode S and the drain electrode D of the general oxide semiconductor thin film transistor exhibit a structure in which the first region is not separated.
도 4b 내지 4h는 소스 전극(S) 및 드레인 전극(D)이 격자 형상을 갖는 복수 개의 아일랜드 패턴으로 형성되고, 제1 영역이 분리된 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터의 광학현미경 이미지이다.4B to 4H are diagrams showing a state in which the source electrode S and the drain electrode D are formed in a plurality of island patterns having a lattice shape and the first region is separated by the optical microscope of the oxide semiconductor thin film transistor according to the embodiment of the present invention Image.
도 4b 내지 4h를 참조하면, 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터의 소스 전극(S) 및 드레인 전극(D)이 제1 영역이 분리된 격자 형상을 갖는 복수 개의 아일랜드 패턴으로 형성된 모습을 확인할 수 있다.4B to 4H, the source electrode S and the drain electrode D of the oxide semiconductor thin film transistor according to the exemplary embodiment of the present invention are formed in a plurality of island patterns having the first region divided into a grid shape can confirm.
또한, 도 4b 내지 4h를 참조하면, 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터의 소스 전극(S) 및 드레인 전극(D)의 격자 형상의 복수 개의 라인 패턴의 폭이 다양한 폭으로 잘 형성되는 것을 확인할 수 있다.4B to 4H, the width of a plurality of lattice-shaped line patterns of the source electrode S and the drain electrode D of the oxide semiconductor thin film transistor according to the embodiment of the present invention is well formed .
도 5a는 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터의 복수 개의 라인 패턴 사이의 간격이 1.5㎛일 경우, 복수 개의 라인 패턴의 폭의 변화에 따른 드레인 전류-게이트 전압 특성을 도시한 그래프이고, 도 5b는 복수 개의 라인 패턴 사이의 간격이 1.5㎛일 경우, 복수 개의 라인 패턴의 폭의 변화에 따른 드레인 전류-드레인 전압 특성을 도시한 그래프이다.5A is a graph showing a drain current-gate voltage characteristic according to a width of a plurality of line patterns when the interval between a plurality of line patterns of the oxide semiconductor thin film transistor according to an embodiment of the present invention is 1.5 mu m And FIG. 5B is a graph showing the drain current-drain voltage characteristics according to the width of a plurality of line patterns when the interval between the plurality of line patterns is 1.5 .mu.m.
도 5c는 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터의 복수 개의 라인 패턴 사이의 간격이 3㎛일 경우, 복수 개의 라인 패턴의 폭의 변화에 따른 드레인 전류-게이트 전압 특성을 도시한 그래프이고, 도 5d는 복수 개의 라인 패턴 사이의 간격이 3㎛일 경우, 복수 개의 라인 패턴의 폭의 변화에 따른 드레인 전류-드레인 전압 특성을 도시한 그래프이다.5C is a graph showing drain current-gate voltage characteristics according to a width of a plurality of line patterns when the interval between a plurality of line patterns of an oxide semiconductor thin film transistor according to an embodiment of the present invention is 3 mu m And FIG. 5D is a graph showing the drain current-drain voltage characteristics according to the width of a plurality of line patterns when the interval between the plurality of line patterns is 3 μm.
도 5e는 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터의 복수 개의 라인 패턴 사이의 간격이 1.5㎛ 또는 3㎛일 때, 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터의 복수 개의 라인 패턴의 폭의 변화에 따른 드레인 전류 특성을 도시한 그래프이다.5E is a cross-sectional view of the oxide semiconductor thin film transistor according to an embodiment of the present invention when the interval between a plurality of line patterns of the oxide semiconductor thin film transistor is 1.5 mu m or 3 mu m, FIG. 5 is a graph showing a drain current characteristic according to a change in width. FIG.
도 5a 내지 도 5e를 참조하면, 복수 개의 라인 패턴 사이의 간격이 1.5㎛ 또는 3㎛일 때 모두, 복수 개의 라인 패턴의 폭이 증가함에 따라 드레인 전류가 증가하는 것을 알 수 있다. 따라서, 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터에 확산 전류(spreading currents)가 존재하는 것을 알 수 있고, 복수 개의 라인 패턴의 폭이 5㎛인 경우, 기준 산화물 반도체 박막 트랜지스터(STD)와 유사한 것을 알 수 있다.5A to 5E, it can be seen that the drain current increases as the width of a plurality of line patterns increases, when the interval between the plurality of line patterns is 1.5 mu m or 3 mu m. Therefore, it can be seen that diffusion currents exist in the oxide semiconductor thin film transistor according to an embodiment of the present invention. When the width of a plurality of line patterns is 5 m, the reference oxide semiconductor thin film transistor STD Similar things can be seen.
도 6a 내지 도 6h는 복수 개의 라인 패턴 사이의 간격에 따른 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터의 특성을 도시한 것이다.6A to 6H illustrate characteristics of an oxide semiconductor thin film transistor according to an embodiment of the present invention in accordance with the interval between a plurality of line patterns.
도 6a 내지 도 6h는 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터에 있어서, 복수 개의 라인 패턴의 사이의 간격이 상이한 복수 개의 아일랜드 패턴으로 형성되고, 제1 영역이 분리된 소스/드레인 전극의 광학현미경 이미지를 도시한 것이다.6A to 6H illustrate an oxide semiconductor thin film transistor according to an exemplary embodiment of the present invention. Referring to FIGS. 6A to 6H, the oxide semiconductor thin film transistor includes a plurality of island patterns having a plurality of line patterns, 1 shows an optical microscope image.
도 6a는 소스 전극(S) 및 드레인 전극(D)의 제1 영역이 분지되지 않은 구조를 가지는 산화물 반도체 박막 트랜지스터의 광학현미경 이미지이다.6A is an optical microscope image of an oxide semiconductor thin film transistor having a structure in which the first regions of the source electrode S and the drain electrode D are not branched.
도 6a를 참조하면, 일반적인 산화물 반도체 박막 트랜지스터의 소스 전극(S) 및 드레인 전극(D)은 제1 영역이 분지되지 않은 모습을 나타내는 것을 확인할 수 있다.Referring to FIG. 6A, it can be seen that the source electrode S and the drain electrode D of the general oxide semiconductor thin film transistor are not branched in the first region.
도 6b 내지 6f는 드레인 전극(D)이 격자 형상을 갖는 복수 개의 아일랜드 패턴으로 형성되고, 제1 영역이 분리된 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터의 광학현미경 이미지이다.6B to 6F are optical microscope images of an oxide semiconductor thin film transistor according to an embodiment of the present invention in which the drain electrode D is formed of a plurality of island patterns having a lattice shape and the first region is separated.
도 6b 내지 6f를 참조하면, 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터의 소스 전극(S) 및 드레인 전극(D)이 제1 영역이 분리된 격자 형상을 갖는 복수 개의 아일랜드 패턴으로 형성된 모습을 확인할 수 있다.6B to 6F, the source electrode S and the drain electrode D of the oxide semiconductor thin film transistor according to the embodiment of the present invention are formed into a plurality of island patterns having the first region separated into a grid shape can confirm.
또한, 도 6b 내지 6f를 참조하면, 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터의 소스 전극(S) 및 드레인 전극(D)의 격자 형상은 복수 개의 라인 패턴이 다양한 간격으로 잘 형성되는 것을 확인할 수 있다. 6B to 6F, the lattice shapes of the source electrode S and the drain electrode D of the oxide semiconductor thin film transistor according to the embodiment of the present invention are such that a plurality of line patterns are well formed at various intervals Can be confirmed.
도 7a는 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터의 복수 개의 라인 패턴의 폭이 5㎛일 경우, 복수 개의 라인 패턴 사이의 간격의 변화에 따른 드레인 전류-게이트 전압 특성을 도시한 그래프이고, 도 7b는 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터의 복수 개의 라인 패턴의 폭이 5㎛일 경우, 복수 개의 라인 패턴 사이의 간격의 변화에 따른 드레인 전류-드레인 전압 특성을 도시한 그래프이다.FIG. 7A is a graph showing drain current-gate voltage characteristics according to a change in the interval between a plurality of line patterns when a width of a plurality of line patterns of an oxide semiconductor thin film transistor according to an embodiment of the present invention is 5 μm And FIG. 7B is a graph showing drain current-drain voltage characteristics according to a change in the interval between a plurality of line patterns when the width of a plurality of line patterns of the oxide semiconductor thin film transistor according to an embodiment of the present invention is 5 μm. to be.
[표 1]은 도 7a 및 도 7b의 특성을 도시한 표이다.Table 1 is a table showing the characteristics of Figs. 7A and 7B.
[표 1][Table 1]
Figure PCTKR2018012903-appb-I000001
Figure PCTKR2018012903-appb-I000001
도 7a, 도 7b 및 표 1을 참조하면, 소스 전극 및 드레인 전극 사이에 확산 전류가 존재하고, 복수 개의 라인 패턴 사이의 간격이 10㎛ 이하일 때 기준 산화물 반도체 박막 트랜지스터(STD)와 유사한 특성을 나타내고, 복수 개의 라인 패턴 사이의 간격이 12㎛일 때 드레인 전류 특성이 기준 산화물 반도체 박막 트랜지스터보다 비교적 감소하는 것을 알 수 있다.Referring to FIGS. 7A, 7B, and 1, when a diffusion current is present between the source electrode and the drain electrode and the interval between the plurality of line patterns is 10 μm or less, the characteristics are similar to those of the reference oxide semiconductor thin film transistor STD , It can be seen that the drain current characteristic is relatively reduced compared to the reference oxide semiconductor thin film transistor when the interval between the plurality of line patterns is 12 mu m.
도 8은 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터의 복수 개의 라인 패턴 사이의 간격의 변화에 따른 캐패시턴스-게이트 전압 특성을 도시한 그래프이다.FIG. 8 is a graph showing a capacitance-gate voltage characteristic according to a change in spacing between a plurality of line patterns of an oxide semiconductor thin film transistor according to an embodiment of the present invention.
도 8을 참조하면, 음의 게이트 전압(VGS)에서 측정된 캐패시턴스(capacitance)는 게이트 전극과 소스/드레인 전극 사이의 공핍 및 오버랩 캐새시턴스의 합이고, 복수 개의 라인 패턴 사이의 간격이 증가할수록 기생 캐패시턴스를 감소시키기 때문에 캐패시턴스는 감소되는 것을 알 수 있다.Referring to FIG. 8, the capacitance measured at the negative gate voltage VGS is the sum of the depletion and the overlap capacitance between the gate electrode and the source / drain electrode, and as the spacing between the plurality of line patterns increases It can be seen that the capacitance is reduced because the parasitic capacitance is reduced.
이러한 특성은, 양의 게이트 전압(VGS)에서도 유사하게 나타났다.This property was similar in the positive gate voltage (VGS).
따라서, 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터는 제1 영역이 분리된 복수개의 아일랜드 패턴을 포함함으로써 기생 캐패시턴스를 월등히 감소시킬 수 있다.Therefore, the oxide semiconductor thin film transistor according to an embodiment of the present invention includes a plurality of isolated island patterns in the first region, thereby greatly reducing the parasitic capacitance.
도 9a는 복수 개의 라인 패턴 사이의 간격의 변화에 따른 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터의 인버터 특성을 도시한 그래프이고, 도 9b는 복수 개의 라인 패턴 사이의 간격의 변화에 따른 주파수를 도시한 그래프이며, 도 9c는 복수 개의 라인 패턴 사이의 간격의 변화에 따른 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터의 드레인 전류 및 캐패시턴스를 도시한 것이고, 도 9d 및 도 9e는 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터의 확산 전류를 도시한 개략도이다.FIG. 9A is a graph showing inverter characteristics of an oxide semiconductor thin film transistor according to an embodiment of the present invention in accordance with a change in the interval between a plurality of line patterns, FIG. 9B is a graph showing frequency characteristics FIG. 9C is a graph showing the drain current and capacitance of an oxide semiconductor thin film transistor according to an embodiment of the present invention in accordance with a change in the interval between a plurality of line patterns, and FIGS. 9D and 9E are cross- FIG. 2 is a schematic view showing a diffusion current of an oxide semiconductor thin film transistor according to one embodiment of the present invention.
도 9d 및 도 9e에서 복수 개의 라인 패턴 사이의 간격은 5㎛이고, 복수 개의 라인 패턴의 폭은 5㎛이다.9D and 9E, the interval between the plurality of line patterns is 5 mu m, and the width of the plurality of line patterns is 5 mu m.
도 9a는 인버터(inverter) 구동 특성을 도시한 것으로, 복수개의 라인 패턴 사이의 폭이 0㎛ 내지 10㎛까지 모두 안정적인 구동 특성을 나타내는 것으로 보아 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터는 회로에 적용하기에 적합한 것을 알 수 있다.9A shows drive characteristics of an inverter. As a result, the oxide semiconductor thin film transistor according to the embodiment of the present invention exhibits stable driving characteristics in a range of a width between a plurality of line patterns ranging from 0 탆 to 10 탆. It can be seen that it is suitable for application to
도 9b는 인버터(inverter)를 여러 개로 역은 링오실레이터(회로)의 특성을 도시한 것으로, 링오실레이터의 경우 기생 캐패시턴스의 영향에 의해 프리컨시(frequency) 영향을 많이 받는 특성을 확인 할 수 있고, 복수개의 라인 패턴이 0㎛ 내지 10㎛ 모두 동일한 전류 값을 가지고, 기생 캐패시턴스가 감소되어 높은 프리컨시 값을 가지는 것을 알 수 있다.FIG. 9B shows characteristics of a ring oscillator (circuit) inverting a plurality of inverters. In the case of a ring oscillator, characteristics that are highly frequency-influenced can be confirmed by the influence of parasitic capacitance , It can be seen that a plurality of line patterns have the same current value in both 0 占 퐉 to 10 占 퐉 and the parasitic capacitance is reduced to have a high precision value.
도 9a 내지 도 9c 및 표 1을 참조하면, 복수 개의 라인 패턴 사이의 간격이 10㎛ 까지는 산화물 박막 트랜지스터의 드레인 전류 특성이 기준 산화물 반도체 박막 트랜지스터(STD)와 유사하나, 복수 개의 라인 패턴 사이의 간격이 12㎛일 때 드레인 전류 특성이 기준 산화물 반도체 박막 트랜지스터보다 비교적 감소하는 것을 알 수 있다.9A to 9C and Table 1, the drain current characteristics of the oxide thin film transistor are similar to those of the reference oxide semiconductor thin film transistor STD up to a distance of 10 mu m between the plurality of line patterns, It can be seen that the drain current characteristics are relatively reduced compared to the reference oxide semiconductor thin film transistor.
또한, 복수 개의 라인 패턴 사이의 간격이 10㎛일 때의 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터의 캐패시턴스는 0.18pF이고, 기준 산화물 반도체 박막 트랜지스터(STD)는 0.45pF로, 기준 산화물 반도체 박막 트랜지스터(STD)보다 60% 정도 감소되는 것을 알 수 있다.The capacitance of the oxide semiconductor thin film transistor according to an embodiment of the present invention is 0.18 pF, the reference oxide semiconductor thin film transistor STD is 0.45 pF, and the reference oxide semiconductor Is about 60% lower than that of the thin film transistor STD.
도 9d 및 도 9e를 참조하면, 실제 전류의 흐름을 화살표로 나타내었고, 실제 전류의 흐름(current Flow)이 복수 개의 라인 패턴의 폭이 훨씬 넓은 것을 알 수 있다.9D and 9E, the actual current flow is indicated by an arrow, and it can be seen that the current flow has a much wider width of a plurality of line patterns.
따라서, 도 9a 내지 도 9d를 참조하면, 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터는 기준 산화물 반도체 박막 트랜지스터(STD) 소스/드레인 전극의 패턴의 폭이 3배 이상 차이가 남에도 불구하고, 기준 산화물 반도체 박막 트랜지스터(STD)와 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터가 거의 유사한 드레인 전류 특성(드레인 전류가 감소되지 않음)을 나타내고, 기준 산화물 반도체 박막 트랜지스터(STD) 보다 기생 캐패시턴스를 감소시키는 것을 알 수 있다.9A to 9D, the oxide semiconductor thin film transistor according to an embodiment of the present invention differs from the reference oxide semiconductor thin film transistor (STD) source / , The reference oxide semiconductor thin film transistor (STD) and the oxide semiconductor thin film transistor according to an embodiment of the present invention exhibit substantially similar drain current characteristics (the drain current is not reduced), and the parasitic capacitance As shown in FIG.
도 10a는 복수 개의 아일랜드 패턴이 아닌 일반적인 구조의 산화물 반도체 박막 트랜지스터의 PBTS(positive bias temperature stress)를 도시한 그래프이고, 도 10b는 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터의 PBTS(positive bias temperature stress)를 도시한 그래프이다.10A is a graph showing a positive bias temperature stress (PBTS) of an oxide semiconductor thin film transistor having a general structure other than a plurality of island patterns, FIG. 10B is a graph showing a positive bias temperature (PBTS) of an oxide semiconductor thin film transistor according to an embodiment of the present invention, temperature stress.
도 10c는 복수 개의 아일랜드 패턴이 아닌 일반적인 구조의 산화물 반도체 박막 트랜지스터의 HCTS(high current temperature stress)를 도시한 그래프이고, 도 10d는 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터의 HCTS(high current temperature stress)를 도시한 그래프이다.FIG. 10C is a graph showing the HCTS (high current temperature stress) of an oxide semiconductor thin film transistor having a general structure other than a plurality of island patterns, FIG. temperature stress.
도 10b 및 도 10d는 복수 개의 라인 패턴 사이의 간격이 10㎛이고, 복수 개의 라인 패턴의 폭이 5㎛일 때의 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터이다.10B and 10D are oxide semiconductor thin film transistors according to an embodiment of the present invention in which the interval between a plurality of line patterns is 10 mu m and the width of a plurality of line patterns is 5 mu m.
도 10a 내지 도 10d를 참조하면, 복수 개의 아일랜드 패턴이 아닌 일반적인 구조의 산화물 반도체 박막 트랜지스터 및 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터는 모두 PBTS 스트레스 시간이 증가할 때마다 문턱 전압이 증가하고, PBTS는 산화물 반도체층/게이트 절연막의 계면에서 전자 트랩핑(trapping)에 기인된다.10A to 10D, an oxide semiconductor thin film transistor having a general structure other than a plurality of island patterns and an oxide semiconductor thin film transistor according to an embodiment of the present invention all increase in threshold voltage each time the PBST stress time increases , And PBTS is caused by electronic trapping at the interface of the oxide semiconductor layer / gate insulating film.
본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터는 복수 개의 아일랜드 패턴이 아닌 일반적인 구조의 산화물 반도체 박막 트랜지스터보다 소스/드레인 전극의 면적이 훨씬 작기 때문에 전이 곡선(transfer curve)의 변화가 없고, 복수 개의 아일랜드 패턴이 아닌 일반적인 구조의 산화물 반도체 박막 트랜지스터는 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터보다 더 많은 열이 남아 있는 것을 알 수 있다.The oxide semiconductor thin film transistor according to an embodiment of the present invention has a smaller area of the source / drain electrode than a general structure of the oxide semiconductor thin film transistor not of a plurality of island patterns, so that there is no change in the transfer curve, It can be seen that the oxide semiconductor thin film transistor having a general structure other than the island pattern has more heat than that of the oxide semiconductor thin film transistor according to an embodiment of the present invention.
따라서, 소스/드레인 전극의 면적을 줄임으로써, 열 방출 성능이 뛰어난 것을 알 수 있다.Therefore, it can be seen that the heat dissipation performance is excellent by reducing the area of the source / drain electrodes.
도 11a 내지 도 11c는 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터가 적용된 플렉서블 디스플레이 장치의 벤딩 테스트(Bending Test) 장비 및 신뢰성 테스트 장비를 도시한 것이다.11A to 11C show a bending test equipment and a reliability test equipment of a flexible display device to which an oxide semiconductor thin film transistor is applied according to an embodiment of the present invention.
구체적으로, 도 11a는 벤딩 테스트 장비(신뢰성 테스트 장비)의 단면도를 도시한 것이고, 11b는 벤딩 테스트 장비의 실제 모습을 나타낸 것이며, 도 11c는 벤딩 테스트 장비(신뢰성 테스트 장비)의 평면도를 나타낸 것이다.11A is a sectional view of the bending test equipment (reliability test equipment), FIG. 11B is an actual view of the bending test equipment, and FIG. 11C is a plan view of the bending test equipment (reliability test equipment).
본 발명의 일 실시예에 따라 사용된 벤딩 테스트 장비는 벤딩 각도(θ)를 0° 내지 ±90°로 변화를 줄 수 있으며, 두 개의 클램프(clamps) 사이에 산화물 반도체 박막 트랜지스터 구비한 플렉서블 디스플레이 장치를 위치시켜 벤딩 스트레스에 대한 신뢰성 테스트를 진행할 수 있다.The bending test equipment used in accordance with an embodiment of the present invention has a bending angle &thetas; To ± 90 ° and a flexible display device including an oxide semiconductor thin film transistor may be disposed between two clamps to perform a reliability test for bending stress.
도 11d는 복수 개의 아일랜드 패턴이 아닌 일반적인 구조의 산화물 반도체 박막 트랜지스터를 구비한 플렉서블 디스플레이 장치를 벤딩 테스트한 후에 측정한 드레인 전류-게이트 전압 특성을 나타낸 그래프이고, 도 11e는 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터를 구비한 플렉서블 디스플레이 장치를 벤딩 테스트한 후에 측정한 드레인 전류-게이트 전압 특성을 나타낸 그래프이다.11D is a graph showing drain current-gate voltage characteristics measured after bending test of a flexible display device having oxide semiconductor thin film transistors of a general structure other than a plurality of island patterns, and FIG. 11E is a graph Gate voltage characteristics measured after a bending test of a flexible display device including an oxide semiconductor thin film transistor according to the present invention.
여기서, 벤딩 테스트시, 벤딩 시간(Bending Time)(s)(벤딩 횟수)은 0번, 100번, 500번, 1,000번, 2000번, 3000번 및 5,000번으로 조건을 달리하였고, 벤딩 반경(Bending radius)은 벤딩 각도가 90°가 되도록 0.32 ㎜로 고정하였다.The bending time (s) (number of bending) was changed to 0, 100, 500, 1,000, 2000, 3000 and 5,000, and the bending radius The radius was fixed to 0.32 ㎜ so that the bending angle was 90 °.
도 11d를 참조하면, 복수 개의 아일랜드 패턴이 아닌 일반적인 구조의 산화물 반도체 박막 트랜지스터의 경우, 90°의 벤딩 각도에 대해 밴딩 횟수(벤딩 시간)에 따라 전류-전압의 특성이 변화하는 것을 확인할 수 있었고, 메탈 전극의 크랙 발생으로 인해 컨택 저항이 커져 산화물 반도체 박막 트랜지스터의 특성이 저하되는 것을 확인할 수 있었다.Referring to FIG. 11D, it can be seen that the characteristics of the current-voltage change with the number of bending times (bending time) with respect to the bending angle of 90 ° in the oxide semiconductor thin film transistor having a general structure other than a plurality of island patterns, It was confirmed that the contact resistance was increased due to cracking of the metal electrode and the characteristics of the oxide semiconductor thin film transistor were deteriorated.
도 11e를 참조하면, 소스/드레인 전극이 복수 개의 아일랜드 패턴을 가짐으로써 강한 응력(strain)에 따른 스트레스(stress)에도 크랙 발생이 최소화되어, 우수한 전류-전압 특성을 나타내는 것을 확인할 수 있었다.Referring to FIG. 11E, cracks are minimized even when the source / drain electrode has a plurality of island patterns, so that it is confirmed that the source-drain electrode exhibits excellent current-voltage characteristics even under stress due to a strong stress.
도 11f는 벤딩 테스트가 진행된 복수 개의 아일랜드 패턴이 아닌 일반적인 구조의 산화물 반도체 박막 트랜지스터를 도시한 광학현미경 이미지이고, 도 11g는 벤딩 테스트가 진행된 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터를 도시한 광학현미경 이미지이다.11F is an optical microscope image showing an oxide semiconductor thin film transistor having a general structure other than a plurality of island patterns on which a bending test is performed, and FIG. 11G shows an oxide semiconductor thin film transistor according to an embodiment of the present invention in which a bending test is performed It is an optical microscope image.
도 11f 및 도 11g를 참조하면, 복수 개의 아일랜드 패턴이 아닌 일반적인 구조의 산화물 반도체 박막 트랜지스터은 벤딩 테스트를 진행한 후, 소스/드레인 전극에 크랙이 발생하였으나, 제1 영역이 분리된 복수 개의 아일랜드 패턴을 포함하는 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터는 제1 영역이 분리된 복수 개의 아일랜드 패턴으로 형성된 소소/드레인 전극에 의해 벤딩 테스트가 진행된 후에도 소소/드레인 전극에서 크랙이 방생하지 않는 것을 알 수 있다.Referring to FIGS. 11F and 11G, after the bending test is performed on the oxide semiconductor thin film transistor having a general structure other than a plurality of island patterns, cracks are generated in the source / drain electrodes, but a plurality of island patterns The oxide semiconductor thin film transistor according to an embodiment of the present invention is characterized in that cracks are not generated in the source / drain electrodes even after the bending test is performed by the source / drain electrodes formed by a plurality of isolated island patterns in the first region .
도 12a 내지 도 12d는 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터에 있어서, 복수 개의 아일랜드 패턴으로 형성되고, 제1 영역이 분리된 소스/드레인 전극 및 산화물 반도체층의 광학현미경 이미지(Optical Microscope) 이다.12A to 12D illustrate an oxide semiconductor thin film transistor according to an embodiment of the present invention, in which a first region is formed by a plurality of island patterns and an optical microscope image of an oxide semiconductor layer and source / ) to be.
도 12a 내지 도 12d를 참조하면, 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터의 소스 전극(S) 및 드레인 전극(D)이 제1 영역이 분리된 격자 형상을 갖는 복수 개의 아일랜드 패턴으로 형성된 모습을 확인할 수 있다.12A to 12D, a source electrode S and a drain electrode D of an oxide semiconductor thin film transistor according to an embodiment of the present invention are formed in a plurality of island patterns having a first lattice shape You can see the figure.
또한, 도 12a 내지 도 12d를 참조하면, 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터는 다양한 폭을 갖는(채널 길이를 갖는) 산화물 반도체층이 잘 형성되는 것을 확인할 수 있다.12A to 12D, it can be seen that the oxide semiconductor thin film transistor according to an embodiment of the present invention well forms an oxide semiconductor layer having various widths (having a channel length).
도 13a 내지 도 13h는 채널 길이에 따른 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터의 전송(transfer) 및 출력(output) 특성을 도시한 그래프이다.FIGS. 13A to 13H are graphs showing transfer and output characteristics of an oxide semiconductor thin film transistor according to an embodiment of the present invention, according to a channel length. FIG.
도 13a 및 도 13b는 채널 길이가 10㎛인 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터의 전송(transfer) 및 출력(output) 특성을 도시한 그래프이고, 도 13c 및 도 13d는 채널 길이가 20㎛인 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터의 전송(transfer) 및 출력(output) 특성을 도시한 그래프이다.13A and 13B are graphs showing transfer and output characteristics of an oxide semiconductor thin film transistor according to an embodiment of the present invention with a channel length of 10 mu m, And FIG. 5 is a graph showing transfer and output characteristics of an oxide semiconductor thin film transistor according to an embodiment of the present invention.
도 13e 및 도 13f는 채널 길이가 30㎛인 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터의 전송(transfer) 및 출력(output) 특성을 도시한 그래프이고, 도 13g 및 도 13h는 채널 길이가 50㎛인 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터의 전송(transfer) 및 출력(output) 특성을 도시한 그래프이다.13E and 13F are graphs showing transfer and output characteristics of an oxide semiconductor thin film transistor according to an embodiment of the present invention with a channel length of 30 mu m, And FIG. 5 is a graph illustrating transfer and output characteristics of an oxide semiconductor thin film transistor according to an embodiment of the present invention.
도 13a 내지 도 13h는 복수 개의 라인 패턴의 폭은 5㎛이고, 복수 개의 라인 패턴 사이의 간격이 10㎛이다.13A to 13H, the width of a plurality of line patterns is 5 mu m, and the interval between a plurality of line patterns is 10 mu m.
도 13a 내지 도 13h는 채널 길이(channel length)에 따른 특성을 도시한 것으로, 최대 채널 길이 50㎛까지 안정적인 산화물 반도체 박막 트랜지스터 특성을 나타내는 것을 알 수 있다.FIGS. 13A to 13H show the characteristics according to the channel length, showing stable characteristics of the oxide semiconductor thin film transistor up to a maximum channel length of 50 μm.
따라서, 도 13a 내지 도 13h를 참조하면, 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터는 드레인 전류는 감소시키지 않고, 기생 캐패시턴스는 감소시키는 것을 알 수 있다.13A to 13H, it can be seen that the oxide semiconductor thin film transistor according to the embodiment of the present invention does not decrease the drain current but decreases the parasitic capacitance.
도 14a는 링 오실레이터(ring oscillator)에 사용되는 복수 개의 아일랜드 패턴이 아닌 일반적인 구조의 산화물 반도체 박막 트랜지스터를 도시한 광학 현미경 이미지이고, 도 14b는 링 오실레이터(ring oscillator)에 사용되는 본 발명의 본 발명의 일 실시예에 따른 산화물 반도체 트랜지스터를 도시한 광학 현미경 이미지이다.FIG. 14A is an optical microscope image showing an oxide semiconductor thin film transistor having a general structure not a plurality of island patterns used in a ring oscillator, and FIG. 14B is a cross- Is an optical microscope image showing an oxide semiconductor transistor according to one embodiment of the present invention.
도 14b를 참조하면, 본 발명의 본 발명의 일 실시예에 따른 산화물 반도체 트랜지스터는 소스/드레인 전극이 복수 개의 아일랜드 패턴으로 형성되고, 복수 개의 아일랜드 패턴의 제1 영역이 분리되어 있는 것을 알 수 있다. Referring to FIG. 14B, it can be seen that the source / drain electrodes of the oxide semiconductor transistor according to an embodiment of the present invention are formed in a plurality of island patterns, and the first regions of the plurality of island patterns are separated .
도 15a 및 도 15b는 본 발명의 일 실시예에 따른 산화물 반도체 트랜지스터의 MOA(metal-over-active)의 열분석을 도시한 광학 현미경 이미지이고, 도 15c 및 도 15d는 본 발명의 일 실시예에 따른 산화물 반도체 트랜지스터의 AOM(active-over-metal)의 열분석을 도시한 광학 현미경 이미지이다.15A and 15B are optical microscope images showing thermal analysis of a metal-over-active (MOA) of an oxide semiconductor transistor according to an embodiment of the present invention, and Figs. 15C and 15D are cross- FIG. 2 is a light microscope image showing an active-over-metal (AOM) thermal analysis of an oxide semiconductor transistor according to the present invention.
도 15a는 소스/드레인 전극이 산화물 반도체층보다 면적이 큰 구조에서의 광학 이미지이고, 도 15b는 VGS=10V 및 VDS=20V을 가했을 때의 열화상 이미지이며, 도 15c는 소스/드레인 전극이 산화물 반도체층보다 면적이 작은 구조에서의 광학 이미지이고, 도 15b는 VGS=10V 및 VDS=20V을 가했을 때의 열화상 이미지이다.15A is an optical image in a structure in which a source / drain electrode is larger in area than an oxide semiconductor layer, FIG. 15B is a thermal image when VGS = 10V and VDS = 20V are applied, 15B is an optical image when the area is smaller than that of the semiconductor layer, and Fig. 15B is a thermal image when VGS = 10 V and VDS = 20 V are applied.
도 15a 내지 도 15d는 5㎛의 채널길이와 20㎛의 산화물 반도체층의 총 너비를 갖는다.15A to 15D have a channel length of 5 mu m and a total width of the oxide semiconductor layer of 20 mu m.
도 15a 내지 도 15d를 참조하면, 산화물 반도체 트랜지스터가 켜지는 경우, 소스 전극 및 드레인 전극 사이의 산화물 반도체층의 채널 너비 방향으로 열이 분산되어 전류가 확산되는 것을 알 수 있다. 15A to 15D, when the oxide semiconductor transistor is turned on, heat is dispersed in the channel width direction of the oxide semiconductor layer between the source electrode and the drain electrode, and the current is diffused.
도 16a 내지 도 16f는 복수 개의 아일랜드 패턴 사이의 간격에 따른 본 발명의 일 실시예에 따른 산화물 반도체 트랜지스터를 포함하는 링 오실레이터의 전압-시간 특성을 도시한 것이다.16A to 16F illustrate voltage-time characteristics of a ring oscillator including an oxide semiconductor transistor according to an embodiment of the present invention, according to the interval between a plurality of island patterns.
도 16a는 복수 개의 아일랜드 패턴 사이의 간격이 0㎛이고, 도 16b는 6㎛이며, 도 16c는 8㎛이고, 도 16d는 10㎛이고, 도 22e는 12㎛이며, 도 16f는 14㎛이다.Fig. 16A shows the interval between a plurality of island patterns is 0 mu m, Fig. 16B is 6 mu m, Fig. 16C is 8 mu m, Fig. 16D is 10 mu m, Fig. 22E is 12 mu m and Fig.
도 16a 내지 도 16f의 총 산화물 반도체층 폭은 240㎛이고, 전원 전압 VDD는 15V이다.The total oxide semiconductor layer width in Figs. 16A to 16F is 240 mu m, and the power supply voltage V DD is 15V.
도 16a 내지 도 16f를 참조하면, 복수 개의 아일랜드 패턴의 폭이 커질수록 기생캐패시턴스가 감소하여 프리컨시(frequency)가 증가되는 것을 알 수 있습니다.16A to 16F, it can be seen that as the width of the plurality of island patterns increases, the parasitic capacitance decreases and the frequency increases.
도 17a 내지 도 17h는 본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터(듀얼 게이트(Dual Gate) 구조)의 제조방법의 전체적인 흐름을 도시한 산화물 반도체 박막 트랜지스터의 단면도를 도시한 것이다.FIGS. 17A to 17H are cross-sectional views illustrating an oxide semiconductor thin film transistor showing an overall flow of a method of manufacturing an oxide semiconductor thin film transistor (dual gate structure) according to another embodiment of the present invention.
본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터는 도 17h에 도시된 바와 같이, 기판(103), 제1 게이트 전극(105), 게이트 절연층(106), 산화물 반도체층(107), 소스/드레인 전극(108, 109), 패시베이션층(110) 및 제2 게이트 전극(112)을 포함하고, 지지층(102), 버퍼층(104) 및 연결전극(미도시)을 더 포함할 수 있다.The oxide semiconductor thin film transistor according to another embodiment of the present invention includes a substrate 103, a first gate electrode 105, a gate insulating layer 106, an oxide semiconductor layer 107, a source / Drain electrodes 108 and 109, a passivation layer 110 and a second gate electrode 112 and may further include a support layer 102, a buffer layer 104 and a connection electrode (not shown).
본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터의 구성요소는 전술한 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터와 동일한 기술적 구성요소를 포함할 수 있고, 중복되는 구성요소에 대해서는 중복 기재를 생략하기로 한다.The elements of the oxide semiconductor thin film transistor according to another embodiment of the present invention may include the same technical elements as those of the oxide semiconductor thin film transistor according to an embodiment of the present invention, It will be omitted.
도 17a를 참조하면, 본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터의 제조방법은, 캐리어 기판(101) 상에 지지층(102)은 및 기판(103)을 형성한다.Referring to FIG. 17A, a method for fabricating an oxide semiconductor thin film transistor according to another embodiment of the present invention includes forming a support layer 102 and a substrate 103 on a carrier substrate 101.
도 17a에 도시된 바와 같이, 지지층(102)은 캐리어 기판(101) 상에 형성된다. 다만, 지지층(102)은 반드시 필요한 구성은 아니다.As shown in Fig. 17A, a support layer 102 is formed on the carrier substrate 101. Fig. However, the supporting layer 102 is not necessarily required.
또한, 기판(103)은 지지층(102) 상에 형성된다. 기판(103)은 산화물 반도체 박막 트랜지스터의 여러 구성 요소들을 지지하기 위한 기판으로서, 가요성(flexibility)을 갖는 기판일 수 있다.Further, a substrate 103 is formed on the support layer 102. [ The substrate 103 is a substrate for supporting various components of the oxide semiconductor thin film transistor, and may be a substrate having flexibility.
도 17b를 참조하면, 본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터의 제조방법은, 기판(103) 상에 버퍼층(buffer layer)(104)을 형성한다.Referring to FIG. 17B, a method of fabricating an oxide semiconductor thin film transistor according to another embodiment of the present invention includes forming a buffer layer 104 on a substrate 103.
도 17b에 도시된 바와 같이, 버퍼층(104)은 기판(103) 상에 형성될 수 있다.As shown in FIG. 17B, the buffer layer 104 may be formed on the substrate 103.
버퍼층(104)은 기판(103)을 통한 수분 또는 산소와 같은 외부 불순물의 침투를 방지하며, 기판(103)의 표면을 평탄화할 수 있다. 다만, 버퍼층(104)은 반드시 필요한 구성은 아니며, 기판(103)의 종류에 따라 채택되거나 생략될 수 있다.The buffer layer 104 prevents penetration of external impurities such as moisture or oxygen through the substrate 103 and can flatten the surface of the substrate 103. [ However, the buffer layer 104 is not necessarily required and may be adopted or omitted depending on the type of the substrate 103. [
도 17c를 참조하면, 본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터의 제조방법은, 버퍼층(104)이 형성된 기판(103) 상에 제1 게이트 전극(105)을 형성한다.Referring to FIG. 17C, a method for fabricating an oxide semiconductor thin film transistor according to another embodiment of the present invention includes forming a first gate electrode 105 on a substrate 103 on which a buffer layer 104 is formed.
도 17c에 도시된 바와 같이, 제1 게이트 전극(105)은 버퍼층(104) 상에 형성된다. 제1 게이트 전극(105)은 하부 게이트 전극(Bottom Gate)일 수 있다.As shown in Fig. 17C, a first gate electrode 105 is formed on the buffer layer 104. Fig. The first gate electrode 105 may be a bottom gate electrode.
도 17d를 참조하면, 본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터의 제조방법은, 제1 게이트 전극(105) 상에 게이트 절연층(106) 및 산화물 반도체막(107a)을 형성한다.Referring to FIG. 17D, a method for fabricating an oxide semiconductor thin film transistor according to another embodiment of the present invention includes forming a gate insulating layer 106 and an oxide semiconductor film 107a on a first gate electrode 105.
도 17d에 도시된 바와 같이, 게이트 절연층(Gate Insulator)(106)은 제1 게이트 전극(105) 상에 형성된다.As shown in FIG. 17D, a gate insulator 106 is formed on the first gate electrode 105.
또한, 산화물 반도체막(107a)은 게이트 절연층(106) 상에 형성된다.Further, an oxide semiconductor film 107a is formed on the gate insulating layer 106. [
구체적으로, 산화물 반도체막(107a)은 산화물 반도체층(107)의 형성을 위한 막으로서, 게이트 절연층(106) 상에서 게이트 절연층(106)의 전면을 덮도록 형성된다. 이후, 산화물 반도체막(107a) 상에 포토레지스트 패턴을 형성하고, 포토레지스트 패턴을 마스크로 하여 산화물 반도체막(107a)을 박막 트랜지스터 영역에서 제1 게이트 전극(105)과 대응되도록 패터닝함으로써 산화물 반도체층(107)(도 14e 참조)이 형성될 수 있다.Specifically, the oxide semiconductor film 107a is formed so as to cover the entire surface of the gate insulating layer 106 on the gate insulating layer 106, as a film for forming the oxide semiconductor layer 107. [ Thereafter, a photoresist pattern is formed on the oxide semiconductor film 107a, and the oxide semiconductor film 107a is patterned to correspond to the first gate electrode 105 in the thin film transistor region using the photoresist pattern as a mask, (See Fig. 14E) can be formed.
도 17e를 참조하면, 본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터의 제조방법은, 제1 게이트 전극(105) 상에 산화물 반도체층(107) 및 소스/드레인 전극(108, 109)을 형성한다.17E, a method of manufacturing an oxide semiconductor thin film transistor according to another embodiment of the present invention includes forming an oxide semiconductor layer 107 and source / drain electrodes 108 and 109 on a first gate electrode 105 do.
도 17e에 도시된 바와 같이, 산화물 반도체층(107)은 게이트 절연층(106) 상에 제1 게이트 전극(105)과 대응되도록 형성된다.As shown in FIG. 17E, the oxide semiconductor layer 107 is formed to correspond to the first gate electrode 105 on the gate insulating layer 106.
또한, 소스/드레인 전극(108, 109)은 산화물 반도체층(107) 상에 서로 이격되어 형성된다.Further, the source / drain electrodes 108 and 109 are formed on the oxide semiconductor layer 107 so as to be spaced apart from each other.
소스/드레인 전극(108, 109)은 제1 영역(P1)이 분리된 복수 개의 아일랜드 패턴으로 형성될 수 있다. 소스/드레인 전극(108, 109)은 제1 영역(P1)이 분리된 복수 개의 아일랜드 패턴으로 형성함으로써, 휨 또는 구부림 등의 외부 스트레스에 대한 내성을 가지게 되어 크랙(Crack)과 같은 외부 스트레스에 의한 손상을 방지할 수 있다.The source / drain electrodes 108 and 109 may be formed of a plurality of island patterns in which the first regions P1 are separated. The source / drain electrodes 108 and 109 are formed by a plurality of island patterns in which the first regions P1 are separated, so that they are resistant to external stresses such as bending or bending, Damage can be prevented.
도 17f를 참조하면, 본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터의 제조방법은, 소스/드레인 전극(108, 109) 상에 패시베이션층(Passivation Layer)(110)을 형성한다.Referring to FIG. 17F, a method for fabricating an oxide semiconductor thin film transistor according to another embodiment of the present invention includes forming a passivation layer 110 on source / drain electrodes 108 and 109.
도 17f에 도시된 바와 같이, 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터(100)는 패시베이션층(Passivation Layer)(110)을 더 포함할 수 있다.As shown in FIG. 17F, the oxide semiconductor thin film transistor 100 according to an embodiment of the present invention may further include a passivation layer 110.
도 17g를 참조하면, 본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터의 제조방법은, 패시베이션층(110) 상에 제2 게이트 전극(112)을 형성한다.Referring to FIG. 17G, a method for fabricating an oxide semiconductor thin film transistor according to another embodiment of the present invention includes forming a second gate electrode 112 on a passivation layer 110.
본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터는 도 17g에 도시된 바와 같이, 제2 게이트 전극(112)을 더 포함하는 것을 특징으로 한다.The oxide semiconductor thin film transistor according to another embodiment of the present invention further includes a second gate electrode 112 as shown in FIG. 17G.
도 17g에 도시된 바와 같이, 제2 게이트 전극(112)은 패시베이션층(110) 상에 형성된다.As shown in Figure 17G, a second gate electrode 112 is formed on the passivation layer 110.
제2 게이트 전극(112)은 상부 게이트 전극(Top Gate)일 수 있고, 제1 게이트 전극(105)과 더불어 듀얼 게이트(Dual Gate) 구조를 이룰 수 있다.The second gate electrode 112 may be a top gate electrode and may have a dual gate structure together with the first gate electrode 105.
제2 게이트 전극(112)은 패시베이션층(110) 상에 게이트 도전막(미도시)을 증착하고, 게이트 도전막 상에 포토레지스트 패턴을 형성한 후, 포토레지스트 패턴을 마스크로 하여 게이트 도전막을 선택적으로 식각, 즉, 패터닝함으로써 형성될 수 있다.The second gate electrode 112 is formed by depositing a gate conductive film (not shown) on the passivation layer 110, forming a photoresist pattern on the gate conductive film, and then using the photoresist pattern as a mask, That is, by patterning.
제2 게이트 전극(112)은 금속 물질로 형성될 수 있으며, 예를 들어, 몰리브덴(Mo), 알루미늄(Al), 크롬(Cr), 금(Au), 티타늄(Ti), 니켈(Ni), 네오디뮴(Nd) 및 구리(Cu) 중 어느 하나 또는 이들의 조합으로 이루어질 수 있으나, 이에 제한되지 않고, 다양한 물질로 이루어질 수 있다. 또한, 제2 게이트 전극(112)은 상술한 물질을 포함하는 단일층 또는 복층 구조로 형성될 수 있다.The second gate electrode 112 may be formed of a metal material such as Mo, Al, Cr, Au, Ti, Ni, Neodymium (Nd), and copper (Cu), or a combination thereof, but is not limited thereto, and may be made of various materials. Further, the second gate electrode 112 may be formed as a single layer or a multi-layer structure including the above-described material.
일 실시예에 따라, 제2 게이트 전극(112)은 산화물 반도체층(107) 상에 형성된 소스/드레인 전극(108, 109)으로부터 수평 방향으로 -1 ㎛ 내지 3 ㎛ 만큼 이격(오프셋 및 오버랩)되도록 형성될 수 있다.The second gate electrode 112 is spaced from the source / drain electrodes 108 and 109 formed on the oxide semiconductor layer 107 in the horizontal direction by 1 占 퐉 to 3 占 퐉 (offset and overlap) .
오프셋 및 오버랩은 제2 게이트 전극(112)의 일단과 소스 전극(108) 사이의 폭 및 제2 게이트 전극(112)의 타단과 드레인 전극(109) 사이의 폭 중 적어도 하나를 의미한다.The offset and the overlap mean at least one of a width between one end of the second gate electrode 112 and the source electrode 108 and a width between the other end of the second gate electrode 112 and the drain electrode 109.
예를 들면, 오버랩(overlap)은 기판에서 수직한 방향으로 제2 게이트 전극(112) 및 소스 전극(108)을 바라보았을 때, 제2 게이트 전극(112)과 소스 전극(108)이 겹쳐지는 부분을 의미한다. 따라서, 오버랩은 0 ㎛ 내지 3 ㎛까지의 너비를 의미한다.For example, when the second gate electrode 112 and the source electrode 108 are viewed in a direction perpendicular to the substrate, the overlap is a portion where the second gate electrode 112 and the source electrode 108 are overlapped with each other . Thus, the overlap means a width from 0 mu m to 3 mu m.
오프셋(offset)은 기판에서 수직한 방향으로 제2 게이트 전극(112) 및 소스 전극(108)을 바라보았을 때, 제2 게이트 전극(112)과 소스 전극(108)이 수평방향으로 이격된 거리를 의미한다. 따라서, 오프셋은 -1 ㎛ 내지 0 ㎛까지의 너비를 의미한다.The offset is the distance between the second gate electrode 112 and the source electrode 108 in the horizontal direction when viewing the second gate electrode 112 and the source electrode 108 in a direction perpendicular to the substrate it means. Therefore, the offset means the width from -1 mu m to 0 mu m.
본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터는 산화물 반도체층(107)을 형성한 다음, 산화물 반도체층(107)의 상단 계면(interface)에서 진행되는 추가 공정이 많기 때문에, 산화물 반도체층(107)의 상단 계면(interface)이 하단 계면(interface)보다 상대적으로 많은 결함(defect)을 포함하고 있다.Since the oxide semiconductor thin film transistor according to another embodiment of the present invention has many additional processes to be performed at the upper interface of the oxide semiconductor layer 107 after the oxide semiconductor layer 107 is formed, Has a relatively higher defect than an interface at the bottom.
그러나, 본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터의 제2 게이트 전극(112)의 오프셋은 산화물 반도체층(107)의 상단 계면(interface)에 형성되어 있는 결함(defect) 영역을 감소시켜, PBS(Positive Bias Stress)에서의 문턱전압 변화를 감소시켜 산화물 반도체 트랜지스터의 전기적 특성을 향상시킬 수 있다.However, the offset of the second gate electrode 112 of the oxide semiconductor thin film transistor according to another embodiment of the present invention reduces the defect region formed at the upper interface of the oxide semiconductor layer 107, The threshold voltage change in the positive bias stress (PBS) can be reduced to improve the electrical characteristics of the oxide semiconductor transistor.
일 실시예에 따라, 산화물 반도체 박막 트랜지스터(100)는 제1 게이트 전극(105)과 제2 게이트 전극(112)을 전기적으로 연결하는 연결 전극(미도시)를 더 포함할 수 있다.According to an embodiment, the oxide semiconductor thin film transistor 100 may further include a connection electrode (not shown) electrically connecting the first gate electrode 105 and the second gate electrode 112.
구체적으로, 상기 연결 전극은 제1 게이트 전극(105) 및 제2 게이트 전극(112)을 전기적으로 연결하기 위한 전극이고, 제1 게이트 전극(105) 및 제2 게이트 전극(112)은 상기 연결 전극을 통하여 동일한 전압을 인가받을 수 있다.Specifically, the connection electrode is an electrode for electrically connecting the first gate electrode 105 and the second gate electrode 112, and the first gate electrode 105 and the second gate electrode 112 are electrically connected to the connection electrode The same voltage can be applied through the resistor Rs.
따라서, 본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터는 제1 게이트 전극(105) 및 제2 게이트 전극(112)에 동일한 전압을 인가하는 경우, 산화물 반도체층(107)에 형성되는 채널의 넓이를 증가시킬 수 있어, 소스 전극(108) 및 드레인 전극(109)을 통과하는 전류의 양을 증가시킬 수 있게 될 뿐 만 아니라 양의 전압, 음의 전압 및 온도에 대한 신뢰성 테스트에서 안정화 특성을 나타낼 수 있다.Therefore, in the oxide semiconductor thin film transistor according to another embodiment of the present invention, when the same voltage is applied to the first gate electrode 105 and the second gate electrode 112, the width of the channel formed in the oxide semiconductor layer 107 Not only can increase the amount of current passing through the source electrode 108 and the drain electrode 109 but also exhibits stabilization characteristics in a reliability test for positive voltage, negative voltage and temperature .
일 실시예에 따라, 산화물 반도체 박막 트랜지스터(100)는 제2 게이트 전극(112) 상에 보호막(passivation layer)을 추가로 형성할 수 있다.According to one embodiment, the oxide semiconductor thin film transistor 100 may further form a passivation layer on the second gate electrode 112.
보호막(passivation layer)은 질화 규소(SiNx) 또는 산화 규소(SiOx)와 같은 무기 절연물, 유기 절연물 및 저유전율 절연물 중 선택되는 적어도 하나 이상의 물질을 포함할 수 있다.The passivation layer may include at least one material selected from inorganic insulators such as silicon nitride (SiNx) or silicon oxide (SiOx), organic insulators and low dielectric constant insulators.
보호막(passivation layer)은 본 발명의 다른 실시예에 따른 산화물 반도체 트랜지스터를 외부로부터 보호할 수 있다.The passivation layer may protect the oxide semiconductor transistor according to another embodiment of the present invention from the outside.
도 17h를 참조하면, 본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터의 제조방법은, 캐리어 기판(101)을 제거한다.Referring to FIG. 17H, a method for fabricating an oxide semiconductor thin film transistor according to another embodiment of the present invention removes a carrier substrate 101.
도 17h에 도시된 바와 같이, 캐리어 기판(101)은 지지층(102)으로부터 제거될 수 있다.As shown in FIG. 17H, the carrier substrate 101 may be removed from the support layer 102.
본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터는 소스/드레인 전극(108, 109)을 제1 영역이 분리된 복수 개의 아일랜드 패턴으로 형성되어 외부 스트레스에 대한 내성을 가질 수 있다.The oxide semiconductor thin film transistor according to another embodiment of the present invention may have resistance to external stress by forming the source / drain electrodes 108 and 109 as a plurality of island patterns separated from the first region.
본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터는 디스플레이 장치, 특히 플렉서블 디스플레이 장치의 화소 소자, 예를 들어 유기 발광 소자를 구동시키기 위해 사용될 수 있다.The oxide semiconductor thin film transistor according to another embodiment of the present invention can be used for driving a pixel element, for example, an organic light emitting element, of a display device, particularly a flexible display device.
도 18a는 종래의 산화물 반도체 박막 트랜지스터의 평면도를 도시한 것이고, 도 18b는 본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터의 평면도를 도시한 것이다.FIG. 18A is a plan view of a conventional oxide semiconductor thin film transistor, and FIG. 18B is a plan view of an oxide semiconductor thin film transistor according to another embodiment of the present invention.
도 18a를 참조하면, 종래의 산화물 반도체 박막 트랜지스터는 게이트 전극(50) 및 산화물 반도체층(70) 상에 서로 이격되는 소스/드레인 전극(80, 90)이 형성되어 있다. 그러나, 종래의 산화물 반도체 박막 트랜지스터는 소스/드레인 전극(80, 90)이 복수 개의 아일랜드 패턴으로 형성되지 않는다.18A, a conventional oxide semiconductor thin film transistor has source / drain electrodes 80 and 90 formed on a gate electrode 50 and an oxide semiconductor layer 70, which are spaced apart from each other. However, in the conventional oxide semiconductor thin film transistor, the source / drain electrodes 80 and 90 are not formed in a plurality of island patterns.
그러나, 도 18b를 참조하면, 본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터 제1 게이트 전극(105) 및 산화물 반도체층(107) 상에 서로 이격되는 소스/드레인 전극(108, 109) 및 제2 게이트 전극(112)이 형성되어 있고, 소스/드레인 전극(108, 109)이 복수 개의 아일랜드 패턴으로 형성되어 있다. 더욱이, 소스/드레인 전극(108, 109)의 복수 개의 아일랜드 패턴은 제1 영역(P1)이 서로 분리되어 있는 복수 개의 아일랜드 패턴으로 형성되어 있다.However, referring to FIG. 18B, source / drain electrodes 108 and 109, which are separated from each other on the first gate electrode 105 and the oxide semiconductor layer 107 of the oxide semiconductor thin film transistor according to another embodiment of the present invention, Two gate electrodes 112 are formed, and the source / drain electrodes 108 and 109 are formed in a plurality of island patterns. Furthermore, a plurality of island patterns of the source / drain electrodes 108 and 109 are formed by a plurality of island patterns in which the first regions P1 are separated from each other.
따라서, 본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터는 종래의 산화물 반도체 박막 트랜지스터 대비 소스/드레인 전극(108, 109)의 면적을 감소시킴으로써, 제1 게이트 전극(105) 또는 제2 게이트 전극(112)과 소스/드레인 전극(108, 109) 사이에서 발생하는 기생캐패시턴스가 발생을 줄일 수 있고, 외부 스트레스에 대한 내성을 향상시킬 수 있다.Accordingly, the oxide semiconductor thin film transistor according to another embodiment of the present invention reduces the area of the source / drain electrodes 108 and 109 compared to the conventional oxide semiconductor thin film transistor, thereby reducing the area of the first gate electrode 105 or the second gate electrode 112 and the source / drain electrodes 108, 109 can be reduced and the immunity against external stress can be improved.
도 19a 내지 도 19c는 본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터(듀얼 게이트 구조)에서의 서로 다른 게이트 구동(gate driving)을 도시한 단면도이다.19A to 19C are cross-sectional views illustrating different gate driving in an oxide semiconductor thin film transistor (dual gate structure) according to another embodiment of the present invention.
도 19a는 제1 게이트 전극에 -15~15V 스윕(sweep; 하부 스윕)하고, 제2 게이트 전극이 접지(ground)될 때의 전자의 분포 및 전류 흐름을 도시한 것이고, 19b는 제2 게이트 전극에 -15~15V 스윕(sweep; 상부 스윕)하고, 제1 게이트 전극이 접지(ground)될 때의 전자의 분포 및 전류 흐름을 도시한 것이며, 도 19c는 제1 게이트 전극 및 제2 게이트 전극을 전기적 또는 물리적으로 연결하여 동시에 -15~15V 스윕(sweep; 듀얼 스윕)하는 것으로 도시한 것이다.19A shows the distribution and current flow of electrons when the first gate electrode is sweeped (-15 to 15V) and the second gate electrode is grounded. FIG. 19C shows the distribution and current flow of electrons when the first gate electrode is grounded with a sweep (upper sweep) of -15 to 15 V, and FIG. 19C shows the first gate electrode and the second gate electrode Electrically or physically connected and sweep (dual sweep) at -15 to 15V at the same time.
도 20a 내지 도 20f는 복수 개의 라인 패턴의 폭에 따른 본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터의 특성을 도시한 것이다.FIGS. 20A to 20F show the characteristics of an oxide semiconductor thin film transistor according to another embodiment of the present invention in accordance with the width of a plurality of line patterns.
도 20a 내지 도 20f는 본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터에 있어서, 패턴의 폭이 상이한 복수 개의 아일랜드 패턴으로 형성되고, 제1 영역이 분리된 소스/드레인 전극의 광학현미경 이미지(Optical Microscope)를 도시한 것이다.FIGS. 20A to 20F are cross-sectional views illustrating an oxide semiconductor thin film transistor according to another embodiment of the present invention. FIGS. 20A to 20F are cross-sectional views illustrating an oxide semiconductor thin film transistor according to another embodiment of the present invention. Microscope.
도 20a는 소스 전극(S) 및 드레인 전극(D)의 제1 영역이 분리되지 않은 구조를 가지는 일반적인 산화물 반도체 박막 트랜지스터의 광학현미경 이미지이다.20A is an optical microscope image of a general oxide semiconductor thin film transistor having a structure in which a first region of a source electrode S and a drain electrode D are not separated.
도 20a를 참조하면, 일반적인 산화물 반도체 박막 트랜지스터의 소스 전극(S) 및 드레인 전극(D)은 제1 영역이 분리되지 않은 구조 모습을 나타내는 것을 확인할 수 있다.Referring to FIG. 20A, it can be seen that the source electrode S and the drain electrode D of the general oxide semiconductor thin film transistor exhibit a structure in which the first region is not separated.
도 20b 내지 20f는 소스 전극(S) 및 드레인 전극(D)이 격자 형상을 갖는 복수 개의 아일랜드 패턴으로 형성되고, 제1 영역이 분리된 본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터의 광학현미경 이미지이다.20B to 20F are cross-sectional views of an oxide semiconductor thin film transistor according to another embodiment of the present invention in which the source electrode S and the drain electrode D are formed in a plurality of island patterns having a lattice shape, Image.
도 20b 내지 20f를 참조하면, 본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터의 소스 전극(S) 및 드레인 전극(D)이 제1 영역이 분리된 격자 형상을 갖는 복수 개의 아일랜드 패턴으로 형성된 모습을 확인할 수 있다.20B to 20F, a source electrode S and a drain electrode D of an oxide semiconductor thin film transistor according to another embodiment of the present invention are formed in a plurality of island patterns having a first lattice-like lattice shape can confirm.
또한, 도 20b 내지 20f를 참조하면, 본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터의 소스 전극(S) 및 드레인 전극(D)의 격자 형상의 복수 개의 아일랜드 패턴의 폭이 다양한 폭으로 잘 형성되는 것을 확인할 수 있다.20B to 20F, the width of a plurality of lattice-shaped island patterns of the source electrode S and the drain electrode D of the oxide semiconductor thin film transistor according to another embodiment of the present invention is well formed .
도 21a 내지 도 21f는 복수 개의 라인 패턴 사이의 간격에 따른 본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터의 특성을 도시한 것이다.FIGS. 21A to 21F show characteristics of an oxide semiconductor thin film transistor according to another embodiment of the present invention in accordance with the interval between a plurality of line patterns.
도 21a 내지 도 21f는 본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터에 있어서, 복수 개의 라인 패턴의 사이의 간격이 상이한 복수 개의 아일랜드 패턴으로 형성되고, 제1 영역이 분리된 소스/드레인 전극의 광학현미경 이미지를 도시한 것이다.FIGS. 21A to 21F are cross-sectional views illustrating an oxide semiconductor thin film transistor according to another embodiment of the present invention. Referring to FIG. 21A to FIG. 21F, the oxide semiconductor thin film transistor includes a plurality of island patterns, 1 shows an optical microscope image.
도 21a는 소스 전극(S) 및 드레인 전극(D)의 제1 영역이 분지되지 않은 구조를 가지는 산화물 반도체 박막 트랜지스터의 광학현미경 이미지이다.21A is an optical microscope image of an oxide semiconductor thin film transistor having a structure in which the first region of the source electrode S and the drain electrode D are not branched.
도 21a를 참조하면, 일반적인 산화물 반도체 박막 트랜지스터의 소스 전극(S) 및 드레인 전극(D)은 제1 영역이 분지되지 않은 모습을 나타내는 것을 확인할 수 있다.Referring to FIG. 21A, it can be seen that the source electrode S and the drain electrode D of the general oxide semiconductor thin film transistor show a state in which the first region is not branched.
도 21b 내지 21f는 드레인 전극(D)이 격자 형상을 갖는 복수 개의 아일랜드 패턴으로 형성되고, 제1 영역이 분리된 본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터의 광학현미경 이미지이다.21B to 21F are optical microscope images of an oxide semiconductor thin film transistor according to another embodiment of the present invention in which the drain electrode D is formed of a plurality of island patterns having a lattice shape and the first region is separated.
도 21b 내지 21f를 참조하면, 본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터의 소스 전극(S) 및 드레인 전극(D)이 제1 영역이 분리된 격자 형상을 갖는 복수 개의 아일랜드 패턴으로 형성된 모습을 확인할 수 있다.21B to 21F, a source electrode S and a drain electrode D of an oxide semiconductor thin film transistor according to another embodiment of the present invention are formed in a plurality of island patterns having a first lattice-like lattice shape can confirm.
또한, 도 21b 내지 21f를 참조하면, 본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터의 소스 전극(S) 및 드레인 전극(D)의 격자 형상은 복수 개의 라인 패턴이 다양한 간격으로 잘 형성되는 것을 확인할 수 있다.21B to 21F, the lattice shape of the source electrode S and the drain electrode D of the oxide semiconductor thin film transistor according to another embodiment of the present invention is such that a plurality of line patterns are well formed at various intervals Can be confirmed.
도 22a 내지 도 22c는 제1 게이트 전극과 제2 게이트 전극이 동일한 사이즈를 갖는 본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터에서 서로 다른 게이트 구동(gate driving)에 따른 전송 특성을 도시한 그래프이다.22A to 22C are graphs showing transmission characteristics according to different gate driving in an oxide semiconductor thin film transistor according to another embodiment of the present invention in which the first gate electrode and the second gate electrode have the same size .
도 22a는 본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터에서 하부 스윕(Bottom sweep) 시 복수 개의 아일랜드 패턴 사이의 간격에 따른 전송 특성을 도시한 것이며, 도 22b는 본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터에서 상부 스윕(top sweep) 시 복수 개의 아일랜드 패턴 사이의 간격에 따른 전송 특성을 도시한 것이고, 도 22c는 본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터에서 듀얼 스윕(Dual sweep) 시 복수 개의 아일랜드 패턴 사이의 간격에 따른 전송 특성을 도시한 것이다.22A is a graph illustrating transmission characteristics according to a distance between a plurality of island patterns in a bottom sweep in an oxide semiconductor thin film transistor according to another embodiment of the present invention, FIG. 22C shows a transmission characteristic according to the interval between a plurality of island patterns in the top sweep of an oxide semiconductor thin film transistor, and FIG. 22C is a graph showing the transmission characteristics according to the dual sweep in the oxide semiconductor thin film transistor according to another embodiment of the present invention. And FIG. 5B shows transmission characteristics according to the interval between a plurality of island patterns.
도 22a 내지 도 22c를 참조하면, 분리된 제1 영역을 포함하는 복수 개의 아일랜드 패턴의 소스 전극 및 드레인 전극을 포함하는 본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터는 기준 산화물 반도체 박막 트랜지스터(0㎛)와 유사한 드레인 특성을 나타내는 것을 알 수 있다.22A to 22C, an oxide semiconductor thin film transistor according to another embodiment of the present invention including a source electrode and a drain electrode of a plurality of island patterns including an isolated first region includes a reference oxide semiconductor thin film transistor 0 Mu] m.
도 22d 내지 도 22f는 제1 게이트 전극과 제2 게이트 전극이 동일한 사이즈를 갖는 본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터에서 서로 다른 게이트 구동(gate driving)에 따른 출력 특성을 도시한 그래프이다.22D to 22F are graphs showing output characteristics according to different gate driving in an oxide semiconductor thin film transistor according to another embodiment of the present invention in which the first gate electrode and the second gate electrode have the same size .
도 22d는 본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터에서 하부 스윕(Bottom sweep) 시 복수 개의 아일랜드 패턴 사이의 간격에 따른 출력 특성을 도시한 것이고, 도 22e는 본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터에서 상부 스윕(top sweep) 시 복수 개의 아일랜드 패턴 사이의 간격에 따른 출력 특성을 도시한 것이며, 도 22f는 본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터에서 듀얼 스윕(Dual sweep) 시 복수 개의 아일랜드 패턴 사이의 간격에 따른 출력 특성을 도시한 것이다.22D is a graph illustrating an output characteristic according to a distance between a plurality of island patterns in a bottom sweep in an oxide semiconductor thin film transistor according to another embodiment of the present invention, and FIG. 22E is a graph illustrating an output characteristic according to another embodiment of the present invention FIG. 22F illustrates an output characteristic according to a distance between a plurality of island patterns in a top sweep of an oxide semiconductor thin film transistor. FIG. 22F illustrates a dual sweep in the oxide semiconductor thin film transistor according to another embodiment of the present invention. And FIG. 5B shows output characteristics according to an interval between a plurality of island patterns.
도 22d 내지 도 22f를 참조하면, 분리된 제1 영역을 포함하는 복수 개의 아일랜드 패턴의 소스 전극 및 드레인 전극을 포함하는 듀얼 게이트 구조의 산화물 반도체 박막 트랜지스터는 출력 특성이 개선되는 것을 알 수 있다.Referring to FIGS. 22D to 22F, it can be seen that the output characteristics of the oxide semiconductor thin film transistor having the dual gate structure including the source electrode and the drain electrode of the plurality of island patterns including the separated first region are improved.
도 22g는 도 22i의 본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터에서 하부 스윕 시, 복수 개의 아일랜드 패턴 사이의 간격 변화에 따른 출력 특성을 도시한 그래프이고, 도 22h는 도 22e의 본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터에서 상부 스윕 시, 복수 개의 아일랜드 패턴 사이의 간격 변화에 따른 출력 특성을 도시한 그래프이며, 도 22i는 도 22f의 본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터에서 듀얼 스윕 시, 복수 개의 아일랜드 패턴 사이의 간격 변화에 따른 출력 특성을 도시한 그래프이다.FIG. 22G is a graph showing output characteristics according to a change in spacing between a plurality of island patterns in a lower sweep in an oxide semiconductor thin film transistor according to another embodiment of the present invention in FIG. 22I, FIG. 22H is a graph FIG. 22I is a graph showing output characteristics of the oxide semiconductor thin film transistor according to another embodiment when the upper gap sweeps between a plurality of island patterns, and FIG. 22I is a graph showing the output characteristics of the oxide semiconductor thin film transistor FIG. 5 is a graph showing output characteristics according to a change in interval between a plurality of island patterns in a dual sweep. FIG.
도 22g 내지 도 22i는 VGS=5V이고, VDS=20V 일 때의 전류 값을 그래프로 나타내었고, 복수 개의 아일랜드 패턴의 폭은 10㎛이다.22G to 22I are graphs showing current values when VGS = 5V and VDS = 20V, and the width of a plurality of island patterns is 10 mu m.
도 22g 내지 도 22i를 참조하면, 본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터는 기준 산화물 반도체 박막 트랜지스터(0㎛)와 유사한 드레인 특성을 나타내는 것을 알 수 있다.22G to 22I, it can be seen that the oxide semiconductor thin film transistor according to another embodiment of the present invention exhibits a drain characteristic similar to that of the reference oxide semiconductor thin film transistor (0 mu m).
도 22a 내지 도 22c는 제1 게이트 전극과 제2 게이트 전극이 동일한 사이즈를 갖는 본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터에서 서로 다른 게이트 구동(gate driving)에 따른 전송 특성을 도시한 그래프이다.22A to 22C are graphs showing transmission characteristics according to different gate driving in an oxide semiconductor thin film transistor according to another embodiment of the present invention in which the first gate electrode and the second gate electrode have the same size .
도 23a 내지 도 23c는 소스/드레인 전극과 제2 게이트 사이의 이격 거리가 -1㎛인 오프셋 구조(제2 게이트 전극)를 갖는 본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터에서 서로 다른 게이트 구동(gate driving)에 따른 전송 특성을 도시한 그래프이다.FIGS. 23A to 23C are diagrams for explaining the case where an oxide semiconductor thin film transistor according to another embodiment of the present invention having an offset structure (second gate electrode) having a distance between a source / drain electrode and a second gate is -1 mu m FIG. 2 is a graph illustrating transmission characteristics according to gate driving. FIG.
도 23a는 본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터에서 하부 스윕(Bottom sweep) 시 복수 개의 아일랜드 패턴 사이의 간격에 따른 전송 특성을 도시한 것이고, 도 23b는 본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터에서 상부 스윕(top sweep) 시 복수 개의 아일랜드 패턴 사이의 간격에 따른 전송 특성을 도시한 것이며, 도 23c는 본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터에서 듀얼 스윕(Dual sweep) 시 복수 개의 아일랜드 패턴 사이의 간격에 따른 전송 특성을 도시한 것이다.FIG. 23A is a graph illustrating transmission characteristics according to a distance between a plurality of island patterns in a bottom sweep in an oxide semiconductor thin film transistor according to another embodiment of the present invention, and FIG. 23B is a graph illustrating transmission characteristics according to another embodiment of the present invention FIG. 23C shows a transmission characteristic according to the interval between a plurality of island patterns in the top sweep of an oxide semiconductor thin film transistor, and FIG. 23C shows a transfer characteristic in a dual sweep mode in the oxide semiconductor thin film transistor according to another embodiment of the present invention. And FIG. 5B shows transmission characteristics according to the interval between a plurality of island patterns.
도 23a 내지 도 23c는 본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터는 기준 산화물 반도체 박막 트랜지스터(0㎛)와 유사한 드레인 특성을 나타내는 것을 알 수 있다.23A to 23C show that the oxide semiconductor thin film transistor according to another embodiment of the present invention exhibits a drain characteristic similar to that of the reference oxide semiconductor thin film transistor (0 mu m).
도 23d 내지 도 23f는 소스/드레인 전극과 제2 게이트 사이의 이격 거리가 -1㎛인 오프셋 구조(제2 게이트 전극)를 갖는 본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터에서 서로 다른 게이트 구동(gate driving)에 따른 출력 특성을 도시한 그래프이다.23D to 23F illustrate an oxide semiconductor thin film transistor according to another embodiment of the present invention having an offset structure (second gate electrode) with a distance between a source / drain electrode and a second gate of -1 mu m, FIG. 2 is a graph showing output characteristics according to gate driving. FIG.
도 23d는 본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터에서 하부 스윕(Bottom sweep) 시 복수 개의 아일랜드 패턴 사이의 간격에 따른 출력 특성을 도시한 것이고, 도 23e는 본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터에서 상부 스윕(top sweep) 시 복수 개의 아일랜드 패턴 사이의 간격에 따른 출력 특성을 나타낸 것이며, 도 23f는 본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터에서 듀얼 스윕(Dual sweep) 시 복수 개의 아일랜드 패턴 사이의 간격에 따른 출력 특성을 도시한 것이다.FIG. 23D is a graph illustrating an output characteristic according to a distance between a plurality of island patterns in a bottom sweep in an oxide semiconductor thin film transistor according to another embodiment of the present invention, and FIG. 23E is a graph illustrating an output characteristic according to another embodiment of the present invention FIG. 23F is a graph illustrating an output characteristic according to a distance between a plurality of island patterns during top sweep in an oxide semiconductor thin film transistor. FIG. 23F is a graph illustrating the output characteristics of the oxide semiconductor thin film transistor according to another embodiment of the present invention when performing a dual sweep And shows an output characteristic according to the interval between a plurality of island patterns.
도 23d 내지 도 23f를 참조하면, 분리된 제1 영역을 포함하는 복수 개의 아일랜드 패턴의 소스 전극 및 드레인 전극을 포함하는 듀얼 게이트 구조의 산화물 반도체 박막 트랜지스터는 출력 특성이 개선되는 것을 알 수 있다.23D to 23F, it can be seen that the output characteristics of the oxide semiconductor thin film transistor of the dual gate structure including the source electrode and the drain electrode of a plurality of island patterns including the separated first region are improved.
도 23g는 도 23d의 본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터에서 하부 스윕 시, 복수 개의 아일랜드 패턴 사이의 간격 변화에 따른 출력 특성을 도시한 그래프이고, 도 23h는 도 23e의 본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터에서 상부 스윕 시, 복수 개의 아일랜드 패턴 사이의 간격 변화에 따른 출력 특성을 도시한 그래프이며, 도 23i는 도 23f의 본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터에서 듀얼 스윕 시, 복수 개의 아일랜드 패턴 사이의 간격 변화에 따른 출력 특성을 도시한 그래프이다.FIG. 23G is a graph showing output characteristics according to a change in interval between a plurality of island patterns in a lower sweep in the oxide semiconductor thin film transistor according to another embodiment of the present invention in FIG. 23D, and FIG. 23H is a graph FIG. 23I is a graph showing output characteristics according to a change in interval between a plurality of island patterns in an upper sweep in an oxide semiconductor thin film transistor according to another embodiment, and FIG. 23I is a graph showing the output characteristics of the oxide semiconductor thin film transistor FIG. 5 is a graph showing output characteristics according to a change in interval between a plurality of island patterns in a dual sweep. FIG.
도 23g 내지 도 23i는 VGS=5V이고, VDS=20V 일 때의 전류 값을 그래프로 나타내었고, 복수 개의 아일랜드 패턴의 폭은 10㎛이다.23G to 23I are graphs showing current values when VGS = 5V and VDS = 20V, and the width of a plurality of island patterns is 10 mu m.
도 23g 내지 도 23i를 참조하면, 본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터는 기준 산화물 반도체 박막 트랜지스터(0㎛)와 유사한 드레인 특성을 나타내는 것을 알 수 있다.Referring to FIGS. 23G to 23I, it can be seen that the oxide semiconductor thin film transistor according to another embodiment of the present invention exhibits a drain characteristic similar to that of the reference oxide semiconductor thin film transistor (0 mu m).
도 24a 및 도 24b는 본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터에서 듀얼 스윕 시 드레인 전류(drain current) 값을 하부 스윕 시의 드레인 전류 값으로 나누었을 때의 값을 비교한 그래프이다.FIGS. 24A and 24B are graphs comparing values obtained by dividing a drain current value in a dual sweep by a drain current value in a bottom sweep in an oxide semiconductor thin film transistor according to another embodiment of the present invention. FIG.
도 24a 및 도 24b는 VDS=20V이고, VGS=7.5, 10V이다.24A and 24B show VDS = 20V and VGS = 7.5, 10V.
도 24a는 제1 게이트 전극과 제2 게이트 전극이 같은 크기의 구조에서의 값을 도시한 것이고, 도 24b는 오프셋 구조(제2 게이트 전극)로 소스/드레인 전극과 제2 게이트 전극 사이의 이격 거리가 1㎛일 때의 값을 도시한 것이다.FIG. 24A shows values in a structure in which the first gate electrode and the second gate electrode have the same size, FIG. 24B shows the offset structure (second gate electrode), the distance between the source / drain electrode and the second gate electrode Is 1 [micro] m.
도 24a 및 도 24b를 참조하면, 복수 개의 아일랜드 패턴 사이의 간격에 상관없이 전체적으로 같은 비율을 나타내고 있는 것으로 보아, 듀얼 게이트 구동 시, 벌크 축적(bulk accumulation)이 잘 일어나고 있는 것을 알 수 있다.Referring to FIGS. 24A and 24B, the same ratio is shown regardless of the interval between a plurality of island patterns. As a result, it can be seen that bulk accumulation occurs well during dual gate driving.
도 25a은 제1 게이트 전극과 제2 게이트 전극이 같은 크기를 갖는 구조에서의 본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터가 듀얼 스윕 시 복수 개의 아일랜드 패턴의 간격의 변화에 따른 캐패시턴스-게이트 전압 특성을 도시한 그래프이고, 도 25b는 소스/드레인 전극과 제2 게이트 전극 사이의 이격 거리가 -1㎛인 오프셋 구조(제2 게이트 전극)의 본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터가 듀얼 스윕 시 복수 개의 아일랜드 패턴의 간격의 변화에 따른 캐패시턴스-게이트 접압 특성을 도시한 그래프이다.25A is a graph showing the relationship between the capacitance-gate voltage < RTI ID = 0.0 > & tilde & FIG. 25B is a graph showing an oxide semiconductor thin film transistor according to another embodiment of the present invention having an offset structure (second gate electrode) in which the distance between the source / drain electrode and the second gate electrode is -1 mu m FIG. 4 is a graph showing a capacitance-gate contact characteristic according to a variation of intervals of a plurality of island patterns in a dual sweep. FIG.
도 25a 및 도 25b를 참조하면, 분리된 제1 영역을 포함하는 복수 개의 아일랜드 패턴을 갖는 소스/드레인 전극을 포함함으로써, 기생 캐패시턴스가 감소되는 것을 알 수 있다.25A and 25B, it can be seen that the parasitic capacitance is reduced by including the source / drain electrode having a plurality of island patterns including the separated first region.
도 26a는 본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터를 1개 포함하는 화소 소자를 구비하는 디스플레이 장치의 회로도를 도시한 것이고, 도 26b는 본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터를 2개 포함하는 화소 소자를 구비하는 디스플레이 장치의 회로도를 도시한 것이다.FIG. 26A is a circuit diagram of a display device having a pixel element including one oxide semiconductor thin film transistor according to another embodiment of the present invention, and FIG. 26B is a cross-sectional view illustrating an oxide semiconductor thin film transistor according to another embodiment of the present invention. 2 shows a circuit diagram of a display device having a pixel element including two pixel elements.
도 26a 및 도 26b를 참조하면, 본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터를 디스플레이 장치의 화소 소자로 사용할 수 있는 것을 알 수 있다.Referring to FIGS. 26A and 26B, it can be seen that the oxide semiconductor thin film transistor according to another embodiment of the present invention can be used as a pixel element of a display device.
이하, 도 27a 내지 도 27g를 참조하여 본 발명의 또 따른 실시예에 따른 산화물 반도체 박막 트랜지스터에 대해 설명하기로 한다.Hereinafter, an oxide semiconductor thin film transistor according to another embodiment of the present invention will be described with reference to FIGS. 27A to 27G.
도 27a 내지 도 27g는 본 발명의 또 다른 실시예에 따른 산화물 반도체 박막 트랜지스터(코플라나(Coplanar) 구조)의 제조방법의 전체적인 흐름을 도시한 산화물 반도체 박막 트랜지스터의 단면도를 도시한 것이다.FIGS. 27A to 27G show cross-sectional views of an oxide semiconductor thin film transistor showing an overall flow of a method of manufacturing an oxide semiconductor thin film transistor (Coplanar structure) according to still another embodiment of the present invention.
본 발명의 또 다른 실시예에 따른 산화물 반도체 박막 트랜지스터는 도 27g에 도시된 바와 같이, 기판(203), 산화물 반도체층(205), 소스/드레인 전극(206, 207), 게이트 절연층(208) 및 제1 게이트 전극(209)을 포함하고, 지지층(202) 및 버퍼층(204)을 더 포함할 수 있다.The oxide semiconductor thin film transistor according to another embodiment of the present invention includes a substrate 203, an oxide semiconductor layer 205, source / drain electrodes 206 and 207, a gate insulating layer 208, And a first gate electrode 209, and may further include a support layer 202 and a buffer layer 204.
본 발명의 또 다른 실시예에 따른 산화물 반도체 박막 트랜지스터의 구성요소는 전술한 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터와 동일한 기술적 구성요소를 포함할 수 있고, 중복되는 구성요소에 대해서는 중복 기재를 생략하기로 한다.The elements of the oxide semiconductor thin film transistor according to another embodiment of the present invention may include the same technical elements as those of the oxide semiconductor thin film transistor according to an embodiment of the present invention, Is omitted.
도 27a를 참조하면, 본 발명의 또 다른 실시예에 따른 산화물 반도체 박막 트랜지스터의 제조방법은, 캐리어 기판(201) 상에 지지층(202)은 및 기판(203)을 형성한다.Referring to FIG. 27A, a method for fabricating an oxide semiconductor thin film transistor according to another embodiment of the present invention includes forming a support layer 202 and a substrate 203 on a carrier substrate 201.
도 27a에 도시된 바와 같이, 지지층(202)은 캐리어 기판(201) 상에 형성된다. 다만, 지지층(202)은 반드시 필요한 구성은 아니다.As shown in Fig. 27A, a support layer 202 is formed on the carrier substrate 201. Fig. However, the supporting layer 202 is not necessarily required.
또한, 기판(203)은 지지층(202) 상에 형성된다. 기판(203)은 산화물 반도체 박막 트랜지스터의 여러 구성 요소들을 지지하기 위한 기판으로서, 가요성(flexibility)을 갖는 기판일 수 있다.In addition, the substrate 203 is formed on the support layer 202. The substrate 203 is a substrate for supporting various components of the oxide semiconductor thin film transistor, and may be a substrate having flexibility.
도 27b를 참조하면, 본 발명의 또 다른 실시예에 따른 산화물 반도체 박막 트랜지스터의 제조방법은, 기판(203) 상에 버퍼층(buffer layer)(204)을 형성한다.Referring to FIG. 27B, a method of fabricating an oxide semiconductor thin film transistor according to another embodiment of the present invention includes forming a buffer layer 204 on a substrate 203.
도 27b에 도시된 바와 같이, 버퍼층(204)은 기판(203) 상에 형성될 수 있다.As shown in FIG. 27B, a buffer layer 204 may be formed on the substrate 203.
버퍼층(204)은 기판(203)을 통한 수분 또는 산소와 같은 외부 불순물의 침투를 방지하며, 기판(203)의 표면을 평탄화할 수 있다. 다만, 버퍼층(204)은 반드시 필요한 구성은 아니며, 기판(203)의 종류에 따라 채택되거나 생략될 수 있다.The buffer layer 204 prevents penetration of external impurities such as moisture or oxygen through the substrate 203 and can flatten the surface of the substrate 203. [ However, the buffer layer 204 is not necessarily required and may be adopted or omitted depending on the type of the substrate 203. [
도 27c를 참조하면, 본 발명의 또 다른 실시예에 따른 산화물 반도체 박막 트랜지스터의 제조방법은, 버퍼층(204)이 형성된 기판(203) 상에 산화물 반도체층(205)을 형성한다.Referring to FIG. 27C, a method for fabricating an oxide semiconductor thin film transistor according to another embodiment of the present invention includes forming an oxide semiconductor layer 205 on a substrate 203 on which a buffer layer 204 is formed.
도 27c에 도시된 바와 같이, 산화물 반도체층(205)은 버퍼층(204) 형성된다.As shown in Fig. 27C, the buffer layer 204 is formed of the oxide semiconductor layer 205. Fig.
도 27d를 참조하면, 본 발명의 또 다른 실시예에 따른 산화물 반도체 박막 트랜지스터의 제조방법은, 버퍼층(204) 및 산화물 반도체층(205) 상에 소스/드레인 전극(206, 207)을 형성한다.Referring to FIG. 27D, a method for fabricating an oxide semiconductor thin film transistor according to another embodiment of the present invention includes forming a source / drain electrode 206 and 207 on a buffer layer 204 and an oxide semiconductor layer 205.
도 27d에 도시된 바와 같이, 소스/드레인 전극(206, 207)은 버퍼층(204) 및 산화물 반도체층(205) 상에 산화물 반도체층(205)과 각각 전기적으로 연결되도록 서로 이격되어 형성된다.The source and drain electrodes 206 and 207 are spaced apart from each other to be electrically connected to the buffer layer 204 and the oxide semiconductor layer 205 on the oxide semiconductor layer 205, respectively.
도 27e를 참조하면, 본 발명의 또 다른 실시예에 따른 산화물 반도체 박막 트랜지스터의 제조방법은, 소스/드레인 전극(206, 207) 상에 게이트 절연층(208)을 형성한다.Referring to FIG. 27E, a method for fabricating an oxide semiconductor thin film transistor according to another embodiment of the present invention includes forming a gate insulating layer 208 on source / drain electrodes 206 and 207.
도 27e에 도시된 바와 같이, 게이트 절연층(208)은 소스/드레인 전극(206, 207) 상에 형성된다.As shown in FIG. 27E, a gate insulating layer 208 is formed on the source / drain electrodes 206 and 207.
도 27f를 참조하면, 본 발명의 또 다른 실시예에 따른 산화물 반도체 박막 트랜지스터의 제조방법은, 게이트 절연층(208) 상에 제1 게이트 전극(209)을 형성한다.Referring to FIG. 27F, a method for fabricating an oxide semiconductor thin film transistor according to another embodiment of the present invention includes forming a first gate electrode 209 on a gate insulating layer 208.
도 27f에 도시된 바와 같이, 제1 게이트 전극(209)은 게이트 절연층(208) 상에 산화물 반도체층(205)과 대응되도록 형성된다. 제1 게이트 전극(209)은 상부 게이트 전극(Top Gate)일 수 있다.The first gate electrode 209 is formed to correspond to the oxide semiconductor layer 205 on the gate insulating layer 208, as shown in Fig. The first gate electrode 209 may be a top gate electrode.
도 27g를 참조하면, 본 발명의 또 다른 실시예에 따른 산화물 반도체 박막 트랜지스터의 제조방법은, 캐리어 기판(201)을 제거한다.Referring to FIG. 27G, a method of manufacturing an oxide semiconductor thin film transistor according to still another embodiment of the present invention removes a carrier substrate 201.
도 27g에 도시된 바와 같이, 캐리어 기판(201)은 지지층(102)으로부터 제거될 수 있다.As shown in Fig. 27G, the carrier substrate 201 can be removed from the support layer 102. Fig.
본 발명의 또 다른 실시예에 따른 산화물 반도체 박막 트랜지스터는 소스/드레인 전극(206, 207)을 제1 영역이 분리된 복수 개의 아일랜드 패턴으로 형성되어 외부 스트레스에 대한 내성을 가질 수 있다.The oxide semiconductor thin film transistor according to another embodiment of the present invention may have resistance to external stress by forming source / drain electrodes 206 and 207 in a plurality of island patterns separated from the first region.
본 발명의 또 다른 실시예에 따른 산화물 반도체 박막 트랜지스터는 디스플레이 장치, 특히 플렉서블 디스플레이 장치의 화소 소자, 예를 들어 유기 발광 소자를 구동시키기 위해 사용될 수 있다.The oxide semiconductor thin film transistor according to another embodiment of the present invention can be used for driving a pixel element, for example, an organic light emitting element, of a display device, in particular, a flexible display device.
지금까지 산화물 반도체 박막 트랜지스터 및 이의 제조방법에 대해 설명하였으나, 이를 이용한 디스플레이 장치 및 이의 제조방법 역시 본 발명의 범위에 속한다.Although the oxide semiconductor thin film transistor and the manufacturing method thereof have been described so far, the display device using the oxide semiconductor thin film transistor and the manufacturing method thereof are also within the scope of the present invention.
구체적으로, 본 발명의 실시예들에 따른 산화물 반도체 박막 트랜지스터는 액정 디스플레이 장치(LCD) 또는 유기 발광 디스플레이 장치(AMOLED) 등의 플렉서블 디스플레이 장치의 화소 소자로 사용될 수 있다. 보다 구체적으로, 상술한 방법을 이용하여 산화물 반도체 박막 트랜지스터를 제조한 후, 소스/드레인 전극 중 어느 하나에 전기적으로 연결되는 화소 전극을 형성하는 단계를 거쳐, 디스플레이 장치를 제조할 수 있다.Specifically, the oxide semiconductor thin film transistor according to embodiments of the present invention can be used as a pixel element of a flexible display device such as a liquid crystal display device (LCD) or an organic light emitting display device (AMOLED). More specifically, a display device can be manufactured through the steps of forming an oxide semiconductor thin film transistor using the above-described method, and then forming a pixel electrode electrically connected to one of the source / drain electrodes.
예를 들어, 도 1a 내지 도 1h에 도시된 바와 같이, 소스/드레인 전극(206, 207) 덮는 패시베이션층을 형성하고, 덮는 패시베이션층의 관통홀을 통해 드레인 전극(207)에 컨택하는 화소 전극을 형성하며, 화소 전극 상에 발광층(미도시)을 포함하는 중간층(미도시)을 형성하고, 그 위에 대향전극(미도시)을 형성함으로써, 유기 발광 디스플레이 장치를 제조할 수 있다.For example, as shown in FIGS. 1A to 1H, a passivation layer is formed to cover the source / drain electrodes 206 and 207, and a pixel electrode that contacts the drain electrode 207 through the through hole of the passivation layer An intermediate layer (not shown) including a light emitting layer (not shown) is formed on the pixel electrode, and an opposite electrode (not shown) is formed thereon.
도 28은 본 발명의 또 다른 실시예에 따른 산화물 반도체 박막 트랜지스터(코플라나(Coplanar) 구조)의 듀얼 게이트 구조의 단면도를 도시한 것이다.28 shows a cross-sectional view of a dual gate structure of an oxide semiconductor thin film transistor (Coplanar structure) according to another embodiment of the present invention.
본 발명의 또 다른 실시예에 따른 산화물 반도체 박막 트랜지스터(코플라나(Coplanar) 구조)의 듀얼 게이트 구조는 기판(203), 기판 상에 형성되는 제2 게이트 전극(210), 제2 게이트 전극(210) 상에 형성되는 버퍼층(204), 버퍼층 상에 형성되는 산화물 반도체층(205), 소스/드레인 전극(206, 207), 게이트 절연층(208) 및 제1 게이트 전극(209)을 포함할 수 있다.A dual gate structure of an oxide semiconductor thin film transistor (Coplanar structure) according to another embodiment of the present invention includes a substrate 203, a second gate electrode 210 formed on the substrate, a second gate electrode 210 The gate insulating layer 208 and the first gate electrode 209 may be formed on the buffer layer 204 formed on the buffer layer 204, the oxide semiconductor layer 205 formed on the buffer layer, the source / drain electrodes 206 and 207, have.
본 발명의 또 다른 실시예에 따른 산화물 반도체 박막 트랜지스터(코플라나(Coplanar) 구조)의 듀얼 게이트 구조의 구성요소는 전술한 본 발명의 일 실시예에 따른 산화물 반도체 박막 트랜지스터 및 본 발명의 다른 실시예에 따른 산화물 반도체 박막 트랜지스터와 동일한 기술적 구성요소를 포함할 수 있고, 중복되는 구성요소에 대해서는 중복 기재를 생략하기로 한다.The components of the dual gate structure of the oxide semiconductor thin film transistor (Coplanar structure) according to another embodiment of the present invention are the oxide semiconductor thin film transistor according to the above-described embodiment of the present invention and the other embodiment The oxide semiconductor thin film transistor according to the present invention can include the same technical components as those of the oxide semiconductor thin film transistor according to the second embodiment.
기판(203)은 산화물 반도체 박막 트랜지스터의 여러 구성 요소들을 지지하기 위한 기판으로서, 가요성(flexibility)을 갖는 기판일 수 있다.The substrate 203 is a substrate for supporting various components of the oxide semiconductor thin film transistor, and may be a substrate having flexibility.
기판(203) 상에 제2 게이트 전극(210)이 형성되고, 제2 게이트 전극(210)은 하부 게이트 전극(Bottom Gate)일 수 있다.The second gate electrode 210 may be formed on the substrate 203 and the second gate electrode 210 may be a bottom gate electrode.
제2 게이트 전극(210) 상에는 버퍼층(buffer layer)(204)이 형성되고, 버퍼층은 게이트 절연막의 역할을 할 수 있고, 실시예에 따라, 제2 게이트 전극(210) 하부에 버퍼층이 형성되고, 제2 게이트 전극(210)의 상부에 게이트 절연막이 형성될 수 있다.A buffer layer 204 is formed on the second gate electrode 210. The buffer layer may serve as a gate insulating layer and a buffer layer may be formed under the second gate electrode 210, A gate insulating layer may be formed on the second gate electrode 210.
버퍼층(204)은 기판(203)을 통한 수분 또는 산소와 같은 외부 불순물의 침투를 방지하며, 기판(203)의 표면을 평탄화할 수 있다. 다만, 버퍼층(204)은 반드시 필요한 구성은 아니며, 기판(203)의 종류에 따라 채택되거나 생략될 수 있다.The buffer layer 204 prevents penetration of external impurities such as moisture or oxygen through the substrate 203 and can flatten the surface of the substrate 203. [ However, the buffer layer 204 is not necessarily required and may be adopted or omitted depending on the type of the substrate 203. [
버퍼층(204)이 형성된 기판(203) 상에 산화물 반도체층(205)이 형성된다.The oxide semiconductor layer 205 is formed on the substrate 203 on which the buffer layer 204 is formed.
또한, 버퍼층(204) 및 산화물 반도체층(205) 상에 소스/드레인 전극(206, 207)이 형성된다.Further, source / drain electrodes 206 and 207 are formed on the buffer layer 204 and the oxide semiconductor layer 205.
본 발명의 또 다른 실시예에 따른 산화물 반도체 박막 트랜지스터(코플라나(Coplanar) 구조)의 듀얼 게이트 구조는 소스/드레인 전극(206, 207)을 제1 영역이 분리된 복수 개의 아일랜드 패턴으로 형성되어 외부 스트레스에 대한 내성을 가질 수 있다.The dual gate structure of the oxide semiconductor thin film transistor (Coplanar structure) according to another embodiment of the present invention includes source / drain electrodes 206 and 207 formed by a plurality of island patterns separated from the first region, It can tolerate stress.
소스/드레인 전극(206, 207)은 버퍼층(204) 및 산화물 반도체층(205) 상에 산화물 반도체층(205)과 각각 전기적으로 연결되도록 서로 이격되어 형성된다.The source / drain electrodes 206 and 207 are formed so as to be electrically connected to the buffer layer 204 and the oxide semiconductor layer 205 on the oxide semiconductor layer 205, respectively.
소스/드레인 전극(206, 207) 상에 게이트 절연층(208)이 형성되고, 게이트 절연층(208) 상에 제1 게이트 전극(209)이 형성된다.A gate insulating layer 208 is formed on the source / drain electrodes 206 and 207 and a first gate electrode 209 is formed on the gate insulating layer 208.
제1 게이트 전극(209)은 게이트 절연층(208) 상에 산화물 반도체층(205)과 대응되도록 형성된다. 제1 게이트 전극(209)은 상부 게이트 전극(Top Gate)일 수 있다.The first gate electrode 209 is formed to correspond to the oxide semiconductor layer 205 on the gate insulating layer 208. The first gate electrode 209 may be a top gate electrode.
본 발명의 또 다른 실시예에 따른 산화물 반도체 박막 트랜지스터(코플라나(Coplanar) 구조)의 듀얼 게이트 구조는 디스플레이 장치, 특히 플렉서블 디스플레이 장치의 화소 소자, 예를 들어 유기 발광 소자를 구동시키기 위해 사용될 수 있다.A dual gate structure of an oxide semiconductor thin film transistor (Coplanar structure) according to another embodiment of the present invention can be used for driving a pixel element of a display device, particularly a flexible display device, for example, an organic light emitting element .
지금까지 산화물 반도체 박막 트랜지스터 및 이의 제조방법에 대해 설명하였으나, 이를 이용한 디스플레이 장치 및 이의 제조방법 역시 본 발명의 범위에 속한다.Although the oxide semiconductor thin film transistor and the manufacturing method thereof have been described so far, the display device using the oxide semiconductor thin film transistor and the manufacturing method thereof are also within the scope of the present invention.
구체적으로, 본 발명의 실시예들에 따른 산화물 반도체 박막 트랜지스터는 액정 디스플레이 장치(LCD) 또는 유기 발광 디스플레이 장치(AMOLED) 등의 플렉서블 디스플레이 장치의 화소 소자로 사용될 수 있다. 보다 구체적으로, 상술한 방법을 이용하여 산화물 반도체 박막 트랜지스터를 제조한 후, 소스/드레인 전극 중 어느 하나에 전기적으로 연결되는 화소 전극을 형성하는 단계를 거쳐, 디스플레이 장치를 제조할 수 있다.Specifically, the oxide semiconductor thin film transistor according to embodiments of the present invention can be used as a pixel element of a flexible display device such as a liquid crystal display device (LCD) or an organic light emitting display device (AMOLED). More specifically, a display device can be manufactured through a step of forming an oxide semiconductor thin film transistor using the above-described method, and then forming a pixel electrode electrically connected to one of the source / drain electrodes.
예를 들어, 도 1a 내지 도 1h에 도시된 바와 같이, 소스/드레인 전극 덮는 패시베이션층을 형성하고, 덮는 패시베이션층의 관통홀을 통해 드레인 전극에 컨택하는 화소 전극을 형성하며, 화소 전극 상에 발광층을 포함하는 중간층(미도시)을 형성하고, 그 위에 대향전극을 형성함으로써, 유기 발광 디스플레이 장치를 제조할 수 있다.For example, as shown in FIGS. 1A to 1H, a passivation layer covering the source / drain electrodes is formed, and pixel electrodes for contacting the drain electrodes through the through holes of the covering passivation layer are formed. An organic light emitting display device can be manufactured by forming an intermediate layer (not shown) on the substrate, and forming an opposite electrode thereon.
이상과 같이 본 발명은 비록 한정된 실시예와 도면에 의해 설명되었으나, 본 발명은 상기의 실시예에 한정되는 것은 아니며, 본 발명이 속하는 분야에서 통상의 지식을 가진 자라면 이러한 기재로부터 다양한 수정 및 변형이 가능하다. 그러므로, 본 발명의 범위는 설명된 실시예에 국한되어 정해져서는 아니 되며, 후술하는 특허청구범위뿐 아니라 이 특허청구범위와 균등한 것들에 의해 정해져야 한다.While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. This is possible. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be determined by the equivalents of the claims, as well as the claims.

Claims (17)

  1. 기판; Board;
    상기 기판 상에 형성된 제1 게이트 전극; A first gate electrode formed on the substrate;
    상기 제1 게이트 전극 상에 형성된 게이트 절연층; A gate insulating layer formed on the first gate electrode;
    상기 제1 게이트 전극과 대응되도록 상기 게이트 절연층 상에 형성된 산화물 반도체층;An oxide semiconductor layer formed on the gate insulating layer to correspond to the first gate electrode;
    상기 산화물 반도체층 상에 소스 전극 및 드레인 전극이 서로 이격되어 형성되고, 각각 복수 개의 아일랜드 패턴으로 형성되는 소스/드레인 전극;A source / drain electrode formed on the oxide semiconductor layer so as to be spaced apart from the source electrode and the drain electrode, the source / drain electrode being formed in a plurality of island patterns;
    상기 소스/드레인 전극 상에 형성된 패시베이션층The passivation layer formed on the source /
    을 포함하고, / RTI >
    상기 소스/드레인 전극은 상기 기판의 수평면을 기준으로 상기 제1 게이트 전극 방향에 형성된 제1 영역 및 제1 영역과 반대 방향에 형성된 제2 영역을 포함하고,Wherein the source / drain electrodes include a first region formed in the first gate electrode direction and a second region formed in a direction opposite to the first region with respect to a horizontal plane of the substrate,
    상기 복수 개의 아일랜드 패턴은 상기 제1 영역이 서로 분리되어 외부 스트레스에 대한 내성을 가지는 것을 특징으로 하는 산화물 반도체 박막 트랜지스터.Wherein the plurality of island patterns are separated from each other to have resistance to external stress.
  2. 제1항에 있어서,The method according to claim 1,
    상기 복수 개의 아일랜드 패턴은 복수 개의 라인 패턴이 반복되어 형성된 복수 개의 라인 형상인 것을 특징으로 하는 산화물 반도체 박막 트랜지스터.Wherein the plurality of island patterns have a plurality of line shapes in which a plurality of line patterns are repeatedly formed.
  3. 제2항에 있어서,3. The method of claim 2,
    상기 복수 개의 라인 패턴의 각각의 폭은 1 ㎛ 내지 10 ㎛인 것을 특징으로 하는 산화물 반도체 박막 트랜지스터.Wherein the width of each of the plurality of line patterns is 1 占 퐉 to 10 占 퐉.
  4. 제2항에 있어서,3. The method of claim 2,
    상기 복수 개의 라인 패턴의 각각이 이격되는 간격은 1 ㎛ 내지 16 ㎛인 것을 특징으로 하는 산화물 반도체 박막 트랜지스터.Wherein the interval between the plurality of line patterns is 1 占 퐉 to 16 占 퐉.
  5. 제1항에 있어서,The method according to claim 1,
    상기 제1 게이트 전극은 상기 산화물 반도체층 상에 형성된 상기 소스/드레인 전극으로부터 수평 방향으로 -1 ㎛ 내지 3 ㎛ 만큼 이격되도록 형성되는 것을 특징으로 하는 산화물 반도체 박막 트랜지스터.Wherein the first gate electrode is formed so as to be spaced apart from the source / drain electrode formed on the oxide semiconductor layer by -1 占 퐉 to 3 占 퐉 in the horizontal direction.
  6. 제1항에 있어서,The method according to claim 1,
    상기 복수 개의 아일랜드 패턴은 복수 개의 라인 패턴이 수직으로 교차하는 격자 형상인 것을 특징으로 하는 산화물 반도체 박막 트랜지스터.Wherein the plurality of island patterns have a lattice shape in which a plurality of line patterns vertically cross each other.
  7. 제1항에 있어서,The method according to claim 1,
    상기 산화물 반도체 박막 트랜지스터는,The oxide semiconductor thin film transistor includes:
    상기 소스/드레인 전극 상에 형성된 패시베이션층 상에 제2 게이트 전극을 더 포함하는 것을 특징으로 하는 산화물 반도체 박막 트랜지스터.And a second gate electrode on the passivation layer formed on the source / drain electrode.
  8. 제7항에 있어서,8. The method of claim 7,
    상기 제2 게이트 전극은 상기 산화물 반도체층 상에 형성된 상기 소스/드레인 전극으로부터 수평 방향으로 -1 ㎛ 내지 3 ㎛ 만큼 이격되도록 형성되는 것을 특징으로 하는 산화물 반도체 박막 트랜지스터.And the second gate electrode is formed to be spaced apart from the source / drain electrode formed on the oxide semiconductor layer by a distance of -1 탆 to 3 탆 in a horizontal direction.
  9. 제7항에 있어서,8. The method of claim 7,
    상기 제1 게이트 전극 및 상기 제2 게이트 전극을 전기적으로 연결하는 연결 전극을 더 포함하는 것을 특징으로 하는 산화물 반도체 박막 트랜지스터.And a connection electrode electrically connecting the first gate electrode and the second gate electrode to each other.
  10. 제9항에 있어서,10. The method of claim 9,
    상기 제1 게이트 전극 및 상기 제2 게이트 전극은 전기적으로 연결되어 동일한 전압을 인가받는 것을 특징으로 하는 산화물 반도체 트랜지스터.Wherein the first gate electrode and the second gate electrode are electrically connected to receive the same voltage.
  11. 기판 상에 형성된 산화물 반도체층, 상기 산화물 반도체층 상에 형성된 제1 게이트 전극 및 각각 복수 개의 아일랜드 패턴으로 형성되는 소스/드레인 전극을 포함하는 코플라나(Coplanar)형 산화물 반도체 박막 트랜지스터에 있어서,1. A Coplanar type oxide semiconductor thin film transistor comprising: an oxide semiconductor layer formed on a substrate; a first gate electrode formed on the oxide semiconductor layer; and source / drain electrodes each formed of a plurality of island patterns,
    상기 소스/드레인 전극은 상기 기판의 수평면을 기준으로 상기 제1 게이트 전극 방향에 형성된 제1 영역 및 제1 영역과 반대 방향에 형성된 제2 영역을 포함하고,Wherein the source / drain electrodes include a first region formed in the first gate electrode direction and a second region formed in a direction opposite to the first region with respect to a horizontal plane of the substrate,
    상기 복수 개의 아일랜드 패턴은 상기 제1 영역이 서로 분리되어 외부 스트레스에 대한 내성을 가지는 것을 특징으로 하는 산화물 반도체 박막 트랜지스터.Wherein the plurality of island patterns are separated from each other to have resistance to external stress.
  12. 제10항에 있어서,11. The method of claim 10,
    상기 산화물 반도체층 하부에 제2 게이트 전극을 더 포함하는 것을 특징으로 하는 산화물 반도체 박막 트랜지스터.And a second gate electrode below the oxide semiconductor layer.
  13. 기판; Board;
    상기 기판 상에 형성된 제1항 내지 제12항 중 어느 한 항에 따른 산화물 반도체 박막 트랜지스터; 및 An oxide semiconductor thin film transistor according to any one of claims 1 to 12 formed on the substrate; And
    상기 산화물 반도체 박막 트랜지스터와 전기적으로 연결된 디스플레이 소자And a display element electrically connected to the oxide semiconductor thin film transistor
    를 포함하는 디스플레이 장치..
  14. 제13항에 있어서,14. The method of claim 13,
    상기 디스플레이 소자는 유기 발광 소자인 것을 특징으로 하는 디스플레이 장치.Wherein the display device is an organic light emitting device.
  15. 기판 상에 제1 게이트 전극을 형성하는 단계; Forming a first gate electrode on the substrate;
    상기 제1 게이트 전극 상에 게이트 절연층을 형성하는 단계; Forming a gate insulating layer on the first gate electrode;
    상기 제1 게이트 전극과 대응되는 상기 게이트 절연층 상에 산화물 반도체층을 형성하는 단계; Forming an oxide semiconductor layer on the gate insulating layer corresponding to the first gate electrode;
    상기 산화물 반도체층 상에 소스/드레인 전극을 서로 이격되되, 복수 개의 아일랜드 패턴으로 패턴화하여 형성하는 단계;Forming source / drain electrodes on the oxide semiconductor layer by patterning the source / drain electrodes in a plurality of island patterns spaced apart from each other;
    상기 소스/드레인 전극 상에 패시베이션층을 형성하는 단계Forming a passivation layer on the source / drain electrode
    를 포함하는 산화물 반도체 박막 트랜지스터의 제조방법.Wherein the oxide semiconductor thin film transistor is formed on the substrate.
  16. 제15항에 있어서,16. The method of claim 15,
    상기 페시베이션층 상에 제2 게이트 전극을 형성하는 단계를 더 포함하는 것을 특징으로 하는 산화물 반도체 박막 트랜지스터의 제조 방법.And forming a second gate electrode on the passivation layer. ≪ RTI ID = 0.0 > 11. < / RTI >
  17. 제16항에 있어서,17. The method of claim 16,
    상기 제1 게이트 전극 또는 상기 제2 게이트 전극은 상기 산화물 반도체층 상에 형성된 상기 소스/드레인 전극으로부터 수평 방향으로 -1 ㎛ 내지 3 ㎛ 만큼 이격되도록 형성되는 것을 특징으로 하는 산화물 반도체 박막 트랜지스터의 제조 방법.Wherein the first gate electrode or the second gate electrode is formed to be spaced apart from the source / drain electrode formed on the oxide semiconductor layer by a distance of -1 탆 to 3 탆 in a horizontal direction .
PCT/KR2018/012903 2017-10-27 2018-10-29 Oxide semiconductor thin-film transistor and method for manufacturing same WO2019083338A1 (en)

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