WO2019071371A1

WO2019071371A1 - Analog-to-digital signal conversion system and method

Info

Publication number: WO2019071371A1
Application number: PCT/CN2017/105317
Authority: WO
Inventors: 林奇青; 徐嘉骏; 杨富强
Original assignee: 深圳市汇顶科技股份有限公司
Priority date: 2017-10-09
Filing date: 2017-10-09
Publication date: 2019-04-18
Also published as: CN110036568B; CN110036568A

Abstract

An analog-to-digital signal conversion system (300) and method. The system (300) comprises a digital signal splitting unit (401), a first digital signal storage unit (411), a second digital signal storage unit (421), a first storage capacitance selection unit (412) and a second storage capacitance selection unit (422), wherein the digital signal splitting unit (401) is used for splitting a signal code N of a digital control signal into a first signal code K represented by a number of bits x and a second signal code P represented by a number of bits y, said signal code N being output and fed back by the analog-to-digital signal conversion system (300) and being represented by a number of bits z; the first and second digital signal storage units (411, 421) are respectively used for sequentially storing the first signal code K and the second signal code P; and the first and second storage capacitance selection units (412, 422) are respectively used for selecting the storage capacitances of the first signal code K and the second signal code P. Therefore, the number of leads and the amount of hardware inside a system is greatly decreased, power consumption is reduced, and the overall operational efficiency of the system is improved.

Description

Analog-digital signal conversion system and method

Technical field

Embodiments of the present invention relate to the field of analog-to-digital signal conversion technologies, and in particular, to an analog-to-digital signal conversion system and method.

Background technique

Converters between digital and analog signals, such as DACs or ADCs, have been widely used in communication systems, consumer electronics and audio equipment. However, inside the DAC or ADC, there is inevitably a noise problem caused by component mismatch. Such problems are often handled by a multi-step feedback Sigma-Delta Modulator (SDM), making multi-order The feedback delta-sigma modulator is particularly important in the application of the ADC. Nowadays, Dynamic Element Matching (DEM) has been proposed to solve the internal nonlinear problem of ADC. Among the many solutions, Data Weighted Averaging (DWA) algorithm is the most in DEM. A common algorithm.

The data weighted averaging algorithm can reduce the problem of storage capacitor matching requirements for digital signals in DAC or ADC systems. The principle is to make each storage capacitor be used as many times as possible, and can be ignored by cyclically selecting storage capacitors. The error caused by the difference in each storage capacitor pushes the noise and distortion introduced by the DAC or ADC nonlinearity error to a higher, less used frequency band. As shown in Figure 1, assume that there is a 3-bit (3-bit) DAC or ADC system that can be stored or stored by a storage capacitor array 11 of 2 ³ -1 (ie, seven) storage capacitors 111. The Binary code is converted into the data of the Thermometer code (as shown in Table 1). If all the storage capacitors of the storage capacitor array 11 have been sequentially stored, the data to be subsequently registered or stored will be The first storage capacitor that loops back to the storage capacitor array 11 continues. The manner in which it is performed can be further referred to Figures 2A-2C. First, referring to FIG. 2A, assuming that the first data received by the system is 2, the pointer 12 of the system selects two storage capacitors 111 from the first storage capacitor of the storage capacitor array 11 to enable registration of the data. Or save. Next, referring to FIG. 2B, when the second data received by the system is 4, the pointer 12 of the system will shift from the original position to the right by a storage capacitor, starting from the third storage capacitor of the storage capacitor array 11. Four storage capacitors 111 are sequentially selected to enable registration or storage of data. Referring to FIG. 2C, when the third data received by the system is 3, the position of the pointer 12 of the system is the sixth storage capacitor of the storage capacitor array 11, and only one storage capacitor is left on the right side. That is, the seventh storage capacitor has not been turned on, so after selecting the seventh storage capacitor, the pointer 12 will jump back to the first storage capacitor of the storage capacitor array 11 and continue to select two storage capacitors 111 to turn on the data. Host or store. In this way, the number of times each storage capacitor 111 of the storage capacitor array 11 is used is nearly the same, so that the error values caused by the difference between the different storage capacitors 111 are equally equalized. It is the working principle of the data weighted average algorithm.

Table I

The data weighted average algorithm is indeed a very practical operation method in the analog-digital signal conversion system based on multi-level feedback trigonometric integration. The required hardware system can be fabricated by semiconductor chips. However, in the modern and rapid advancement of science and technology, as various electronic devices need to increase the amount of information to be processed, the data weighted average algorithm needs to process data levels more and more complicated, requiring higher-order data processing capabilities, and its hardware system. The area of semiconductor chips consumed and the power consumption of their systems have also increased rapidly.

Summary of the invention

An object of the embodiments of the present invention is to provide an analog-to-digital signal conversion system and method, which can reduce the number of components required for processing high-order data by reducing the operation correction of the data weighted average algorithm in the system, thereby reducing the number of components. Cost, while reducing the overall power consumption of the system, improving overall efficiency.

An embodiment of the present invention provides an analog-to-digital signal conversion system, including: a digital signal splitting unit that splits a signal code N of a digital control signal represented by a bit number z, which is fed back by the analog-to-digital signal conversion system The first signal code K represented by the number of bits x and the second signal code P, N, K, P, x, y, and z represented by the number of bits y are positive integers, N=2K+P, x +y=z+1, y is at least 2, [2*(2 ^x -1)+(2 ^y -1)]≧(2 ^z -1); a first digital signal storage unit having 2 ^x -1 a storage capacitor for sequentially storing the first signal code K; a second digital signal storage unit having 2 ^y -1 storage capacitors for sequentially storing the second signal code P; a storage capacitor selection unit, configured to select a storage capacitor for storing the first signal code K according to a first signal code K and a position number of a storage capacitor storing the last data stored in the first digital signal storage unit; And a second storage capacitor selection unit, according to the second signal code P and the storage capacitor of the last one of the second digital signal storage units storing data Position number, select the second storage capacitor for storing the channel number of P.

An embodiment of the present invention provides an analog-to-digital signal conversion method, including the steps of: receiving a feedback-output digital control signal, the signal code N of the digital control signal is represented by a bit number z; and splitting the signal code N is a first signal code K and a second signal code P, the first signal code K is represented by a bit number x and the second signal code is represented by a bit number y, N, K, P, x, y, z Are positive integers, N=2K+P, x+y=z+1, y is at least 2, [2*(2 ^x -1)+(2 ^y -1)]≧(2 ^z -1); Selecting, by the first signal code K, a result of the operation of the position number of the storage capacitor storing the data of the last storage capacitor of 2 ^x -1 storage capacitors, and selecting a storage capacitor for storing the first signal code K; The storage result of the second signal code P and the position number of the last storage capacitor storing the data of the 2 ^y -1 storage capacitors is selected to store the storage capacitor of the second signal code P.

The technical solution of the embodiment of the present invention has the following advantages: (1) Compared with the use of a typical data weighted average algorithm, the present invention can reduce the number of leads required for conversion between the digital area and the analog area within the system; (2) The analog-to-digital signal conversion system can save a large amount of hardware used by the system and reduce the cost due to the splitting of the signal code; (3) the analog-digital signal conversion system can reduce the power consumption due to the separation of the signal code Quantity, improve the overall performance of the system.

DRAWINGS

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, a brief description of the drawings used in the embodiments or the prior art description will be briefly described below. Obviously, the drawings in the following description It is a certain embodiment of the present application, and other drawings can be obtained according to the drawings without any creative work for those skilled in the art.

1 is a schematic diagram of a storage capacitor array of a typical 3-bit data weighted average algorithm;

2A to 2C are schematic diagrams showing storage capacitor selection of a typical 3-bit data weighted average algorithm;

3 is a schematic structural diagram of a cascaded integral feedback (CIFB) structure of an analog-digital signal conversion system applied to a delta-sigma modulator according to an embodiment of the present invention;

4 is a schematic structural diagram of a DAC unit of the analog-digital signal conversion system of FIG. 3;

FIG. 5 is a schematic structural diagram of a first storage capacitor selection unit of FIG. 4; FIG.

6 is a schematic structural diagram of a second storage capacitor selection unit of FIG. 4;

FIG. 7 is a schematic flowchart diagram of an analog-digital signal conversion method according to an embodiment of the present invention; FIG.

FIG. 8 is a schematic structural diagram of a digital signal splitting unit according to an embodiment of the present invention; FIG.

FIG. 9 is a schematic structural diagram of a digital signal splitting unit according to another embodiment of the present invention.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the drawings in the embodiments of the present invention. It is a partial embodiment of the invention, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present invention without creative efforts are within the scope of the present invention.

The technical solutions of the present application are further described below through specific embodiments. Embodiments of the present invention relate to an improved data weighted average algorithm capable of reducing the number of components used in a hardware system of an analog-digital signal conversion system, improving the overall efficiency of the system, and a system for implementing the algorithm.

FIG. 3 is a schematic structural diagram of a Cascaded Integrator Feedback (CIFB) structure of an analog-digital signal conversion system applied to a delta-sigma modulator according to an embodiment of the present invention. Referring to FIG. 3, an analog-to-digital signal conversion system 300 is shown. The analog signal U is input to the left side of FIG. 3, and is output via the operation of the adder unit 1, the integrator unit 2, and the ADC unit 3 in the system. Digital signal N. In order to make the output digital signal N closer to the original input analog signal U, there is another DAC unit 4 below the ADC unit 3 on the right side of FIG. 3, which can convert the output digital signal N back to the analog signal. The feedback is returned to the adder, and after the integral input analog signal is superimposed and integrated, the original input analog signal U is compared, and then the integrated value of the signal is moderately adjusted to make the output digital signal N closer to the input. Analog signal U reduces the generation of errors. The technical feature of the present invention is the signal processing applied inside the DAC unit 4, which improves the efficiency of signal processing and reduces the number of hardware system components required by the DAC unit 4.

4 is a schematic structural diagram of a DAC unit 4 of the analog-to-digital signal conversion system 300 of FIG. 3; as shown in FIGS. 3 and 4, an analog-to-digital signal conversion system 300 according to an embodiment of the present invention includes a DAC unit 4 Located on a feedback path of the analog-to-digital signal conversion system 300, the DAC unit 4 includes a digital signal splitting unit 401 that outputs the signal code of the digital control signal represented by the bit number z fed back by the analog-to-digital signal conversion system 300 (or The data N is split into a first signal code K represented by the number of bits x and a second signal code P represented by the number of bits y, wherein N, K, P, x, y, and z are positive integers. And satisfy N=2K+P, x+y=z+1, y is at least 2, and [2*(2 ^x -1)+(2 ^y -1)]≧(2 ^z -1). Converting the binary code of the first signal code K and the second signal code P into a thermal code for subsequent signal processing. The DAC unit 4 further includes a first digital signal storage unit 411 having 2 ^x -1 storage capacitors for sequentially storing the first signal code K; and a second digital signal storage unit 421 having 2 ^y -1 a storage capacitor for sequentially storing the second signal code P; a first storage capacitor selection unit 412, which determines the last storage of the first signal code K and the 2 ^x -1 storage capacitors Whether the position numbers of the storage capacitors having data are added to be greater than 2 ^x -1, and selecting the first signal code K from the storage capacitors of the 2 ^x -1 storage capacitors that do not store data according to the judgment result The storage capacitor of the hot code, that is, if the result of adding the first signal code K to the position number s of the last storage capacitor storing the data is less than or equal to 2 ^x -1, the s+1 to s are sequentially selected. +K storage capacitors are used to store the hot code corresponding to the first signal code K. If the first signal code K is added to the position number s of the last storage capacitor storing the data, the result is greater than 2 ^x -1, then select the number of the storage capacitor to s + 1 and the number of 2 ^x -1 to 1 s + K- (2 ^x -1) for storing A signal code corresponding to the hot code K, note, s maximum value is 2 ^x -1, when s = 2 ^x -1, i.e., a first digital signal represents a storage capacitor memory cell has stored the last 411 data , s+1 is greater than the maximum position number 2 ^x -1, then the selected storage capacitor should actually start from sequence number 1, to [(2 ^x -1)+K]-(2 ^x -1) end; and a second The storage capacitor selection unit 422 determines whether the second signal code P is greater than 2 ^y -1 after adding the position number of the last storage capacitor storing the data of the 2 ^y -1 storage capacitors, and The result of the determination is that the storage capacitor of the thermal code of the second signal code P is selected from the storage capacitors that do not store data of the 2 ^y -1 storage capacitors, and the specific process is similar to the storage of the first signal code K, Let me repeat.

In the present embodiment, the analog-to-digital signal conversion system 300 and its DAC unit 4 are all operated based on the triangular integral modulation. In order to effectively solve the DAC unit 4 of the analog-digital signal conversion system 300, it takes a lot of hardware system components to process high-order data. For the problem of high cost and low efficiency, the present embodiment adopts a digital signal splitting unit 401 and according to the relation N=2*K+P, the output of the analog-to-digital signal conversion system 300 is represented by a bit number z. The signal code N of the digital control signal is split into a first signal code K represented by the number of bits x and a second signal code P represented by the number of bits y. It can be understood from the relationship that in this embodiment, the signal code N of the digital signal represented by the bit number z is split into a first signal code K which can be expressed by the number of bits x by degrading the number of bits, and Another second signal code P, represented by the number of bits y, which can be expressed using a lower number of bits, such as x = z - 1, y = 2. This can reduce the number of hardware system components that the DAC unit 4 of the analog-to-digital signal conversion system 300 needs to use, and can also reduce the number of leads required for conversion between the digital zone and the analog zone, simplifying the complexity of the analog-digital signal conversion system 300. Experiments in this application demonstrate that when the value of z is 4 or more, there is a considerable significant reduction in the effects of hardware system components. In another embodiment, the DAC unit 4 of the analog-to-digital signal conversion system 300 may further include a storage body that stores the signal code N and is split into the first signal code K and the second signal. The truth value representation table (Truth Table) of the number P.

FIG. 5 is a schematic structural diagram of the first storage capacitor selection unit 412 of FIG. 4. As shown in FIG. 5, the first storage capacitor selection unit 412 includes a first adder unit 4121, a first data buffer unit 4122, a first post-binary code to hot code unit 4123, and a first pre-binary code. The hot code unit 4124 and a first control unit 4125, the first adder unit 4121 can receive the signal code K output after the signal code N is split by the aforementioned digital signal splitting unit 401; the first data buffer unit 4122 can receive And delaying the previous signal code Ptr(n-1) output by the first adder unit 4121, waiting for the first adder unit 4121 to receive the next signal code K, and then the previous signal code The Ptr(n-1) output is fed back to the first adder unit 4121 and added to the next signal code K as the output of the latter signal code Ptr(n); the first post-binary code to the hot code unit 4123 receives the latter signal code Ptr(n) output by the first adder unit 4121, and converts the latter signal code Ptr(n) into a subsequent thermal code and outputs the same; the first pre-binary code heat-transfer code Unit 4124 receives the previous signal code Ptr(n-1) output by the first data buffer unit 4122. And converting the previous signal code Ptr(n-1) to the previous thermal code and outputting; the first control unit 4125 is internally provided with a first comparator 41251 and a first data selector 41252, A comparator 41251 can receive the latter thermal code output by the first post-binary code transcoding unit 4123 and compare it with the previous thermal code output by the first pre-binary code transcoding unit 4124 to determine whether the foregoing The judgment condition of the first storage capacitor selection unit 412, that is, whether the first signal code K is added to the position number of the last storage capacitor storing the data of the 2 ^x -1 storage capacitors is greater than 2 ^x - 1. The first data selector 41252 selects to open the storage capacitor circuit of the first digital signal storage unit 411 according to the determination result of the first comparator 41251 and the received subsequent thermal code, and sequentially stores the first A thermal code of a signal code K conversion. Similarly, FIG. 6 is a schematic structural diagram of the second storage capacitor selection unit 422 in FIG. As shown in FIG. 6, the inside of the second storage capacitor selection unit 422 also has a structure similar to that of the first storage capacitor selection unit 412 to process the converted thermal code of the second signal code P, and thus will not be described again.

FIG. 7 is a schematic flow chart of an analog-digital signal conversion method according to an embodiment of the present invention. As shown in FIG. 7, an embodiment of the present application provides an analog-to-digital signal conversion method for an analog-to-digital signal conversion system that operates based on triangulation integration modulation, including the following steps:

Step 501: Receive a signal code N of a digital control signal that is outputted by feedback, and the signal code N of the digital control signal is represented by a bit number z;

Step 502: Split the signal code N into a first signal code K and a second signal code P, the first signal code K is represented by the number of bits x and the second signal code P is represented by the number of bits y , N, K, P, x, y, z are positive integers, N = 2K + P, x + y = z + 1, y is at least 2, [2 * (2 ^x -1) + (2 ^y - 1)]≧(2 ^z -1);

Step 503: Convert the binary code of the first signal code K into a hot code.

Step 504: Determine a position number of the first signal code K and a storage capacitor storing the last data storage of the 2 ^x -1 storage capacitors (that is, a storage capacitor from the beginning of all storage capacitors) Whether it is greater than 2 ^x -1 after the addition; if yes, go to step 505; if not, go to step 506;

Step 505: If the first signal code K is added to the position number of the last storage capacitor storing the data of the 2 ^x -1 storage capacitors and is greater than 2 ^x -1, then from the last one The next storage capacitor storing the storage capacitor of the data begins to store the thermal code of the first signal code K, and when the storage capacitor storing the thermal code of the first signal code K is the last of the 2 ^x -1 storage capacitors At one time, the hot code of the first signal code K is allowed to continue to be stored from the first storage capacitor of the 2 ^x -1 storage capacitors until the hot code corresponding to the first signal code K is stored;

Step 506: If the first signal code K is added to the position number of the last storage capacitor storing the data of the 2 ^x -1 storage capacitors and is less than or equal to 2 ^x -1, then the most The next storage capacitor of the last storage capacitor storing the data starts to store the hot code of the first signal code K;

Step 507: Convert the binary code of the second signal code P into a hot code.

Step 508: Determine the position number of the storage capacitor of the last data code P and the 2 ^y -1 storage capacitors (that is, the storage capacitors from the beginning to the first storage capacitors) Whether it is greater than 2 ^y -1 after the addition; if yes, step 509 is performed; if not, step 510 is performed;

Step 509: If the second signal code P is added to the position number of the last storage capacitor storing the data of the 2 ^y -1 storage capacitors, and is greater than 2 ^y -1, then from the last one The next storage capacitor storing the storage capacitor of the data starts to store the thermal code of the second signal code P, and when the storage capacitor storing the thermal code of the second signal code P is the last of the 2 ^y -1 storage capacitors One time, allowing to continue to store the thermal code of the second signal code P from the first storage capacitor of the 2 ^y -1 storage capacitors until the hot code corresponding to the second signal code P is stored;

Step 510: If the second signal code P is added to the position number of the last storage capacitor storing the data of the 2 ^y -1 storage capacitors, and is less than or equal to 2 ^y -1, then the most The next storage capacitor of the last storage capacitor storing the data starts to store the thermal code of the second signal code P;

Step 511: Determine whether the system receives the signal code N of the next digital control signal that is output by feedback; if yes, execute step 501; if not, end.

In the method described in the above embodiments, the steps are numbered for convenience of description, but this does not mean that the entire method flow needs to be sequentially performed in the stated order, for example, step 503 and step 507 may be combined into one step, or It is said that the two steps can be performed simultaneously; for example, step 504 and step 503 can be interchanged, and steps 508 and 507 can also be interchanged. Those skilled in the art will appreciate that other variable schemes are also possible and will not be described herein.

In another embodiment, the step 502 of splitting the signal code N into the first signal code K and the second signal code P shown in FIG. 7 further includes: The number N is split into a truth value representation table of the first signal code K and the second signal code P, as shown in Table 2.

Table II

Referring to Table 2, in an embodiment of the present application, the digital signal splitting unit 401 splits the signal code N of the digital control signal with a bit number z=4 outputted by the analog-to-digital signal conversion system 300 into one. The first signal code K of the bit number x=3 and the second signal code P of one bit number y=2, the possible binary code true value representing the expression. In the embodiment, two different signal splitting modes, Expr=0 and Expr=1, are provided, which allows the user to input the Expr value and select one of the signal splitting modes to execute, or not to input the Expr value. Let the system choose the better signal splitting method. It can be observed from the binary code truth value shown in Table 2. In the signal splitting mode of Expr=0, the second signal code P with the bit number y=2 uses only one bit number (O11) to store the letter. The number, while the other number of bits (O10) seems to have not been used in this embodiment. In contrast, in the signal splitting mode of Expr=1, the second signal code P of the bit number y=2 is used to register the signal code by two bit numbers (O10 and O11). The signal splitting mode shown in this embodiment is only an example. It is not limited to the above two signal splitting methods. In addition, according to the foregoing description and illustration, we can use a series logic gate (AND gate, AND), reverse series logic gate (NAND gate, ND), parallel logic gate (or gate, OR), reverse Parallel logic gate (NOR gate, NR), mutually exclusive parallel logic gate (exclusive OR gate, XOR, Exclusive-OR), reverse logic gate (NAND gate, INV), delay flip-flop (D flip-flop, or delay) The flip-flop D-Flip-flop is combined with a logical operation unit such as a data selector (multiplexer, MUX) to form a digital signal splitting unit 401.

FIG. 8 is a schematic structural diagram of a digital signal splitting unit 401a according to an embodiment of the present invention. As shown in FIG. 8, the digital signal splitting unit 401a used in the present embodiment can be reverse Logic gate 601, Any of the components of the reverse series logic gate 602 and the reverse parallel logic gate 603 are combined. Please refer to Table 2 at the same time. There is an expression (EXPR) input above the left input terminal 604 of FIG. 8. As described above, the user can input the Expr value and select a preset signal splitting method to remove. Divided into digital signal code N. There are 4 input terminals of I0, I1, I2 and I3 below, and the binary value codes of the signal code N with the number of bits shown in Table 2 can be input respectively, and then the operation is performed by the internal logic gate to split the letter. number. In the right output end 605 of FIG. 8, there are five output terminals of O10, O11, O20, O21 and O22, wherein the output of O20, O21 and O22 is the signal code K of the number of bits after the signal splitting, and The output code of O10 and O11 is the signal code P with the number of bits after the signal is split. In Figure 8, there are 5 reverse logic gates, 9 reverse series logic gates, and 3 reverse parallel logic gates. However, the number and configuration relationship shown in the figure are only examples, and are not limited to this case. Only the digital signal splitting unit 401a of Fig. 8 can be used without other better choices.

FIG. 9 is a schematic structural diagram of a digital signal splitting unit 401b according to another embodiment of the present invention. As shown in FIG. 9, the digital signal splitting unit 401b used in the present embodiment can be combined by any one of the reverse logic gate 701, the reverse series logic gate 702, and the reverse parallel logic gate 703. Please also refer to Table 3, there is an expression (EXPR) input above the left input 704 of Figure 9. As described above, the user can input the Expr value and select a preset signal splitting method to remove. Divided into digital signal code N. There are 5 input terminals I0, I1, I2, I3 and I4 below, which can input the binary value code of the signal code N with the number of bits 5 shown in Table 3, and then operate by its internal logic gate. Split the signal code. In the right output end 705 of FIG. 9, there are 6 output terminals O10, O11, O20, O21, O22 and O23, wherein the signals output by O20, O21, O22 and O23 are 4 after the signal split. The number K, and the output of O10 and O11 is the signal code P of which the number of bits after the signal split is 2. In Figure 9, there are 8 reverse logic gates, 12 reverse series logic gates, and 5 reverse parallel logic gates. However, the number and configuration relationship shown in the figure are only examples, and are not limited to this case. Only the digital signal splitting unit 401b of Fig. 9 can be used without other better choices.

Table 3

Please continue to refer to Table 4 for a statistical comparison of the number of system components required to perform the data weighted averaging algorithm for the analog-to-digital conversion systems with known number of

bits

2, 3, 4, and 5, respectively, presented in the left half of the table. From the statistics below the chart, we can see that the number of hardware system components required by the known data weighted average algorithm system will increase rapidly as the number of processed data bits or the square of the order increases. As we have described above, the area of the semiconductor chip is consumed in a large amount to increase the cost, and the power consumed by the system is rapidly increased to lower the overall efficiency.

Table 4

In contrast, the two embodiments of the present application are shown in the right half of Table 4, showing the statistics of the number of hardware system components required to perform the split data weighted averaging algorithm. One is that the digital signal splitting unit 401a shown in FIG. 8 splits the signal code N of the digital control signal of one bit number z=4 fed back by the analog-to-digital signal conversion system into a bit number x=3. a signal code K and a second signal code P of a bit number y=2; the second is a bit number z=5 of the digital signal splitting unit 401b outputted by the analog signal conversion system as shown in FIG. The signal code N of the digital control signal is split into a first signal code K of one bit number x=4 and a second signal code P of one bit number y=2. In other words, the storage capacitor selection method with one bit number x=3 and one bit number y=2 replaces the storage capacitor selection method with one bit number z=4, and the storage capacitor selection method with one bit number x=4 and one The storage capacitor selection method of the number of bits y=2 replaces the storage capacitor selection mode of one bit number z=5, thereby counting the number of hardware system components required for data weighted average calculation. Comparing the statistics below the chart, we can see that although the alternatives of the above two embodiments will locally increase the number of components used by the hardware system by using the digital signal splitting unit, the number of bits replaced with the number z Comparing the storage capacitance of =4 with the system of storage capacitors with the number of bits z=5, it is still possible to save a large number of components used due to the degradation and splitting of the number of bits of the signal code, wherein the data weighted average of the number of bits z=4 An alternative to the algorithmic system can reduce the number of components by 18.5% ((189-153)/189*100%), while the alternative to a storage capacitor system with a bit count of z=5 can reduce the number of components by up to 31.2% (( 378-256)/378*100%), it is clear that higher-order alternatives can show the value of the technology requested in this application.

In the above embodiment of the system for replacing the storage capacitor of the number of bits z=5 with a data weighted average algorithm system of a storage capacitor system of one bit number x=4 and a storage capacitor of one bit number y=2, we try to change A system of storage capacitors with a number of bits x=3 and a system of storage capacitors with another number of bits y=3 replaces the system of storage capacitors with a number of bits z=5. However, in the process of performing its signal code value and its binary code conversion, it can be found that two storage capacitor systems with 3 bits only have 2*(2 ³ -1)+(2 ³ -1)=21 storage capacitors, low. A storage capacitor system with a bit number of 5 has (2 ⁵ -1) = 31 storage capacitors, so a system with two storage capacitors of 3 bits cannot replace a system with a storage capacitor of 5 bits. It is inferred that when we try to replace the system of storage capacitors with a bit number z=M with a system of storage capacitors with a bit number x=I and a storage capacitor with a bit number y=J, I and J are A positive integer less than M, and must satisfy a relation [2*(2 ^I -1)+(2 ^J -1)]≧(2 ^M -1), which is also used to verify the signal code splitting in this application. The conditions of the alternative. Therefore, from the above embodiment, we obtain an analog-to-digital signal conversion system of the present application, in which the number of bits I, J and M conforms to the relationship I + J = M + 1 is the most efficient.

The above embodiments are only used to explain the technical solutions of the present application, and are not limited thereto; although the applicant has explained the present application in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still implement the foregoing embodiments. The technical solutions described in the examples are modified, or the equivalents of the technical features are replaced by the equivalents of the technical solutions of the embodiments of the present application. Thus, the present application also includes such modified or alternative embodiments.

Claims

An analog-to-digital signal conversion system, comprising:

a digital signal splitting unit that splits the signal code N of the digital control signal represented by the bit number z fed back by the analog-to-digital signal conversion system into the first signal code K expressed by the number of bits x and the number of bits The second signal codes P, N, K, P, x, y, and z represented by y are positive integers, where N=2K+P, x+y=z+1, y is at least 2, and [2* (2 x -1)+(2 y -1)]≧(2 z -1);

a first digital signal storage unit, comprising 2 x -1 storage capacitors for sequentially storing the first signal code K;

a second digital signal storage unit, comprising 2 y -1 storage capacitors for sequentially storing the second signal code P;

a first storage capacitor selection unit that selects a first signal code K for storing the first signal code K according to a first signal code K and a position number of a storage capacitor storing the last data stored in the first digital signal storage unit. Storage capacitor; and

a second storage capacitor selection unit, configured to store the second signal code P according to a second signal code P and a position number of a storage capacitor storing the last data storage unit in the second digital signal storage unit Storage capacitor.
The analog-to-digital signal conversion system according to claim 1, wherein said binary code of said first signal code K is converted into a thermal code, said first signal code K and said 2 x -1 storage capacitors The position number of the last storage capacitor storing the data is added to be greater than 2 x -1, and the first digital signal storage unit stores the data from the last one of the 2 x -1 storage capacitors. The next storage capacitor of the capacitor begins to store the thermal code of the first signal code K, and the storage capacitor of the thermal code storing the first signal code K has been the last one of the 2 x -1 storage capacitors And continuing to store the hot code of the first signal code K from the first storage capacitor of the 2 x -1 storage capacitor; or the binary code of the second signal code P is converted into a hot code, when The second signal code P is added to the position number of the last storage capacitor storing the data of the 2 y -1 storage capacitors to be greater than 2 y -1, and the second digital signal storage unit is a last time said 2 y -1 stored a storage capacitance of the storage capacitor has a data Storing the heat storage capacitor begins a second channel code number P and the last has a heat storage capacitor when the second code stored channel number P 2 y -1 is the storage capacitance, and then from The first storage capacitor of the 2 y -1 storage capacitors continues to store the thermal code of the second signal code P.
The analog-to-digital signal conversion system according to claim 2, wherein said first signal code K is added to a position number of a storage capacitor of said last stored data of said 2 x -1 storage capacitors After the second digital signal storage unit is less than or equal to 2 x -1, the first digital signal storage unit stores the first letter from a storage capacitor of the last storage capacitor storing the data of the 2 x -1 storage capacitors a hot code of the number K; or, when the second signal code P is added to the position number of the last storage capacitor storing the data of the 2 y -1 storage capacitors, less than or equal to 2 y -1, Then, the second digital signal storage unit stores the thermal code of the second signal code P from a storage capacitor of the last storage capacitor storing the data of the 2 y -1 storage capacitors.
The analog-to-digital signal conversion system according to claim 1, wherein the first storage capacitor selection unit comprises:

a first adder unit, receiving the first signal code K;

a first data buffer unit that receives and delays a previous signal code output by the first adder unit, and feeds back the previous signal code output back to the first adder unit, the first addition The unit unit adds the previous signal code output by the first data buffer unit to the first signal code K, and outputs the result as a subsequent signal code;

a first post-binary code transcoding unit, receiving the latter signal code output by the first adder unit, converting the latter signal code into a subsequent thermal code;

a first pre-binary code to hot code unit, receiving the previous signal code output by the first data buffer unit, converting the previous signal code into a previous hot code;

a first control unit, comprising: a first comparator for receiving the comparison of the latter thermal code with the previous thermal code, and a first data selector for comparing the result of the first comparator with the first comparator The received latter thermal code is selected to open the storage capacitor circuit of the first digital signal storage unit, and sequentially store the converted thermal code of the first signal code K.
The analog-to-digital signal conversion system according to claim 1, wherein the second storage capacitor selection unit comprises:

a second adder unit, receiving the second signal code P;

a second data buffer unit that receives and delays a previous signal code output by the second adder unit, and feeds back the previous signal code output back to the second adder unit, the second addition The unit unit adds the previous signal code output by the second data buffer unit and the second signal code P, and outputs the result as a subsequent signal code;

a second post-binary code to hot code unit, receiving the latter signal code output by the second adder unit, converting the latter signal code into a subsequent thermal code;

a second pre-binary code transcoding unit, receiving the previous signal code output by the second data buffer unit, converting the previous signal code into a previous thermal code;

a second control unit, comprising: a second comparator for receiving the comparison of the latter thermal code with the previous thermal code, and a second data selector for comparing the comparison result of the second comparator with the second comparator The received latter thermal code is selected to open the storage capacitor circuit of the second digital signal storage unit, and sequentially store the converted thermal code of the second signal code P.
The analog-to-digital signal conversion system of claim 1 wherein z is at least four.
The analog-to-digital signal conversion system according to claim 1, further comprising a memory bank storing a truth value representation table including two or more different signal splitting modes for using the signal code N Splitting into the first signal code K and the second signal code P.
The analog-to-digital signal conversion system according to claim 1, wherein said x is 3, said y is 2, and said z is 4.
The analog-to-digital signal conversion system according to claim 1, wherein said x is 4, said y is 2, and said z is 5.
The analog-to-digital signal conversion system of claim 1 wherein said digital signal splitting unit comprises one of a reverse logic gate, an inverse series logic gate, an inverse parallel logic gate, or any combination thereof.
The analog-to-digital signal conversion system of claim 1 wherein said analog to digital signal conversion system is a delta-sigma modulator.
An analog-to-digital signal conversion method, comprising:

Receiving a digital control signal outputted by feedback, the signal code N of the digital control signal is represented by a bit number z;

Splitting the signal code N into a first signal code K and a second signal code P, the first signal code K is represented by the number of bits x and the second signal code is represented by the number of bits y, N, K , P, x, y, z are positive integers, N = 2K + P, x + y = z + 1, y is at least 2, [2 * (2 x -1) + (2 y -1)] (2 z -1);

Selecting a storage capacitor for storing the first signal code K according to a calculation result of a position number of the first signal code K and a storage capacitor of the last one storing data of 2 x -1 storage capacitors; and

The storage capacitor for storing the second signal code P is selected based on a result of the operation of the position number of the storage capacitor of the last data code P and 2 y -1 storage capacitors.
The analog-to-digital signal conversion method according to claim 12, wherein the binary code of the first signal code K is converted into a thermal code, if the first signal code K and the 2 x -1 storage The position number of the last storage capacitor storing the data is greater than 2 x -1, and the next storage capacitor of the storage capacitor storing the data is stored from the last 2 x -1 storage capacitor. And storing a thermal code of the first signal code K, and when the storage capacitor storing the thermal code of the first signal code K has been the last one of the 2 x -1 storage capacitors, allowing to proceed from the The first storage capacitor of 2 x -1 storage capacitors continues to store the thermal code of the first signal code K; or converts the binary code of the second signal code P into a thermal code, if the second letter The number P is added to the position number of the last storage capacitor storing the data of the 2 y -1 storage capacitors, and is greater than 2 y -1, and the last storage from the 2 y -1 storage capacitors The next storage capacitor of the storage capacitor having data begins to store the thermal code of the second signal code P, and When the storage capacitor storing the thermal code of the second signal code P is already the last one of the 2 y -1 storage capacitors, allowing the first storage capacitor from the 2 y -1 storage capacitors The hot code of the second signal code P is continued to be stored.
The analog-to-digital signal conversion method according to claim 13, wherein if said first signal code K is added to a position number of a storage capacitor of said last stored data of said 2 x -1 storage capacitors After being less than or equal to 2 x -1, storing the hot code of the first signal code K from a storage capacitor of the last storage capacitor storing the data of the 2 x -1 storage capacitor; or If the second signal code P is added to the position number of the last storage capacitor storing the data of the 2 y -1 storage capacitors and is less than or equal to 2 y -1, then from the 2 y -1 The next storage capacitor of the last storage capacitor storing the data begins to store the thermal code of the second signal code P.
The analog-to-digital signal conversion method according to claim 12, wherein z is at least 4.
The analog-to-digital signal conversion method according to claim 12, wherein the step of splitting the signal code N into the first signal code K and the second signal code P further comprises: The signal code N is split into a truth value representation table of the first signal code K and the second signal code P.
The analog-digital signal conversion method according to claim 12, wherein said x is 3, said y is 2, and said z is 4.
The analog-digital signal conversion method according to claim 12, wherein said x is 4, said y is 2, and said z is 5.
The analog-to-digital signal conversion method according to claim 12, wherein the step of splitting the signal code N into the first signal code K and the second signal code P utilizes reverse logic One of the gate, the reverse series logic gate, and the reverse parallel logic gate or any combination thereof.
The analog-to-digital signal conversion method according to claim 12, wherein said analog-digital signal conversion method is used for a delta-sigma modulator.