WO2019066876A1

WO2019066876A1 - An apparatus with a noise absorber

Info

Publication number: WO2019066876A1
Application number: PCT/US2017/054165
Authority: WO
Inventors: Shaowu Huang; Beom-Taek Lee; Xiaoning Ye; Kai Xiao
Original assignee: Intel Corporation
Priority date: 2017-09-28
Filing date: 2017-09-28
Publication date: 2019-04-04

Abstract

Embodiments of the present disclosure provide an apparatus with an electric noise absorber. The apparatus may comprise, for example, a PCB or semiconductor package. In embodiments, the apparatus may include a power plane disposed in a layer of a plurality of layers of the apparatus, to provide delivery of power to components of the apparatus. The apparatus may further include at least one via that extends through at least some of the plurality of layers of the apparatus, including the layer with the power plane. The apparatus may also include at least one absorber component disposed through the plurality of layers of the apparatus, adjacent to or inside the power plane. The absorber component may be filled with an absorbing material, to mitigate electric noise generated by the via or the power plane. Other embodiments may be described and/or claimed.

Description

AN APPARATUS WITH A NOISE ABSORBER

Field

Embodiments of the present disclosure generally relate to the field of printed circuit board fabrication and in particular to techniques for mitigation of noise and crosstalk in a printed circuit board.

Background

Currently, computer products, such as printed circuit boards (PCB) or

semiconductor packages may be required to accommodate high density design, due to demands provided by high performance computing (HPC), communications, cloud computing, and storage. Due to design requirements, power integrity (PI), signal integrity (SI), electromagnetic interference or electromagnetic compatibility (EMI/EMC) issues (e.g., power supply noise or crosstalk) may arise in PCB-based computer system designs. For example, cavity resonant effects of power delivery network (PDN) planes in PCB may amplify the power noise, aggravate the EMI emissions, and/or boost crosstalk and SI/PI couplings.

Brief Description of the Drawings

Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example and not by way of limitation in the figures of the accompanying drawings.

FIG. 1 is a schematic diagram of an example apparatus with an electric noise absorber, in accordance with some embodiments.

FIGS. 2-3 illustrate an example embodiment of a portion of the apparatus with a noise absorber, in accordance with some embodiments.

FIGS. 4-6 illustrate example embodiments of a portion of the apparatus with a noise absorber, in accordance with some embodiments.

FIGS. 7-9 illustrate another example embodiment of a portion of the apparatus with a noise absorber, in accordance with some embodiments.

FIG. 10 illustrates a blown up top view of the portion of the apparatus of FIGS. 7-

9, in accordance with some embodiments.

FIGS. 11-12 illustrate example embodiments of a portion of an apparatus with a noise absorber, in accordance with some embodiments. FIG. 13 is an example process flow diagram for providing an apparatus with a noise absorber, in accordance with some embodiments.

FIG. 14 is an example process flow diagram for providing a PCB with a noise absorber, in accordance with some embodiments.

FIG. 15 illustrates an example computing device that may employ the apparatuses and/or methods described herein, in accordance with some embodiments.

Detailed Description

Embodiments of the present disclosure include techniques and configurations for an electronic apparatus with an electric noise absorber. The apparatus may comprise, for example, a PCB or semiconductor package. In embodiments, the apparatus may include a power plane disposed in a layer of a plurality of layers of the apparatus, to provide delivery of power to components of the apparatus. The apparatus may further include at least one via that extends through at least some of the plurality of layers of the apparatus, including the layer with the power plane. The apparatus may also include at least one absorber component disposed through the plurality of layers of the apparatus, adjacent to or inside the power plane. The absorber component may be filled with an absorbing material, to mitigate electric noise generated by the via or the power plane.

In the following detailed description, reference is made to the accompanying drawings that form a part hereof, wherein like numerals designate like parts throughout, and in which are shown by way of illustration embodiments in which the subject matter of the present disclosure may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense, and the scope of embodiments is defined by the appended claims and their equivalents.

For the purposes of the present disclosure, the phrase "A and/or B" means (A), (B), (A) or (B), or (A and B). For the purposes of the present disclosure, the phrase "A, B, and/or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).

The description may use perspective-based descriptions such as top/bottom, in/out, over/under, and the like. Such descriptions are merely used to facilitate the discussion and are not intended to restrict the application of embodiments described herein to any particular orientation.

The description may use the phrases "in an embodiment" or "in embodiments," which may each refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," and the like, as used with respect to embodiments of the present disclosure, are synonymous.

The term "coupled with," along with its derivatives, may be used herein.

"Coupled" may mean one or more of the following. "Coupled" may mean that two or more elements are in direct physical, electrical, or optical contact. However, "coupled" may also mean that two or more elements indirectly contact each other, but yet still cooperate or interact with each other, and may mean that one or more other elements are coupled or connected between the elements that are said to be coupled with each other. The term "directly coupled" may mean that two or more elements are in direct contact.

FIG. 1 is a schematic diagram of an example apparatus with an electric noise absorber, in accordance with some embodiments. In embodiments, the apparatus 100 may comprise, for example, a PCB or semiconductor package.

In embodiments, the apparatus 100 may comprise a multilayered structure. For example, the apparatus 100 may comprise a PCB, which may be compiled by stacking multiple layers 104, 106, 108 on a substrate. Three layers are shown in FIG. 1 for ease of explanation, although the apparatus 100 may include any number of layers, depending on design characteristics. Some of the layers may be may be used to route electric signals between the components 110 disposed on (or coupled with) the apparatus 100. In general, different components may be disposed on the apparatus 100, implemented, for example, as a PCB. Some of these components may comprise integrated circuits (IC), and others may comprise discrete components of different types, such as capacitors, inductors, resistors, or other types of electric components.

In embodiments, the apparatus 100 may include a power supply unit 112, to provide power to various components 110 of the apparatus 100. The power supply unit 112 may be implemented in a number of different ways, for example, as power supply circuitry provided on-chip or otherwise coupled with the apparatus 100 (e.g., a PCB).

In embodiments, the apparatus 100 may include a signal source 112, to provide electronic communications between the components of the apparatus 100 and/or between the apparatus 100 and other electronic devices (not shown). The signal source 112 may comprise a number of components capable of generate signals, e.g., data or control signals. For example, the signal source 112 may comprise a processor implemented in an integrated circuit, which may be coupled with a PCB comprising the apparatus 100. In another example, the signal source 112 may comprise a processor implemented in an integrated circuit as a part of a package comprising the apparatus 100. To route power supply and communication signals throughout the apparatus 100, various electric interconnect structures may be employed in the apparatus 100. For example, a power delivery network (PDN) may be provided in the apparatus 100, to provide delivery of power from the power supply unit 1 12 to the components 1 10. In embodiments, the PDN may be implemented as a power plane 116 disposed in the layer 104. In some embodiments, the power plane 1 16 may be embedded in the layer 104. In some embodiments, the power plane 1 16 may be disposed on a ground plane (layer), e.g., 106. In some embodiments, the power plane 1 16 may be disposed on a dielectric layer (e.g., 106), which may be disposed on a ground layer (plane, e.g., 108).

The power and signal routing in the apparatus 100 may be further provided by interconnects. In embodiments, such interconnects may comprise a combination of pads, solder balls, traces, and/or vias provided in the apparatus 100, to deliver power and/or signals to the components 1 10. For example, some vias (e.g., signal via 1 18) may provide signal routing through at least some of the layers 104, 106, 108 of the apparatus 100. Some vias, (e.g., power via 120) may provide power to various components of the apparatus 100. Some vias (e.g., ground vias, not shown) may provide grounding for various components of the apparatus 100.

In embodiments, the vias may include blind vias, e.g., vias that may begin on a top, or bottom surface of the apparatus 100 (e.g., PCB), and may end inside the PCB. In some embodiments, the vias may include through hole vias, e.g., they may be provided through all the layers of the apparatus 100. The vias may be provided in accordance with conventional methods, such as by drilling or using other laser or mechanical processes. In embodiments, the vias may be plated, to provide electrical connectivity as described below.

In embodiments, vias, particularly ones disposed adj acent to each other, may cause undesirable effects, such as crosstalk. Further, as described above, cavity resonant effects of power planes (e.g., 1 16) in PCB or semiconductor package may amplify the power noise, aggravate the EMI emissions, and/or boost crosstalk.

Conventional solutions aimed at suppressing power supply noises may involve using decoupling capacitors in the PCB structure. However, there are some restrictions associated with the decoupling solutions. For example, the bandwidth of a single decoupling capacitor may be narrow. In order to achieve broadband suppression of PDN noise, complicated multiple decoupling capacitors may be needed. This may not only increase the cost but also take more board space. Further, the parasitic series inductance and resistance of decoupling capacitors may have negative effects on the PDN impedance.

Conventional solutions may also involve metal enclosure shielding for EMI control. Applying metal enclosures on a chassis or components can shield off radiated field emissions, most of which may come from the PCB and package edge. However, metal enclosures may have several limitations. For example, they may only mitigate the external radiation issues, not a solution for suppression of the power/ground noise.

Further, metal enclosures may impose mechanical restrictions for placing external enclosures. Also, metal components such as heat sink may act as antenna structures and become sources of radiated emissions. Yet further, metal enclosures may be not helpful for the open-chassis requirements in EMC testing.

Conventional solutions may also involve stitching vias in the PCB. However, because the stitching ground vias are disconnected from the power plane, they may create discontinuities in the power planes. The discontinuities may convert the surface field (current) on the stitching ground vias into scattering cylindrical waves. This may prevent stitching ground vias from effectively suppressing the PDN resonances.

According to the embodiments of present disclosure, an electrical noise absorber component 122 (hereinafter, a noise absorber component or noise absorber) may disposed through the plurality of layers of the apparatus 100, e.g., "through hole." As further described below, the noise absorber component 122 may be disposed adjacent to or inside the power plane 116. The noise absorber component 122 may be filled with an absorbing material, to mitigate noise generated by the vias (e.g., 118 and/or 120) disposed in the apparatus 100 or the power plane 116. The noise absorber component may comprise different shapes, such as through holes, slots or slices of various geometric shapes (e.g., rectangular), or other shape types.

Different kinds of epoxy-like absorbing materials may be used in the noise absorber component 122. For example, absorbing materials of Cuming Microwave Corporation®, such C-RAM MT-30 or sprayable or castable absorbers of 340 or 330 series may be used. In another example, ARC Technologies® ML-73, or Kitagawa Industries® MG-10A may be used as absorbing materials for the noise absorber component 122.

Provision of a through hole noise absorber component filled with absorbing materials may substantially mitigate the power supply noise, crosstalk and EMI/EMC problems in computer system designs, such as in PCB or semiconductor packages. In some embodiments, the noise absorber component according the embodiments of the present disclosure may be provided on-chip for power noise suppression. While on- chip PDN may have a grid structure, which may be different from the plane structures of on-board or on-package PDN, the principles of implementation of the noise absorber component on-chip may be the same. Absorbing material may be integrated onto on-chip PDN to suppress the power noise.

In some embodiments, the noise absorber component according the embodiments of the present disclosure may be provided to mitigate the crosstalk between through silicon vias (TSV). For example, a noise absorber component (e.g., in a shape of a via) may be placed between two TSV to suppress the crosstalk.

The noise absorber component according to the embodiments of this disclosure may provide for the noise suppression for entire power planes (for packages and PCBs) or grids (for chips), due to attenuation of the energy of the resonant modes by the absorbing material. For example, absorbing vias may be placed at the ends of the power plane (as described in detail below), to suppress the noise for entire power plane.

FIGS. 2-3 illustrate an example embodiment of a portion of the apparatus with a noise absorber, in accordance with some embodiments. More specifically, FIG. 2 illustrates a perspective view of a portion of the apparatus 100 of FIG. 1 including a power plane with a noise absorber component. FIG. 3 illustrates a top view of the power plane of FIG. 2, showing a the noise absorber component in more detail.

As shown, the power plane 202 of the apparatus 100 may be disposed on top of a ground plane 204. The power plane 202 may include one or more vias, e.g., ground, power, or signal vias 206 provided through the power plane 202 in the apparatus 100 of FIG. 1 (e.g., a PCB). As shown, the power plane 202 may have an elongated, substantially rectangular shape. In embodiments, the apparatus 100 may include a noise absorber component 210. The noise absorber component 210 may comprise a plurality of through hole absorber vias 208 filled with an absorbing materials and disposed as shown in FIGS. 2-3.

More specifically, absorber vias 208 may be disposed adjacent to the power plane 202, for example, in rows at the ends of the power plane 202, away from noise sources (e.g., signal vias), and along the edges 212 and 214 of the power plane 202, to form the noise absorber component 210. As shown, the through hole absorber vias 208 may have a circular shape. However, the absorber vias 208 may have different shapes, e.g., oval, square, rectangular, or the like. The noise absorber component 210, comprising multiple through hole absorber vias 208 may be created by drilling through holes in the apparatus 100 (e.g., PCB) and filling the hole with absorbing materials.

FIGS. 4-6 illustrate example embodiments of a portion of the apparatus with a noise absorber, in accordance with some embodiments. More specifically, FIGS. 4-5 illustrate perspective views of a portion of the apparatus of FIG. 1 including a power plane with a noise absorber component. FIG. 6 illustrates a top view of the power plane of FIGS. 4-5, showing the noise absorber component in more detail. As shown in FIGS. 4-6, a power plane 402 may be disposed on a ground plane 404 of the apparatus 100. The power plane 402 may include one or more vias, e.g., ground, power, or signal vias 406 provided through the power plane 402 in the apparatus 100 of FIG. 1 (e.g., a PCB). As shown, the power plane 402 may have an elongated, substantially rectangular shape.

In embodiments, a noise absorber component may be provided in the apparatus with the power plane 402. As shown in FIG. 4, the noise absorber component may comprise substantially rectangular slots (slices) 412, 414, disposed adjacent to the power plane 402, e.g., along respective ends (edges 416 and 418) of the power plane 402. As shown in FIG. 5, the noise absorber component may further comprise substantially rectangular slots (slices) 502, 504 disposed along the sides 506, 508 of the power plane 402, in addition to the slots 412, 414. While slots 412, 414, 502, 504 are shown as having substantially rectangular shapes, any other appropriate shapes may be applied to provide the slots or slices.

In embodiments, the noise absorber component 210 may be provided by drilling through hole slots 412, 414, 502, 504 in the apparatus 100 (e.g., PCB), and filling the slots with absorbing materials.

As shown in FIGS. 2-6, the noise absorber component may be located adjacent to the power plane, for example, along the edge (or edges) of the power plane. For example, the noise absorber component may be disposed inside or at the boundary of a PCB. The noise absorber component may absorb the electromagnetic energy of standing waves that are associated with the PDN resonances, providing an effective solution for mitigation of power noise, EMI, and crosstalk.

FIGS. 7-9 illustrate another example embodiment of a portion of the apparatus with a noise absorber, in accordance with some embodiments. More specifically, FIG. 7 illustrates a portion of the apparatus 100 (e.g., a PCB) seen from the front (indicated by letter A in FIG. 9). FIG. 8 illustrates the portion of the apparatus of FIG. 1 seen from the left side (indicated by letter B in FIG. 9). FIG. 9 illustrates a top view of portion of the apparatus 100.

The portion of the apparatus 100 illustrated in FIGS. 7-9 includes ground planes 702 and 704, coupled with a dielectric layer 706. A power plane 708 may be embedded in the dielectric layer 706, between the ground planes 702 and 704 as shown. For ease of explanation, the power plane 708 is exposed in FIG. 9, in order to highlight the power plane 708.

The apparatus 100 may further include one or more signal vias 710 (FIGS. 7 and 9) provided through the planes 702, 704, a dielectric layer 706, and power plane 708. The apparatus 100 may further include one or more ground vias 712 (FIGS. 8 and 9) provided through the planes 702, 704, a dielectric layer 706, and power plane 708. For ease of understanding, the apparatus 100 is shown as having the layers (planes) described above. However, in various implementations, the apparatus 100 (e.g., a PCB) may include different numbers of layers, for example, between 6 and 24 layers. The signal and power vias 710 and 712 may travel through multiple power and ground planes of the apparatus 100.

In embodiments, the apparatus 100 may include a noise absorber component, which may comprise multiple through hole absorber vias filled with an absorbing materials and disposed inside the power plane 708, adjacent to signal via 710 or power via 712. For example, through hole absorber vias 714 and 716 may be disposed adjacent to, and at either side of, via 710. The absorber vias 714 and 718 may be disposed adjacent to, and at either side of, via 712.

In general, the disposition of the absorber vias comprising the noise absorber component relative to signal or power vias (e.g., distance between the power or signal vias and absorber vias) may vary, depending on space availability and technological demands to the apparatus 100. A number of ground and power vias, as well as a number and disposition of absorber vias are provided in FIGS. 7-9 for purposes of explanation and do not limit this disclosure.

FIG. 10 illustrates a blown up top view of the portion of the apparatus of FIGS. 7- 9, in accordance with some embodiments. For ease of understanding, like components are indicated by like numerals. As shown, absorber vias 710 and 716 may be placed inside a power plane 708, adjacent to the signal via 710. Absorber vias 718 and 1004 may be placed inside the power plane 708, adjacent to a signal via 1002. Similarly, absorber vias 718 and 714 may be placed adjacent to the ground via 712, and absorber vias 716 and 1004 may be placed adjacent to the ground via 1006. An absorber via 1008 may be disposed relative to signal vias 710 and 1002, and ground vias 712 and 1006 so as to form an absorber via triangle around each signal or ground visa. For example, the signal via 710 is surrounded by absorber vias 714, 716, and 1008, forming a triangle around the signal via 710.

FIGS. 11-12 illustrate example embodiments of a portion of an apparatus with a noise absorber, in accordance with some embodiments.

As shown in FIG. 11, a noise absorber component 1102 may comprise a plurality of through hole absorber vias 1104 filled with an absorbing material. The absorber vias 1104 may be disposed around a power plane 1106 of the apparatus lOO of FIG. 1 (e.g., PCB or semiconductor package), to form a cage adjacent to and around the power plane 1106. Similar to the earlier described embodiments, the power plane 1106 may be disposed on top of a ground plane 1108.

An shown in FIG. 12, a noise absorber component 1202 may comprise a plurality of slots 1204, 1210, 1212, 1214. The slots 1204, 1210, 1212, 1214 may connected with each other, to surround a power plane 1206 of the apparatus 100 (e.g., PCB or

semiconductor package). Similar to the earlier described embodiments, the power plane 1206 may be disposed on top of a ground plane 1208.

FIG. 13 is an example process flow diagram for providing an apparatus with a noise absorber, in accordance with some embodiments. The process 1300 may comport with embodiments described in reference to FIGS. 1-12. The actions described in the process 1300 may occur in a different order or in parallel. The order provided below is for purposes of illustration and does not limit this disclosure.

The process 1300 may begin at block 1302 and include disposing an absorber component to extend through a plurality of layers of an apparatus, adjacent to or inside a power plane disposed in a layer of the plurality of layers of the apparatus. The power plane may include at least one via extending through at least some of the plurality of layers of the apparatus. The via may comprises one of a signal via to route electric signals from one layer to another layer of the apparatus, or a power via to provide power to a component of the apparatus.

In some embodiments, the noise absorber component may comprise one or more through hole vias. Disposing the absorber component may include: providing the through hole vias adjacent to the via, surrounding the power plane with the through hole vias, or providing the through hole vias to form rows along at least two opposing edges of the power plane.

In some embodiments, the noise absorber component may comprise one or more through slots or slices. Disposing the absorber component may include providing the through slots along respective one or more edges of the power plane.

At block 1304, the process 1300 may include filling the absorber component with absorbing material, to mitigate noise generated by the via or power plane. The absorbing material may include one of: Cuming Microwave Corporation® C-RAM MT-30, Cuming Microwave Corporation® sprayable or castable absorbers of 340 or 330 series, ARC Technologies® ML-73, or Kitagawa Industries® MG-10A.

The process of provision of the apparatus with an electric noise absorber described in reference to FIG. 13 may be applied to standard manufacturing flows of a PCB or semiconductor package, providing minor additions to the flows.

FIG. 14 is an example process flow diagram for providing a PCB with a noise absorber, in accordance with some embodiments. Some of the process actions, such as inner layer imaging and etching (block 1402), lamination of the PCB (block 1404), drilling of necessary through holes etc. (block 1406), and copper plating (block 1408) may be used in a standard PCB manufacturing. In embodiments, the actions of providing an absorber component (e.g., by drilling) and applying absorbing material to the absorber component (blocks 1410 and 1412) may be added to the PCB manufacturing flow. The remaining actions, such as outer layer imaging and etching (block 1414), soldermask application (block 1416), and testing of the PCB (block 1418) may be applied similarly to the standard PCB manufacturing flow.

The semiconductor package manufacturing flow, albeit different than that of the PCB flow, may be modified in a similar manner, to provide a package with a noise absorber in accordance with embodiments described herein.

FIG. 15 illustrates an example computing device 1500 that may employ the apparatuses and/or methods described herein, in accordance with some embodiments.

The motherboard 1502 may include a number of components, including but not limited to a processor 1504 and at least one communication chip 1506. The processor 1504 may be physically and electrically coupled to the motherboard 1502. In some implementations, the communication chip 1506 may also be physically and electrically coupled to the motherboard 1502. In further implementations, the communication chip 606 may be part of the processor 1504. In addition, the computing device 1500 may further include an antenna 1516. In embodiments, the computing device 1500 (e.g., motherboard 1502 or semiconductor packages comprising processor 1504, chip 1506 or other integrated circuit components) may include one or more electric noise absorber components 1590 provided in accordance with embodiments described herein.

Depending on its applications, the computing device 1500 may include other components that may or may not be physically and electrically coupled to the motherboard 1502. Some of these components are shown in FIG. 15 for purposes of explanation. These other components may include, but are not limited to, volatile memory (e.g., dynamic random-access memory (DRAM)) 1508, static random access memory (SRAM) 1509, non- volatile memory (e.g., read-only memory (ROM)) 1510, flash memory 1511, a graphics central processing unit (CPU) 1512, a digital signal processor 1513, a chipset 1514, a display (e.g., a touchscreen display) 1518, a touchscreen controller 1520, a battery 1522, an audio codec, a video codec, a power amplifier (not shown), a global positioning system (GPS) device 1526, a compass 1528, a Geiger counter, an accelerometer, a gyroscope (not shown), a speaker 1530, a camera 1517, and a mass storage device 1532. These components may be included in IC packages, some of which may be disposed on 1502.

The communication chip 1506 may enable wireless communications for the transfer of data to and from the computing device 1500. The communication chip 1506 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.7 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultra mobile broadband (UMB) project (also referred to as "3GPP2"), etc.). IEEE 802.16 compatible broadband wireless access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 802.16 standards.

The communication chip 1506 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 1506 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E- UTRAN). The communication chip 1506 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication chip 1506 may operate in accordance with other wireless protocols in other embodiments.

The computing device 1500 may include a plurality of communication chips 1506. For instance, a first communication chip 1506 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 1506 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, and others.

In various implementations, the computing device 1500 may be a server, a mobile computing device, a laptop, a netbook, a notebook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 800 may be any other electronic device that processes data.

The embodiments described herein may be further illustrated by the following examples.

Example 1 may be an apparatus, comprising: a power plane disposed in a layer of a plurality of layers of the apparatus, to provide delivery of power to components of the apparatus; at least one via that extends through at least some of the plurality of layers of the apparatus, including the layer with the power plane, to provide electric connectivity for the apparatus; and at least one absorber component disposed through the plurality of layers of the apparatus, adjacent to or inside the power plane, wherein the absorber component is filled with absorbing material, to mitigate noise generated by the at least one via or the power plane.

Example 2 may include the apparatus of example 1, wherein the apparatus comprises a printed circuit board (PCB).

Example 3 may include the apparatus of example 1, wherein the apparatus comprises a semiconductor package.

Example 4 may include the apparatus of example 1, wherein the at least one via comprises one of: a signal via to route electric signals from at least one layer to at least another layer of the apparatus, or a power via to provide power to at least one component of the apparatus. Example 5 may include the apparatus of example 1, wherein the absorber component comprises one or more through hole vias.

Example 6 may include the apparatus of example 5, wherein the one or more through hole vias comprise multiple through hole vias disposed adjacent to the at least one via.

Example 7 may include the apparatus of example 5, wherein the one or more through hole vias comprise a plurality of through hole vias disposed in a row along at least one edge of the power plane.

Example 8 may include the apparatus of example 7, wherein the power plane comprises an elongated shape, wherein the at least one edge comprises a first edge defining a first end of the elongated shape, and a second edge defining a second end of the elongated shape, wherein the plurality of through hole vias comprises a first subset of through hole vias disposed in a row along the first edge, and a second subset of through hole vias disposed in a row along the second edge.

Example 9 may include the apparatus of example 7, wherein the plurality of through hole vias is further disposed around the power plane, to form a cage around the power plane.

Example 10 may include the apparatus of example 1 , wherein the at least one absorber component comprises one or more slots disposed along respective one or more edges of the power plane.

Example 11 may include the apparatus of example 10, wherein the power plane comprises an elongated shape, wherein the one or more edges comprise a first edge defining a first end of the elongated shape, and a second edge defining a second end of the elongated shape, wherein the one or more slots comprises a first slot disposed along the first edge, and a second slot disposed along the second edge.

Example 12 may include the apparatus of example 10, wherein the one or more slots comprise a plurality of slots that are connected with each other, to surround the power plane.

Example 13 may include the apparatus of any examples 1 to 12, wherein the apparatus comprises a computing device.

Example 14 may include the apparatus of any examples 1 to 12, wherein the absorbing material comprises one of: Cuming Microwave Corporation® C-RAM MT-30, Cuming Microwave Corporation® sprayable or castable absorbers of 340 or 330 series, ARC Technologies® ML-73, or Kitagawa Industries® MG-10A. Example 15 may be a computer system, comprising: a printed circuit board (PCB) having a plurality of layers; a power plane disposed in a layer of the plurality of layers, to provide delivery of power to components of the PCB; at least one via that extends through at least some of the plurality of layers of the PCB, including the layer with the power plane, to provide electric connectivity for the PCB; and at least one absorber component disposed through the plurality of layers of the PCB, adjacent to or inside the power plane, wherein the absorber component is filled with absorbing material, to mitigate signal noise generated by the at least one via or the power plane.

Example 16 may include the computer system of example 15, wherein the at least one via comprises one of: a signal via to route electric signals from at least one layer to at least another layer of the apparatus, or a power via to provide power to at least one component of the apparatus.

Example 17 may include the computer system of example 15, wherein the absorber component comprises one or more through hole vias, disposed adjacent to the at least one via, or disposed in rows along at least two opposing edges of the power plane.

Example 18 may include the computer system of any examples 15 to 17, wherein the absorber component comprises one or more through slots disposed along respective one or more edges of the power plane.

Example 19 may be a method, comprising: disposing at least one absorber component to extend through a plurality of layers of an apparatus, adjacent to or inside a power plane disposed in a layer of the plurality of layers of the apparatus, wherein the power plane includes at least one via extending through at least some of the plurality of layers of the apparatus; and filling the at least one absorber component with absorbing material, to mitigate noise generated by the at least one via or the power plane.

Example 20 may include the method of example 19, wherein the at least one absorber component comprises one or more through hole vias, wherein disposing at least one absorber component includes: providing the one or more through hole vias adjacent to the at least one via, surrounding the power plane with the one or more through hole vias, or providing the one or more through hole vias to form rows along at least two opposing edges of the power plane.

Example 21 may include the method of example 19, wherein the absorber component comprises one or more through slots, wherein disposing at least one absorber component includes providing the one or more through slots along respective one or more edges of the power plane. Example 22 may include the method of example 19, wherein the apparatus comprises a semiconductor package or a printed circuit board (PCB).

Example 23 may include the method of any examples 19 to 22, wherein filling the at least one absorber component with an absorbing material includes applying to the absorber component at least one of: Cuming Microwave Corporation® C-RAM MT-30, ARC Technologies® ML-73, or Kitagawa Industries® MG-10A.

Example 24 may include the method of any examples 19 to 22, wherein the at least one via comprises one of: a signal via to route electric signals from at least one layer to at least another layer of the apparatus, or a power via to provide power to at least one component of the apparatus.

Various operations are described as multiple discrete operations in turn, in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. Embodiments of the present disclosure may be implemented into a system using any suitable hardware and/or software to configure as desired.

Although certain embodiments have been illustrated and described herein for purposes of description, a wide variety of alternate and/or equivalent embodiments or implementations calculated to achieve the same purposes may be substituted for the embodiments shown and described without departing from the scope of the present disclosure. This application is intended to cover any adaptations or variations of the embodiments discussed herein. Therefore, it is manifestly intended that embodiments described herein be limited only by the claims and the equivalents thereof.

Claims

Claims What is claimed is:

1. An apparatus, comprising:

a power plane disposed in a layer of a plurality of layers of the apparatus, to provide delivery of power to components of the apparatus;

at least one via that extends through at least some of the plurality of layers of the apparatus, including the layer with the power plane, to provide electric connectivity for the apparatus; and

at least one absorber component disposed through the plurality of layers of the apparatus, adj acent to or inside the power plane, wherein the absorber component is filled with absorbing material, to mitigate noise generated by the at least one via or the power plane.

2. The apparatus of claim 1, wherein the apparatus comprises a printed circuit board (PCB).

3. The apparatus of claim 1, wherein the apparatus comprises a semiconductor package.

4. The apparatus of claim 1 , wherein the at least one via comprises one of:

a signal via to route electric signals from at least one layer to at least another layer of the apparatus, or

a power via to provide power to at least one component of the apparatus.

5. The apparatus of claim 1, wherein the absorber component comprises one or more through hole vias.

6. The apparatus of claim 5, wherein the one or more through hole vias comprise multiple through hole vias disposed adjacent to the at least one via.

7. The apparatus of claim 5, wherein the one or more through hole vias comprise a plurality of through hole vias disposed in a row along at least one edge of the power plane.

8. The apparatus of claim 7, wherein the power plane comprises an elongated shape, wherein the at least one edge comprises a first edge defining a first end of the elongated shape, and a second edge defining a second end of the elongated shape, wherein the plurality of through hole vias comprises a first subset of through hole vias disposed in a row along the first edge, and a second subset of through hole vias disposed in a row along the second edge.

9. The apparatus of claim 7, wherein the plurality of through hole vias is further disposed around the power plane, to form a cage around the power plane.

10. The apparatus of claim 1, wherein the at least one absorber component comprises one or more slots disposed along respective one or more edges of the power plane.

11. The apparatus of claim 10, wherein the power plane comprises an elongated shape, wherein the one or more edges comprise a first edge defining a first end of the elongated shape, and a second edge defining a second end of the elongated shape, wherein the one or more slots comprises a first slot disposed along the first edge, and a second slot disposed along the second edge.

12. The apparatus of claim 10, wherein the one or more slots comprise a plurality of slots that are connected with each other, to surround the power plane.

13. The apparatus of any of claims 1 to 12, wherein the apparatus comprises a computing device.

14. The apparatus of any of claims 1 to 12, wherein the absorbing material comprises one of: Cuming Microwave Corporation® C-RAM MT-30, Cuming Microwave Corporation® sprayable or castable absorbers of 340 or 330 series, ARC Technologies® ML-73, or Kitagawa Industries® MG-10A.

15. A computer system, comprising:

a printed circuit board (PCB) having a plurality of layers;

a power plane disposed in a layer of the plurality of layers, to provide delivery of power to components of the PCB;

at least one via that extends through at least some of the plurality of layers of the PCB, including the layer with the power plane, to provide electric connectivity for the PCB; and

at least one absorber component disposed through the plurality of layers of the PCB, adjacent to or inside the power plane, wherein the absorber component is filled with absorbing material, to mitigate signal noise generated by the at least one via or the power plane.

16. The computer system of claim 15, wherein the at least one via comprises one of:

a power via to provide power to at least one component of the apparatus.

17. The computer system of claim 15, wherein the absorber component comprises one or more through hole vias, disposed adjacent to the at least one via, or disposed in rows along at least two opposing edges of the power plane.

18. The computer system of any of claims 15 to 17, wherein the absorber component comprises one or more through slots disposed along respective one or more edges of the power plane.

19. A method, comprising:

disposing at least one absorber component to extend through a plurality of layers of an apparatus, adjacent to or inside a power plane disposed in a layer of the plurality of layers of the apparatus, wherein the power plane includes at least one via extending through at least some of the plurality of layers of the apparatus; and

filling the at least one absorber component with absorbing material, to mitigate noise generated by the at least one via or the power plane.

20. The method of claim 19, wherein the at least one absorber component comprises one or more through hole vias, wherein disposing at least one absorber component includes:

providing the one or more through hole vias adjacent to the at least one via, surrounding the power plane with the one or more through hole vias, or providing the one or more through hole vias to form rows along at least two opposing edges of the power plane.

21. The method of claim 19, wherein the absorber component comprises one or more through slots, wherein disposing at least one absorber component includes providing the one or more through slots along respective one or more edges of the power plane.

22. The method of claim 19, wherein the apparatus comprises a semiconductor package or a printed circuit board (PCB).

23. The method of any of claims 19 to 22, wherein filling the at least one absorber component with an absorbing material includes applying to the absorber component at least one of: Cuming Microwave Corporation® C-RAM MT-30, ARC Technologies® ML-73, or Kitagawa Industries® MG-10A.

24. The method of any of claims 19 to 22, wherein the at least one via comprises one of:

a signal via to route electric signals from at least one layer to at least another layer of the apparatus, or a power via to provide power to at least one component of the apparatus.