WO2019066821A1

WO2019066821A1 - A negative differential resistance based memory

Info

Publication number: WO2019066821A1
Application number: PCT/US2017/053831
Authority: WO
Inventors: Charles C. Kuo; Benjamin Chu-Kung; Charles Augustine
Original assignee: Intel Corporation
Priority date: 2017-09-27
Filing date: 2017-09-27
Publication date: 2019-04-04

Abstract

Described is an apparatus which comprises: a storage node; a first device coupled to the storage node; a second device coupled to a first reference and the storage node, wherein the second device has negative differential resistance (NDR); a third device coupled to a second reference and the storage node, wherein the third device has NDR; and a circuitry for reading data, the circuitry coupled to the storage node and the first, second, and third devices.

Description

A NEGATIVE DIFFERENTIAL RESISTANCE BASED MEMORY BACKGROUND

[0001] Dense and high performance embedded memory is an essential ingredient for high performance Central Processing Units (CPUs), Graphics Processing Units (GPUs), and System-on-Chips (SoCs). Static Random Access Memory (SRAM) is a commonly used memory, but it is not scaling well to low power supply voltages (e.g., less than 1 Volt (V)) at advanced process nodes. For example, six transistor (6T) SRAM is becoming unstable and slow at low voltages (e.g., less than 1 V) and also need a higher minimum operating voltage (Vmin). While 8T SRAM improves speed over a 6T SRAM, it does so at the cost of area.

BRIEF DESCRIPTION OF THE DRAWINGS

[0002] The embodiments of the disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure, which, however, should not be taken to limit the disclosure to the specific embodiments, but are for explanation and understanding only.

[0003] Fig. 1 illustrates a high-level circuit of a negative differential resistance ( DR) device based memory bit-cell, according to one embodiment of the disclosure.

[0004] Figs. 2A-C illustrate plots showing I-V characteristics of an NDR diode and associated circuit.

[0005] Fig. 3 illustrates a schematic of an NDR memory cell with separate read and write ports, in accordance with some embodiments of the disclosure.

[0006] Fig. 4Α illustrates a top view of a 2-fin 2-gate layout of the NDR memory cell of

Fig. 3, in accordance with some embodiments.

[0007] Fig. 4B illustrates a cross-section of the series coupled NDR devices of Fig. 4Α, in accordance with some embodiments of the disclosure.

[0008] Fig. 5 illustrates a top view of a 3 -fin 2-gate layout of the NDR memory cell of

Fig. 3, in accordance with some embodiments.

[0009] Fig. 6 illustrates a top view of a three-dimensional (3D) 2-fin 2-gate layout of the

NDR memory cell of Fig. 3, in accordance with some embodiments.

[0010] Fig. 7 illustrates a schematic of an NDR memory cell for a field programmable grid array (FPGA), in accordance with some embodiments of the disclosure. [0011] Fig. 8 illustrates a top view of a 1-fin 2-gate layout of the DR memory cell of

Fig. 7, in accordance with some embodiments.

[0012] Fig. 9 illustrates a top view of a 2-fin 2-gate layout of the NDR memory cell of

Fig. 7, in accordance with some embodiments.

[0013] Fig. 10 illustrates a top view of a 3D 1-fin 2-gate layout of the NDR memory cell of Fig. 7, in accordance with some embodiments.

[0014] Fig. 11 illustrates a smart device or a computer system or a SoC (System-on-

Chip) with NDR device based memory, according to one embodiment of the disclosure.

DETAILED DESCRIPTION

[0015] Some embodiments describe a memory bit-cell which comprises: a storage node; a device coupled to the storage node; a first negative differential resistance (NDR) device coupled to a first reference and the storage node; a second NDR device coupled to a second reference and the storage node; and a circuitry for reading data, the circuitry coupled to the storage node, device, and first and second NDR devices. In some embodiments, the circuitry comprises a second device having a gate terminal coupled to the storage node, and a source terminal coupled to the second reference. In some embodiments, the circuitry comprises a third device having a gate terminal coupled to a read word-line (RWL), a source/drain terminal coupled to a read bit-line (RBL), and a drain/source terminal coupled to the second device. In some embodiments, the first reference is a power supply node (Vdd) while the second reference is a ground supply node (Vss). The memory bit-cell of various embodiments is smaller in size (e.g., x and y layout dimensions are smaller) compared to a traditional six transistor (6T) static random access memory (SRAM) bit-cell. For example, the layout of a memory bit-cell of various embodiments is three times smaller than a 6T SRAM bit-cell layout.

[0016] In some embodiments, the first and second NDR devices include one of: an Esaki diode; a resonant tunneling diode (RTD); or a tunneling FET (TFET). In some embodiments, the device has a gate terminal coupled to a write word-line (WWL). In some embodiments, the device is coupled to a write bit-line (WBL). In some embodiments, the device is one of: a p-type transistor; or an n-type transistor. In some embodiments, the device comprises thin film transistor (TFT). In some embodiments, the circuit comprises a field programmable grid array (FPGA). In some embodiments, the device is positioned in a backend of line (BEOL) of a die, wherein the circuitry and the first and second DR devices are positioned in a frontend of line (FEOL) of the die.

[0017] Here, the term "backend" of BEOL generally refers to a section of a die which is opposite of a "frontend" and where an IC (integrated circuit) package couples to IC die bumps. For example, high level metal layers (e.g., metal layer 6 and above in a ten metal stack die) and corresponding vias that are closer to a die package are considered part of the backend of the die. The BEOL is the portion of IC fabrication where individual semiconductor devices (whether embedded memory or logic transistors) are interconnected to one another with electrically conductive features such as metal interconnect traces (lines) within a given metallization level and metal-filled conductive vias between multiple metallization levels. These conductive interconnects are embedded in a dielectric material so that the memory device is a monolithic integrated circuit. Conversely, the term "frontend" or FEOL generally refers to a section of the die that includes the traditional active region (e.g., where transistors (e.g., BJT, MOS) are fabricated) and low level metal layers and corresponding vias that are closer to the active region (e.g., metal layer 5 (M5) and below in a ten metal stack die example).

[0018] In the following description, numerous details are discussed to provide a more thorough explanation of the embodiments of the present disclosure. It will be apparent, however, to one skilled in the art, that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring embodiments of the present disclosure.

[0019] Note that in the corresponding drawings of the embodiments, signals are represented with lines. Some lines may be thicker, to indicate more constituent signal paths, and/or have arrows at one or more ends, to indicate primary information flow direction. Such indications are not intended to be limiting. Rather, the lines are used in connection with one or more exemplary embodiments to facilitate easier understanding of a circuit or a logical unit. Any represented signal, as dictated by design needs or preferences, may actually comprise one or more signals that may travel in either direction and may be implemented with any suitable type of signal scheme.

[0020] Throughout the specification, and in the claims, the term "connected" means a direct connection, such as electrical, mechanical, or magnetic connection between the things that are connected, without any intermediary devices. The term "coupled" means a direct or indirect connection, such as a direct electrical, mechanical, or magnetic connection between the things that are connected or an indirect connection, through one or more passive or active intermediary devices. The term "circuit" or "module" may refer to one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. The term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data/clock signal. The meaning of "a," "an," and "the" include plural references. The meaning of "in" includes "in" and "on."

[0021] The terms "substantially," "close," "approximately," "near," and "about," generally refer to being within +/- 10% of a target value (unless specifically specified). Unless otherwise specified the use of the ordinal adjectives "first," "second," and "third," etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.

[0022] For the purposes of the present disclosure, phrases "A and/or B" and "A or B" mean (A), (B), or (A and B). For the purposes of the present disclosure, the phrase "A, B, and/or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0023] The terms "left," "right," "front," "back," "top," "bottom," "over," "under," and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. The terms "over," "under," "between," and "on" as used herein refer to a relative position of one component or material with respect to other components or materials where such physical relationships are noteworthy. For example in the context of materials, one material or material disposed over or under another may be directly in contact or may have one or more intervening materials. Moreover, one material disposed between two materials or materials may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first material "on" a second material is in direct contact with that second material. Similar distinctions are to be made in the context of component assemblies.

[0024] As used throughout this description, and in the claims, a list of items joined by the term "at least one of or "one or more of can mean any combination of the listed terms. For example, the phrase "at least one of A, B or C" can mean A; B; C; A and B; A and C; B and C; or A, B and C.

[0025] It is pointed out that those elements of a figure having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0026] Fig. 1 illustrates a high-level circuit 100 of an NDR device based memory bit- cell, according to one embodiment of the disclosure. In some embodiments, circuit 100 comprises one or more Transistors 101 (e.g., access device), first and second NDR devices 102 and 103, respectively, Storage node (SN), and read port circuitry 104.

[0027] A device with NDR characteristic exhibits higher conductance at low voltages than at high voltages. A variety of materials and device structures exhibit an NDR characteristic including: Esaki diodes, RTD, and TFETs. The ratio of the maximum current at low voltage to the minimum current at higher voltage is called the peak-to-valley ratio (PVR), and the voltages at which these current levels are observed are known as the peak voltage and valley voltage, respectively. NDR devices have a general limitation of low peak-to-valley ratios and low peak currents. The bit-cells of some embodiments described here work with the low peak currents (e.g., less than 0.1 nA (nano-Ampere)). The bit-cells would work with NDR devices with higher peak current levels as well.

[0028] When the two tunneling NDR devices 102 and 103 are coupled in series, the resulting combination is a circuit element called a twin. The twin forms a bi-stable memory element with the middle or common node as SN. In some embodiments, first NDR device 102 is coupled to a reference supply Vref2 (e.g., power supply Vdd) and SN. In some embodiments, second NDR device 103 is coupled to another reference supply Vrefl (e.g., ground supply Vss) and SN. In some embodiments, when the voltage on SN is at a high voltage (e.g., close to Vdd), first NDR device 102 (also referred to as the pull-up NDR device) sources current more strongly than the second NDR device 103 (also referred to as the pull-down NDR device) can sink it, thus keeping the voltage on SN high. Conversely, when the voltage on SN is at a low voltage pulldown second NDR device 103 sinks current more strongly and SN can be held at a low voltage.

[0029] Here, first and second NDR devices 102 and 103 are represented as two terminal devices but in general devices 102 and 103 may have two or more physical terminals with an NDR characteristic between at least two terminals. For example, a TFET may show NDR characteristics between source and drain terminals when the TFET gate terminal has a separate biasing voltage.

[0030] In some embodiments, the one or more Transistors 101 (also referred here as access transistor(s)) is a single n-type or p-type transistor. In some embodiments, a combination of TFETs may be used for the one or more Transistors 101. In some embodiments, the gate terminal of the one or more Transistors 101 is coupled to WWL or WWLB (an inverse of WWL) depending on whether Transistor 101 is an n-type transistor or a p-type transistor. In some embodiments, the source or drain terminals of Transistor 101 is coupled to WBL while the drain or source terminal of Transistor 101 is coupled to the SN. In some embodiments, the SN is coupled to read port circuitry 104.

[0031] The twin cell (e.g., first and second NDR devices 102 and 103) helps to hold memory state on SN. Current driving capability of NDR twin is low (as shown in Figs. 2A-B), but sufficient to overcome leakage that gradually drains charge through transistors of read port circuitry 104. In some embodiments, current from NDR device (e.g., one of NDR devices 102 or 103) mitigates the loss of charge from leakage on SN and can restore the stored charge on SN to the original value.

[0032] Figs. 2A-C illustrate plots 200 and 220 and associated circuit 230, respectively, showing I-V characteristics of an NDR diode. For Fig. 2A, the x-axis is voltage in volts on SN (i.e., VSN), and the y-axis is current in nA through the NDR device (e.g.., 102 and 103). For Fig. 2B, the x-axis is voltage on in volts on SN (i.e., VSN), and the y-axis is current I_x in nA into SN. Plots 200 and 220 are formed using circuit 230 of Fig. 2C, in which NDR devices 102 and 103 are replaced with Esaki diodes. Here, Vref2 is Vdd (power supply) while Vrefl is ground (Vss), and voltage source Vx is used to drive or sink current to or from SN.

[0033] Referring back to Fig. 2A, when VSN increases from 0 V, pull down current 201

(e.g., current from SN to ground through NDR device 103) increases while the pull up current 202 (e.g., current from SN to Vdd through NDR device 102) remains zero or close to zero until near 0.5 V VSN. Near 0.5 V on SN, pull down current 201 suddenly falls close to zero while pull up current 202 suddenly rises. As VSN further increases, pull up current 202 declines and reaches near zero as VSN approaches near equal to Vdd, while the pull down current 201 remains substantially near to zero and equal to current 202. The region near VSN of 0.5 V is a meta-stable region as shown in Fig. 2B. [0034] In Fig. 2B, plot 220 shows the current I_x when SN stores a '0' and when SN stores a T . When VSN is at a high voltage, first NDR device 102 sources current more strongly than the second NDR device 103 can sink it, thus keeping the voltage on SN high. Conversely, when VSN is at a low voltage, pull-down NDR device 103 sinks current more strongly and SN can be held at a low voltage.

[0035] Fig. 3 illustrates a schematic of an NDR memory cell 300 with separate read and write ports, in accordance with some embodiments of the disclosure. While various

embodiments here are described with reference to n-type transistors, p-type transistors may also be used. In some embodiments, a combination of p-type and n-type transistors may be used for the various embodiments described here. In this example, the access transistor 101 is an n-type transistor MN1, first and second NDR devices 102 and 103 are diodes, and read port circuitry 103 comprises n-type transistors MN2 and MN3. In some embodiments, the cathode of diode Dl (first NDR device 102) is coupled to SN while the anode of diode Dl is coupled to Vdd (an example of Vref2). In some embodiments, the anode of diode D2 (second NDR device 103) is coupled to the SN while the cathode of diode D2 is coupled to Vss (an example of Vrefl).

[0036] In some embodiments, the gate terminal of transistor MN2 is coupled to SN, the source of transistor MN2 is coupled to Vss (an example of Vrefl), and the drain of transistor MN2 is coupled to transistor MN3. In some embodiments, the source terminal of transistor MN3 is coupled to transistor MN2. In some embodiments, the drain terminal of transistor MN3 is coupled to the read bit-line (RBL). In some embodiments, the gate terminal of transistor MN3 is coupled to the read word-line (RWL).

[0037] The memory cell here operates similarly to an 8-T SRAM cell, where there are separate read/write ports. For the reading, current differences can be used to detect a "0" or "1". For example, RBL is pre-charged to a value before the read, and depending if the storage node is "0" or "1", the node will be left alone or start to discharge to lower value. In some embodiments, to write data to the memory cell, RWL is de-activated (e.g., turned to logic low to turn off transistor MN3), and access transistor MNl is turned on (e.g., WWL is set to logic high), and data on WBL is transferred to SN. In various embodiments, first and second NDR devices 102 and 103 assist with holding the data on SN.

[0038] Fig. 4A illustrates a top view of a 2-fin 2-gate layout 400 of the NDR memory cell of Fig. 3, in accordance with some embodiments. Layout 400 illustrates a high density layout of the NDR memory cell of Fig. 3 where the bit-cell is drawn over two fins (in a Fin FET process technology). In this example, the devices and connection layers are formed on the FEOL of the die. Here, layer 401 is the gate (e.g., a high-K gate), layer 402 is diffusion contact, layer 403 is the fin (e.g., Si, and higher electron mobility material such as Group III-V semiconductors like gallium-arsenide (GaAs)), layer 404 is the NDR, and layer 405 is the NDR contact for the first and second NDR devices 102 and 103, respectively.

[0039] Various materials can yield NDR behavior. For example, Group VI elements such as oxygen, sulfur, selenium, and tellurium can be used for forming first and second NDR devices 102 and 103, respectively. In some embodiments, diffusion contact is also referred to as TCN (trench contact), which is a trench opening that contacts a diffusion region. In some embodiments, the gate contact is also referred to as GCN which is a trench or via opening that contacts the gate stack of a transistor. Materials used for TCN and GCN are conductive materials such as W, Al, Cu, Ag, Au, Co, Ti, Graphene, or a combination of them. While the embodiments here are described with reference to Esaki diodes for NDR devices, other types of NDR devices may be used without departing from the scope of the embodiments.

[0040] In some embodiments, transistors MNl, MN2 and MN3 can be tunneling FETs

(TFETs). TFETs are promising devices in that they may provide significant performance increase and energy consumption decrease due to a steeper sub-threshold slope. In this example, one or more Transistors 101 are replaced with two n-type TFETs MNT1 and MNT2 (not shown). In this embodiment, since TFETs' channel current is asymmetric (e.g., the current flows substantially in one direction), the source terminal of MNTl is coupled to drain terminal of MNT2, and the drain terminal of MNTl is coupled to source terminal of MNT2. A similar bit- cell can be formed using p-type TFETs MPT1 and MPT2 (not shown) with similar topology of NDR device(s) as shown with reference to other embodiments. Using TFET's may improve the low voltage performance of the bit-cell or provide for an easier integration of devices with NDR characteristics.

[0041] Fig. 4B illustrates a cross-section 420 of the series coupled NDR devices of Fig.

4A, in accordance with some embodiments of the disclosure. Cross-section 420 is a simplified illustration of cross-section AA' of Fig. 4A. Cross-section 420 illustrates how first and second NDR devices 102 and 103, respectively, are formed and coupled to storage node 401 (SN). In some embodiments, each NDR device comprises two ohmic layers 421a/b and 423a/b and NDR behaving material (e.g., Si, and higher electron mobility material such as Group III-V semiconductors like gallium-arsenide (GaAs)). The ohmic layers 421a/b couple one another and to metal via or trench filled with metal forming storage node 401 (SN).

[0042] Fig. 5 illustrates a top view of a 3-fin 2-gate layout 500 of the DR memory cell of Fig. 3, in accordance with some embodiments. Layout 500 has a large pitch (e.g., x-y footprint) than layout 400. In this example, the x dimension is greater than the y dimension. One reason to use layout 500 is that it easily accommodates resonant tunneling diode (RTD) for the NDR devices. In some embodiments, the top layer of the center fin can be of different materials or dopant type. As the pitch of layout 500 increases, the storage node (SN) is connected to first and second NDR devices 102/103 and transistor MNl (whose gate is connected to WWL) through gate contact layer 506. An example of gate contact layer is GCN.

[0043] Fig. 6 illustrates a top view of a three-dimensional (3D) 2-fin 2-gate layout 600 of the NDR memory cell of Fig. 3, in accordance with some embodiments. Compared to layout 500, here, the pitch is smaller because transistor MNl is formed on a higher layer. For example, transistor MNl is a thin film transistor (TFT) which is formed on the BEOL of a die (as indicated by region 601) over the NDR devices 102/103 and transistors MN2 and MN3 (as indicated by region 602), in accordance with some embodiments. In some embodiments, NDR devices 102/103 and transistors MN2 and MN3 are formed on the FOEL of the die.

[0044] Thin-film transistors (TFTs) are a class of field-effect transistors (FETs) in which the channel material is a deposited thin film rather than a monocrystalline material. A common application of TFT technology is liquid crystal displays (LCDs), but TFTs are also advantageous in other applications as the thin film deposition processes employed in TFT fabrication can be relatively low (e.g., below 450 °C), allowing TFTs to be inserted within layers of interconnect metallization of the type that is typically formed only after higher-temperature processing is completed in conventional silicon MOSFET fabrication technology. TFTs can be fabricated using a wide variety of semiconductor materials, such as silicon, germanium, silicon-germanium, as well as various oxide semiconductors (a.k.a. semiconducting oxides) including metal oxides such as indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), and the like.

[0045] Fig. 7 illustrates a schematic of an NDR memory cell 700 for a field

programmable grid array (FPGA) 701, in accordance with some embodiments of the disclosure. In this example, the read port 104 is implemented using FPGA 701. In some embodiments, FPGA 701 comprises one or programmable pass-gates. In some embodiments, transistor MN1 and programmable pass-gates 701 are formed on the BOEL of the die, while DR devices 102/103 are formed on the FOEL devices. In some embodiments, transistor MN1 and programmable pass-gates 701 are formed using TFTs. In some embodiments, all devices of NDR memory cell 700 are formed on the FOEL of the die. Figs. 8-10 illustrate various layout configurations for the NDR memory cells minus the FPGA portion 701.

[0046] Fig. 8 illustrates a top view of a 1-fin 2-gate layout 800 of the NDR memory cell of Fig. 7, in accordance with some embodiments. Layout 800 is similar to layout 500 but for the absence of read port circuitry 104. This is a high density 2D layout that can be used for condensed memory using FPGA as the read port.

[0047] Fig. 9 illustrates a top view of a 2-fin 2-gate layout 900 of the NDR memory cell of Fig. 7, in accordance with some embodiments. Layout 900 is similar to layout 600 but for the read port circuitry 104. In this example, the pitch of the memory cell (minus the FPGA read port) is 2 fins and 2 gates.

[0048] Fig. 10 illustrates a top view of a 3D 1-fin 2-gate layout 1000 of the NDR memory cell of Fig. 7, in accordance with some embodiments. Layout 1000 is similar to layout 700 but for the read port circuitry 104. In this example, the pitch of the memory cell (minus the FPGA read port) is 1 fin and 2 gates.

[0049] Fig. 11 is a smart device or a computer system or a SoC (System-on-Chip) with

NDR device based memory, according to one embodiment of the disclosure. It is pointed out that those elements of Fig. 11 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0050] Fig. 11 illustrates a block diagram of an embodiment of a mobile device in which flat surface interface connectors could be used. In one embodiment, computing device 1600 represents a mobile computing device, such as a computing tablet, a mobile phone or smart- phone, a wireless-enabled e-reader, or other wireless mobile device. It will be understood that certain components are shown generally, and not all components of such a device are shown in computing device 1600.

[0051] In one embodiment, computing device 1600 includes a first processor 1610 with

NDR device based memory, according to the embodiments discussed. Other blocks of the computing device 1600 may also include the apparatus of DR device based memory of the embodiments. The various embodiments of the present disclosure may also comprise a network interface within 1670 such as a wireless interface so that a system embodiment may be incorporated into a wireless device, for example, cell phone or personal digital assistant.

[0052] In one embodiment, processor 1610 (and/or processor 1690) can include one or more physical devices, such as microprocessors, application processors, microcontrollers, programmable logic devices, or other processing means. The processing operations performed by processor 1610 include the execution of an operating platform or operating system on which applications and/or device functions are executed. The processing operations include operations related to I/O (input/output) with a human user or with other devices, operations related to power management, and/or operations related to connecting the computing device 1600 to another device. The processing operations may also include operations related to audio I/O and/or display I/O.

[0053] In one embodiment, computing device 1600 includes audio subsystem 1620, which represents hardware (e.g., audio hardware and audio circuits) and software (e.g., drivers, codecs) components associated with providing audio functions to the computing device. Audio functions can include speaker and/or headphone output, as well as microphone input. Devices for such functions can be integrated into computing device 1600, or connected to the computing device 1600. In one embodiment, a user interacts with the computing device 1600 by providing audio commands that are received and processed by processor 1610.

[0054] Display subsystem 1630 represents hardware (e.g., display devices) and software

(e.g., drivers) components that provide a visual and/or tactile display for a user to interact with the computing device 1600. Display subsystem 1630 includes display interface 1632, which includes the particular screen or hardware device used to provide a display to a user. In one embodiment, display interface 1632 includes logic separate from processor 1610 to perform at least some processing related to the display. In one embodiment, display subsystem 1630 includes a touch screen (or touch pad) device that provides both output and input to a user.

[0055] I/O controller 1640 represents hardware devices and software components related to interaction with a user. I/O controller 1640 is operable to manage hardware that is part of audio subsystem 1620 and/or display subsystem 1630. Additionally, I/O controller 1640 illustrates a connection point for additional devices that connect to computing device 1600 through which a user might interact with the system. For example, devices that can be attached to the computing device 1600 might include microphone devices, speaker or stereo systems, video systems or other display devices, keyboard or keypad devices, or other I/O devices for use with specific applications such as card readers or other devices.

[0056] As mentioned above, I/O controller 1640 can interact with audio subsystem 1620 and/or display subsystem 1630. For example, input through a microphone or other audio device can provide input or commands for one or more applications or functions of the computing device 1600. Additionally, audio output can be provided instead of, or in addition to display output. In another example, if display subsystem 1630 includes a touch screen, the display device also acts as an input device, which can be at least partially managed by I/O controller 1640. There can also be additional buttons or switches on the computing device 1600 to provide I/O functions managed by I/O controller 1640.

[0057] In one embodiment, I/O controller 1640 manages devices such as accelerometers, cameras, light sensors or other environmental sensors, or other hardware that can be included in the computing device 1600. The input can be part of direct user interaction, as well as providing environmental input to the system to influence its operations (such as filtering for noise, adjusting displays for brightness detection, applying a flash for a camera, or other features).

[0058] In one embodiment, computing device 1600 includes power management 1650 that manages battery power usage, charging of the battery, and features related to power saving operation. Memory subsystem 1660 includes memory devices for storing information in computing device 1600. Memory can include nonvolatile (state does not change if power to the memory device is interrupted) and/or volatile (state is indeterminate if power to the memory device is interrupted) memory devices. Memory subsystem 1660 can store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of the applications and functions of the computing device 1600. In some embodiments, Memory subsystem 1660 comprises DR based memory as discussed in various embodiments.

[0059] Elements of embodiments are also provided as a machine-readable medium (e.g., memory 1660) for storing the computer-executable instructions (e.g., instructions to implement any other processes discussed herein). The machine-readable medium (e.g., memory 1660) may include, but is not limited to, flash memory, optical disks, CD-ROMs, DVD ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, phase change memory (PCM), or other types of machine-readable media suitable for storing electronic or computer-executable instructions. For example, embodiments of the disclosure may be downloaded as a computer program (e.g., BIOS) which may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of data signals via a communication link (e.g., a modem or network connection).

[0060] Connectivity 1670 includes hardware devices (e.g., wireless and/or wired connectors and communication hardware) and software components (e.g., drivers, protocol stacks) to enable the computing device 1600 to communicate with external devices. The computing device 1600 could be separate devices, such as other computing devices, wireless access points or base stations, as well as peripherals such as headsets, printers, or other devices.

[0061] Connectivity 1670 can include multiple different types of connectivity. To generalize, the computing device 1600 is illustrated with cellular connectivity 1672 and wireless connectivity 1674. Cellular connectivity 1672 refers generally to cellular network connectivity provided by wireless carriers, such as provided via GSM (global system for mobile

communications) or variations or derivatives, CDMA (code division multiple access) or variations or derivatives, TDM (time division multiplexing) or variations or derivatives, or other cellular service standards. Wireless connectivity (or wireless interface) 1674 refers to wireless connectivity that is not cellular, and can include personal area networks (such as Bluetooth, Near Field, etc.), local area networks (such as Wi-Fi), and/or wide area networks (such as WiMax), or other wireless communication.

[0062] Peripheral connections 1680 include hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) to make peripheral connections. It will be understood that the computing device 1600 could both be a peripheral device ("to" 1682) to other computing devices, as well as have peripheral devices ("from" 1684) connected to it. The computing device 1600 commonly has a "docking" connector to connect to other computing devices for purposes such as managing (e.g., downloading and/or uploading, changing, synchronizing) content on computing device 1600. Additionally, a docking connector can allow computing device 1600 to connect to certain peripherals that allow the computing device 1600 to control content output, for example, to audiovisual or other systems. [0063] In addition to a proprietary docking connector or other proprietary connection hardware, the computing device 1600 can make peripheral connections 1680 via common or standards-based connectors. Common types can include a Universal Serial Bus (USB) connector (which can include any of a number of different hardware interfaces), DisplayPort including MiniDisplayPort (MDP), High Definition Multimedia Interface (HDMI), Firewire, or other types.

[0064] Reference in the specification to "an embodiment," "one embodiment," "some embodiments," or "other embodiments" means that a particular feature, structure, or

characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments. The various appearances of "an

embodiment," "one embodiment," or "some embodiments" are not necessarily all referring to the same embodiments. If the specification states a component, feature, structure, or characteristic "may," "might," or "could" be included, that particular component, feature, structure, or characteristic is not required to be included. If the specification or claim refers to "a" or "an" element, that does not mean there is only one of the elements. If the specification or claims refer to "an additional" element, that does not preclude there being more than one of the additional element.

[0065] Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment anywhere the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.

[0066] While the disclosure has been described in conjunction with specific

embodiments thereof, many alternatives, modifications and variations of such embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. For example, other memory architectures e.g., Dynamic RAM (DRAM) may use the embodiments discussed. The embodiments of the disclosure are intended to embrace all such alternatives, modifications, and variations as to fall within the broad scope of the appended claims.

[0067] In addition, well known power/ground connections to integrated circuit (IC) chips and other components may or may not be shown within the presented figures, for simplicity of illustration and discussion, and so as not to obscure the disclosure. Further, arrangements may be shown in block diagram form in order to avoid obscuring the disclosure, and also in view of the fact that specifics with respect to implementation of such block diagram arrangements are highly dependent upon the platform within which the present disclosure is to be implemented (i.e., such specifics should be well within purview of one skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the disclosure, it should be apparent to one skilled in the art that the disclosure can be practiced without, or with variation of, these specific details. The description is thus to be regarded as illustrative instead of limiting.

[0068] The following examples pertain to further embodiments. Specifics in the examples may be used anywhere in one or more embodiments. All optional features of the apparatus described herein may also be implemented with respect to a method or process.

[0069] Example 1. An apparatus comprising: a storage node; a first device coupled to the storage node; a second device coupled to a first reference and the storage node, wherein the second device has negative differential resistance (NDR); a third device coupled to a second reference and the storage node, wherein the third device has NDR; and a circuitry for reading data, the circuitry coupled to the storage node and the first, second, and third devices.

[0070] Example 2. The apparatus of claim 1, wherein the circuitry comprises a fourth device having a gate terminal coupled to the storage node, and a source terminal coupled to the second reference.

[0071] Example 3. The apparatus of claim 2, wherein the circuitry comprises a fifth device having a gate terminal coupled to a read word-line (RWL), a source/drain terminal coupled to a read bit-line (RBL), and a drain/source terminal coupled to the fourth device.

[0072] Example 4. The apparatus according to any one of preceding claims, wherein the first reference is a power supply node while the second reference is a ground supply node.

[0073] Example 5. The apparatus according to any one of preceding claims, wherein the second and third devices include one of: an Esaki diode; a resonant tunneling diode (RTD); or a tunneling FET (TFET).

[0074] Example 6. The apparatus according to any one of preceding claims, wherein the first device has a gate terminal coupled to a write word-line (WWL).

[0075] Example 7. The apparatus according to any one of preceding claims, wherein the first device is coupled to a write bit-line (WBL). [0076] Example 8. The apparatus according to any one of preceding claims, wherein the first device is one of: a p-type transistor or an n-type transistor.

[0077] Example 9. The apparatus according to any one of preceding claims, wherein the first device comprises a thin film transistor (TFT).

[0078] Example 10. The apparatus according to any one of preceding claims, wherein the circuitry comprises a field programmable grid array (FPGA).

[0079] Example 11. The apparatus according to any one of preceding claims, wherein the first device is positioned in a backend of line (BEOL) of a die, and wherein the circuitry and the second and third devices are positioned in a frontend of line (FEOL) of the die.

[0080] Example 12. A system comprising: a processor having a memory array including memory bit-cells organized in rows and columns, wherein each memory bit-cell is according to any one of claims 1 to 11; and a wireless interface to allow the processor to communicate with another device.

[0081] Example 13. The system of claim 12 further comprises a memory die stacked over or under the processor.

[0082] Example 14. A method comprising: forming a storage node; forming a device coupled to the storage node; forming a first negative differential resistance (NDR) device coupled to a first reference and the storage node; forming a second NDR device coupled to a second reference and the storage node; and forming a circuitry for reading data, the circuitry coupled to the storage node, device, and first and second NDR devices.

[0083] Example 15. The method of claim 14, wherein forming the circuitry comprises forming a second device having a gate terminal coupled to the storage node, and a source terminal coupled to the second reference.

[0084] Example 16. The method of claim 15, wherein forming the circuitry comprises forming a third device having a gate terminal coupled to a read word-line (RWL), a source/drain terminal coupled to a read bit-line (RBL), and a drain/source terminal coupled to the second device.

[0085] Example 17. The method according to any one of preceding method claims, wherein the first reference is a power supply node while the second reference is a ground supply node. [0086] Example 18. The method according to any one of preceding method claims, wherein forming the first and second NDR devices include forming one of: an Esaki diode; a resonant tunneling diode; or a tunneling FET (TFET).

[0087] Example 19. The method according to any one of preceding method claims comprises coupling a gate terminal of the device to a write word-line (WWL).

[0088] Example 20. The method according to any one of preceding method claims comprises coupling the device to a write bit-line (WBL).

[0089] Example 21. The method according to any one of preceding method claims, wherein forming the device comprises forming one of: a p-type transistor; or an n-type transistor.

[0090] Example 22. The method according to any one of preceding method claims, wherein forming the device comprises forming thin film transistor (TFT).

[0091] Example 23. The method according to any one of preceding method claims, wherein the circuitry comprises a field programmable grid array (FPGA).

[0092] Example 24. The method according to any one of preceding method claims, wherein forming the device comprises forming the device in a backend of line (BEOL) of a die, and wherein forming the circuitry and the first and second NDR devices comprises forming the circuitry and the first and second NDR devices in a frontend of line (FEOL) of the die.

[0093] Example 25. An apparatus comprising: means for storing; a first means coupled to the means for storing; a second means coupled to a first reference and the means for storing, wherein the second means has negative differential resistance (NDR); a third means coupled to a second reference and the means for storing, wherein the third means has NDR; and a fourth means for reading data, the fourth means coupled to the means for storing and the first, second, and third means.

[0094] Example 26. The apparatus of claim 25, wherein the fourth means comprises a fifth means having a gate terminal coupled to the means for storing, and a source terminal coupled to the second reference.

[0095] Example 27. The apparatus of claim 26, wherein the fourth means comprises a sixth means having a gate terminal coupled to a read word-line (RWL), a source/drain terminal coupled to a read bit-line (RBL), and a drain/source terminal coupled to the fifth means. [0096] Example 28. The apparatus according to any one of preceding claims 25 to 27, wherein the first reference is a power supply node while the second reference is a ground supply node.

[0097] Example 29. The apparatus according to any one of preceding claims 25 to 28, wherein the second and third means include one of: an Esaki diode; a resonant tunneling diode (RTD); or a tunneling FET (TFET).

[0098] Example 30. The apparatus according to any one of preceding claims 25 to 29, wherein the first device has a gate terminal coupled to a write word-line (WWL).

[0099] Example 31. The apparatus according to any one of preceding claims 25 to 30, wherein the first means is coupled to a write bit-line (WBL).

[00100] Example 32. The apparatus according to any one of preceding claims 25 to 31, wherein the first means comprises: a p-type transistor or an n-type transistor.

[00101] Example 33. The apparatus according to any one of preceding claims 25 to 32, wherein the first means comprises a thin film transistor (TFT).

[00102] Example 34. The apparatus according to any one of preceding claims 25 to 33, wherein the fourth means comprises a field programmable grid array (FPGA).

[00103] Example 35. The apparatus according to any one of preceding claims 25 to 34, wherein the first means is positioned in a backend of line (BEOL) of a die, and wherein the fourth means and the second and third means are positioned in a frontend of line (FEOL) of the die.

[00104] An abstract is provided that will allow the reader to ascertain the nature and gist of the technical disclosure. The abstract is submitted with the understanding that it will not be used to limit the scope or meaning of the claims. The following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.

Claims

CLAIMS We claim:

1. An apparatus comprising:

a storage node;

a first device coupled to the storage node;

a second device coupled to a first reference and the storage node, wherein the second device has negative differential resistance ( DR);

a third device coupled to a second reference and the storage node, wherein the third device has NDR; and

a circuitry for reading data, the circuitry coupled to the storage node and the first, second, and third devices.

The apparatus of claim 1, wherein the circuitry comprises a fourth device having a gate terminal coupled to the storage node, and a source terminal coupled to the second reference.

The apparatus of claim 2, wherein the circuitry comprises a fifth device having a gate terminal coupled to a read word-line (RWL), a source/drain terminal coupled to a read bit-line (RBL), and a drain/source terminal coupled to the fourth device.

The apparatus according to any one of preceding claims, wherein the first reference is a power supply node while the second reference is a ground supply node.

The apparatus according to any one of preceding claims, wherein the second and third devices include one of: an Esaki diode; a resonant tunneling diode (RTD); or a tunneling FET (TFET).

6. The apparatus according to any one of preceding claims, wherein the first device has a gate terminal coupled to a write word-line (WWL).

7. The apparatus according to any one of preceding claims, wherein the first device is coupled to a write bit-line (WBL).

8 The apparatus according to any one of preceding claims, wherein the first device is one of: a p-type transistor or an n-type transistor.

9. The apparatus according to any one of preceding claims, wherein the first device

comprises a thin film transistor (TFT).

10. The apparatus according to any one of preceding claims, wherein the circuitry comprises a field programmable grid array (FPGA).

11. The apparatus according to any one of preceding claims, wherein the first device is

positioned in a backend of line (BEOL) of a die, and wherein the circuitry and the second and third devices are positioned in a frontend of line (FEOL) of the die.

12. A system comprising:

a processor having a memory array including memory bit-cells organized in rows and columns, wherein each memory bit-cell is according to any one of claims 1 to 11; and

a wireless interface to allow the processor to communicate with another device.

13. The system of claim 12 further comprises a memory die stacked over or under the

processor.

14. A method comprising:

forming a storage node;

forming a device coupled to the storage node;

forming a first negative differential resistance (NDR) device coupled to a first reference and the storage node;

forming a second NDR device coupled to a second reference and the storage node; and forming a circuitry for reading data, the circuitry coupled to the storage node, device, and first and second NDR devices.

15. The method of claim 14, wherein forming the circuitry comprises forming a second

device having a gate terminal coupled to the storage node, and a source terminal coupled to the second reference.

16. The method of claim 15, wherein forming the circuitry comprises forming a third device having a gate terminal coupled to a read word-line (RWL), a source/drain terminal coupled to a read bit-line (RBL), and a drain/source terminal coupled to the second device.

17. The method according to any one of preceding method claims, wherein the first reference is a power supply node while the second reference is a ground supply node.

18. The method according to any one of preceding method claims, wherein forming the first and second NDR devices include forming one of: an Esaki diode; a resonant tunneling diode; or a tunneling FET (TFET).

19. The method according to any one of preceding method claims comprises coupling a gate terminal of the device to a write word-line (WWL).

20. The method according to any one of preceding method claims comprises coupling the device to a write bit-line (WBL).

21. The method according to any one of preceding method claims, wherein forming the device comprises forming one of: a p-type transistor; or an n-type transistor.

22. The method according to any one of preceding method claims, wherein forming the device comprises forming thin film transistor (TFT).

23. The method according to any one of preceding method claims, wherein the circuitry comprises a field programmable grid array (FPGA).

24. The method according to any one of preceding method claims, wherein forming the device comprises forming the device in a backend of line (BEOL) of a die, and wherein forming the circuitry and the first and second NDR devices comprises forming the circuitry and the first and second NDR devices in a frontend of line (FEOL) of the die.

25. An apparatus comprising:

means for storing;

a first means coupled to the means for storing;

a second means coupled to a first reference and the means for storing, wherein the second means has negative differential resistance (NDR);

a third means coupled to a second reference and the means for storing, wherein the third means has NDR; and

a fourth means for reading data, the fourth means coupled to the means for storing and the first, second, and third means.