WO2019066814A1 - Procédé de liaison utilisant des réactions entre des monocouches - Google Patents

Procédé de liaison utilisant des réactions entre des monocouches Download PDF

Info

Publication number
WO2019066814A1
WO2019066814A1 PCT/US2017/053787 US2017053787W WO2019066814A1 WO 2019066814 A1 WO2019066814 A1 WO 2019066814A1 US 2017053787 W US2017053787 W US 2017053787W WO 2019066814 A1 WO2019066814 A1 WO 2019066814A1
Authority
WO
WIPO (PCT)
Prior art keywords
monolayer
reaction
addition reaction
surface portion
dielectric layer
Prior art date
Application number
PCT/US2017/053787
Other languages
English (en)
Inventor
Veronica Strong
Aleksandar Aleksov
Aranzazu MAESTRE CARO
Adel ELSHERBINI
Original Assignee
Intel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corporation filed Critical Intel Corporation
Priority to PCT/US2017/053787 priority Critical patent/WO2019066814A1/fr
Publication of WO2019066814A1 publication Critical patent/WO2019066814A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H05K1/186—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/145—Organic substrates, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0137—Materials
    • H05K2201/0141—Liquid crystal polymer [LCP]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0137—Materials
    • H05K2201/0145—Polyester, e.g. polyethylene terephthalate [PET], polyethylene naphthalate [PEN]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0137—Materials
    • H05K2201/015—Fluoropolymer, e.g. polytetrafluoroethylene [PTFE]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0137—Materials
    • H05K2201/0154—Polyimide
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10015—Non-printed capacitor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10022—Non-printed resistor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/1003—Non-printed inductor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10098—Components for radio transmission, e.g. radio frequency identification [RFID] tag, printed or non-printed antennas
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10151—Sensor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10159—Memory
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10166—Transistor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10174—Diode
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/10378—Interposers

Definitions

  • Embodiments of the invention generally relate to integrated circuit (IC) package and printed circuit board (PCB) technologies and, more particularly but not exclusively, to techniques for bonding layers of a substrate.
  • IC integrated circuit
  • PCB printed circuit board
  • High density substrates are moving toward feature sizes which test the capabilities of traditional manufacturing technologies.
  • Such technologies often use low numerical aperture (NA) lithography - e.g., NA ⁇ 0.1 - laser via drilling, and surface roughening of dielectric or metal layers.
  • NA numerical aperture
  • Roughening is a mechanically driven process used in both PCB and package substrate technology to promote adhesion between one dielectric layer and another, or between one dielectric layer and a metal layer. The effectiveness of roughening tends to be compromised as substrate feature sizes approach a few microns.
  • FIG. 1 shows various views illustrating elements of a substrate including layers which are bonded to one another according to an embodiment.
  • FIG. 2 is a flow diagram illustrating elements of a method for providing bonded layers of a substrate according to an embodiment.
  • FIG. 3 shows cross-sectional diagrams each illustrating structures at a respective stage of a substrate manufacture process according to an embodiment.
  • FIG. 4 shows cross-sectional diagrams each illustrating structures at a respective stage of a substrate manufacture process according to an embodiment.
  • FIG. 5 is a structural formula diagram showing a chemical process to bond layers of a substrate according to an embodiment.
  • FIG. 6 is a structural formula diagram showing a chemical process to bond layers of a substrate according to an embodiment.
  • FIG. 7 is a functional block diagram illustrating a computing device in accordance with one embodiment.
  • FIG. 8 is a cross-sectional view of an interposer implementing one or more embodiments.
  • Embodiments discussed herein variously provide techniques and mechanisms for bonding layers of a substrate using an addition reaction between respective molecules of two monolayers.
  • the term "monolayer” refers herein to a film of a given molecule, wherein the film is only one molecule thick on a surface structure.
  • Self-assembled monolayer (or “SAM”) refers herein to a monolayer formed by a reaction at a surface, wherein such reaction results in the monolayer molecules lining up in a uniform manner. More particularly, molecules may "self assemble” by each forming a respective highly selective bond at the surface and orientate itself perpendicular to the face of the surface. Through such a reaction a uniform monolayer film may be formed.
  • a molecule (or molecules) of the monolayer refers herein to those molecules which each of the majority molecule type in the monolayer.
  • addition reaction refers herein to a reaction between two molecules which combine to form, as a single reaction product (the "adduct"), a larger molecule which includes all atoms of the two molecules - e.g., where the reaction does not further produce any other by-product.
  • the reaction does not further produce any other by-product.
  • some embodiments variously provide for very strong bonding that, for example, may be tailored to a particular combination of material layers which are to be joined together.
  • Non-limiting examples of electronic devices that may utilize the technologies described herein include any kind of mobile device and/or stationary device, such as cameras, cell phones, computer terminals, desktop computers, electronic readers, facsimile machines, kiosks, netbook computers, notebook computers, internet devices, payment terminals, personal digital assistants, media players and/or recorders, servers (e.g., blade server, rack mount server, combinations thereof, etc.), set-top boxes, smart phones, tablet personal computers, ultra-mobile personal computers, wired telephones, combinations thereof, and the like. Such devices may be portable or stationary.
  • mobile device and/or stationary device such as cameras, cell phones, computer terminals, desktop computers, electronic readers, facsimile machines, kiosks, netbook computers, notebook computers, internet devices, payment terminals, personal digital assistants, media players and/or recorders, servers (e.g., blade server, rack mount server, combinations thereof, etc.), set-top boxes, smart phones, tablet personal computers, ultra-mobile personal computers, wired telephones, combinations thereof, and the like.
  • servers
  • the technologies described herein may be employed in a desktop computer, laptop computer, smart phone, tablet computer, netbook computer, notebook computer, personal digital assistant, server, combinations thereof, and the like. More generally, the technologies described herein may be employed in any of a variety of electronic devices including a substrate having patterned metallization structures.
  • FIG. 1 illustrates features of a substrate 100 which, in accordance with an embodiment, includes structures that are bonded to each other with a monolayer of a compound.
  • FIG. 1 also includes a cross-sectional detail side view 104 illustrating structures of substrate 100.
  • Substrate 100 is one example of an embodiment comprising metallization structures and one or more organic insulator materials which provide electrical isolation between various ones of said metallization structures.
  • substrate 100 may be a package substrate or a printed circuit board (PCB).
  • a first layer and a second layer of substrate 100 may be bonded together by a monolayer of a compound which is an adduct produced by an addition reaction of two monolayers.
  • metallization structures of substrate 100 include horizontal layers 122 of patterned conductive traces - e.g,. where layers 122 variously extend in parallel with the xy plane of the xyz coordinate system shown. Such metallization structures may further include vias (or metal traces) 124 which variously extend vertically (e.g., along the z-axis) to couple respective ones of layers 122 to each other.
  • Layers 122 and vias 124 - e.g,. comprising copper, aluminum, nickel, gold, silver and/or any of various other conductor materials - may facilitate electrical connectivity with one or each of two opposite sides 1 10, 1 12 of substrate 100.
  • connectivity with substrate 100 e.g., through substrate 100
  • conductive contacts e.g., including the illustrative pads 126 shown
  • insulator layers 120 may promote electrical isolation of various ones of layers 122 and/or various ones of vias 124.
  • insulator layers 120 include any of a variety of dielectric compounds used, for example, in conventional package substrates and/or PCBs. Such compounds may include, but are not limited to, polyimide (PI), polytetrafluoroethylene (PTFE), Build-up Film (in general, any of various silica particle filled epoxy materials), a liquid crystal polymer (LCP), and polyetheretherketone (PEEK).
  • insulator layers 120 include a laminate material such as FR4, FR5, bismaleimide triazine (BT) resin, etc.
  • Substrate 100 may have a woven or reinforced core (not shown) or - alternatively - may be coreless, in various embodiments.
  • Cross-sectional detail side view 104 illustrates structures that, for example, may be found in a region 102 of substrate 100.
  • a metallization layer 140 may comprise metallization structures - such as the illustrative structures 142 - that, for example, include one of layers 122 and/or various ones of vias 124.
  • Metallization layer 140 may be disposed on a dielectric layer 130 (such as one of insulator layers 120), wherein one of metallization layer 140 and dielectric layer 130 includes a first surface portion.
  • the first surface portion may be a surface portion of dielectric layer 130 which is in one of the interface regions 152 shown.
  • the first surface portion may be a surface portion of metallization structures 142 in one of the interface regions 162, 164 shown.
  • another dielectric layer 134 may be disposed on one or both of metallization layer 140 and dielectric layer 130.
  • Dielectric layer 134 may include a second surface portion which is in the same one of interface regions 152, 162, 164 as is the first surface portion.
  • the second surface portion may be bonded to the first surface portion via a monolayer of a compound.
  • the monolayer of the compound may, for example, be an artifact of a process to bond various ones of metallization layer 140 and dielectric layers 130, 134 to each other. More particularly, in some embodiments, a molecule of the compound is the same as an adduct molecule which may be produced by an addition reaction between two molecules which are each capable of forming a respective monolayer.
  • a first monolayer 150 extending in some or all of interface regions 150, may facilitate at least in part a bonding of dielectric layers 130, 134 to one another.
  • a second monolayer 160 extending in one or both of interface regions 162, 164, may facilitate at least in part a bonding of metallization layer 140 and dielectric layer 134 to one another.
  • First monolayer 150 and second monolayer 160 may be contiguous with one another and/or may each include the same type of molecule, although some embodiments are not limited in this regard.
  • FIG. 1 also shows, in cross-sectional detail side views, respective stages 106, 108 of one example process to form a monolayer such as first monolayer 150 and/or second monolayer 160.
  • molecules of a monolayer 170 may be attached to a side 132 of dielectric layer 130, wherein molecules of another monolayer 172 are attached to a side 136 of dielectric layer 134.
  • molecules of monolayer 170 are additionally or alternatively attached to one or more metallization structures 142 for subsequent bonding of metallization layer 140 with dielectric layer 134.
  • a SAM molecule may comprise a head group which is to anchor to a surface, a terminal group that is to provide a reaction site, and a molecular chain (referred to herein as a "tail") which extends between the head group and the terminal group.
  • the head group and tail group are represented symbolically with circles and diamonds (respectively) in the view of stage 106.
  • the head group and tail group for monolayer 172 are represented symbolically with squares and triangles, respectively.
  • a head group of a SAM molecule may include any of a variety of groups to facilitate reaction which attaches the SAM molecule to a surface such as that of a dielectric material or a metallization structure. SAM molecules may adhere to such a surface through chemisorption or physisorption, for example. Examples of such groups include, but are not limited to, a thiol group (-SH), a silanol group (-Si(OH) x ), an amine group (-NH2), a hydroxy group (-OH), a carboxyl group (-COOH), a methyl group (CH3), or any such functional group capable of adhering to respective layer.
  • groups include, but are not limited to, a thiol group (-SH), a silanol group (-Si(OH) x ), an amine group (-NH2), a hydroxy group (-OH), a carboxyl group (-COOH), a methyl group (CH3), or any such functional group capable
  • SAM molecules have the same type of functional group for both the head group and the terminal group.
  • a tail group of a SAM molecule may similarly include any of a variety of such reactive groups.
  • the tail of a SAM molecule comprises a hydrophobic molecular chain, such as (-CH2-)n, (-CF 2 ) n , or any of various other organic chain structures.
  • monolayers 170, 172 may be brought in contact with one another to facilitate an addition reaction thereof.
  • An adduct produced by such reaction may form the resulting monolayer 174 (e.g., including some or all of monolayers 150, 160).
  • the respective terminal groups of monolayers 170, 172 may be susceptible to an addition reaction with each other.
  • groups are referred to herein as being "complementary" to one another.
  • complementary pairs of terminal groups include, but are not limited to, an epoxy/amine group pair (for reaction between an epoxy group and an amine group), a hydroxyl/epoxy group pair, an amine/carboxyl group pair, and an alkyne/azide group pair.
  • reaction between monolayers 170, 172 includes any of various Diels-Alder reactions or any other click chemistry reactions that form adduct products or produce a minimum amount of by-products.
  • FIG. 2 shows features of a method 200 to bond layers of a substrate according to an embodiment.
  • Method 200 may include processes to fabricate some or all of the structure of substrate 100, for example. To illustrate certain features of various embodiments, method 200 is described herein with reference to structures shown in FIG. 3. However, any of a variety of additional or alternative structures may be fabricated according to method 200, in different embodiments.
  • method 200 may include, at 210, forming a patterned metallization layer on a first dielectric layer, wherein one of the patterned metallization layer and the first dielectric layer includes a first surface portion.
  • a patterned metallization layer on a first dielectric layer, wherein one of the patterned metallization layer and the first dielectric layer includes a first surface portion.
  • FIG. 3 cross-sectional side views are shown for respective stages 300-303 of processing to adhere layers of a substrate according to an embodiment. Processing such as which includes stages 300-303 may, for example, bond some or all of metallization layer 140 and dielectric layer 130, 134 to each other.
  • a metallization layer 320 may be disposed on a side 312 of a layer 310.
  • Metallization layer 320 may include patterned metallization structures 322 that, for example, have been formed by metal deposition - e.g., including electroplating, electroless deposition or the like - and subsequent etching of the deposited metal through a patterned mask (not shown).
  • Metallization layer 320 may include copper (Cu), gold (Au), silver (Ag), aluminum (Al), platinum (Pt), nickel (Ni) and/or any of a variety of other metals (e.g., wherein metallization layer 320 may include a metal oxide).
  • Layer 310 may include a dielectric material which includes any of a variety of functional groups - e.g., such as, but not limited to a hydroxide group, epoxide group, carboxyl group, amine group, thiol group - to which SAM molecules may adhere.
  • a hydroxide group e.g., such as, but not limited to a hydroxide group, epoxide group, carboxyl group, amine group, thiol group - to which SAM molecules may adhere.
  • Method 200 may further comprise, at 220, forming on the first surface portion a first monolayer of first molecules.
  • a SAM 330 may be formed on exposed portions of side 312 and/or one or more respective surfaces of metallization structures 322 - e.g., some or all of which may include the first surface portion. Formation of SAM 330 may include dip-coating, spray coating, atomic layer deposition, chemical vapor deposition and/or other processes adapted, for example, from conventional techniques. It is to be appreciated that a linker compound may be utilized to promote chemisorption by a metal (of metallization structures 322, for example) with molecules of SAM 330.
  • method 200 further includes, at 230, disposing a second monolayer of second molecules on the first monolayer.
  • another SAM 340 may be disposed on SAM 330 to facilitate an addition reaction between the two.
  • SAM 340 may be disposed on a side of a layer 350 that, for example, includes a dielectric material to facilitate electrical isolation of metallization structures 322.
  • SAM 340 may be brought into contact with SAM 330 while layer 350 is coupled to SAM 340.
  • Layers 310, 350 may correspond functionally to dielectric layers 130, 134, for example.
  • method 200 may couple the first surface portion to a second surface portion of a second dielectric layer, including performing first addition reactions between respective ones of the first molecules and respective ones of the second molecules.
  • a first molecule of SAM 330 may include a terminal group that is susceptible to an addition reaction with a terminal group of a second molecule, wherein SAM 340 includes the second molecule.
  • reaction between SAM 330 and SAM 340 may result in the formation of a SAM 360 which is attached to both layer 350 and one or both of layer 310 and some or all metallization structures 322.
  • a molecule of SAM 360 may be an adduct which includes all atoms of the first molecule and all atoms of the second molecule.
  • Reactivity between SAMs 330, 340 may facilitate a click chemistry to form SAM 360.
  • click chemistry includes a Diels-Alder reaction, an azide- alkyne cycloaddition reaction, or a nucleophilic opening of an epoxide group or an aziridine group.
  • click chemistry with SAMs 330, 340 includes non-Aldol type carbonyl chemistry, or an addition reaction of an alkene group and an alkyne group.
  • a Diels-Alder cycloaddition reaction between an alkyne terminal group of SAM 330 and a pyrrole terminal group of SAM 340 may form a cyclodiene adduct.
  • an azide-alkyne cycloaddition type click reaction may include an alkyne terminal group of SAM 330 reacting with an azide terminal group of SAM 340.
  • any of a variety of other click chemistry reactions may be provided to form SAM 360, in other embodiments.
  • Formation of SAM 360 may include exposing SAMs 330, 340 to one or more conditions (e.g., including UV light, heat, pressure and/or the presence of a metal catalyst) to promote reaction between SAM 330 and SAM 340.
  • one or more conditions e.g., including UV light, heat, pressure and/or the presence of a metal catalyst
  • an azide-alkyne cycloaddition reaction may be promoted by a warm temperature - e.g., at least 80 degrees Celsius (D C) - by application of light pressure, and/or in the presence of a Cu(I) catalyst.
  • method 200 may further comprise additional processing (not shown) to facilitate electrical connectivity with some or all of the patterned metallization layer 320.
  • additional processing such as etching, planarization, or the like
  • any of a variety of subtractive processes may be performed to remove portions of layer 350 and/or portions of SAM 360 - e.g., wherein a remaining portion 352 of layer 350 leaves respective surfaces 324 of metallization structures 322 exposed for later electrical coupling.
  • bonding of substrate structures includes performing addition reactions between different pairs of molecules types.
  • FIG. 4 cross-sectional side views are shown for respective stages 400-403 of processing to adhere layers of a substrate according to an embodiment. Processing such as that which includes stages 400-403 may, for example, include some or all of the features of method 200.
  • a metallization layer 420 may be disposed on a side 412 of a layer 410.
  • Metallization layer 420 may include patterned metallization structures 422 that, for example, have been formed by metal deposition and subsequent etching of the deposited metal through a patterned mask (not shown).
  • Layer 410 may include a dielectric material to which SAM molecules may adhere.
  • a SAM 430 may be formed on exposed portions of side 412, wherein a different SAM 432 is instead disposed on one or more of the respective surfaces of metallization structures 422.
  • Molecules of SAM 430 may each include a head group which provides bonding to a dielectric material of layer 410.
  • molecules of SAM 432 may instead include a different head group which is more effective at bonding to a metal surface metallization structures 422.
  • Masked deposition techniques may be adapted to provide for the selective formation of SAMs 430, 432 on different respective material surface portions of side 412 and metallization structures 422.
  • SAMs 440, 442 may be disposed, respectively, on SAMs 430, 432 to facilitate various addition reactions to facilitate adhering of layer 450.
  • SAM 440 may be disposed one or more regions, on a side of a layer 450, which are to align with regions of SAM 430.
  • SAM 442 may be disposed in one or more other regions, on the same side of layer 450, which are instead to align with regions of SAM 432.
  • molecules of SAM 440 and molecules of SAM 442 may include respective groups which variously provide bonding to a dielectric material of layer 450.
  • Molecules of SAM 430 and molecules of SAM 440 may include respective terminal groups which are complementary to each other at least insofar as they are prone to first type of addition reaction with each other.
  • molecules of SAM 432 and molecules of SAM 442 may include respective tail group which are complementary to each other, enabling a second type of addition reaction with each other.
  • a first addition reaction between SAM 430 and SAM 440 may result in the formation of a SAM 460 which is attached to both layer 450 and to one or more surface portions layer 410.
  • a second addition reaction between SAM 432 and SAM 442 may result in the formation of a SAM 462 which is attached to both layer 450 and to one or more surface portions of metallization structures 422.
  • the first addition reaction and the second addition reaction may variously include respective characteristics of SAM reactions which are described herein.
  • a single SAM - disposed on one surface - is to bond with multiple SAMs which are each disposed on another surface.
  • respective molecules of the multiple SAMs may have the same terminal group or similar terminal groups, wherein the single SAM is complementary to the terminal group or groups.
  • each of SAMs 440, 442 may alternatively include the same type of molecule, the terminal groups of which are complementary to both terminal groups of SAM 430 and terminal groups of SAM 432.
  • SAMs 460, 462 formed by respective types of addition reactions may include different respective molecules which, nevertheless, variously bond to layer 450 via the same type of functional group.
  • FIG. 5 shows stages 500, 501 of an addition reaction between self-assembled monolayers to bond structures of a substrate according to an embodiment.
  • the reaction illustrated by stages 500, 501 may be performed to form one of SAMs 360, 460, 462, for example. In an embodiment, such a reaction may bond structures of substrate 100 - e.g., according to method 200.
  • a SAM 512 may be exposed to another SAM 522 to facilitate the addition reaction. Molecules of SAM 512 may include a trihydroxysilyl head group (-Si(OH)3) to bond with a surface of a dielectric 510.
  • -Si(OH)3 trihydroxysilyl head group
  • Molecules of SAM 522 may include a hydroxyl head group -(OH) to bond with a surface of another dielectric 520.
  • a Diels-Alder cycloaddition reaction between SAMs 512, 522 includes reaction between an alkyne terminal group of SAM 522 and a pyrrole terminal group of SAM 512. As shown at stage 501, such a Diels-Alder cycloaddition reaction may result in the formation of a SAM 530, wherein adduct molecules of SAM 530 include a
  • FIG. 6 shows stages 600, 601 of an addition reaction between self-assembled monolayers to bond structures of a substrate according to another embodiment.
  • the reaction illustrated by stages 600, 601 may be performed to form one of SAMs 360, 460, 462 - e.g., to bond structures of substrate 100 according to method 200.
  • a SAM 612 may be exposed to another SAM 622 to facilitate the addition reaction.
  • Molecules of SAM 612 may include a trihydroxysilyl head group (-Si(OH)3) to bond with a surface of a dielectric 610.
  • Molecules of SAM 622 may include a hydroxyl head group -(OH) to bond with a surface of another dielectric 620.
  • an azide-alkyne cycloaddition type click reaction between SAMs 612, 622 includes reaction between an alkyne terminal group of SAM 622 and an azide terminal group of SAM 612. As shown at stage 601, such an azide-alkyne
  • cycloaddition reaction may result in the formation of a SAM 630, wherein adduct molecules of SAM 630 includes a triazole group.
  • FIG. 7 illustrates a computing device 700 in accordance with one embodiment.
  • the computing device 700 houses a board 702.
  • the board 702 may include a number of components, including but not limited to a processor 704 and at least one communication chip 706.
  • the processor 704 is physically and electrically coupled to the board 702.
  • at least one communication chip 706 is also physically and electrically coupled to the board 702.
  • the communication chip 706 is part of the processor 704.
  • computing device 700 may include other components that may or may not be physically and electrically coupled to the board 702. These other components include, but are not limited to, volatile memory (e.g., DRAM), nonvolatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).
  • volatile memory e.g., DRAM
  • nonvolatile memory e.g., ROM
  • flash memory e.g., a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display,
  • the communication chip 706 enables wireless communications for the transfer of data to and from the computing device 700.
  • wireless and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
  • the communication chip 706 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond.
  • the computing device 700 may include a plurality of communication chips 706.
  • a first communication chip 706 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 706 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
  • the processor 704 of the computing device 700 includes an integrated circuit die packaged within the processor 704.
  • the term "processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
  • the communication chip 706 also includes an integrated circuit die packaged within the communication chip 706.
  • the computing device 700 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder.
  • the computing device 700 may be any other electronic device that processes data.
  • Some embodiments may be provided as a computer program product, or software, that may include a machine-readable medium having stored thereon instructions, which may be used to program a computer system (or other electronic devices) to perform a process according to an embodiment.
  • a machine-readable medium includes any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer).
  • a machine-readable (e.g., computer-readable) medium includes a machine (e.g., a computer) readable storage medium (e.g., read only memory (“ROM”), random access memory (“RAM”), magnetic disk storage media, optical storage media, flash memory devices, etc.), a machine (e.g., computer) readable transmission medium (electrical, optical, acoustical or other form of propagated signals (e.g., infrared signals, digital signals, etc.)), etc.
  • ROM read only memory
  • RAM random access memory
  • magnetic disk storage media e.g., magnetic disks, optical storage media, flash memory devices, etc.
  • a machine (e.g., computer) readable transmission medium electrical, optical, acoustical or other form of propagated signals (e.g., infrared signals, digital signals, etc.)
  • FIG. 8 illustrates an interposer 800 that includes one or more embodiments.
  • the interposer 800 is an intervening substrate used to bridge a first substrate 802 to a second substrate 804.
  • the first substrate 802 may be, for instance, an integrated circuit die.
  • the second substrate 804 may be, for instance, a memory module, a computer motherboard, or another integrated circuit die.
  • the purpose of an interposer 800 is to spread a connection to a wider pitch or to reroute a connection to a different connection.
  • an interposer 800 may couple an integrated circuit die to a ball grid array (BGA) 806 that can subsequently be coupled to the second substrate 804.
  • BGA ball grid array
  • first and second substrates 802, 804 are attached to opposing sides of the interposer 800. In other embodiments, the first and second substrates 802, 804 are attached to the same side of the interposer 800. And in further embodiments, three or more substrates are interconnected by way of the interposer 800.
  • the interposer 800 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further implementations, the interposer may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. [0057] The interposer may include metal interconnects 808 and vias 810, including but not limited to through-silicon vias (TSVs) 812. The interposer 800 may further include embedded devices 814, including both passive and active devices.
  • TSVs through-silicon vias
  • Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer 800. In accordance with some embodiments, apparatuses or processes disclosed herein may be used in the fabrication of interposer 800.
  • RF radio-frequency
  • apparatuses or processes disclosed herein may be used in the fabrication of interposer 800.
  • a circuit device comprises a first dielectric layer, a patterned metallization layer on the first dielectric layer, wherein one of the patterned metallization layer and the first dielectric layer includes a first surface portion, and a second dielectric layer including a second surface portion bonded to the first surface portion via a first monolayer of a first compound, wherein a molecule of the first compound is a chemical equivalent to an adduct produced by a first addition reaction between a first molecule of a second monolayer and a second molecule of a third monolayer.
  • the first addition reaction includes a Diels-Alder reaction. In another embodiment, the first addition reaction includes an azide-alkyne cycloaddition reaction. In another embodiment, the first addition reaction includes a nucleophilic opening of an epoxide group or an aziridine group. In another embodiment, the first addition reaction includes a reaction of an alkene group and an alkyne group.
  • the other of the patterned metallization layer and the first dielectric layer includes a third surface portion, wherein the third surface portion is bonded to a fourth surface portion of the second dielectric layer via a fourth monolayer, wherein a molecule of the fourth monolayer is a chemical equivalent to another adduct produced by a second addition reaction between a fifth molecule of a fifth monolayer and a sixth molecule of a sixth monolayer.
  • one of the first addition reaction or the second addition reaction includes a Diels-Alder reaction.
  • one of the first addition reaction or the second addition reaction includes an azide-alkyne cycloaddition reaction.
  • one of the first addition reaction or the second addition reaction includes a reaction of an alkene group and an alkyne group.
  • a method comprises forming a patterned metallization layer on a first dielectric layer, wherein one of the patterned metallization layer and the first dielectric layer includes a first surface portion, forming on the first surface portion a first monolayer of first molecules, disposing a second monolayer of second molecules on the first monolayer, and coupling the first surface portion to a second surface portion of a second dielectric layer, including performing first addition reactions between respective ones of the first molecules and respective ones of the second molecules.
  • performing the first addition reactions includes performing Diels-Alder reactions. In another embodiment, performing the first addition reactions includes performing an azide-alkyne cycloaddition reaction. In another embodiment, performing the first addition reactions includes performing a nucleophilic opening of an epoxide group or an aziridine group. In another embodiment, performing the first addition reactions includes performing a reaction of an alkene group and an alkyne group.
  • the other of the patterned metallization layer and the first dielectric layer includes a third surface portion
  • the method further comprises forming on the third surface portion a third monolayer of third molecules, disposing a fourth monolayer of fourth molecules on the third monolayer, and coupling the third surface portion to a fourth surface portion of the second dielectric layer, including performing second addition reactions between respective ones of the third molecules and respective ones of the fourth molecules.
  • one of the first addition reaction or the second addition reaction includes a Diels-Alder reaction.
  • one of the first addition reaction or the second addition reaction includes an azide-alkyne cycloaddition reaction.
  • one of the first addition reaction or the second addition reaction includes a reaction of an alkene group and an alkyne group.
  • a system comprises a circuit device comprising a first dielectric layer, a patterned metallization layer on the first dielectric layer, wherein one of the patterned metallization layer and the first dielectric layer includes a first surface portion, and a second dielectric layer including a second surface portion bonded to the first surface portion via a first monolayer of a first compound, wherein a molecule of the first compound is a chemical equivalent to an adduct produced by a first addition reaction between a first molecule of a second monolayer and a second molecule of a third monolayer.
  • the system further comprises a display device to display an image based on a signal communicated with the circuit device.
  • the first addition reaction includes a Diels-Alder reaction. In another embodiment, the first addition reaction includes an azide-alkyne cycloaddition reaction. In another embodiment, the first addition reaction includes a nucleophilic opening of an epoxide group or an aziridine group. In another embodiment, the first addition reaction includes a reaction of an alkene group and an alkyne group.
  • the other of the patterned metallization layer and the first dielectric layer includes a third surface portion, wherein the third surface portion is bonded to a fourth surface portion of the second dielectric layer via a fourth monolayer, wherein a molecule of the fourth monolayer is a chemical equivalent to another adduct produced by a second addition reaction between a fifth molecule of a fifth monolayer and a sixth molecule of a sixth monolayer.
  • one of the first addition reaction or the second addition reaction includes a Diels-Alder reaction.
  • one of the first addition reaction or the second addition reaction includes an azide-alkyne cycloaddition reaction.
  • one of the first addition reaction or the second addition reaction includes a reaction of an alkene group and an alkyne group.
  • inventions also relate to apparatus for performing the operations herein.
  • This apparatus may be specially constructed for the required purposes, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer.
  • a computer program may be stored in a computer readable storage medium, such as, but is not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs) such as dynamic RAM (DRAM), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, and coupled to a computer system bus.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

L'invention concerne des techniques et des mécanismes pour lier des couches d'un substrat à l'aide d'une monocouche d'un composé. Dans un mode de réalisation, une première monocouche de premières molécules est disposée sur une couche parmi une couche diélectrique et une couche de métallisation, une deuxième monocouche de troisièmes molécules étant disposée sur une autre couche diélectrique. Une réaction d'addition entre la première monocouche et la deuxième monocouche produit un premier adduit qui forme une troisième monocouche pour lier des parties de surface respectives les unes aux autres. Dans un autre mode de réalisation, une troisième monocouche de troisièmes molécules est disposée sur une couche parmi la couche diélectrique et la couche de métallisation, une quatrième monocouche de quatrièmes molécules étant également disposée sur l'autre couche diélectrique. Une seconde réaction d'addition entre la troisième monocouche et la quatrième monocouche produit un second adduit qui forme une autre monocouche pour lier davantage les parties de surface respectives les unes aux autres.
PCT/US2017/053787 2017-09-27 2017-09-27 Procédé de liaison utilisant des réactions entre des monocouches WO2019066814A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/US2017/053787 WO2019066814A1 (fr) 2017-09-27 2017-09-27 Procédé de liaison utilisant des réactions entre des monocouches

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2017/053787 WO2019066814A1 (fr) 2017-09-27 2017-09-27 Procédé de liaison utilisant des réactions entre des monocouches

Publications (1)

Publication Number Publication Date
WO2019066814A1 true WO2019066814A1 (fr) 2019-04-04

Family

ID=65902611

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2017/053787 WO2019066814A1 (fr) 2017-09-27 2017-09-27 Procédé de liaison utilisant des réactions entre des monocouches

Country Status (1)

Country Link
WO (1) WO2019066814A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022108710A1 (fr) * 2020-10-27 2022-05-27 Applied Materials, Inc. Dépôt de couches atomiques sélectif en surface de couches de passivation

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5639555A (en) * 1993-12-08 1997-06-17 Mcgean-Rohco, Inc. Multilayer laminates
US20050017759A1 (en) * 2003-05-28 2005-01-27 Infineon Technologies Ag Circuit element having a first layer of an electrically insulating substrate material and method for manufacturing a circuit element
US20060289115A1 (en) * 2005-06-22 2006-12-28 Changchun Institute Of Applied Chemistry Chinese Academy Of Science Method for bonding two solid planes via surface assembling of active functional groups
WO2010095046A2 (fr) * 2009-02-21 2010-08-26 Sofradim Production Dispositifs médicaux incorporant des adhésifs fonctionnels
US20130319610A1 (en) * 2010-08-13 2013-12-05 Forschungszentrum Juelich Gmbh Method for applying a first metal onto a second metal, an isolator or semiconductor substrate, and the respective binding units
US20160027373A1 (en) * 2014-07-24 2016-01-28 Samsung Electronics Co., Ltd. Display apparatus, power control module and power control method thereof

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5639555A (en) * 1993-12-08 1997-06-17 Mcgean-Rohco, Inc. Multilayer laminates
US20050017759A1 (en) * 2003-05-28 2005-01-27 Infineon Technologies Ag Circuit element having a first layer of an electrically insulating substrate material and method for manufacturing a circuit element
US20060289115A1 (en) * 2005-06-22 2006-12-28 Changchun Institute Of Applied Chemistry Chinese Academy Of Science Method for bonding two solid planes via surface assembling of active functional groups
WO2010095046A2 (fr) * 2009-02-21 2010-08-26 Sofradim Production Dispositifs médicaux incorporant des adhésifs fonctionnels
US20130319610A1 (en) * 2010-08-13 2013-12-05 Forschungszentrum Juelich Gmbh Method for applying a first metal onto a second metal, an isolator or semiconductor substrate, and the respective binding units
US20160027373A1 (en) * 2014-07-24 2016-01-28 Samsung Electronics Co., Ltd. Display apparatus, power control module and power control method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022108710A1 (fr) * 2020-10-27 2022-05-27 Applied Materials, Inc. Dépôt de couches atomiques sélectif en surface de couches de passivation
US11569088B2 (en) 2020-10-27 2023-01-31 Applied Materials, Inc. Area-selective atomic layer deposition of passivation layers

Similar Documents

Publication Publication Date Title
US11887946B2 (en) Semiconductor packages with antennas
US10770387B2 (en) Integrated circuit package substrate
US9299602B2 (en) Enabling package-on-package (PoP) pad surface finishes on bumpless build-up layer (BBUL) package
US11495873B2 (en) Device comprising multi-directional antennas in substrates coupled through flexible interconnects
US11728077B2 (en) Magnetic material having coated ferromagnetic filler particles
US11177234B2 (en) Package architecture with improved via drill process and method for forming such package
US11094587B2 (en) Use of noble metals in the formation of conductive connectors
WO2019066814A1 (fr) Procédé de liaison utilisant des réactions entre des monocouches
US11289263B2 (en) Electronic substrates having embedded magnetic material using photo-imagable dielectric layers
EP4057783A1 (fr) Matériau de promotion d'adhésion diélectrique au métal
US9824962B1 (en) Local dense patch for board assembly utilizing laser structuring metallization process
US11177232B2 (en) Circuit device with monolayer bonding between surface structures
US11528811B2 (en) Method, device and system for providing etched metallization structures
WO2019066815A1 (fr) Substrat avec élément de circuit résistif intégré et son procédé de fourniture

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17926404

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 17926404

Country of ref document: EP

Kind code of ref document: A1