WO2019063289A1

WO2019063289A1 - Method for operating an actuation device for an inductive load

Info

Publication number: WO2019063289A1
Application number: PCT/EP2018/074587
Authority: WO
Inventors: Stefan Koch; Thomas Malich; Michael Wendl
Original assignee: Robert Bosch Gmbh
Priority date: 2017-09-28
Filing date: 2018-09-12
Publication date: 2019-04-04
Also published as: DE102017217260A1

Abstract

The invention relates to a method for operating an actuation device (100) for an inductive load (30), wherein the actuation device (100) is formed as a half bridge with two MOS-FETs (10, 20) and a connecting point of the two MOS-FETs (10, 20) is galvanically connected to the inductive load (30), the method having the following, cyclically performed steps: - with a positive phase current, where electrical current flows from the half bridge into the inductive load (30): a) in the event of an electrical current flow after high-resistance switching of the HS-MOS-FET (10) via the intrinsic diode of the LS-MOS-FET (20): - subsequent activation of the LS-MOS-FET (20) in a defined rapid manner; b) in the event of an electrical current flow after high-resistance switching of the LS-MOS-FET (20) via the intrinsic diode of the LS-MOS-FET (20): - subsequent activation of the HS-MOS-FET (10) in a defined slow manner; - with a negative electrical phase current, where electrical current flows from the inductive load (30) into the half bridge: a) in the event of an electrical current flow after high-resistance switching of the LS-MOS-FET (20) via the intrinsic diode of the HS-MOS-FET (10); - subsequent activation of the HS-MOS-FET (10) in a defined rapid manner; b) in the event of an electrical current flow after high-resistance switching of the HS-MOS-FET (10) via the intrinsic diode of the HS-MOS-FET; - subsequent activation of the LS-MOS-FET (20) in a defined slow manner.

Description

Description title

Method for operating a drive device for an inductive load

The invention relates to a method for operating a drive device for an inductive load. The invention further relates to a drive device for cyclically driving an inductive load. The invention further relates to a computer program product.

State of the art

Engine cooling fans are part of a thermal management, e.g. of internal combustion engines. The cooling fan is driven by an electronically commutated motor. The motor topology is usually designed such that a B6 bridge can be used for driving. The B6 bridge generates the necessary (variant) electrical voltage levels at the motor terminals by means of pulse width modulated control signals.

As a rule, the engine cooling fan with an electrical supply voltage of approx. 8V ... approx. 16V from a low voltage electrical network ("electrical on-board voltage") of the vehicle operated.

The pulse-width-modulated drive method of the B6 bridge disadvantageously generates losses in the semiconductor power devices. Loss-power components of semiconductor switching elements of the B6 bridge in the form of MOS-FETs are, for example:

- Lead losses

- Diode conduction losses

- Switching losses - Reverse recovery losses when clearing charge carriers from the intrinsic diode of the MOS-FETs

The setting of the variant electrical voltage level at the motor terminals generated at the supply voltage terminals, among others

high-frequency interference emissions (CEV).

Efficiency, power dissipation and the amount of emitted interference are important technical parameters of the B6 bridge or of the electrical product controlled by the B6 bridge.

Disclosure of the invention

An object of the invention is therefore to provide an improved method for

Operate to provide a drive device for an inductive load.

The object is achieved according to a first aspect with a method for operating a drive device for an inductive load, wherein the drive device is designed as a half bridge with two MOS FETs, wherein a connection point of the two MOS FETs is galvanically connected to the inductive load, comprising the following cyclical steps: with positive electric phase current, with electric current flowing from the half-bridge into the inductive load:

a) in the case of an electric current flow after high-resistance switching of the HS-MOS-FETs via the intrinsic diode of the LS-MOS-FETs:

the following defines fast switching on of the LS-MOS-FETs b) in the case of an electric current flow after high-resistance switching of the LS-MOS-FETs via the intrinsic diode of the LS-MOS-FETs:

- the following defines slow turn-on of the HS-MOS-FETs; with negative electric phase current, with electric current flowing from the inductive load into the half-bridge:

a) in the case of an electric current flow after high-resistance switching of the LS-MOS-FETs via the intrinsic diode of the HS-MOS-FETs: the following defines fast switching on of the HS-MOS-FET b) in the case of an electric current flow after high-resistance switching of the HS-MOS-FET via the intrinsic diode of the HS-MOS-FET:

- the following defines slow switching on of the LS-MOS-FETs.

In this way, the lowest possible EMC emission is generated by means of the low-side MOS FETs when performing a large voltage swing. This defines fast switching on of the MOS FETs when performing a small voltage swing advantageously generates a low EMC emission with low power loss.

In this way, the electronic switching elements are specifically operated so that the lowest possible losses are generated by the rapid switching of the MOSFETs with component-internal commutation of the current from diode to the channel of the MOS-FETs. Advantageously, this supports the fact that, for the electronic switching elements in the form of the MOS FETs, they remain below the maximum permissible temperature of the barrier layer (English, junction temperature). Relatively little EMC-relevant interference is generated by the fact that the switched voltage gradient is rather low. Relatively low power losses are produced by keeping a duration of an electric current flow via the current line through the intrinsic diode as short as possible.

In this way, a low-loss operation of the drive device for the inductive load is provided because drive operations for the semiconductor power devices are designed low. Suppressor can be designed inexpensively in this way.

According to a second aspect, the invention is achieved with a drive device for cyclically driving an inductive load comprising:

at least one half-bridge having a high-side MOS-FET and a low-side MOS-FET, wherein a connection point of the high-side MOS FET and the low-side MOS FET is connected to the inductive load, wherein which is rapidly turned on to generate the lowest possible power dissipation of the high-side MOS FET when switching the electric current flow from the intrinsic diode of the high-side MOS FET to the electric current flow through the channel of the high-side MOS FET ; and where

is defined for generating the lowest possible EMC emission is slowly turned on, wherein

the drive device is designed to make an adaptation of the speed of the switching operation of the switched voltages depending on the size of the switched voltage swing with the aim of minimizing the losses while adhering to interference limits.

Advantageous developments of the method are the subject of dependent claims.

An advantageous development of the method provides that based on an adaptation of a voltage gradient of the switched signals of the MOS-FETS a minimization of the losses is performed. In this way, an amplitude and slope of the drive signals can be specified in such a way that operation of the electronic MOS-FET switching elements with as little loss as possible is provided.

A further advantageous development of the method provides that the minimization of the losses achieved by switching the MOS FETs is determined on the basis of an interference spectrum. In this way, the effectiveness of the control processes carried out can be verified on the basis of concrete interference spectra. For example, simulation methods can be used for this purpose.

A further advantageous embodiment of the method provides that a defined rapid turn on with about Ι ΟΟθν / μβ is performed and wherein a defined slow turn on with about 10θν / μβ is performed. In this way, specific numerical values for the terms defined for the terms "fast" and defined "slow" switching are defined. A further advantageous development of the method provides that an EC motor is activated as the inductive load. In this way, a useful application, especially in the automotive environment is provided for the process.

The invention will be described in detail below with further advantages and features with reference to several figures. All features, regardless of their representation in the description or in the figures and regardless of their relationship in the claims form the subject of the invention. The figures are particularly intended to illustrate the principles of the invention.

Disclosed method features are analogous to corresponding disclosed device features and vice versa. This means, in particular, that features, technical advantages and embodiments relating to the method result analogously from corresponding embodiments, features and advantages of the drive device and vice versa.

In the figures shows:

Fig. 1 is a schematic representation of an embodiment of a

Drive device for driving an inductive load;

Fig. 2 is a schematic diagram of an interference frequency spectrum;

Fig. 3 is a timing signal diagram with drive signals of a high

Side MOS FETs of the drive device;

4 is a time signal diagram with activation signals of the low

Side MOS FETs of the drive device; and

Fig. 5 is a schematic flow diagram of a proposed

Drive device for driving an inductive load.

Description of embodiments Fig. 1 shows a schematic diagram of an embodiment of a

Device 100 according to the invention for driving an inductive load 30.

Recognizable is a half-bridge with a high-side MOS-FET 10, which is electrically connected to a low-side MOS-FET 20. An inductive load 30 is connected to a galvanic connection point of the high-side MOS FET 10 and the low-side MOS FET 20. In this case, the inductive load 30 may be part of a winding of an electronically commutated EC motor (not shown), a DC-DC converter, a transformer winding, etc., and may preferably be used in the automotive sector.

A central idea of the invention is, in particular, to reduce a power loss during operation of said half-bridge, at the same time also electromagnetic interference emissions should be kept as low as possible. The high-side MOS-FET 10 and the low-side MOS-FET 20 are driven by a driver element 40, which by means of a current limiting or a voltage shaping explained in more detail below

Switching operations of the MOS-FETs 10, 20 controls. 2 shows a basic relationship between a switching edge steepness and a resulting interference frequency spectrum. Recognizable is a periodic signal with a period T, a rise time t _r and a duration D from the beginning of an increase to the beginning of a fall of the signal. The aim is, due to a suitable rise time tR the

Attenuation at 40 dB / decade as early as possible.

The signal level or an amplitude of this signal plays a role for the emitted electromagnetic interference spectrum, which is not shown in Fig. 2.

The driver module 40 may, for example, be known per se

Control module with various setting options for the

Edge steepness of the switched signals, e.g. by means of

Current limitation or by means of voltage shaping. For example, the driver chip 40 may have a writable register with which the maximum electrical drive current can be configured. In this way, the switching edge steepness at the switching inputs of the MOS FETs 10, 20 can be influenced.

An effect of the proposed switching of the MOS FETs 10, 20 with the resulting effect on power loss and EMC interference emissions is explained below with reference to Figures 3 and 4.

By way of example, the low-side MOS FET 20 of the drive apparatus 100 designed as a half-bridge for the electrical supply of a phase U is considered below, the electric current in the phase U being due to the inductive load

30 is assumed to be sinusoidal. This results in the following, with reference to FIG. 3 in more detail states defined in the low-side MOS FET 20th

FIG. 3 shows, in a right upper section, the area which is shown in detail in the left-hand area of FIG. 3. As a result, it can be seen that the switching operations in FIG. 3 are carried out periodically, alternately switching the low-side MOS-FET 20 and the high-side MOS-FET 10.

Fig. 3 shows a time course of the electric current I _g . The electric current is determined by means of a Rogowski coil and represents the electric current through the low-side MOS-FET 20 (channel and diode). Furthermore, FIG. 3 shows a voltage UGS which represents an electrical voltage between gate and source of the low-side MOS FET 20. Furthermore, in the figure, a time profile of an electrical voltage UDS can be seen, which is an electrical voltage between the drain and source of the low

Side MOS FETs 20 represents.

Shown is a situation in which the electrical phase current Ip _h , that is, the total electrical current of the low-side MOS FET 20 and the high-side MOS FETs 10 is positive. In a phase 1a, the low-side MOSFET 20 carries electrical current over the channel because the FET is turned on.

In this case:

P _v - f (RDSON) With:

Pv power dissipation of the low-side MOS-FET

DSON. .. Ohm ^'s resistance of the channel of the low-side MOS-FET

In a phase 2a, the low-side MOS-FET 20 carries electrical current via its intrinsic diode, since the low-side MOS-FET 20 is switched off in this time.

In this case:

In a phase 3a, the high-side MOS-FET 10 has turned on and carries electrical current through its channel, whereby the voltage UDS at the low-side MOS-FET 20 jumps to the level of the supply voltage of about 13V.

In a phase 4a, the high-side MOS-FET 10 has turned off and the low-side MOS-FET 20 carries electrical current via its intrinsic diode. Also in this case:

Pv = f (U _DS )

In a phase 5a, the high side MOS FET 10 has turned off, and the low side MOS FET 20 is supplying electric current through the channel since the low side MOS FET 20 is turned on. In this case:

Pv = f (RüSON)

FIG. 4 shows further time profiles of the signals already mentioned above in FIG. 3, with four phases 1 to 4 following one another in time being marked. A small portion in a left portion of FIG. 4 is shown enlarged in a right portion of FIG. 4.

In a phase 1, the low-side MOS-FET 20 carries electrical current through its channel, since the low-side MOS-FET 20 is turned on. In this case: Pv - f (RüSON)

In a phase 2, the low-side MOS-FET 20 turns off.

In a phase 3, the low-side MOS FET 20 is turned off. In this case:

Pv = 0

In a phase 4, the low-side MOS-FET 20 is turned on, the low-side MOS-FET 20 carries electrical current through its channel.

In the case of the low-side MOS FET 20, two different cases are therefore to be distinguished:

case 1

The electric phase current Ip _h is positive. During the transition from phase 4a to phase 5a, the low-side MOS FET 20 is turned on after the electric current has flowed through the intrinsic diode low-side MOS FETs 20.

Case 2

The electric phase current Ip _h is negative. In the transition from phase 3 to phase 4, the low-side MOS FET 20 is turned on after the electric

Current has flowed through the intrinsic diode of the high-side MOS FETs 10.

It is proposed to carry out the transition from phase 4a to phase 5a "fast" in case 1. This advantageously achieves that the electrical power loss of the low-side MOSFET 20 is minimized.

It is also proposed to perform the transition from phase 4a to phase 5a defined in case 2 "slowly", this is done to minimize the electromagnetic interference emitted in this junction due to the existing large voltage swing of about 13V. In principle, the two switch-on processes mentioned above differ with regard to their relevance with regard to the interference emission in the FM frequency spectrum. Switching on in the case of a large voltage swing has a dominant influence on the disturbance-determining voltage amplitude, while switching on with a small voltage swing hardly causes any relevant generation of a disturbance spectrum.

Case 1 LS-FET

Phase 4a: UDS ~ Uoiode (l _Ph ) ... approx. 1V (losses in the MOS-FET)

Phase 5a: UDS = RDSON ^* l _Ph .... approx. 0 to 0.5 V (losses in the MOS-FET)

Case 2 LS-FET

Phase 3: UDS = UZK - Uoiode

Phase 4: UDS = RDSON * Iph .... approx. 0 to 0.5 V.

UZK .... Electrical DC link voltage, approx. Corresponds to the electrical supply voltage

Uoiode electrical voltage at the intrinsic diode

It has been found that a turn-on speed in Case 1 affects the power dissipation of the low-side MOS FET 20 in the following way:

Phase 4a: P _v = f (U _D s, IDS) Phase 5a: Pv = f (RDsoN, IDS)

Depending on the magnitude of the electrical current IDS, as is known from the use of synchronous rectifiers, the losses in the MOSFET are clearly different.

For example, if = 60 A:

Phase 4: Pv = 0.7 V ^* 60A = 42W to phase 5a: P _v = 60A ^* 60A ^* 2mq = 7.2W It can therefore be seen that in phase 5a, the electrical power loss of the low-side MOS FETs 20 compared to the electrical power dissipation of the low-side MOS FETs 20 in phase 4 is substantially smaller, which is why it is proposed that the transition from phase 4a to perform on phase 5a defined fast. Defined "fast" in this context means, for example, an edge steepness dUDs / dt> approx. 1000 V / μβ.

It is also proposed to make the transition from phase 3 to phase 4 slower, just so long as to meet requirements regarding the interference spectrum.

In this context, "slow" can be understood to mean an edge steepness dUüs / dt <100 V / μβ.

An essential core idea of the invention therefore consists in rapidly switching on the MOS FETs 10, 20 in case 1 and switching them on slowly in case 2.

This reduces the switch-on losses and at the same time high-frequency

Emissions in the VHF range are effectively limited to the manufacturing specification.

Necessary Entstörungsmaßnahmen can thereby advantageously small

dimensioned and thus realized cost-effectively.

Proposed is thus at positive electric phase current, with electric current from the half-bridge flows into the inductive load 30: a) in the case of an electric current flow after high-resistance switching of the HS-MOS FETs 10 via the intrinsic diode of the LS-MOS-FETs 20th :

the following defines fast turn-on of the LS-MOS FET 20;

b) in the case of an electric current flow after high-resistance switching of the LS-MOS-FETs 20 via the intrinsic diode of the LS-MOS-FETs 20:

the following defines slow turn-on of the HS-MOS FET 10;

Proposed is thus at negative electric phase current, with electric current from the inductive load 30 flows into the half-bridge: a) in the case of an electric current flow after high-resistance switching of the LS-MOS-FETs 20 via the intrinsic diode of the HS-MOS-FETs 10:

the following defines fast switching on of the HS-MOS FET 10; b) in the case of an electric current flow after high-resistance switching of the HS-MOS-FETs 10 via the intrinsic diode of the HS-MOS-FETs 10:

The following defines slow switching on of the LS-MOS-FET 20.

FIG. 5 shows a basic sequence of a proposed method: In a step 200, the high-side MOS FET 10 is switched on when the electric phase current Ip _{h is} positive, with the high-side MOSFET 10 generating as little as possible Power loss of the high-side MOS FETs 10 when switching the electric current flow from the intrinsic diode of the high-side MOS FETs 10 on the electric current flow through the channel of the high-side MOS FETs 10 defines quickly turned on.

In a step 210, the low-side MOS FET 20 is switched on when the phase current Ip _{h is} negative, with the low-side MOS FET 20 being switched on slowly in order to generate the lowest possible EMC emission.

It goes without saying that due to the fact that the MOS-FETs 10, 20 are cyclically switched, the proposed principle explained above, depending on the phase position of the phase current Iph on both the low-side MOS FET 20 and on the High-side MOS FET 10 is applicable. Furthermore, it goes without saying that the described arrangement of the drive device 100 may also include a plurality of half-bridges, so that the proposed

Method e.g. also applicable to a B6 bridge. This can

For example, a device for driving an electronically commutated EC motor can be realized.

It goes without saying that the numerical values mentioned above

Flank slopes are merely exemplary and other flank slopes for the drive signals of the MOS-FETs can be used to achieve the aforementioned loss performance or interference emission minimization. Although the invention has been described above with reference to specific embodiments, it is by no means limited thereto. One skilled in the art will thus be able to alter or combine the described features without deviating from the gist of the invention.

Claims

claims

1 . Method for operating a drive device (100) for an inductive

Load (30), wherein the drive device (100) as a half-bridge with two MOS-FETs (10, 20) is formed, wherein a connection point of the two MOS-FETs (10, 20) is galvanically connected to the inductive load (30) comprising the following cyclical steps: with positive phase electric current, with electric current flowing from the half-bridge into the inductive load (30):

a) in the case of an electrical current flow after Hochohmig switching of the HS-MOS-FETs (10) via the intrinsic diode of the LS-MOS-FETs (20):

the following defines fast turn-on of the LS-MOS FET (20);

b) in the case of an electrical current flow after high-resistance switching of the LS-MOS-FETs (20) via the intrinsic diode of the LS-MOS-FETs (20):

the following defines slow turn-on of the HS-MOS FET (10); with negative electrical phase current, with electric current flowing from the inductive load (30) into the half-bridge:

a) in the case of an electric current flow after high-resistance switching of the LS-MOS-FETs (20) via the intrinsic diode of the HS-MOS-FETs (10):

- the following defines fast turn-on of the HS-MOS FET (10); b) in the case of an electrical current flow after high-resistance switching of the HS-MOS-FETs (10) via the intrinsic diode of the HS-MOS-FETs (10):

- the following defines slow activation of the LS-MOS-FET (20).

2. The method of claim 1, wherein based on an adaptation of a

Voltage slope of the switched signals of the MOS-FETs (10, 20) a

Minimization of losses is carried out. Method according to claim 1 or 2, wherein the minimization of the losses achieved from the switching of the MOS-FETs (10, 20) is determined by means of an interference spectrum.

Method according to one of the preceding claims, wherein a defined rapid turn-on with about ΙΟΟθν / μβ is performed and wherein a defined slow turn on with about ΙΟθν / μβ is performed.

Method according to one of the preceding claims, wherein as inductive load (30) an EC motor is driven.

Drive device (100) for cyclically driving an inductive load (30) comprising:

at least one half-bridge having a high-side MOS-FET (10) and a low-side MOS-FET (20), wherein a connection point of the high-side MOS-FETs (10) and the low-side MOS-FETs (20) is connected to the inductive load (30), wherein

the high-side MOS FET (10) in each case with a positive phase current (Ip _h ) for generating the lowest possible power loss of the high-side MOS FET (10) when switching the electrical current flow from the intrinsic diode of the high-side MOS FETs (10) is defined as quickly switching on the electric current flow through the channel of the high-side MOS FET (10); and where

the low-side MOS-FET (20) is in each case slowly turned on when there is a negative electrical phase current (Ip _h ) for generating the lowest possible EMC emission; in which

the drive device (100) is designed to adapt the speed of the switching operation of the switched voltages depending on the size of the switched voltage swing, with the aim of minimizing the losses while observing interference limits.

The driver device (100) of claim 6, further comprising a driver device (40) that performs current-based or voltage-based switching of the MOS FETs (10, 20).

8. Computer program product, with program code means for performing the method according to one of claims 1 to 5, when it runs on a drive device (100) for cyclically driving an inductive load (30) or is stored on a computer-readable medium.