WO2019062787A1 - 充电控制方法、相关设备及计算机存储介质 - Google Patents

充电控制方法、相关设备及计算机存储介质 Download PDF

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Publication number
WO2019062787A1
WO2019062787A1 PCT/CN2018/107791 CN2018107791W WO2019062787A1 WO 2019062787 A1 WO2019062787 A1 WO 2019062787A1 CN 2018107791 W CN2018107791 W CN 2018107791W WO 2019062787 A1 WO2019062787 A1 WO 2019062787A1
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WIPO (PCT)
Prior art keywords
voltage
battery voltage
charging
battery
limiting
Prior art date
Application number
PCT/CN2018/107791
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English (en)
French (fr)
Inventor
余安富
罗伟
王朝
Original Assignee
华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to US16/651,724 priority Critical patent/US11411423B2/en
Publication of WO2019062787A1 publication Critical patent/WO2019062787A1/zh

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Classifications

    • H02J7/0077—
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/007—Regulation of charging or discharging current or voltage
    • H02J7/00712—Regulation of charging or discharging current or voltage the cycle being controlled or terminated in response to electric parameters
    • H02J7/007182—Regulation of charging or discharging current or voltage the cycle being controlled or terminated in response to electric parameters in response to battery voltage
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/0029—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with safety or protection devices or circuits
    • H02J7/00308—Overvoltage protection
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/02—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries for charging batteries from ac mains by converters
    • H02J7/04—Regulation of charging current or voltage
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J2207/00—Indexing scheme relating to details of circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J2207/30—Charge provided using DC bus or data bus of a computer

Definitions

  • the present application relates to the field of electronic circuit technologies, and in particular, to a charging control method, related equipment, and a computer storage medium.
  • FIG. 1 is a schematic structural view of a battery charging circuit.
  • a charger also referred to as an adapter, an adaptor
  • USB universal serial bus
  • the charging voltage can both charge the battery and supply power to the system load.
  • the speed of charging such as the output power of the charger, the impedance of the USB cable, the conversion efficiency of the charging chip, and the input voltage of the charging chip.
  • Vdpm Dynamic power management
  • an initial Vdpm parameter and a constant-voltage (CV) protection parameter of the battery are generally set at the beginning of insertion of the charger, and the constant voltage protection parameter refers to a charging chip.
  • the limiting voltage of the battery power supply terminal illustrated as the maximum limiting voltage of VBAT
  • Vdpm is only set once, that is, it only has one gear position, and cannot adjust the battery charging speed flexibly.
  • the charging time is too long, especially in the case of low battery voltage, the charging speed is slower and the charging time is delayed.
  • the embodiment of the invention discloses a charging control method, a related device and a computer storage medium, which can shorten the charging duration while ensuring the charging safety of the terminal device.
  • an embodiment of the present invention provides a terminal device, including a charging chip, a processor, and a battery, where the charging chip is configured to convert a power voltage into a battery voltage to charge the battery, where The power supply voltage is greater than the limit power supply voltage, the battery voltage is less than the limit battery voltage, the limit power supply voltage is a minimum limit voltage of the charge input end of the charging chip, and the limit battery voltage is a maximum limit of the battery power supply end of the charging chip a voltage; the processor is configured to simultaneously increase the limited power supply voltage and the limit battery voltage while satisfying the first condition, or simultaneously increase the limit battery voltage and reduce a charging current; When the second condition is satisfied, the limiting power supply voltage and the limiting battery voltage are simultaneously reduced, or at the same time, the limiting battery voltage is decreased and the charging current is increased; wherein the charging current is a current for charging the battery, the first condition including at least the battery voltage being greater than a battery a voltage threshold, the second condition comprising at least the battery voltage being less than a battery
  • a charging circuit in order to realize charging of the terminal device, a charging circuit is disposed in the terminal device, and the charging circuit includes but is not limited to a switch charging circuit and a linear charging circuit.
  • the charging circuit includes a charging chip, a processor and a battery, and optionally other components such as a load, a peripheral device and the like.
  • the embodiment of the present application can adjust related parameters in the charging circuit, for example, in the switching charging circuit, the limiting power source is synchronously adjusted according to the battery voltage.
  • the voltage Vdpm and the limiting battery voltage ie, the constant voltage protection parameter); in the linear charging circuit, the limiting battery voltage is adjusted according to the battery voltage, or the limiting battery voltage and the charging current in the charging circuit are synchronously adjusted.
  • the charging duration of the terminal device can be shortened while ensuring the charging security of the terminal device.
  • the first condition further includes: the test voltage is less than a preset The threshold, and/or the number of times the target exceeds the preset number of times.
  • the second condition further includes: the test voltage is less than a preset threshold, and/or, The number of goals exceeds the preset number of times.
  • the test voltage refers to a charging input end (VBUS) voltage of the charging chip during charging of the terminal device, and the voltage may be an actual voltage of the charging input terminal when the terminal device is normally charged, or may refer to The voltage detected by the charging input terminal is tested by a test current, which is not limited in the present invention.
  • a test current which is not limited in the present invention.
  • the voltage of the charging input terminal is collected as the test voltage after a preset period of time.
  • the target number refers to the number of times the test voltage is less than a preset threshold.
  • the terminal device may obtain whether the test voltage is less than a preset threshold multiple times, and determine that the adjustment needs to be adjusted when the test voltage is less than the preset threshold.
  • the relevant parameters in the charging circuit for example, if at least two test voltages are less than a preset threshold in the three test voltage determinations, the relevant parameters in the charging circuit are adjusted.
  • the first condition further includes the first condition It is also included that the battery voltage is in a rising phase.
  • the second condition further includes the battery voltage being In the rising period, or the battery voltage is in a falling period.
  • the charging chip can collect and record the voltage of the battery power supply terminal (ie, the battery voltage in the present application) in real time or periodically and save it.
  • the processor can analyze the change trend of the battery voltage by the battery voltage within the preset preset duration, for example, in a rising period or a falling period.
  • the battery voltage threshold in a case where the second condition further includes that the battery voltage is in a rising period, the battery voltage threshold is a first battery voltage threshold; and the second condition further includes the battery Where the voltage is in a falling period, the battery voltage threshold is a second battery voltage threshold; wherein the first battery voltage threshold is greater than the second battery voltage threshold.
  • an embodiment of the present invention discloses a charging control method for controlling charging of a terminal device, where the terminal device includes a charging chip, a processor, and a battery, and the method includes:
  • a power source voltage to a battery voltage by the charging chip to charge the battery, wherein the power source voltage is greater than a limit power source voltage, the battery voltage is less than a limit battery voltage, and the limiting power source voltage is the charging chip a minimum limiting voltage of the charging input, the limiting battery voltage being a maximum limiting voltage of a battery powered end of the charging chip;
  • the limiting power supply voltage and the limiting battery voltage are simultaneously increased by the processor, or the charging current is decreased while the limiting battery voltage is increased;
  • the limiting power supply voltage and the limiting battery voltage are simultaneously reduced by the processor, or the charging current is increased while the limiting battery voltage is decreased; wherein
  • the charging current is a current for charging the battery, the first condition comprising at least the battery voltage being greater than a battery voltage threshold, and the second condition comprising at least the battery voltage being less than a battery voltage threshold.
  • an embodiment of the present invention provides a terminal device, including a charging chip and a battery.
  • the charging chip is configured to convert a power voltage into a battery voltage to charge the battery, wherein the power voltage is greater than a limit power voltage, the battery voltage is less than a limit battery voltage, and the limiting power voltage is the charging a minimum limiting voltage of a charging input of the chip, the limiting battery voltage being a maximum limiting voltage of a battery powered end of the charging chip;
  • the charging chip is configured to simultaneously increase the limiting power supply voltage and the limiting battery voltage while satisfying the first condition, or simultaneously increase the limiting battery voltage and reduce the charging current;
  • the second condition is satisfied, the limiting power supply voltage and the limiting battery voltage are simultaneously reduced, or at the same time, the limiting battery voltage is decreased and the charging current is increased; wherein the charging current is used
  • the first condition includes at least the battery voltage being greater than a battery voltage threshold, and the second condition comprising at least the battery voltage being less than a battery voltage threshold.
  • an embodiment of the present invention provides a charging chip, including a processor and one or more interfaces coupled to the processor, where
  • the processor is configured to convert a power voltage to a battery voltage to charge a battery, wherein the power voltage is greater than a limit power voltage, the battery voltage is less than a limit battery voltage, and the limit power voltage is a charge of the charging chip a minimum limiting voltage at the input end, the limiting battery voltage being a maximum limiting voltage of a battery powered end of the charging chip;
  • the processor is further configured to simultaneously increase the limited power supply voltage and the limit battery voltage while satisfying the first condition, or simultaneously increase the limit battery voltage and reduce the charging current;
  • the second condition is satisfied, the limiting power supply voltage and the limiting battery voltage are simultaneously reduced, or at the same time, the limiting battery voltage is decreased and the charging current is increased; wherein the charging current is A current for charging the battery, the first condition comprising at least the battery voltage being greater than a battery voltage threshold, and the second condition comprising at least the battery voltage being less than a battery voltage threshold.
  • an embodiment of the present invention provides a terminal device, including a memory, a communication interface, and a processor coupled to the memory and a communication interface, where the memory is used to store an instruction, and the processor is configured to execute the instruction.
  • the communication interface is configured to communicate with the terminal device under control of the processor; wherein the processor executes the instructions to perform the method described in the second aspect above.
  • a computer readable storage medium storing program code for mail transmission.
  • the program code includes instructions for performing the method described in the second aspect above.
  • a computer program product comprising instructions which, when run on a computer, cause the computer to perform the method described in the second aspect above.
  • FIG. 1 is a schematic diagram of a charging circuit provided by the prior art
  • FIG. 2A is a schematic structural diagram of a terminal device according to an embodiment of the present invention.
  • FIG. 2B is a schematic structural diagram of still another terminal device according to an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of a switch charging circuit according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of still another terminal device according to an embodiment of the present invention.
  • FIG. 5 is a schematic diagram of a linear charging circuit according to an embodiment of the present invention.
  • FIG. 6 is a schematic structural diagram of still another terminal device according to an embodiment of the present disclosure.
  • FIG. 7 is a schematic flowchart diagram of a charging control method according to an embodiment of the present invention.
  • FIG. 8 is a schematic structural diagram of still another terminal device according to an embodiment of the present invention.
  • FIG. 8B is a schematic structural diagram of still another terminal device according to an embodiment of the present disclosure.
  • FIG. 9 is a schematic structural diagram of a device according to an embodiment of the present invention.
  • terminal device charging is generally divided into four stages, trickle-charge, pre-charge, and constant-current charge.
  • CC constant voltage charge
  • CV constant voltage charge
  • the constant current charging CC is one of the stages that mainly affect the charging speed.
  • the designer hopes that the terminal equipment stays in the CC stage for a long enough time, and the current is large enough, and the charging time is accordingly reduced.
  • the charging chip can convert the input power voltage into the charging voltage Vsys, and then convert and output the corresponding components (such as the switch tube) through the battery power supply terminal VBAT.
  • Battery voltage which is used to charge the battery.
  • the constant voltage protection parameter and the Vdpm parameter are set for the charging chip at the beginning of the insertion of the charger. When the battery voltage reaches the constant voltage protection parameter, the battery will enter the constant voltage charging phase CV to protect The safety of the rechargeable battery. How to set the constant voltage protection parameter and the Vdpm parameter in the prior art, specifically the following two implementation schemes:
  • the initial constant voltage protection parameter and the Vdpm parameter are set after the charger is inserted, and the two parameters are no longer set during the charging process of the entire device, and the battery charging speed cannot be flexibly adjusted, and the charging time is long. Especially in the case of low battery voltage of the device, the performance is most obvious.
  • the initial constant voltage protection parameter and the Vdpm parameter can be set after the charger is inserted, and the Vdpm parameter can be dynamically adjusted according to the battery voltage during the charging cycle, and the constant voltage protection parameter is unchanged.
  • the battery voltage is the actual voltage of the battery, as shown in Figure 1, the battery voltage is the actual voltage of VBAT.
  • Vdpm parameter setting is low (that is, Vdpm is in the low gear position)
  • the Vdpm parameter it is found that when the Vdpm parameter setting is low (that is, Vdpm is in the low gear position)
  • the Vdpm parameter if the system crashes or other faults cause the Vdpm parameter to be unable to be updated, that is, it cannot be set to the high-end position, which will cause the internal pressure of the charging chip.
  • the work tube buck appears to collide, damage the charging chip, and may even cause the register of the charging chip to be rewritten, the battery voltage may exceed the constant voltage protection parameter, and there is a safety hazard such as battery explosion.
  • FIG. 2A is a schematic structural diagram of a terminal device according to an embodiment of the present invention.
  • the terminal device 100 as shown in FIG. 2A includes a charging circuit for device charging, which may include a charging chip 102, a processor 104, and a battery 106.
  • the charging chip 102 is configured to convert a power supply voltage into a battery voltage to charge the battery 106, wherein the power supply voltage is greater than a limit power supply voltage, and the battery voltage is less than a limit battery voltage; the processor 104 For increasing the limiting power supply voltage and the limiting battery voltage while satisfying the first condition, or decreasing the charging current while increasing the limiting battery voltage, the first condition Include at least that the battery voltage is greater than a battery voltage threshold; the processor 104 is further configured to simultaneously reduce the limited power supply voltage and the limit battery voltage if the second condition is met, or The charging current is increased while the battery voltage is decreasing, the second condition including at least the battery voltage being less than the battery voltage threshold.
  • the limiting power supply voltage is a minimum limiting voltage of a charging input terminal of the charging chip.
  • the minimum allowable limit voltage set for the charging input terminal that is, Vdpm as described above, is the minimum limiting voltage Vdpm parameter of the VBUS terminal shown in FIG.
  • the limiting battery voltage is a maximum limiting voltage of the battery power supply end of the charging chip, and specifically may be an allowable maximum limiting voltage set by the battery power supply end, that is, the constant voltage protection parameter as described above, as shown in FIG.
  • the maximum limit voltage parameter of the terminal refers to the actual voltage of the charging input terminal of the charging chip, as shown in FIG. 1 at the actual voltage of the VBUS terminal.
  • the battery voltage refers to the actual voltage of the battery power supply terminal of the charging chip, as shown in FIG. 1 at the actual voltage of the VBAT terminal.
  • the charging circuit includes, but is not limited to, a switching charging circuit and a linear charging circuit.
  • the processor 104 can adjust the corresponding charging parameters by comparing the battery voltage with the battery voltage threshold.
  • the battery voltage threshold may be set independently by the user side or the terminal device side, which is not limited by the present invention.
  • the limited power supply voltage (Vdpm) and the limit battery voltage may be synchronously increased.
  • the limiting power supply voltage ie, constant voltage protection parameter
  • the limited power supply voltage (Vdpm) and the limit battery voltage may be synchronously reduced.
  • the limiting battery voltage may be reduced if the battery voltage is less than the battery voltage threshold, or the charging current may be increased while the limiting battery voltage is decreased. How to adjust the relevant parameters in the charging circuit will be specifically explained below.
  • the charging input of the charging chip (VBUS shown in Figure 1) sets the limiting power supply voltage to Vdpm, and the charging link impedance is R (as shown in Figure 1 for the adapter to the VBUS terminal). The impedance between).
  • I (V0-Vdpm)/R
  • I can be proportional to the voltage difference (V0-Vdpm) on the charging cable when R is constant, when the battery voltage is lower than the battery voltage threshold (ie, the battery In the case where the remaining capacity is less than the preset capacity value, the charging current should be increased, that is, Vdpm is decreased to shorten the charging time. Accordingly, in the case where the battery voltage (battery capacity) is greater than the battery voltage threshold, the charging current should be reduced, that is, Vdpm is increased to protect the safe charging of the device battery.
  • the Vdpm and the constant voltage protection parameters are set in the prior art, and the charging speed of the device cannot be flexibly, the charging time is too long, or the charging chip is damaged due to Vdpm cannot be updated in time, and the battery is charged and exploded. .
  • the charging chip 102 in the terminal device shown in FIG. 2A may include a processor, the processor of the charging chip 102, and the processor 104 may be the same physical processor, that is, processing.
  • the device 104 can also be disposed on the charging chip 102.
  • FIG. 2B shows a schematic diagram of another possible terminal device.
  • the terminal device 200 includes a charging circuit for device charging, and the charging circuit may include a charging chip 202 and a battery 206. among them,
  • the charging chip 202 is configured to convert a power voltage into a battery voltage to charge the battery 206, wherein the power voltage is greater than a limit power voltage, and the battery voltage is less than a limit battery voltage;
  • the charging chip 202 is further configured to simultaneously increase the limited power supply voltage and the limiting battery voltage if the first condition is satisfied, or reduce the charging current while increasing the limiting battery voltage
  • the first condition includes at least the battery voltage being greater than a battery voltage threshold
  • the charging chip 202 is further configured to simultaneously reduce the limited power supply voltage and the limiting battery voltage if the second condition is satisfied, or increase the charging current while decreasing the limiting battery voltage
  • the second condition includes at least the battery voltage being less than a battery voltage threshold.
  • the embodiment of the present invention will be based on the terminal device shown in FIG. 2A as an example, and specifically introduces two charging circuits according to the present invention and a charging control embodiment based on the terminal devices corresponding to the two charging circuits.
  • 3 and 4 illustrate related embodiments of the present invention in relation to a switch charging circuit.
  • Figures 5 and 6 illustrate related embodiments of the present invention with respect to a linear charging circuit.
  • the switch charging circuit 300 can include a charging chip 302, a processor 304, and a battery 306.
  • the charging chip 302 is electrically connected to the processor 304 and the battery 306, respectively.
  • the charging chip may include a charging input terminal VBUS and a battery power supply terminal VBAT.
  • the charging input terminal can be externally connected to a power source (such as an external charger) for inputting a power supply voltage.
  • the battery power supply end is electrically connected to the battery 306 for outputting a charging current or outputting a charging voltage to charge the battery.
  • the processor can be electrically connected to the charging chip through an inter-integrated circuit (I2C).
  • I2C bus may include a system clock line (SCL) and a serial line (SDA), which are not described in detail herein.
  • the switch charging circuit may further include a load, and the charging chip is electrically connected to the load.
  • the switch charging circuit may further include a peripheral device.
  • the charging chip of FIG. 3 may further include a capacitor C and an inductor L, and the charging chip may further include a first port, a second port, and a third port.
  • the illustrations correspond to the LX port, the BST port, and the SYS port, respectively.
  • the LX port is electrically connected to the load through the inductor.
  • the BST port is electrically connected to the LX port and one end of the inductor through the capacitor.
  • the SYS port is electrically connected to the load.
  • the switch charging circuit further includes an overvoltage protection (OVP) chip, a main and sub board connection interface, and a charging interface.
  • OVP overvoltage protection
  • the OVP chip is used to protect the charging chip, and the actual voltage of the charging input end of the charging chip does not exceed the upper limit threshold of the chip.
  • the upper threshold of the chip may be set independently by the user side or the terminal device side. Do not elaborate too much.
  • the main sub-board connection interface is used for electrically connecting the main board and the sub board, wherein the main board may include but is not limited to the charging chip 302, the processor 304, the battery 306, and subsequent alternative embodiments.
  • the components of the load, the OVP chip, and the connection interface of the motherboard may include, but are not limited to, a connection interface of the sub-board and a charging interface, as shown in FIG. 3 .
  • the main and auxiliary board connection interfaces can be connected by a flexible printed circuit (FPC).
  • the charging interface is used for an external charging power source to input a power voltage to the charging chip, and the charging interface includes, but is not limited to, a universal serial bus (USB) interface.
  • USB universal serial bus
  • the charging interface when charging with a switch charging circuit, can be externally connected to a charger or an adapter, as shown in FIG. Regarding the related components involved in the present invention, the present application does not elaborate too much.
  • FIG. 4 is a schematic structural diagram of a terminal device according to an embodiment of the present invention.
  • the terminal device may include all or a part of the connection components of the switch charging circuit in the embodiment of FIG. 3, which is not limited by the present invention.
  • the terminal device is shown here to include a charging chip 302, a processor 304, and a battery 306. Specific embodiments relating to these components are described below.
  • the charging chip 302 is configured to convert a power voltage into a battery voltage to charge the battery 306, wherein the power voltage is greater than a limit power voltage, and the battery voltage is less than a limit battery voltage;
  • the processor 304 is configured to simultaneously increase the limited power supply voltage and the limiting battery voltage if a first condition is met, the first condition including at least the battery voltage being greater than a battery voltage threshold;
  • the processor 304 is further configured to simultaneously reduce the limited power supply voltage and the limit battery voltage if the second condition is met, the second condition including at least the battery voltage being less than a battery voltage threshold.
  • the processor 304 may determine whether the first condition is met, and if so, the processor 304 may synchronously limit the limited power supply voltage (Vdpm) and the limited battery voltage ( That is, the constant voltage protection parameter) is increased/increased.
  • the first condition may include the battery voltage being greater than a battery voltage threshold.
  • the battery voltage threshold, the limiting power supply voltage, and the limiting battery voltage refer to related descriptions in the foregoing embodiments, and details are not described herein again.
  • the processor 304 may send a first acquisition instruction to the charging chip 302, where the first acquisition instruction is used to acquire a voltage of a battery powered terminal (VBAT) of the charging chip, that is, in the present application. battery voltage.
  • the charging chip 302 can receive the first obtaining instruction, and collect the voltage of the battery power supply end (ie, the battery voltage) according to the first obtaining instruction and feed back to the processor 304. Then, the processor 304 can adjust the correlation in the charging circuit according to the acquired battery voltage. For example, when the processor 304 determines that the battery voltage is greater than or equal to a battery voltage threshold (eg, 4.08V), Controllable synchronization increases the regulated supply voltage (Vdpm) and the regulated battery voltage. If it is determined that the battery voltage is less than a battery voltage threshold (eg, 4.08V), then the control can synchronize the regulated supply voltage (Vdpm) and the regulated battery voltage.
  • a battery voltage threshold eg, 4.08V
  • the first condition or the second condition may further include that the test voltage is less than a preset threshold, and/or the target number of times exceeds a preset number of times.
  • the test voltage may refer to a voltage that is actually detected after the terminal device is inserted into the charger, or a voltage of the charging input that is detected by the charging chip by using the test current.
  • the target number refers to the number of times the test voltage is less than a preset threshold.
  • the preset threshold and the preset number of times may be set autonomously by the user side or the terminal device side.
  • the preset threshold may be a limit power threshold set by the system, such as 4.675V or the like, or a threshold set by other users/systems, which is not limited by the present invention. The following two implementations involved in the specific implementation are described below.
  • the processor 304 may send a read instruction to the charging chip 302, where the read instruction is used for reading.
  • the charging chip is in a DPM state
  • the DPM state is used to indicate that the test voltage is less than or equal to a preset threshold.
  • the DPM state may be used to indicate that the test voltage triggers a preset threshold, and the test voltage is less than or maintained at a preset threshold.
  • the charging chip can receive the read instruction, and feed back the state of the charging chip to the processor according to the instruction of the read instruction.
  • the state of the charging chip includes being in a DPM state or not in a DPM state, and the state may be preset for the charging chip, as described in detail below.
  • the processor 304 may continue to send the first acquisition instruction to the charging chip 302, according to the acquired
  • the battery voltage synchronously adjusts the limit supply voltage Vdpm and the limit battery voltage (ie, constant voltage protection parameter).
  • the state of the charging chip may be identified by a preset character string, including but not limited to a preset letter, a preset number, etc., for example, the charging may be represented by “0”.
  • the chip is not in the DPM state, and the "1" indicates that the charging chip is in the DPM state.
  • the state of the charging chip may be preset for the charging chip.
  • the charging chip may collect the voltage of the charging input terminal (VBUS) after the first preset time period, as the test. Voltage.
  • the charging chip may mark itself in a DPM state, for example, marking the state of the charging chip as "1” or the like.
  • the charging chip may mark itself not in a DPM state, for example, marking a state of the charging chip as “0” or the like.
  • the charging chip can record the magnitude of the current on the data line and serve as the first current.
  • the data line is a cable connecting the charger and the charging chip (ie, the terminal device), and may also be referred to as a charging line. Since the specifications of the charging lines produced by different manufacturers are different (that is, the impedances on the charging lines are different), the charging chip can detect the voltage of the charging input terminal of the charging chip by using the test current as the test voltage. Specifically, the charging chip can set the current on the charging line to be a test current (eg, 900 mA, mA), and after passing the second preset duration, collect the voltage of the charging input as the test voltage.
  • a test current eg, 900 mA, mA
  • the charging chip is marked in a DPM state.
  • the charging chip is marked not to be in the DPM state.
  • test current and the second preset duration may be set autonomously on the user side or the terminal device side, which is not limited by the present invention.
  • the charging chip After the charging chip marks whether it is in the DPM state, the charging chip can set the current of the charging line to the first current, and the first current is normal for the terminal device to be inserted into the charger. The current on the charging line during charging.
  • the processor 304 may acquire the state of the charging chip multiple times if the number of times the charging chip is in the DPM state exceeds The preset number of times (that is, the number of times the test voltage is less than the preset threshold), the processor 304 may continue the subsequent process, and send a first acquisition instruction to the charging chip 302 to synchronously adjust according to the acquired battery voltage.
  • Related parameters in the charging circuit such as limiting the supply voltage Vdpm and limiting the battery voltage.
  • the processor 304 may determine the The terminal device is currently in a weak charge state, and the weak charge state is associated with the DPM state or the number of times of the DPM state. Accordingly, the processor 304 can continue to perform subsequent processes to adjust relevant parameters in the charging circuit based on the acquired battery voltage, such as limiting the supply voltage Vdpm and limiting the battery voltage.
  • the processor 304 may determine that the terminal device is currently In the non-weak state, the subsequent process can be ended.
  • the processor 304 may directly send a second acquisition instruction to the charging chip 302, where the second acquisition instruction A test voltage for obtaining a charging input of the charging chip.
  • the test voltage of the charging input end is collected according to the indication of the second obtaining instruction, and is fed back to the processor 304.
  • the processor 304 may compare the obtained test voltage with a preset threshold, and if the test voltage is less than or equal to a preset threshold, may send a first acquisition instruction to the charging chip 302, to The relevant parameters are adjusted according to the obtained battery voltage. In the case where the test voltage is greater than a preset threshold, the flow may be ended. Two specific implementations involved in obtaining the test voltage are described below.
  • the processor 304 sends a second acquisition instruction to the charging chip 302.
  • the charging chip 302 receives the second acquisition instruction, and acquires a voltage of the charging input terminal (VBUS) as the test voltage according to the instruction of the second obtaining instruction.
  • VBUS charging input terminal
  • the processor 304 sends a second acquisition instruction to the charging chip 302.
  • the charging chip 302 receives the second acquisition instruction, and the charging chip can record the magnitude of the current on the data line and serve as the first current. Then, the charging chip 302 can detect the voltage of the charging input end of the charging chip as the test voltage by using the test current.
  • the target differential voltage V 1 is the difference between the output voltage V out of the charger and the test voltage V in .
  • the processor 304 may acquire the test voltage of the charging input terminal in the charging chip multiple times, where the test voltage is less than or equal to If the number of preset thresholds (ie, the target number of times) exceeds the preset number of times, the processor 304 may continue the subsequent process, and details are not described herein again. Conversely, if the number of times the test voltage is less than or equal to the preset threshold does not exceed the preset number of times, the process may be terminated without adjusting related parameters (such as Vdpm and constant voltage protection parameters) in the charging circuit.
  • related parameters such as Vdpm and constant voltage protection parameters
  • the processor 304 determines that the test voltage is less than or equal to a preset threshold, or the test voltage is less than or equal to a preset threshold, the processor 304 It can be determined that the terminal device is in a weak charging state, and further can continue to adjust related parameters in the charging circuit according to the acquired battery voltage, and details are not described herein again. On the other hand, if the processor 304 determines that the test voltage is less than or equal to a preset threshold, or the test voltage is less than or equal to the preset threshold, the processor 304 may determine the The terminal device is in a non-weak state, and the process can be ended without adjusting the relevant parameters in the charging circuit.
  • the first condition may further include the battery voltage being in a rising period.
  • the second condition may further include the battery voltage being in a rising period, or the battery voltage being in a falling period.
  • the charging chip 302 can record the voltage of the battery power supply terminal (VBAT), that is, the battery voltage in the present application, in real time or periodically.
  • the form of recording of the battery voltage is not limited in the present invention, and is stored, for example, in the form of a data table, a vector, a matrix, or the like.
  • the processor 304 can obtain the battery voltage recorded in the third preset duration, and analyze the battery voltages to know whether the battery voltage is in a rising period or a falling period in the third preset duration. Illustratively, if the battery voltage recorded during the third preset duration increases gradually with time, it indicates that the battery voltage is in a rising period, and vice versa, that the battery voltage is in a falling period.
  • the third preset duration may be set autonomously by the user side or the terminal device side, which is not limited by the present invention.
  • the processor 304 can synchronously adjust the limited power supply voltage (Vdpm) and the limit battery voltage according to the acquired battery voltage.
  • the processor 304 may synchronize the limited power supply voltage (Vdpm) when it is determined that the battery voltage is in a rising period and the battery voltage is greater than a battery voltage threshold (ie, the first condition is met). And limiting the battery voltage to increase.
  • the processor 304 determines that the battery voltage is less than a battery voltage threshold, and the limiting power supply voltage may be synchronously, regardless of whether the battery voltage is in a rising period or a falling period (ie, satisfying a second condition). Vdpm and the limiting battery voltage are reduced.
  • the battery voltage threshold when the second condition further includes that the battery voltage is in a rising period, the battery voltage threshold is a first battery voltage threshold; and the second condition further includes the battery voltage In the case of a falling period, the battery voltage threshold is a second battery voltage threshold; wherein the first battery voltage threshold is greater than the second battery voltage threshold.
  • the voltage hysteresis interval can be set.
  • the processor 304 can obtain a battery voltage within a third preset duration, and if the processor knows that the battery voltage is in a rising period by analysis, and the battery voltage is less than or equal to the first battery voltage threshold, The limiting power supply voltage Vdpm and the limiting battery voltage (reducing. Accordingly, if the processor knows that the battery voltage is in a falling period by analysis, the voltage hysteresis interval may be set, that is, the battery voltage is less than or equal to the second battery voltage threshold.
  • the limiting power supply voltage Vdpm and the limiting battery voltage may be synchronously reduced, wherein the first battery voltage threshold is greater than the second battery voltage threshold, and the voltage hysteresis interval is the first battery voltage threshold to the second battery voltage Threshold.
  • the charging chip 302 can record the first current on the charging line, the charging line.
  • the charging chip can detect the voltage of the charging input end of the charging chip on the charging line by using a test current, and collect the voltage of the charging input terminal after a first preset duration (for example, delay of 100 ms, milliseconds). Take as the test voltage.
  • the charging chip may mark that the charging chip is in a DPM state (or a weak charging state) when it is determined that the test voltage is less than or equal to a preset threshold (eg, 4.675V is an example); otherwise, marking the charging chip Not in DPM state.
  • a preset threshold eg, 4.675V is an example
  • the charging chip can also set current reduction on the charging line to the first current to restore normal charging of the terminal device.
  • the processor 304 can send a read command to the charging chip to read whether the charging chip is in a DPM state. After the processor 304 reads that the charging chip is not in the DPM state, it may be determined that the terminal device is currently in a non-weak state, and the process ends. After the processor 304 reads that the charging chip is in the DPM state, it may be determined that the terminal device is currently in a weak charging state, and further the processor 304 may acquire a voltage of a battery power supply end of the charging chip, that is, The battery voltage in this application.
  • the processor may synchronously adjust the limited power supply voltage (Vdpm) and the limit battery voltage (ie, constant voltage protection parameter) according to the battery voltage.
  • Vdpm and the constant voltage protection parameter refer to the foregoing embodiment. The relevant description is not repeated here.
  • the processor may synchronously adjust the limited power supply voltage (Vdpm) to a high level. (such as 4.675V), adjust the limit battery voltage increase to 4.4V and so on.
  • the processor may synchronously adjust the limited supply voltage (Vdpm) to a low gear (eg 4.46V) when the battery voltage is in a rising phase and the battery voltage is less than or equal to a first battery voltage threshold of 4.08V.
  • the limit battery voltage is reduced to 4.15V or the like.
  • a voltage hysteresis interval eg, 280 mV millivolts
  • the limited supply voltage (Vdpm) can be synchronously adjusted to a low gear (eg, 4.46V), and the limited battery voltage can be reduced to 4.15V or the like.
  • the charging current should be increased.
  • V0 the charging power supply 5V
  • R the impedance on the charging line.
  • Vdpm the charging current
  • the battery capacity exceeds the set threshold that is, when the battery voltage is greater than the first battery voltage threshold, in order to ensure the safety of the battery charging
  • the charging current should be reduced. See the impedance on the charging line as described above. In the case, to reduce the charging current I, Vdpm should be increased.
  • the processor 304 can also record the charging duration of the terminal device during the charging process of the terminal device for charging, so that the user can view the charging duration of the device, and intuitively understand the application of the application. It can shorten the charging time of the terminal device.
  • Table 1 below exemplarily shows a test data table, which intuitively reflects that the charging time of the terminal device after using the application is significantly smaller than the charging time of the terminal device in the conventional technology.
  • the above standard data line refers to a data line for connecting a charger and a terminal device, that is, the charging line described above. Since the impedances on the standard data lines produced by different manufacturers are different, some are smaller and some are larger. Therefore, in the test, in order to ensure the accuracy of the test data, an appropriate size of impedance can be connected in series on the standard data line, as shown in Table 1 above, 0.75 or 0.5 ohm impedance is connected, and under the same test conditions, multiple data lines are used. test.
  • the processor may acquire the battery voltage in real time or periodically during insertion of the charger charging to adjust relevant parameters in the charging circuit according to the battery voltage, such as the limiting battery Voltage and the limited supply voltage Vdpm.
  • the processor may detect that the battery is fully charged, the charger may be prompted to end charging.
  • the power supply voltage Vdpm cannot be updated in time to cause damage to the charging chip, or the register is rewritten to cause a battery explosion or the like, or the prior art supports setting a limited power supply voltage Vdpm.
  • the problem is that the charging speed cannot be adjusted flexibly, and the charging time is too long. Under the premise of ensuring the charging safety of the terminal device, the charging time is shortened.
  • the linear charging circuit 500 can include a charging chip 502, a processor 504, and a battery 506.
  • the charging chip 502 is electrically connected to the processor 504 and the battery 506, respectively.
  • the processor and the battery reference may be made to related descriptions in the foregoing embodiments, and details are not described herein again.
  • the switch charging circuit may further include a load, and the charging chip is electrically connected to the load.
  • the linear charging circuit may further include an amplifier Q1, a resistor R, a charging interface, or other peripheral devices.
  • the linear charging circuit in FIG. 5 further includes an amplifier Q1 and a resistor R, and the charging chip further includes a One port (shown as Isense).
  • the base of Q1 is electrically connected to the charging input end (VBUS) of the charging chip, and the collector of Q1 is electrically connected to the battery 506 through a resistor R.
  • the Isense end of the charging chip and the set of Q1 respectively
  • the electrode and the resistor R are electrically connected to one end of the battery
  • the battery power supply terminal (VBAT) of the charging chip is electrically connected to the other end of the battery and the resistor R
  • the emitter of the Q1 is electrically connected to the charging interface.
  • each port (or pin) of the charging chip has a corresponding withstand voltage range, and if the port voltage exceeds the specified withstand voltage range of the port, the charging chip will be damaged.
  • the withstand voltage range of the Isense terminal of the charging chip is 0 to 4.5V.
  • the charging interface when charging with a linear charging circuit, may be externally connected to a direct current (DC), such as charging the battery with a charger, as shown in FIG. 5.
  • DC direct current
  • FIG. 6 is a schematic structural diagram of a terminal device according to an embodiment of the present invention.
  • the terminal device may include all or part of the connecting components of the linear charging circuit in the embodiment of FIG. 5, which is not limited by the present invention.
  • the terminal device is shown here to include a charging chip 502, a processor 504, and a battery 506. Specific embodiments relating to these components are described below.
  • the charging chip 502 is configured to convert a power voltage into a battery voltage to charge the battery 506, wherein the power voltage is greater than a limit power voltage, and the battery voltage is less than a limit battery voltage;
  • the processor 504 is configured to increase the limiting battery voltage or reduce the charging current while increasing the limiting battery voltage, if the first condition is met, the first condition including at least Said battery voltage is greater than the battery voltage threshold;
  • the processor 504 is further configured to reduce the limiting battery voltage or increase the charging current while decreasing the limiting battery voltage if the second condition is met, the second condition including at least The battery voltage is less than a battery voltage threshold.
  • the processor 504 may send a read command to the charging chip 502, where the read command is used to obtain a battery voltage, and the battery voltage is used to supply power to the battery of the charging chip 502. The voltage at the end.
  • the charging chip receives the read command, and reads a voltage of the battery power supply end, that is, the battery voltage in the present application according to the instruction of the read instruction.
  • the processor 504 can adjust the limit battery voltage (ie, constant voltage protection parameter) according to the battery voltage, or synchronously adjust the limit battery voltage and the charging current.
  • the limit battery voltage ie, constant voltage protection parameter
  • the processor 504 can adjust the limit battery voltage (ie, constant voltage protection parameter) according to the battery voltage, or synchronously adjust the limit battery voltage and the charging current.
  • the charging chip can obtain a battery voltage and a charging current by detecting a voltage across the resistor R. Accordingly, the processor can control/adjust the magnitude of the charging current by adjusting the base (also referred to as the control terminal) of Q1. Specifically, the processor 504 increases the limiting battery voltage or decreases the charging current while increasing the limiting battery voltage, if it is determined that the battery voltage is greater than a battery voltage threshold. Conversely, the processor 504, when it is determined that the battery voltage is less than the battery voltage threshold, reduces the limit battery voltage or increases the charging current while decreasing the limit battery voltage.
  • the battery voltage threshold is set autonomously on the user side or the terminal device side, and is not limited in the present invention.
  • the processor may obtain the voltage of the battery powered terminal (VBAT) from the charging chip (ie, the battery voltage of the present application).
  • the processor can correspondingly adjust related parameters in the charging circuit according to a threshold interval in which the battery voltage is located. For example, when the battery voltage is less than or equal to a first battery voltage threshold (eg, 4.24V), the processor may reduce a maximum limit voltage of the battery power supply terminal (ie, the limit battery voltage or constant voltage protection parameter) Set to the first battery voltage (eg, 4.25V), optionally also by adjusting the collector of Q1 to set the charge current I increase to the first charge current (eg, 1A).
  • a first battery voltage threshold eg, 4.24V
  • the processor may reduce a maximum limit voltage of the battery power supply terminal (ie, the limit battery voltage or constant voltage protection parameter) Set to the first battery voltage (eg, 4.25V), optionally also by adjusting the collector of Q1 to set the charge current I increase to the first charge current (eg, 1A).
  • the processor may set the limit battery voltage increase to the second battery voltage (eg, 4.3V), optionally, the charging current I can also be reduced to a second charging current (eg, 0.7A).
  • the processor may set the limit battery voltage increase to a third battery voltage (eg, 4.35V), optionally also charging The current I is reduced to a third charging current (eg, 0.45A).
  • the first battery voltage is less than the second battery voltage is less than the third battery voltage, and the first charging current is greater than the second charging current is greater than the third charging current.
  • the processor may acquire the battery voltage in real time or periodically during insertion of the charger charging to adjust relevant parameters in the charging circuit according to the battery voltage, such as the limiting battery Voltage and charging current.
  • the processor may detect that the battery is fully charged, the charger may be prompted to end charging.
  • the charging duration can be shortened while ensuring the charging safety of the terminal device.
  • FIG. 7 is a schematic flowchart diagram of a charging control method according to an embodiment of the present invention.
  • the charging control method shown in FIG. 7 includes the following implementation steps:
  • Step S702 the terminal device converts the power voltage into a battery voltage by the charging chip to charge the battery, wherein the power voltage is greater than the limit power voltage, the battery voltage is less than the limit battery voltage, and the limiting power voltage is a minimum limiting voltage of a charging input end of the charging chip, the limiting battery voltage being a maximum limiting voltage of a battery power supply end of the charging chip;
  • Step S704 the terminal device increases the limited power supply voltage and the limit battery voltage by the processor simultaneously, or increases the limit battery voltage while charging current while satisfying the first condition. Decrease
  • Step S706 The terminal device reduces the limited power supply voltage and the limiting battery voltage by the processor simultaneously, or reduces the charging battery voltage while reducing the battery voltage.
  • the charging current is a current for charging the battery
  • the first condition includes at least the battery voltage being greater than a battery voltage threshold
  • the second condition includes at least the battery voltage being less than a battery voltage Threshold.
  • the terminal device in order to realize charging of the terminal device, the terminal device is internally provided with a charging circuit, which includes but is not limited to a switch charging circuit, a linear charging circuit and the like.
  • the charging circuit is instructed to include a charging chip, a processor, a battery, and some other components, such as a load, and the like.
  • the limiting supply voltage is a minimum limiting voltage of the charging input (VBUS) of the charging chip, ie Vdpm as previously described.
  • the limiting battery voltage is a maximum limiting voltage of a battery powered terminal (VBAT) of the charging chip, that is, a constant voltage protection parameter as described above.
  • the power supply voltage refers to the actual voltage of the charging input terminal of the charging chip.
  • the battery voltage refers to the actual voltage of the battery power supply terminal of the charging chip.
  • the charging current refers to a current for charging the battery, such as a charging current flowing through the resistor R in FIG.
  • the first condition may further include that the test voltage is less than The preset threshold, and/or the target number of times exceeds a preset number of times, wherein the target number of times refers to the number of times the test voltage is less than a preset threshold.
  • the first condition may further include that the test voltage is less than a preset threshold, And/or the target number of times exceeds a preset number of times, wherein the target number of times refers to the number of times the test voltage is less than a preset threshold.
  • the test voltage is a voltage detected at a charging input end of the charging chip.
  • the test voltage may be an actual voltage of the charging input terminal after the terminal device is inserted into the charger; or the test voltage detected by the test current at the charging input end, which may be specifically referred to in the foregoing embodiment. The relevant description is not repeated here.
  • the first condition further includes the battery voltage It is on the rise.
  • the second condition further includes the battery voltage It is in a rising period, or the battery voltage is in a falling period.
  • the battery voltage threshold in a case where the second condition further includes that the battery voltage is in a rising period, is a first battery voltage threshold;
  • the battery voltage threshold is a second battery voltage threshold in which the battery voltage is in a falling period; wherein the first battery voltage threshold is greater than the second battery voltage threshold.
  • step S704 and the step S706 may be performed in parallel, that is, the terminal device may perform any one of the steps S7104 and S706, which is not limited by the present invention.
  • the charging duration of the terminal device can be shortened while ensuring the charging security of the terminal device.
  • the terminal device includes corresponding hardware structures and/or software modules for executing the respective functions.
  • the embodiments of the present invention can be implemented in a combination of hardware or hardware and computer software in combination with the elements and algorithm steps of the various examples described in the embodiments disclosed herein. Whether a function is implemented in hardware or computer software to drive hardware depends on the specific application and design constraints of the solution. A person skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the technical solutions of the embodiments of the present invention.
  • the embodiment of the present invention may divide the functional unit into the message processing device according to the foregoing method example.
  • each functional unit may be divided according to each function, or two or more functions may be integrated into one processing unit.
  • the above integrated unit can be implemented in the form of hardware or in the form of a software functional unit. It should be noted that the division of the unit in the embodiment of the present invention is schematic, and is only a logical function division, and the actual implementation may have another division manner.
  • FIG. 8A shows a possible structural diagram of the terminal device involved in the above embodiment.
  • the terminal device 800 includes a processing unit 802 and a communication unit 803.
  • the processing unit 802 is configured to control and manage the actions of the terminal device 800.
  • the processing unit 802 is configured to support the terminal device 800 to perform steps S702, S704, and S706 in FIG. 7, and/or other techniques for performing the techniques described herein. step.
  • Communication unit 803 is used to support communication of terminal device 800 with other terminal devices, for example, communication unit 803 is used to support terminal device 800 for data communication with a charger, and/or for performing other steps of the techniques described herein.
  • the terminal device 800 may further include a storage unit 801 for storing program codes and data of the terminal device 800.
  • the processing unit 802 can be a processor or a controller, and can be, for example, a central processing unit (CPU), a general-purpose processor, a digital signal processor (DSP), and an application-specific integrated circuit (Application-Specific). Integrated Circuit (ASIC), Field Programmable Gate Array (FPGA) or other programmable logic device, transistor logic device, hardware component, or any combination thereof. It is possible to implement or carry out the various illustrative logical blocks, modules and circuits described in connection with the present disclosure.
  • the processor may also be a combination of computing functions, for example, including one or more microprocessor combinations, a combination of a DSP and a microprocessor, and the like.
  • the communication unit 803 can be a communication interface, a transceiver, a transceiver circuit, etc., wherein the communication interface is a collective name and can include one or more interfaces, such as an interface between the message processing device and the terminal device.
  • the storage unit 801 can be a memory.
  • the processing unit 802 may be the processor and the charging chip in the embodiment described in FIG. 2A; or the charging chip in the embodiment shown in FIG. 2B, which is not limited in the present invention.
  • the terminal device When the processing unit 802 is a processor, the communication unit 803 is a communication interface, and the storage unit 801 is a memory, the terminal device according to the embodiment of the present invention may be the terminal device shown in FIG. 8B.
  • the terminal device 810 includes a processor 812, a communication interface 813, and a memory 811.
  • the terminal device 810 may also include a bus 814.
  • the communication interface 813, the processor 812, and the memory 811 may be connected to each other through a bus 814.
  • the bus 814 may be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA). Bus, etc.
  • PCI Peripheral Component Interconnect
  • EISA Extended Industry Standard Architecture
  • the bus 814 can be divided into an address bus, a data bus, a control bus, and the like. For ease of representation, only one thick line is shown in Figure 8B, but it does not mean that there is only one bus or one type of bus.
  • FIG. 8A or FIG. 8B may also correspond to the corresponding description of the embodiment shown in FIG. 2A to FIG. 7 , and details are not described herein again.
  • FIG. 9 is a schematic structural diagram of a device provided by the present application.
  • device 900 eg, a charging chip
  • the processor 901 can be used to read and execute computer readable instructions.
  • the processor 901 may mainly include a controller, an operator, and a register.
  • the controller is mainly responsible for instruction decoding, and sends a control signal for the operation corresponding to the instruction.
  • the operator is mainly responsible for performing fixed-point or floating-point arithmetic operations, shift operations, and logic operations, as well as performing address operations and conversions.
  • the register is mainly responsible for saving the register operands and intermediate operation results temporarily stored during the execution of the instruction.
  • the hardware architecture of the processor 901 may be an Application Specific Integrated Circuits (ASIC) architecture, a MIPS architecture, an ARM architecture, or an NP architecture.
  • the processor 901 can be single core or multi-core.
  • the interface 902 can be used to input data to be processed to the processor 901, and can output the processing result of the processor 901 to the outside.
  • the interface 902 can be a General Purpose Input Output (GPIO) interface, and can be connected to multiple peripheral devices (such as a battery, a display (LCD), a camera, a radio frequency module, etc.).
  • GPIO General Purpose Input Output
  • the interface 902 may also include a plurality of independent interfaces, such as a battery interface, a Ethernet interface, an LCD interface, a Camera interface, etc., responsible for communication between different peripheral devices and the processor 901, respectively.
  • the processor 901 can be used to invoke the implementation program of the charging control method provided by the present application on the terminal device side from the memory, and execute the instructions included in the program.
  • the interface 902 can be used to output the execution result of the processor 901.
  • the interface 902 can be specifically used to output the battery voltage of the processor 901.
  • processor 901 and the interface 902 can be implemented by using a hardware design or a software design, and can also be implemented by a combination of software and hardware, which is not limited herein.
  • the steps of the method or algorithm described in connection with the disclosure of the embodiments of the present invention may be implemented in a hardware manner, or may be implemented by a processor executing software instructions.
  • the software instructions may be composed of corresponding software modules, which may be stored in a random access memory (RAM), a flash memory, a read only memory (ROM), an erasable programmable read only memory ( Erasable Programmable ROM (EPROM), electrically erasable programmable read only memory (EEPROM), registers, hard disk, removable hard disk, compact disk read only (CD-ROM) or any other form of storage medium known in the art.
  • An exemplary storage medium is coupled to the processor to enable the processor to read information from, and write information to, the storage medium.
  • the storage medium can also be an integral part of the processor.
  • the processor and the storage medium can be located in an ASIC.
  • the ASIC can be located in a network device.
  • the processor and the storage medium can also exist as discrete components in the network device.
  • the foregoing storage medium includes various media that can store program codes, such as a ROM, a RAM, a magnetic disk, or an optical disk.

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Abstract

一种充电控制方法、相关设备及计算机存储介质，其中终端设备（100）包括充电芯片（102）、处理器（104）以及电池（106），所述充电芯片（102）用于将电源电压转换为电池电压，以向所述电池（106）充电，其中，所述电源电压大于限制电源电压，所述电池电压小于限制电池电压；所述处理器（104）用于在满足第一条件的情况下，同时将所述限制电源电压以及所述限制电池电压增大，或者，同时将所述限制电池电压增大以及将充电电流减小；在满足第二条件的情况下，同时将所述限制电源电压以及所述限制电池电压减小，或者，同时将所述限制电池电压减小以及将充电电流增大。能够在保证充电安全的前提下，缩短充电时长。

Description

充电控制方法、相关设备及计算机存储介质
本申请要求于2017年9月30日提交中国国家知识产权局、申请号为201710927470.6、申请名称为“充电控制方法、相关设备及计算机存储介质”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及电子电路技术领域，尤其涉及充电控制方法、相关设备及计算机存储介质。
背景技术
随着LCD屏、双摄像头等技术的不断发展，终端设备的功耗越来越大。在设备电池容量一定的情况下，充电快慢显得尤为重要，甚至直接影响用户对设备产品的选择。
如图1示出一种电池充电电路的结构示意图。如图1，充电器(也可称为适配器，adaptor)通过通用串行总线(universal serial bus，USB)连接到终端设备的USB端口，经过充电芯片(charger)转换为充电电压Vsys。该充电电压既可给电池(battery)充电，又可给系统负载(load)供电。在实践中发现，影响充电速度快慢的因素有很多，例如充电器的输出功率、USB线缆的阻抗、充电芯片的转换效率、充电芯片的输入电压动态电源管理(dynamic power management，DPM，以下简称Vdpm)，即充电芯片的充电输入端的限制电压(图示为VBUS的最小限制电压)、电池内阻等等。其中，充电芯片Vdpm参数的设置是影响充电速度快慢的重要参数之一。
现有技术中为保护设备的安全充电，在插入充电器的开始阶段通常会设置一个初始Vdpm参数以及电池的恒压(constant-voltage，CV)保护参数，该恒压保护参数是指充电芯片的电池供电端的限制电压(图示为VBAT的最大限制电压)，后续将不重复设置这两个参数，直至经由充电芯片完成电池的整个充电过程。但是，Vdpm仅设置一次，即只拥有一个档位，不能灵活调节电池充电速度，充电时间过长，特别是在电池电压较低情况下，采用上述方案充电速度较慢，延迟充电时长。
发明内容
本发明实施例公开了充电控制方法、相关设备及计算机存储介质，能够在保证终端设备充电安全的情况下，缩短充电时长。
第一方面，本发明实施例公开提供了一种终端设备，包括充电芯片、处理器以及电池，所述充电芯片用于将电源电压转换为电池电压，以向所述电池充电，其中，所述电源电压大于限制电源电压，所述电池电压小于限制电池电压，所述限制电源电压为所述充电芯片的充电输入端的最小限制电压，所述限制电池电压为所述充电芯片的 电池供电端的最大限制电压；所述处理器用于在满足第一条件的情况下，同时将所述限制电源电压以及所述限制电池电压增大，或者，同时将所述限制电池电压增大以及将充电电流减小；在满足第二条件的情况下，同时将所述限制电源电压以及所述限制电池电压减小，或者，同时将所述限制电池电压减小以及将充电电流增大；其中，所述充电电流为用于向所述电池充电的电流，所述第一条件至少包括所述电池电压大于电池电压阈值，所述第二条件至少包括所述电池电压小于电池电压阈值。
本申请中，为实现终端设备充电，该终端设备中设置有充电电路，所述充电电路包括但不限于开关充电电路、线性充电电路。所述充电电路中均包括充电芯片、处理器以及电池，可选的还可包括其他元器件，例如负载、外围器件等。为缩短终端设备的充电时长，在终端设备插入充电器进行充电过程中，本申请实施例可对充电电路中的相关参数进行调节，例如在开关充电电路中，根据电池电压同步调节所述限制电源电压Vdpm以及所述限制电池电压(即恒压保护参数)；在线性充电电路中，根据电池电压调节所述限制电池电压，或者同步调节所述限制电池电压以及充电电路中的充电电流。
通过实施本发明实施例，能够在保证终端设备充电安全的前提下，缩短终端设备的充电时长。
在一些可能的实施例中，在充电电路为开关充电电路，即所述同时将所述限制电源电压以及所述限制电池电压增大的情况下，所述第一条件还包括测试电压小于预设阈值，和/或目标次数超过预设次数。或者，在充电电路为开关充电电路，即所述同时将所述限制电源电压以及所述限制电池电压减小的情况下，所述第二条件还包括测试电压小于预设阈值，和/或，目标次数超过预设次数。
其中，所述测试电压是指所述终端设备充电过程中所述充电芯片的充电输入端(VBUS)电压，该电压可以是所述终端设备正常充电时所述充电输入端的实际电压，也可是指利用测试电流测试所述充电输入端所检测的电压，本发明不做限定。通常，为保证测试电压数据的准确性，可经过预设时长后，采集所述充电输入端的电压以作为所述测试电压。
所述目标次数是指所述测试电压小于预设阈值的次数。为避免误判，保证参数调节的准确性，所述终端设备可多次获取所述测试电压是否小于预设阈值，当所述测试电压小于预设阈值的次数超过预设次数，则确定需要调节充电电路中的相关参数，例如3次测试电压判断中存在至少两次测试电压小于预设阈值，则调节充电电路中的相关参数。
在一些可能的实施例中，在充电电路为开关充电电路，即所述同时将所述限制电源电压以及所述限制电池电压增大的情况下，所述第一条件还包括所述第一条件还包括所述电池电压处于上升期。
在一些可能的实施例中，在充电电路为开关充电电路，在所述同时将所述限制电源电压以及所述限制电池电压减小的情况下，所述第二条件还包括所述电池电压处于上升期，或者，所述电池电压处于下降期。
为保证参数调节的准确性，还可考虑加入电池电压的变化趋势以调节充电电路中的相关参数。具体实现中，充电芯片可实时或周期性地采集并记录所述电池供电端的 电压(即本申请中电池电压)并保存。相应地所述处理器可通过记录的预设时长内的电池电压分析该电池电压的变化趋势，例如处于上升期或下降期等。
在一些可能的实施例中，在所述第二条件还包括所述电池电压处于上升期的情况下，所述电池电压阈值为第一电池电压阈值；在所述第二条件还包括所述电池电压处于下降期的情况下，所述电池电压阈值为第二电池电压阈值；其中，所述第一电池电压阈值大于第二电池电压阈值。
第二方面，本发明实施例公开了一种充电控制方法，用于控制终端设备充电，该终端设备包括充电芯片、处理器和电池，所述方法包括：
通过所述充电芯片将电源电压转换为电池电压，以向所述电池充电，其中，所述电源电压大于限制电源电压，所述电池电压小于限制电池电压，所述限制电源电压为所述充电芯片的充电输入端的最小限制电压，所述限制电池电压为所述充电芯片的电池供电端的最大限制电压；
在满足第一条件的情况下，通过所述处理器同时将所述限制电源电压以及所述限制电池电压增大，或者，将所述限制电池电压增大的同时将充电电流减小；在满足第二条件的情况下，通过所述处理器同时将所述限制电源电压以及所述限制电池电压减小，或者，将所述限制电池电压减小的同时将充电电流增大；其中，所述充电电流为用于向所述电池充电的电流，所述第一条件至少包括所述电池电压大于电池电压阈值，所述第二条件至少包括所述电池电压小于电池电压阈值。
本发明实施例未描述或未示出的内容，可参见前述第一方面所述实施例中的相关描述，这里不再赘述。
第三方面，本发明实施例公开提供了一种终端设备，包括充电芯片以及电池，
所述充电芯片用于将电源电压转换为电池电压，以向所述电池充电，其中，所述电源电压大于限制电源电压，所述电池电压小于限制电池电压，所述限制电源电压为所述充电芯片的充电输入端的最小限制电压，所述限制电池电压为所述充电芯片的电池供电端的最大限制电压；
所述充电芯片用于在满足第一条件的情况下，同时将所述限制电源电压以及所述限制电池电压增大，或者，同时将所述限制电池电压增大以及将充电电流减小；在满足第二条件的情况下，同时将所述限制电源电压以及所述限制电池电压减小，或者，同时将所述限制电池电压减小以及将充电电流增大；其中，所述充电电流为用于向所述电池充电的电流，所述第一条件至少包括所述电池电压大于电池电压阈值，所述第二条件至少包括所述电池电压小于电池电压阈值。
本发明实施例未描述或未示出的内容，可参见前述第一方面所述实施例中的相关描述，这里不再赘述。
第四方面，本发明实施例公开提供了一种充电芯片，包括处理器以及与所述处理器耦合的一个或多个接口，其中，
所述处理器用于将电源电压转换为电池电压，以向电池充电，其中，所述电源电压大于限制电源电压，所述电池电压小于限制电池电压，所述限制电源电压为所述充电芯片的充电输入端的最小限制电压，所述限制电池电压为所述充电芯片的电池供电端的最大限制电压；
所述处理器还用于在满足第一条件的情况下，同时将所述限制电源电压以及所述限制电池电压增大，或者，同时将所述限制电池电压增大以及将充电电流减小；在满足第二条件的情况下，同时将所述限制电源电压以及所述限制电池电压减小，或者，同时将所述限制电池电压减小以及将充电电流增大；其中，所述充电电流为用于向所述电池充电的电流，所述第一条件至少包括所述电池电压大于电池电压阈值，所述第二条件至少包括所述电池电压小于电池电压阈值。
第五方面，本发明实施例提供了一种终端设备，包括存储器、通信接口及与所述存储器和通信接口耦合的处理器；所述存储器用于存储指令，所述处理器用于执行所述指令，所述通信接口用于在所述处理器的控制下与终端设备进行通信；其中，所述处理器执行所述指令时执行上述第二方面描述的方法。
第六方面，提供了一种计算机可读存储介质，所述计算机可读存储介质存储了用于邮件传输的程序代码。所述程序代码包括用于执行上述第二方面描述的方法的指令。
第七方面，提供了一种包括指令的计算机程序产品，当其在计算机上运行时，使得计算机执行上述第二方面描述的方法。
通过实施本发明实施例，能够在保证设备电池安全充电的情况下，缩短充电时长。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍。
图1是现有技术提供的一种充电电路示意图；
图2A是本发明实施例提供的一种终端设备的结构示意图；
图2B是本发明实施例提供的又一种终端设备的结构示意图；
图3是本发明实施例提供的一种开关充电电路的示意图；
图4是本发明实施例提供的又一种终端设备的结构示意图；
图5是本发明实施例提供的一种线性充电电路的示意图；
图6是本发明实施例提供的又一种终端设备的结构示意图；
图7是本发明实施例提供的一种充电控制方法的流程示意图；
图8A是本发明实施例提供的又一种终端设备的结构示意图；
图8B是本发明实施例提供的又一种终端设备的结构示意图；
图9是本发明实施例提供的一种装置的结构示意图。
具体实施方式
下面将结合本发明的附图，对本发明实施例中的技术方案进行详细描述。
本申请的发明人在提出本申请的过程中发现：终端设备充电通常分为4个阶段，涓流充电(trickle-charge)、预充(pre-charge)、恒流充电(constant-current charge，CC)、恒压充电(constant-voltage charge，CV)。其中，恒流充电CC是主要影响充电快慢的阶段之一，通常设计者们希望终端设备停留在CC阶段的时间足够长，电流足够大，相应地充电时间才会减小。
如图1现有终端设备充电方案中，在插入充电器充电时，充电芯片可将输入的电 源电压转换为充电电压Vsys，然后经由电池供电端VBAT内部的元器件(如开关管)转换输出相应的电池电压，该电池电压用于向电池充电。为保护设备充电的安全性，在插入充电器的开始阶段会为充电芯片设置恒压保护参数和Vdpm参数，在电池电压达到该恒压保护参数时，电池将进入恒压充电阶段CV，以保护充电电池的安全性。现有技术中如何设置该恒压保护参数以及Vdpm参数，具体存在以下两种实现方案：
第一种方案，在插入充电器后设置初始的恒压保护参数和Vdpm参数，后面整个设备充电过程中不再对这两个参数进行设置，不能灵活地调节电池充电速度，充电时间较长，特别是在设备电池电压较低的情况下，表现最明显。
第二种方案，在插入充电器后可设置初始的恒压保护参数和Vdpm参数，在充电周期内可根据电池电压动态调整Vdpm参数，恒压保护参数不变。该电池电压为电池的实际电压，如图1电池电压为VBAT的实际电压。然而在实践中发现，在Vdpm参数设置较低(即Vdpm处于低档位)时，如果系统出现死机或其他故障导致Vdpm参数不能更新，即无法设置为高档位，将会导致充电芯片内部的降压工作管buck出现串通，损坏充电芯片，甚至还可能会导致充电芯片的寄存器被改写，电池电压可能超过恒压保护参数，出现电池充爆等安全隐患。
为解决上述问题，请参见图2A，图2A是本发明实施例提供的一种终端设备的架构示意图。如图2A所示的终端设备100包括用于设备充电的充电电路，该充电电路可包括充电芯片102、处理器104以及电池106。其中，所述充电芯片102用于将电源电压转换为电池电压，以向所述电池106充电，其中，所述电源电压大于限制电源电压，所述电池电压小于限制电池电压；所述处理器104用于在满足第一条件的情况下，同时将所述限制电源电压以及所述限制电池电压增大，或者，将所述限制电池电压增大的同时将充电电流减小，所述第一条件至少包括所述电池电压大于电池电压阈值；所述处理器104还用于在满足第二条件的情况下，同时将所述限制电源电压以及所述限制电池电压减小，或者，将所述限制电池电压减小的同时将充电电流增大，所述第二条件至少包括所述电池电压小于电池电压阈值。
本申请中，所述限制电源电压为所述充电芯片的充电输入端的最小限制电压。具体可为所述充电输入端设置的允许的最小限制电压，即前文所述的Vdpm，如图1所示VBUS端的最小限制电压Vdpm参数。所述限制电池电压为所述充电芯片的电池供电端的最大限制电压，具体可为所述电池供电端设置的允许的最大限制电压，即前文所述的恒压保护参数，如图1所示VBAT端的最大限制电压参数。所述电源电压是指所述充电芯片的充电输入端的实际电压，如图1所示VBUS端的实际电压。所述电池电压是指所述充电芯片的电池供电端的实际电压，如图1所示VBAT端的实际电压。
可选实施例中，所述充电电路包括但不限于开关充电电路、线性充电电路。在不同的充电电路中，所述处理器104可通过比较所述电池电压与所述电池电压阈值来对应调节相应地的充电参数。其中，所述电池电压阈值可为用户侧或终端设备侧自主设置的，本发明不做限定。
例如，开关充电电路中，在所述电池电压大于所述电池电压阈值的情况下，可同步将所述限制电源电压(Vdpm)以及所述限制电池电压增大。在线性充电电路中，在 所述电池电压大于所述电池电压阈值的情况下，可将所述限制电源电压(即恒压保护参数)增大，或者在将所述限制电源电压增大的同时将充电电流减小。其中，所述充电电流是指通过所述充电芯片的电池供电端输出的向所述电池106充电的电流大小。相应地，开关充电电路中，在所述电池电压小于所述电池电压阈值的情况下，可同步将所述限制电源电压(Vdpm)以及所述限制电池电压减小。线性充电电路中，在所述电池电压小于所述电池电压阈值的情况下，可将所述限制电池电压减小，或者在将所述限制电池电压减小的同时将所述充电电流增大。关于如何调节充电电路中的相关参数，将在下文进行具体阐述。
应理解的是，在终端设备充电过程中，插入充电器后，充电器的输出端口到充电芯片的充电输入端之间的线缆存在阻抗(电阻)。假设充电器的输入电压为V0，充电芯片的充电输入端(如图1所示的VBUS)设置的限制电源电压为Vdpm，充电链路的阻抗为R(如图1所示为适配器到VBUS端之间的阻抗)。相应地，根据欧姆定律I＝(V0-Vdpm)/R可知，R一定的情况下，I与充电线缆上的电压差(V0-Vdpm)成正比，当电池电压小于电池电压阈值(即电池剩余容量小于预设容量值)的情况下，应增大充电电流，即减小Vdpm，以缩短充电时长。相应地，在电池电压(电池容量)大于电池电压阈值的情况下，应减小充电电流，即增大Vdpm，以保护设备电池的安全充电。
通过实施本发明实施例，能够避免现有技术中设置一次Vdpm和恒压保护参数导致不能灵活条件设备充电速度、充电时间过长，或者Vdpm不能及时更新导致的充电芯片损坏、电池充电爆炸等问题。
需要说明的是，在实际应用中，如图2A示出的终端设备中所述充电芯片102可以包括处理器，充电芯片102的处理器以及所述处理器104可以是同一物理处理器，即处理器104也可设置在充电芯片102上，具体请参见图2B示出又一种可能的终端设备的架构示意图。
如图2B，所述终端设备200包括用于设备充电的充电电路，该充电电路可包括充电芯片202以及电池206。其中，
所述充电芯片202用于将电源电压转换为电池电压，以向所述电池206充电，其中，所述电源电压大于限制电源电压，所述电池电压小于限制电池电压；
所述充电芯片202还用于在满足第一条件的情况下，同时将所述限制电源电压以及所述限制电池电压增大，或者，将所述限制电池电压增大的同时将充电电流减小，所述第一条件至少包括所述电池电压大于电池电压阈值；
所述充电芯片202还用于在满足第二条件的情况下，同时将所述限制电源电压以及所述限制电池电压减小，或者，将所述限制电池电压减小的同时将充电电流增大，所述第二条件至少包括所述电池电压小于电池电压阈值。
关于本发明实施未示出或未描述的部分，可参见前述图2A所述实施例中的相关介绍，这里不再赘述。
下面本发明实施例将基于图2A所示的终端设备为例，具体介绍本发明涉及的两种 充电电路以及基于两种充电电路各自对应的终端设备的充电控制实施例。图3和图4示出本发明关于开关充电电路的相关实施例。图5和图6示出本发明关于线性充电电路的相关实施例。
如图3示出一种开关充电电路的示意图。该开关充电电路300可包括充电芯片302、处理器304以及电池306。其中，所述充电芯片302分别与所述处理器304以及电池306电性连接。
在可选实施例中，所述充电芯片可包括充电输入端VBUS和电池供电端VBAT。所述充电输入端可外接电源(如外接充电器)，用于输入电源电压。所述电池供电端与所述电池306电性连接，用于输出充电电流或者输出充电电压向所述电池充电。
在可选实施例中，所述处理器可通过串行总线(inter-integrated circuit，I2C)与所述充电芯片电性连接。所述I2C总线可包括时钟线(system clock line，SCL)和数据线(serial data，SDA)，本申请不做过多详述。
在可选实施例中，所述开关充电电路还可包括负载(load)，所述充电芯片与所述负载电性连接。可选地，所述开关充电电路还可包括外围器件，例如图3所述充电芯片还可包括电容C和电感L，所述充电芯片还可包括第一端口、第二端口以及第三端口，图示对应分别为LX端口、BST端口以及SYS端口。其中，所述LX端口通过所述电感与所述负载电性连接。所述BST端口通过所述电容分别与所述LX端口以及所述电感的一端电性连接。所述SYS端口与所述负载电性连接。
在可选实施例中，所述开关充电电路还包括过压保护(overvoltage protection，OVP)芯片、主副板连接接口以及充电接口。其中，所述OVP芯片用于保护所述充电芯片，控制所述充电芯片的充电输入端的实际电压不超过芯片上限阈值，所述芯片上限阈值可为用户侧或终端设备侧自主设置的，本发明不做过多详述。所述主副板连接接口用于电性连接主板和副板，其中，所述主板可包括但不限于所述充电芯片302、所述处理器304、所述电池306以及后续可选实施例中的负载、OVP芯片以及主板的连接接口等元器件，所述副板可包括但不限于副板的连接接口以及充电接口，具体如图3所示。其中，所述主副板连接接口可通过柔性印刷电路(flexible printed circuit，FPC)连接。所述充电接口用于外接充电电源，以向所述充电芯片输入电源电压，所述充电接口包括但不限于通用串行总线(universal serial bus，USB)接口。
在可选实施例中，在利用开关充电电路充电时，所述充电接口可外接充电器或适配器，具体如图3所示。关于本发明涉及的相关元器件，本申请不做过多阐述。
基于图3所示的开关充电电路示意图，请参见图4，是本发明实施例提供的一种终端设备的结构示意图。所述终端设备可包括图3所述实施例中开关充电电路的所有或者部分连接元器件，本发明不做限定。如图4，这里仅示出所述终端设备包括充电芯片302、处理器304以及电池306，下面介绍涉及这些元器件的具体实施例。
所述充电芯片302用于将电源电压转换为电池电压，以向所述电池306充电，其中，所述电源电压大于限制电源电压，所述电池电压小于限制电池电压；
所述处理器304用于在满足第一条件的情况下，同时将所述限制电源电压以及所述限制电池电压增大，所述第一条件至少包括所述电池电压大于电池电压阈值；
所述处理器304还用于在满足第二条件的情况下，同时将所述限制电源电压以及所述限制电池电压减小，所述第二条件至少包括所述电池电压小于电池电压阈值。
下面介绍本发明涉及的一些具体实施例以及可选实施例。
在终端设备插入充电器进行充电后，所述处理器304可判断是否满足第一条件，如果满足，则所述处理器304可同步将所述限制电源电压(Vdpm)以及所述限制电池电压(即恒压保护参数)调高/增大。其中，所述第一条件可包括所述电池电压大于电池电压阈值。关于所述电池电压、所述电池电压阈值、所述限制电源电压以及所述限制电池电压可参见前述实施例中的相关描述，这里不再赘述。
具体实现中，所述处理器304可向所述充电芯片302发送第一获取指令，所述第一获取指令用于获取所述充电芯片的电池供电端(VBAT)的电压，即本申请中的电池电压。相应地所述充电芯片302可接收所述第一获取指令，根据所述第一获取指令采集所述电池供电端的电压(即所述电池电压)并反馈给所述处理器304。接着，所述处理器304可根据获取的所述电池电压对充电电路中的相关进行调节，例如所述处理器304在判断到所述电池电压大于等于电池电压阈值(如4.08V)时，则可控制同步将所述限制电源电压(Vdpm)以及所述限制电池电压增大。如果在判断到所述电池电压小于电池电压阈值(如4.08V)时，则可控制同步将所述限制电源电压(Vdpm)以及所述限制电池电压减小。
在可选实施例中，所述第一条件或者所述第二条件还可包括测试电压小于预设阈值，和/或目标次数超过预设次数。其中，所述测试电压可以是指在终端设备插入充电器后实际检测到所述充电输入端的电压，或者是指所述充电芯片利用测试电流检测的所述充电输入端的电压。所述目标次数是指所述测试电压小于预设阈值的次数。所述预设阈值和所述预设次数可以是用户侧或终端设备侧自主设置的。可选地，所述预设阈值可以是系统默认设置的限制电源阈值，如4.675V等，或其他用户/系统自定义设置的阈值，本发明不做限定。下面介绍具体实施时涉及的两种实施方式。
第一种实施方式中，所述处理器304向所述充电芯片302发送第一获取指令之前，所述处理器304可向所述充电芯片302发送读取指令，所述读取指令用于读取所述充电芯片是否处于DPM状态，所述DPM状态用于指示测试电压小于等于预设阈值。可选的，所述DPM状态可用于指示测试电压触发了预设阈值，所述测试电压小于或保持在预设阈值。
相应地所述充电芯片可接收所述读取指令，根据所述读取指令的指示将所述充电芯片的状态反馈给所述处理器。其中，所述充电芯片的状态包括处于DPM状态，或者不处于DPM状态，所述状态可为所述充电芯片预先设置的，具体在下文中详述。当所述处理器304确定到所述充电芯片处于DPM状态(即测试电压小于等于预设阈值)时，所述处理器304可继续向所述充电芯片302发送第一获取指令，以根据获取的所述电池电压同步调整所述限制电源电压Vdpm以及所述限制电池电压(即恒压保护参数)。
在可选实施例中，所述充电芯片的状态可用预设字符串来标识，所述预设字符串包括但不限于预设字母、预设数字等等，例如可用“0”表示所述充电芯片不处于DPM 状态，用“1”表示所述充电芯片处于DPM状态。
在可选实施例中，所述充电芯片的状态可为所述充电芯片预先设置的。在一种具体实施方式中，在终端设备插入充电器后，为保证数据可靠性，经过第一预设时长后所述充电芯片可采集所述充电输入端(VBUS)的电压，作为所述测试电压。在所述测试电压小于等于预设阈值的情况下，所述充电芯片可标记自身处于DPM状态，例如将所述充电芯片的状态标记为“1”等。相应地，在所述测试电压大于预设阈值的情况下，所述充电芯片可标记自身不处于DPM状态，例如将所述充电芯片的状态标记为“0”等。
在又一种具体实施方式中，在终端设备插入充电器后，所述充电芯片可记录数据线上的电流大小，并作为第一电流。所述数据线为连接所述充电器与所述充电芯片(即终端设备)的线缆，也可称为充电线。由于不同厂商生产的充电线的规格不同(即充电线上的阻抗不同)，所述充电芯片可利用测试电流检测所述充电芯片的充电输入端的电压，作为所述测试电压。具体的，所述充电芯片可设置所述充电线上的电流为测试电流(如900mA，毫安)，在经过第二预设时长后，采集所述充电输入端的电压，作为所述测试电压。接着，在确定到所述测试电压小于等于预设阈值的情况下，标记所述充电芯片处于DPM状态。相应地，在确定到所述测试电压大于预设阈值的情况下，标记所述充电芯片不处于DPM状态。
在可选实施例中，所述测试电流以及所述第二预设时长可为用户侧或终端设备侧自主设置的，本发明不做限定。在所述充电芯片标记完自身是否处于DPM状态后，所述充电芯片可将所述充电线的电流还原设置为所述第一电流，所述第一电流为所述终端设备插入充电器进行正常充电时所述充电线上的电流。
在可选实施例中，为保证参数调节的准确性以及设备充电控制的高可靠性，所述处理器304可多次获取所述充电芯片的状态，如果所述充电芯片处于DPM状态的次数超过预设次数(即所述测试电压小于预设阈值的次数)，则所述处理器304可继续后续流程，向所述充电芯片302发送第一获取指令，以根据获取的所述电池电压同步调整充电电路中的相关参数，如所述限制电源电压Vdpm以及所述限制电池电压。
在可选实施例中，当所述处理器304确定到所述充电芯片处于DPM状态，或者所述充电芯片处于DPM状态的次数超过预设次数的情况下，所述处理器304可确定所述终端设备当前处于弱充状态，所述弱充状态与所述DPM状态或者所述DPM状态的次数关联。相应地所述处理器304可继续执行后续流程，以根据获取的电池电压调节充电电路中的相关参数，如所述限制电源电压Vdpm以及所述限制电池电压。反之，当所述处理器304确定到所述充电芯片不处于DPM状态，或者所述充电芯片处于DPM状态的次数不超过预设次数的情况下，所述处理器304可确定所述终端设备当前处于非弱充状态，可结束后续流程。
第二种实施方式中，所述处理器304向所述充电芯片302发送第一获取指令之前，所述处理器304可直接向所述充电芯片302发送第二获取指令，所述第二获取指令用于获取所述充电芯片的充电输入端的测试电压。相应地所述充电芯片接收所述第二获取指令后，根据所述第二获取指令的指示采集所述充电输入端的测试电压，并反馈给 所述处理器304。进一步地所述处理器304可将获取的所述测试电压和预设阈值进行比较，在所述测试电压小于等于预设阈值的情况下，可向所述充电芯片302发送第一获取指令，以根据获取的电池电压进行相关参数的调节。在所述测试电压大于预设阈值的情况下，可结束流程。下面介绍获取所述测试电压涉及的两种具体实施方式。
在一种具体实施方式中，所述处理器304向所述充电芯片302发送第二获取指令。相应地所述充电芯片302接收所述第二获取指令，根据所述第二获取指令的指示获取所述充电输入端(VBUS)的电压，作为所述测试电压。
在又一种具体实施方式中，所述处理器304向所述充电芯片302发送第二获取指令。相应地所述充电芯片302接收所述第二获取指令，所述充电芯片可记录数据线上的电流大小，并作为第一电流。接着，所述充电芯片302可利用测试电流检测所述充电芯片的充电输入端的电压作为所述测试电压，具体可参见前述第一实施方式中的相关介绍，这里不再赘述。
在可选实施例中，所述处理器304还可确定所述数据线上的阻抗。具体的，所述处理器304可根据目标压差V 1以及所述数据线上的电流I，确定所述数据线上的阻抗R 1。其中，V 1＝I*R 1，V 1、I和R 1均为正数。所述目标压差V 1为所述充电器的输出电压V out与所述测试电压V in之间的差值。
在可选实施例中，为保证参数调节的准确性以及设备充电控制的高可靠性，所述处理器304可多次获取所述充电芯片中充电输入端的测试电压，在所述测试电压小于等于预设阈值的次数(即目标次数)超过预设次数的情况下，所述处理器304可继续后续流程，这里不再赘述。反之，在所述测试电压小于等于预设阈值的次数不超过预设次数的情况下，可结束流程，不对充电电路中的相关参数(如Vdpm及恒压保护参数)进行调节。
在可选实施例中，在所述处理器304确定到所述测试电压小于等于预设阈值，或者所述测试电压小于等于预设阈值的次数超过预设次数的情况下，所述处理器304可确定所述终端设备处于弱充状态，进一步地可继续后面的根据获取的电池电压调节充电电路中的相关参数，这里不再赘述。反之，在所述处理器304确定到所述测试电压小于等于预设阈值，或者所述测试电压小于等于预设阈值的次数不超过预设次数的情况下，所述处理器304可确定所述终端设备处于非弱充状态，可结束流程，不对充电电路中的相关参数进行调节。
在可选实施例中，所述第一条件还可包括所述电池电压处于上升期。可选地，所述第二条件还可包括所述电池电压处于上升期，或者所述电池电压处于下降期。
具体实现中，所述充电芯片302可实时或者周期性地记录所述电池供电端(VBAT)的电压，即本申请中的电池电压。关于所述电池电压的记录形式本发明不做限定，例如以数据表格、向量、矩阵等形式存储。所述处理器304可获取第三预设时长内记录的所述电池电压，分析这些电池电压，可获知第三预设时长内所述电池电压是处于上升期还是下降期。示例性地如在所述第三预设时长内记录的电池电压随着时间变化逐渐增大，则表示所述电池电压处于上升期，反之则表示所述电池电压处于下降期。其中，所述第三预设时长可为用户侧或终端设备侧自主设置的，本发明不做限定。
相应地，所述处理器304可根据获取的所述电池电压同步调节所述限制电源电压(Vdpm)以及所述限制电池电压。具体的，所述处理器304可在确定到所述电池电压处于上升期，且所述电池电压大于电池电压阈值(即满足第一条件)的情况下，同步将所述限制电源电压(Vdpm)以及所述限制电池电压增大。相应地，所述处理器304在确定到所述电池电压小于电池电压阈值，不论所述电池电压处于上升期或者下降期(即满足第二条件)的情况下，可同步将所述限制电源电压Vdpm以及所述限制电池电压减小。
在可选实施例中，在所述第二条件还包括所述电池电压处于上升期的情况下，所述电池电压阈值为第一电池电压阈值；在所述第二条件还包括所述电池电压处于下降期的情况下，所述电池电压阈值为第二电池电压阈值；其中，所述第一电池电压阈值大于第二电池电压阈值。
为保证参数调节的稳定性，可设置电压回滞区间。具体的，在所述处理器304可获取第三预设时长内的电池电压，如果处理器通过分析获知电池电压处于上升期，且所述电池电压小于等于第一电池电压阈值，则可同步将所述限制电源电压Vdpm以及所述限制电池电压(减小。相应地，如果处理器通过分析获知电池电压处于下降期，可设置电压回滞区间，即所述电池电压小于等于第二电池电压阈值，则可同步将所述限制电源电压Vdpm以及所述限制电池电压减小。其中，第一电池电压阈值大于第二电池电压阈值，该电压回滞区间为第一电池电压阈值至第二电池电压阈值。
以4.4V的电池、5V的充电器(即充电器连接5V的充电电源)为例，在终端设备插入充电器为电池充电后，充电芯片302可记录充电线上的第一电流，该充电线为用于连接所述充电器与所述终端设备的数据线。进一步地，所述充电芯片可用测试电流在所述充电线上去检测所述充电芯片的充电输入端的电压，经过第一预设时长(例如延迟100ms，毫秒)后，采集所述充电输入端的电压，以作为测试电压。所述充电芯片在判断到所述测试电压小于等于预设阈值(如4.675V为例)的情况下，可标记所述充电芯片处于DPM状态(或者弱充状态)；否则，标记所述充电芯片不处于DPM状态。相应地，所述充电芯片还可将所述充电线上的电流还原设置为所述第一电流，以恢复所述终端设备的正常充电。
相应地，处理器304可向所述充电芯片发送读取指令，以读取所述充电芯片是否处于DPM状态。在所述处理器304读取到所述充电芯片不处于DPM状态后，可确定所述终端设备当前处于非弱充状态，结束流程。在所述处理器304读取到所述充电芯片处于DPM状态后，可确定所述终端设备当前处于弱充状态，进一步地所述处理器304可获取所述充电芯片的电池供电端的电压，即本申请中的所述电池电压。
接着，所述处理器可根据所述电池电压同步调整所述限制电源电压(Vdpm)以及所述限制电池电压(即恒压保护参数)，关于Vdpm以及恒压保护参数可具体参见前述实施例中的相关描述，这里不再赘述。例如，在所述电池电压处于上升期，且所述电池电压大于第一电池电压阈值(如4.08V)时，所述处理器可同步将所述限制电源电压(Vdpm)增大调节至高档位(如4.675V)，将所述限制电池电压增大调节至4.4V等。在所述电池电压处于上升期，且所述电池电压小于等于第一电池电压阈值4.08V 时，所述处理器可同步将所述限制电源电压(Vdpm)减小调节至低档位(如4.46V)，将所述限制电池电压减小调节至4.15V等。在所述电池电压处于下降期，可设置电压回滞区间(如280mV毫伏)，即所述电池电压小于等于第二电池电压阈值(4.08V-0.28V＝3.8V)时，所述处理器可同步将所述限制电源电压(Vdpm)减小调节至低档位(如4.46V)，将所述限制电池电压减小调节至4.15V等。
应理解的是，在终端设备充电初始阶段，即电池电压小于等于第一电池电压阈值时，为减小充电时长，应增大充电电流，参见前述图2A所述实施例中的相关描述，I＝(V0-Vdpm)/R，其中，V0为充电电源5V，R为充电线上的阻抗。在充电线上的阻抗一定的情况下，为增大充电电流I，则应减小Vdpm。相应地，在电池容量超过设定门限，即所述电池电压大于第一电池电压阈值时，为保证电池充电的安全性，应减小充电电流，参见前文所述在充电线上的阻抗一定的情况下，为减小充电电流I，则应增大Vdpm。
在可选实施例中，在终端设备插入充电器进行充电的过程中，所述处理器304还可记录所述终端设备的充电时长，以供用户查看设备的充电时长，直观了解采用本申请后能够缩短终端设备的充电时长。如下表1示例性给出一个测试数据表，该测试数据表直观反映了采用本申请后终端设备的充电时长明显小于常规技术中终端设备的充电时长。
表1
Figure PCTCN2018107791-appb-000001
由上表1可知，上述标配数据线是指用于连接充电器与终端设备的数据线，即前文所述的充电线。由于不同厂商生产的标配数据线上的阻抗不同，有些较小，有些较大。因此在测试环节，为保证测试数据的准确性，可在标配数据线上串联适当大小的阻抗，如上表1串联0.75或0.5欧姆的阻抗，且在同一测试条件下，采用多条数据线进行测试。由上表1可直观获知，采用本申请实施例来对应调节充电电路上的相关参数(如限制电源电压Vdpm以及限制电池电压，即恒压保护参数)可明显缩短充电时长。
在可选实施例中，在插入充电器充电过程中，所述处理器可实时或周期性地获取所述电池电压，以根据所述电池电压调整充电电路中的相关参数，例如所述限制电池电压以及所述限制电源电压Vdpm。可选地，当所述处理器检测到所述电池满电时，可提示拔出充电器，以结束充电。
通过实施本发明实施例，能够克服现有技术中限制电源电压Vdpm不能及时更新导致充电芯片损坏，或者寄存器被改写导致出现电池充爆等安全隐患，或者现有技术中支持设置一次限制电源电压Vdpm造成不能灵活调节充电速度，充电时间过长等问题。在保证终端设备充电安全的前提下，缩短充电时长。
如图5示出一种线性充电电路的示意图。该线性充电电路500可包括充电芯片502、处理器504以及电池506。其中，所述充电芯片502分别与所述处理器504以及电池506电性连接。关于所述充电芯片、所述处理器以及所述电池可参见前述实施例中的相关介绍，这里不再赘述。
在可选实施例中，所述开关充电电路还可包括负载(load)，所述充电芯片与所述负载电性连接。可选地，所述线性充电电路还可包括放大器Q1、电阻R、充电接口，或者其他外围器件，例如图5中所述线性充电电路还包括放大器Q1以及电阻R，所述充电芯片还包括第一端口(图示为Isense端)。其中，Q1的基极与所述充电芯片的充电输入端(VBUS)电性连接，Q1的集电极通过电阻R与所述电池506电性连接，所述充电芯片的Isense端分别与Q1的集电极和电阻R的一端电性连接，所述充电芯片的电池供电端(VBAT)分别与所述电池和电阻R的另一端电性连接，Q1的发射极与充电接口电性连接。
在可选实施例中，所述充电芯片的每个端口(或引脚)均存在相应地耐压范围，如果端口电压超过该端口规定的耐压范围，将会损坏充电芯片。如图5，以4.4V的电池为例，充电芯片的Isense端的耐压范围是0～4.5V。相应地在充电过程中，需保证充电芯片的Isense端不能超过4.5V，即可解除芯片过压损坏等风险。
在可选实施例中，在利用线性充电电路充电时，所述充电接口可外接恒压源(direct current，DC)，如利用充电器对电池进行充电，具体如图5所示。关于本发明涉及的相关元器件可参见前述实施例中的相关描述，这里不再赘述。
基于图5所示的线性充电电路示意图，请参见图6，是本发明实施例提供的一种终端设备的结构示意图。所述终端设备可包括图5所述实施例中线性充电电路的所有或部分连接元器件，本发明不做限定。如图6，这里仅示出所述终端设备包括充电芯片502、处理器504以及电池506，下面介绍涉及这些元器件的具体实施例。
所述充电芯片502用于将电源电压转换为电池电压，以向所述电池506充电，其中，所述电源电压大于限制电源电压，所述电池电压小于限制电池电压；
所述处理器504用于在满足第一条件的情况下，将所述限制电池电压增大，或者将所述限制电池电压增大的同时将充电电流减小，所述第一条件至少包括所述电池电压大于电池电压阈值；
所述处理器504还用于在满足第二条件的情况下，将所述限制电池电压减小，或 者将所述限制电池电压减小的同时将充电电流增大，所述第二条件至少包括所述电池电压小于电池电压阈值。
下面介绍本发明涉及的一些具体实施例以及可选实施例。
在终端设备插入充电器进行充电后，所述处理器504可向所述充电芯片502发送读取指令，所述读取指令用于获取电池电压，该电池电压为所述充电芯片502的电池供电端的电压。相应地，所述充电芯片接收所述读取指令，根据所述读取指令的指示读取所述电池供电端的电压，即本申请中的所述电池电压。
进一步地，所述处理器504可根据所述电池电压来调整所述限制电池电压(即恒压保护参数)，或者同步调整所述限制电池电压以及充电电流。其中，关于所述限制电池电压和充电电流可参见前述实施例中的相关描述，这里不再赘述。
具体实现中，如图5，所述充电芯片可通过检测电阻R两端的电压来获取电池电压以及充电电流。相应地，所述处理器可通过对Q1的基极(也可称为控制端)的调节，进而控制/调节充电电流的大小。具体的，所述处理器504在判断到所述电池电压大于电池电压阈值的情况下，将所述限制电池电压增大，或者将所述限制电池电压增大的同时将充电电流减小。反之，所述处理器504在判断到所述电池电压小于电池电压阈值的情况下，将所述限制电池电压减小，或者将所述限制电池电压减小的同时将充电电流增大。所述电池电压阈值为用户侧或终端设备侧自主设置的，本发明不做限定。
以4.4V电池为例，如图5，在充电过程中，所述处理器可从所述充电芯片处获取所述电池供电端(VBAT)的电压(即本申请的所述电池电压)。相应地，所述处理器可根据所述电池电压所处的阈值区间来对应调节充电电路中的相关参数。例如，当所述电池电压小于等于第一电池电压阈值(如4.24V)时，所述处理器可将所述电池供电端的最大限制电压(即所述限制电池电压或恒压保护参数)减小设置为第一电池电压(如4.25V)，可选地还可通过调节Q1的集电极以将充电电流I增大设置为第一充电电流(如1A)。当所述电池电压大于第一电池电压阈值4.24V，且小于等于第二电池电压阈值(如4.29V)时，所述处理器可将所述限制电池电压增大设置为第二电池电压(如4.3V)，可选地还可将充电电流I减小设置为第二充电电流(如0.7A)。相应地，当所述电池电压大于第二电池电压阈值4.29V时，所述处理器可将所述限制电池电压增大设置为第三电池电压(如4.35V)，可选地还可将充电电流I减小设置为第三充电电流(如0.45A)。其中，所述第一电池电压小于第二电池电压小于第三电池电压，所述第一充电电流大于第二充电电流大于第三充电电流。
在可选实施例中，在插入充电器充电过程中，所述处理器可实时或周期性地获取所述电池电压，以根据所述电池电压调整充电电路中的相关参数，例如所述限制电池电压以及充电电流。可选地，当所述处理器检测到所述电池满电时，可提示拔出充电器，以结束充电。
本发明实施例中未描述的内容，可参见前述图2A至图5实施例中的相关描述，这里不再赘述。
通过实施本发明实施例，能够在保证终端设备充电安全的前提下，缩短充电时长。
基于同一发明构思，下面介绍本发明对应涉及的方法实施例。请参见图7，是本发明实施例提供的一种充电控制方法的流程示意图。如图7所示的充电控制方法，包括如下实施步骤：
步骤S702、终端设备通过充电芯片将电源电压转换为电池电压，以向所述电池充电，其中，所述电源电压大于限制电源电压，所述电池电压小于限制电池电压，所述限制电源电压为所述充电芯片的充电输入端的最小限制电压，所述限制电池电压为所述充电芯片的电池供电端的最大限制电压；
步骤S704、所述终端设备在满足第一条件的情况下，通过处理器同时将所述限制电源电压以及所述限制电池电压增大，或者，将所述限制电池电压增大的同时将充电电流减小；
步骤S706、所述终端设备在满足第二条件的情况下，通过处理器同时将所述限制电源电压以及所述限制电池电压减小，或者，将所述限制电池电压减小的同时将充电电流增大；其中，所述充电电流为用于向所述电池充电的电流，所述第一条件至少包括所述电池电压大于电池电压阈值，所述第二条件至少包括所述电池电压小于电池电压阈值。
本申请中，为实现终端设备的充电，所述终端设备内部设置有充电电路，该充电电路包括但不限于开关充电电路、线性充电电路等。所述充电电路指示包括充电芯片、处理器、电池以及一些其他的元器件，例如负载等等，具体可参见前述实施例中的相关阐述，这里不再赘述。
在可选实施例中，所述限制电源电压为所述充电芯片的充电输入端(VBUS)的最小限制电压，即前文所述的Vdpm。所述限制电池电压为所述充电芯片的电池供电端(VBAT)的最大限制电压，即前文所述的恒压保护参数。所述电源电压是指所述充电芯片的充电输入端的实际电压。所述电池电压是指所述充电芯片的电池供电端的实际电压。所述充电电流是指用于向所述电池充电的电流，如图5中流过电阻R的充电电流。
在可选实施例中，在所述充电电路为开关充电电路，即所述同时将所述限制电源电压以及所述限制电池电压减小的情况下，所述第一条件还可包括测试电压小于预设阈值，和/或目标次数超过预设次数，其中所述目标次数是指所述测试电压小于预设阈值的次数。
相应地，在所述充电电路为开关充电电路，即所述同时将所述限制电源电压以及所述限制电池电压增大的情况下，所述第一条件还可包括测试电压小于预设阈值，和/或目标次数超过预设次数，其中所述目标次数是指所述测试电压小于预设阈值的次数。
其中，所述测试电压为在所述充电芯片的充电输入端所检测的电压。具体的，所述测试电压可在终端设备插入充电器后，检测的所述充电输入端的实际电压；或者，利用测试电流在所述充电输入端所检测的测试电压，具体可参见前述实施例中的相关描述，这里不再赘述。
在可选实施例中，在所述充电电路为开关充电电路，即所述同时将所述限制电源电压以及所述限制电池电压减小的情况下，所述第一条件还包括所述电池电压处于上 升期。
在可选实施例中，在所述充电电路为开关充电电路，即所述同时将所述限制电源电压以及所述限制电池电压减小的情况下，所述第二条件还包括所述电池电压处于上升期，或者，所述电池电压处于下降期。
在可选实施例中，在开关充电电路中，在所述第二条件还包括所述电池电压处于上升期的情况下，所述电池电压阈值为第一电池电压阈值；在所述第二条件还包括所述电池电压处于下降期的情况下，所述电池电压阈值为第二电池电压阈值；其中，所述第一电池电压阈值大于第二电池电压阈值。
需要说明的是，本申请中上述步骤S704和步骤S706可以并列执行的，即终端设备可执行步骤S7104和步骤S706中的任一步骤，本发明不做限定。
关于本发明实施未描述的内容，可具体前述图2A至图6所述实施例中的相关描述，这不再赘述。
通过实施本发明实施例，能够在保证终端设备充电安全的前提下，缩短终端设备的充电时长。
上述主要从终端设备的角度出发对本发明实施例提供的方案进行了介绍。可以理解的是，终端设备为了实现上述功能，其包含了执行各个功能相应的硬件结构和/或软件模块。结合本发明中所公开的实施例描述的各示例的单元及算法步骤，本发明实施例能够以硬件或硬件和计算机软件的结合形式来实现。某个功能究竟以硬件还是计算机软件驱动硬件的方式来执行，取决于技术方案的特定应用和设计约束条件。本领域技术人员可以对每个特定的应用来使用不同的方法来实现所描述的功能，但是这种实现不应认为超出本发明实施例的技术方案的范围。
本发明实施例可以根据上述方法示例对消息处理设备进行功能单元的划分，例如，可以对应各个功能划分各个功能单元，也可以将两个或两个以上的功能集成在一个处理单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。需要说明的是，本发明实施例中对单元的划分是示意性的，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式。
在采用集成的单元的情况下，图8A示出了上述实施例中所涉及的终端设备的一种可能的结构示意图。终端设备800包括：处理单元802和通信单元803。处理单元802用于对终端设备800的动作进行控制管理，例如，处理单元802用于支持终端设备800执行图7中步骤S702、S704和S706，和/或用于执行本文所描述的技术的其它步骤。通信单元803用于支持终端设备800与其它终端设备的通信，例如，通信单元803用于支持终端设备800与充电器进行数据通信，和/或用于执行本文所描述的技术的其它步骤。终端设备800还可以包括存储单元801，用于存储终端设备800的程序代码和数据。
其中，处理单元802可以是处理器或控制器，例如可以是中央处理器(Central Processing Unit，CPU)，通用处理器，数字信号处理器(Digital Signal Processor，DSP)，专用集成电路(Application-Specific Integrated Circuit，ASIC)，现场可编程门阵列(Field Programmable Gate Array，FPGA)或者其他可编程逻辑器件、晶体管逻辑器件、硬件 部件或者其任意组合。其可以实现或执行结合本发明公开内容所描述的各种示例性的逻辑方框，模块和电路。所述处理器也可以是实现计算功能的组合，例如包含一个或多个微处理器组合，DSP和微处理器的组合等等。通信单元803可以是通信接口、收发器、收发电路等，其中，通信接口是统称，可以包括一个或多个接口，例如消息处理设备与终端设备之间的接口。存储单元801可以是存储器。
在本申请中，所述处理单元802可为如上图2A所述实施例中的处理器以及充电芯片；也可为如上图2B所述实施例中的充电芯片，本发明不做限定。
当处理单元802为处理器，通信单元803为通信接口，存储单元801为存储器时，本发明实施例所涉及的终端设备可以为图8B所示的终端设备。
参阅图8B所示，该终端设备810包括：处理器812、通信接口813、存储器811。可选地，终端设备810还可以包括总线814。其中，通信接口813、处理器812以及存储器811可以通过总线814相互连接；总线814可以是外设部件互连标准(Peripheral Component Interconnect，PCI)总线或扩展工业标准结构(Extended Industry Standard Architecture，EISA)总线等。所述总线814可以分为地址总线、数据总线、控制总线等。为便于表示，图8B中仅用一条粗线表示，但并不表示仅有一根总线或一种类型的总线。
上述图8A或图8B所示的消息处理设备的具体实现还可以对应参照图2A至图7所示实施例的相应描述，此处不再赘述。
参见图9，图9示出了本申请提供的一种装置的结构示意图。如图9所示，装置900(例如充电芯片)可包括：处理器901，以及耦合于处理器901的一个或多个接口902。其中：
处理器901可用于读取和执行计算机可读指令。具体实现中，处理器901可主要包括控制器、运算器和寄存器。其中，控制器主要负责指令译码，并为指令对应的操作发出控制信号。运算器主要负责执行定点或浮点算数运算操作、移位操作以及逻辑操作等，也可以执行地址运算和转换。寄存器主要负责保存指令执行过程中临时存放的寄存器操作数和中间操作结果等。具体实现中，处理器901的硬件架构可以是专用集成电路(Application Specific Integrated Circuits,ASIC)架构、MIPS架构、ARM架构或者NP架构等等。处理器901可以是单核的，也可以是多核的。
接口902可用于输入待处理的数据至处理器901，并且可以向外输出处理器901的处理结果。具体实现中，接口902可以是通用输入输出(General Purpose Input Output，GPIO)接口，可以和多个外围设备(如电池、显示器(LCD)、摄像头、射频模块等等)连接。接口902还可以包括多个独立的接口，例如以电池接口、太网接口、LCD接口、Camera接口等，分别负责不同外围设备和处理器901之间的通信。
本申请中，处理器901可用于从存储器中调用本申请提供的所述充电控制方法在终端设备侧的实现程序，并执行该程序包含的指令。接口902可用于输出处理器901的执行结果。本申请中，接口902可具体用于输出处理器901的电池电压。关于本申请提供的所述充电控制方法可参考前述各个实施例中的相关描述，这里不再赘述。
需要说明的，处理器901、接口902各自对应的功能既可以通过硬件设计实现， 也可以通过软件设计来实现，还可以通过软硬件结合的方式来实现，这里不作限制。
结合本发明实施例公开内容所描述的方法或者算法的步骤可以硬件的方式来实现，也可以是由处理器执行软件指令的方式来实现。软件指令可以由相应的软件模块组成，软件模块可以被存放于随机存取存储器(Random Access Memory，RAM)、闪存、只读存储器(Read Only Memory，ROM)、可擦除可编程只读存储器(Erasable Programmable ROM，EPROM)、电可擦可编程只读存储器(Electrically EPROM，EEPROM)、寄存器、硬盘、移动硬盘、只读光盘(CD-ROM)或者本领域熟知的任何其它形式的存储介质中。一种示例性的存储介质耦合至处理器，从而使处理器能够从该存储介质读取信息，且可向该存储介质写入信息。当然，存储介质也可以是处理器的组成部分。处理器和存储介质可以位于ASIC中。另外，该ASIC可以位于网络设备中。当然，处理器和存储介质也可以作为分立组件存在于网络设备中。
本领域普通技术人员可以理解实现上述实施例方法中的全部或部分流程，是可以通过计算机程序来指令相关的硬件来完成，所述的程序可存储于计算机可读取存储介质中，该程序在执行时，可包括如上述各方法的实施例的流程。而前述的存储介质包括：ROM、RAM、磁碟或者光盘等各种可以存储程序代码的介质。

Claims (16)

  1. 一种终端设备，其特征在于，所述终端设备包括充电芯片、处理器以及电池，
    所述充电芯片用于将电源电压转换为电池电压，以向所述电池充电，其中，所述电源电压大于限制电源电压，所述电池电压小于限制电池电压，所述限制电源电压为所述充电芯片的充电输入端的最小限制电压，所述限制电池电压为所述充电芯片的电池供电端的最大限制电压；
    所述处理器用于在满足第一条件的情况下，同时将所述限制电源电压以及所述限制电池电压增大，或者，同时将所述限制电池电压增大以及将充电电流减小；在满足第二条件的情况下，同时将所述限制电源电压以及所述限制电池电压减小，或者，同时将所述限制电池电压减小以及将充电电流增大；其中，所述充电电流为用于向所述电池充电的电流，所述第一条件至少包括所述电池电压大于电池电压阈值，所述第二条件至少包括所述电池电压小于电池电压阈值。
  2. 根据权利要求1所述的终端设备，其特征在于，
    在所述同时将所述限制电源电压以及所述限制电池电压增大的情况下，所述第一条件还包括测试电压小于预设阈值，和/或，目标次数超过预设次数；
    在所述同时将所述限制电源电压以及所述限制电池电压减小的情况下，所述第二条件还包括测试电压小于预设阈值，和/或，目标次数超过预设次数；
    其中，所述测试电压为所述充电芯片的充电输入端的电压，所述目标次数为所述测试电压小于预设阈值的次数。
  3. 根据权利要求1或2所述的终端设备，其特征在于，在所述同时将所述限制电源电压以及所述限制电池电压增大的情况下，所述第一条件还包括所述电池电压处于上升期。
  4. 根据权利要求1或2所述的终端设备，其特征在于，在所述同时将所述限制电源电压以及所述限制电池电压减小的情况下，所述第二条件还包括所述电池电压处于上升期，或者，所述电池电压处于下降期。
  5. 根据权利要求4所述的终端设备，其特征在于，
    在所述第二条件还包括所述电池电压处于上升期的情况下，所述电池电压阈值为第一电池电压阈值；
    在所述第二条件还包括所述电池电压处于下降期的情况下，所述电池电压阈值为第二电池电压阈值；
    其中，所述第一电池电压阈值大于第二电池电压阈值。
  6. 一种充电控制方法，其特征在于，用于控制终端设备充电，所述终端设备包括充电芯片、处理器以及电池，所述方法包括：
    通过所述充电芯片将电源电压转换为电池电压，以向所述电池充电，其中，所述 电源电压大于限制电源电压，所述电池电压小于限制电池电压，所述限制电源电压为所述充电芯片的充电输入端的最小限制电压，所述限制电池电压为所述充电芯片的电池供电端的最大限制电压；
    在满足第一条件的情况下，通过所述处理器同时将所述限制电源电压以及所述限制电池电压增大，或者，同时将所述限制电池电压增大以及将充电电流减小；在满足第二条件的情况下，通过所述处理器同时将所述限制电源电压以及所述限制电池电压减小，或者，同时将所述限制电池电压减小以及将充电电流增大；其中，所述充电电流为用于向所述电池充电的电流，所述第一条件至少包括所述电池电压大于电池电压阈值，所述第二条件至少包括所述电池电压小于电池电压阈值。
  7. 根据权利要求6所述的方法，其特征在于，
    在所述同时将所述限制电源电压以及所述限制电池电压增大的情况下，所述第一条件还包括测试电压小于预设阈值，和/或，目标次数超过预设次数；
    在所述同时将所述限制电源电压以及所述限制电池电压减小的情况下，所述第二条件还包括测试电压小于预设阈值，和/或，目标次数超过预设次数；
    其中，所述测试电压为所述充电芯片的充电输入端的电压，所述目标次数为所述测试电压小于预设阈值的次数。
  8. 根据权利要求6或7所述的方法，其特征在于，在所述同时将所述限制电源电压以及所述限制电池电压增大的情况下，所述第一条件还包括所述电池电压处于上升期。
  9. 根据权利要求6或7所述的方法，其特征在于，在所述同时将所述限制电源电压以及所述限制电池电压减小的情况下，所述第二条件还包括所述电池电压处于上升期，或者，所述电池电压处于下降期。
  10. 根据权利要求9所述的方法，其特征在于，
    在所述第二条件还包括所述电池电压处于上升期的情况下，所述电池电压阈值为第一电池电压阈值；
    在所述第二条件还包括所述电池电压处于下降期的情况下，所述电池电压阈值为第二电池电压阈值；
    其中，所述第一电池电压阈值大于第二电池电压阈值。
  11. 一种终端设备，其特征在于，所述终端设备包括处理单元，
    所述处理单元用于将电源电压转换为电池电压，以向电池充电，其中，所述电源电压大于限制电源电压，所述电池电压小于限制电池电压，所述限制电源电压为所述充电芯片的充电输入端的最小限制电压，所述限制电池电压为所述充电芯片的电池供电端的最大限制电压；
    所述处理单元还用于在满足第一条件的情况下，同时将所述限制电源电压以及所 述限制电池电压增大，或者，同时将所述限制电池电压增大以及将充电电流减小；在满足第二条件的情况下，同时将所述限制电源电压以及所述限制电池电压减小，或者，同时将所述限制电池电压减小以及将充电电流增大；其中，所述充电电流为用于向所述电池充电的电流，所述第一条件至少包括所述电池电压大于电池电压阈值，所述第二条件至少包括所述电池电压小于电池电压阈值。
  12. 根据权利要求11所述的终端设备，其特征在于，
    在所述同时将所述限制电源电压以及所述限制电池电压增大的情况下，所述第一条件还包括测试电压小于预设阈值，和/或，目标次数超过预设次数；
    在所述同时将所述限制电源电压以及所述限制电池电压减小的情况下，所述第二条件还包括测试电压小于预设阈值，和/或，目标次数超过预设次数；
    其中，所述测试电压为在所述充电芯片的充电输入端的电压，所述目标次数为所述测试电压小于预设阈值的次数。
  13. 根据权利要求11或12所述的终端设备，其特征在于，在所述同时将所述限制电源电压以及所述限制电池电压增大的情况下，所述第一条件还包括所述电池电压处于上升期。
  14. 根据权利要求11或12所述的终端设备，其特征在于，在所述同时将所述限制电源电压以及所述限制电池电压减小的情况下，所述第二条件还包括所述电池电压处于上升期，或者，所述电池电压处于下降期。
  15. 根据权利要求14所述的终端设备，其特征在于，
    在所述第二条件还包括所述电池电压处于上升期的情况下，所述电池电压阈值为第一电池电压阈值；
    在所述第二条件还包括所述电池电压处于下降期的情况下，所述电池电压阈值为第二电池电压阈值；
    其中，所述第一电池电压阈值大于第二电池电压阈值。
  16. 一种计算机可读存储介质，所述计算机可读存储介质存储有计算机程序，其特征在于，所述计算机程序被处理器执行时实现如权利要求6至10任一项所述方法。
PCT/CN2018/107791 2017-09-30 2018-09-27 充电控制方法、相关设备及计算机存储介质 WO2019062787A1 (zh)

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Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113364067B (zh) * 2020-03-03 2022-08-05 荣耀终端有限公司 充电精度校准方法及电子设备
JP2021164302A (ja) * 2020-03-31 2021-10-11 パナソニックＩｐマネジメント株式会社 充電システム、充電方法、及びプログラム
CN111697653A (zh) * 2020-06-18 2020-09-22 深圳禾苗通信科技有限公司 一种提高通信设备续航时间的方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010239860A (ja) * 2009-03-13 2010-10-21 Toshiba Corp 電池パック及び充電器システム
CN104638726A (zh) * 2015-02-04 2015-05-20 惠州Tcl移动通信有限公司 一种基于移动终端的充电电压控制方法及控制系统
CN105098268A (zh) * 2014-05-14 2015-11-25 中兴通讯股份有限公司 一种终端的充电方法及装置
CN205901342U (zh) * 2016-06-20 2017-01-18 深圳天珑无线科技有限公司 一种电池的充电电路及电子设备
CN106785134A (zh) * 2016-12-19 2017-05-31 北京小米移动软件有限公司 终端设备的电池充电方法及装置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5625275A (en) * 1995-05-24 1997-04-29 Ast Research, Inc. Power supply which provides a variable charging current to a battery in a portable computer system
CA2246579A1 (en) * 1998-09-03 2000-03-03 Neil Simmonds Lithium-ion cell charging circuit with current-limiting transformer and linear integrated circuit
CN202014109U (zh) 2011-03-02 2011-10-19 江苏嘉钰新能源技术有限公司 一种调整电池充电电压的电源
US20130257381A1 (en) * 2012-03-29 2013-10-03 Steven Diamond Peak-equalized battery charge balancing
US20160164324A1 (en) * 2013-06-03 2016-06-09 Mediatek Inc. Portable device capable of controlling output characteristics of adaptor, and corresponding method
EP3022826B1 (en) * 2013-07-18 2018-03-28 MediaTek Inc. Method, charger device, and adaptor capable of maximum output power point tracking
TWI619330B (zh) * 2016-04-22 2018-03-21 立錡科技股份有限公司 充電裝置及其充電控制電路與充電控制方法
CN105978065A (zh) * 2016-05-12 2016-09-28 Tcl移动通信科技（宁波）有限公司 一种移动终端反向供电输出电流设置方法及装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010239860A (ja) * 2009-03-13 2010-10-21 Toshiba Corp 電池パック及び充電器システム
CN105098268A (zh) * 2014-05-14 2015-11-25 中兴通讯股份有限公司 一种终端的充电方法及装置
CN104638726A (zh) * 2015-02-04 2015-05-20 惠州Tcl移动通信有限公司 一种基于移动终端的充电电压控制方法及控制系统
CN205901342U (zh) * 2016-06-20 2017-01-18 深圳天珑无线科技有限公司 一种电池的充电电路及电子设备
CN106785134A (zh) * 2016-12-19 2017-05-31 北京小米移动软件有限公司 终端设备的电池充电方法及装置

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