WO2019059892A1

WO2019059892A1 - Metallic glass barriers for electrodes and contacts in semiconductor devices

Info

Publication number: WO2019059892A1
Application number: PCT/US2017/052261
Authority: WO
Inventors: Elijiah V. KARPOV; Christopher J. Jezewski; Mauro J. KOBRINSKY; Hui Jae YOO; Ravi Pillarisetty
Original assignee: Intel Corporation
Priority date: 2017-09-19
Filing date: 2017-09-19
Publication date: 2019-03-28

Abstract

Disclosed are electronic devices, memory devices, and computing devices including a metallic glass barrier material for an electrode or a contact. An electronic device (100) includes a semiconductor substrate (110), an electrical component (120) formed on or in the semiconductor substrate, an electrically conductive material (130) on or in the electrical component and configured to conduct electrical charge at least one of to or from the electrical component, and a barrier material (132) including a metallic glass material in contact with the electrically conductive material. A memory device includes a memory cell including a metallic glass barrier material. A computing device includes an electronic device including a metallic glass barrier material.

Description

METALLIC GLASS BARRIERS FOR ELECTRODES AND

CONTACTS IN SEMICONDUCTOR DEVICES

Technical Field

[0001] The disclosure relates generally to metallic glass barriers for electrodes and contacts in semiconductor devices, and more specifically to metallic class barriers to oxygen in memory devices.

Background

[0002] Some semiconductor devices suffer degradation from oxygen or oxidation. Oxygen can be a particular problem during thermal processing, etching, deposition, and other processing, or during use after fabrication at elevated temperatures and/or for long periods of time. An example of a device that is particularly sensitive to oxygen is oxygen vacancy filament RRAM. Oxygen vacancy filament RRAM devices should maintain the same composition of the oxygen vacancy filament for 10 years at 85° Celsius (C), for a few minutes at 260° C, and other combinations of

temperatures at different time durations. Other devices with contacts to

semiconductor devices such as embedded magnetic memories, ferroelectric memories, and transistors also may experience oxidation degradation operation over time and/or operation at elevated temperatures.

Brief Description of the Drawings

[0003] FIG. 1 is a simplified view of an electronic device, according to some embodiments.

[0004] FIG. 2 is a simplified cross-sectional view of a memory cell, according to some embodiments.

[0005] FIG. 3 is a simplified plan view of an array of memory cells, according to some embodiments.

[0006] FIG. 4 is an interposer implementing one or more embodiments of the disclosure.

[0007] FIG. 5 is a computing device built in accordance with an embodiment of the disclosure.

Detailed Description of Preferred Embodiments

[0008] Described herein are electronic devices, memory devices, and computing devices including electrically conductive materials that are protected by barrier materials including metallic glass materials. In the following description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. However, it will be apparent to those skilled in the art that the present disclosure may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative implementations.

However, it will be apparent to one skilled in the art that the present disclosure may be practiced without the specific details. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative implementations.

[0009] Various operations will be described as multiple discrete operations, in turn, in a manner that is helpful in understanding the present disclosure; however, the order of description should not be construed to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation.

[0010] The terms "over," "under," "between," and "on" as used herein refer to a relative position of one material layer or component with respect to other layers or components. For example, one layer disposed over or under another layer may be directly in contact with the other layer or may have one or more intervening layers. Moreover, one layer disposed between two layers may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first layer "on" a second layer is in direct contact with that second layer. Similarly, unless explicitly stated otherwise, one feature disposed between two features may be in direct contact with the adjacent features or may have one or more intervening layers.

[0011] Implementations of the disclosure may be formed or carried out on a substrate, such as a semiconductor substrate. In one implementation, the

semiconductor substrate may be a crystalline substrate formed using a bulk silicon or a silicon-on-insulator (SOI) substructure (e.g., silicon on glass, silicon on sapphire, etc.). In other implementations, the semiconductor substrate may be formed using alternate materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of group lll-V or group IV materials. Although a few examples of materials from which the substrate may be formed are described here, any material that may serve as a foundation upon which a semiconductor device may be built falls within the spirit and scope of the present disclosure. [0012] Currently, oxygen diffusion barriers are not implemented in memory devices. As a result, reliability may be improved by implementing oxygen diffusion barriers in these devices. Typically used electrodes in back-end memory and back-end transistor devices often include metal elements, such as Ti, or binary compounds, for example TiN. Ti films are poor oxygen barriers. For example, single metals such as Ti and Nb are relatively "transparent" to oxygen. Also, typical films such as TiN have a columnar structure, and are poor barriers for oxygen due to numerous grain boundaries serving as a fast pathway for oxygen diffusion.

Moreover, even two layer metal stacks allow oxygen to diffuse through. This is particularly troublesome for oxygen sensitive devices, such as RRAM devices.

[0013] An oxygen barrier material may be used to protect a semiconductor device. In particular, oxygen sensitive devices, such as oxygen vacancy filament RRAM, may be protected from oxygen and oxidation by an oxygen barrier material during thermal processing, etching, deposition processing, other processing, or combinations thereof, and during usage of the device after processing at elevated temperature or for long period of time, an oxygen barrier layer may be used to cap electrodes and/or contacts of the device. For example, barrier materials may enable oxygen vacancy filament RRAM devices to maintain the same composition of the oxygen vacancy filament for 10 years at 85° C, for a few minutes at 260° C, or at other various temperature and time combinations. Barrier materials may also protect other semiconductor devices besides RRAM devices, such as embedded magnetic memories, ferroelectric memories, and transistors, each of which includes electrically conductive electrodes and/or contacts.

[0014] Metallic glass materials are good oxygen barrier materials because oxygen diffusion in metallic glass is slower than oxygen diffusion in single-elemental metals and in metal alloys that are commonly used in semiconductor devices.

Metallic glass materials have a disordered or amorphous atomic-scale lattice structure. Often times, the lattice structure of metallic glass materials is built from several different elements. In such lattices, an atom may not diffuse from a first location to an adjacent location unless the atom has a relatively high potential energy, as compared to a relatively lower diffusion potential energy for lattices of other materials (e.g., common single-element metals, binary materials, common alloys, etc.). For example, a mean difference in potential energy is generally higher for metallic glass than for common single-element metals and alloys. Also, experiments show that self-diffusion is significantly reduced in metallic glass materials as compared to common single-element metals and alloys. Furthermore, various studies have shown that metallic glass materials are much more resistant to corrosion and/or oxidation than common single-element metals and alloys. In addition, metallic glass materials do not have intrinsic length scale, and do not have grain/column boundaries, which are fast diffusion pathways for oxygen. Moreover, metallic glass materials are dense with filled interstitial sites, which block interstitial diffusion.

[0015] Examples of metallic glass materials that may be used in embodiments disclosed herein include AICoCrCuFeNi, AICoCrFeNi, AI_{0 5}CoCrFeNi, CoCrCuFeNi, AICoCrFeNiTio.5, AICoCrCuFeNiTi₀.₅, AICoCrFeNiMo_{0 5}, Alo.sCrFetsMnNio.s,

Alo.sCrFeisMnNio.s, AICoCrFeNiNb_{0 5}, AICoCrFeNiSi_{0 4}, AICoCrFeNi_{2 1} ,

AIMoo.sNbTao.sTiZr, AINbisTao.sT .sZro.s, Al₀.₄Hfo.₆NbTaTiZr, Alo.sNbTaT ^Zn.s,

AI0.5NbTa0.8Ti1.5V0.2Zr, NbMoTaW, VnbMoTaW,

TaNbHfZrTi, NbCrMo_0.5Ta_0.5TiZr, and NbTiVZr. As a specific, non-limiting example, a specific class of metallic glass material may include silicon (Si), such as

AICoCrFeNiSi_{0 4}.

[0016] Although metallic glass materials are not typically used in semiconductor devices, these materials may be applied to semiconductor devices using known semiconductor processes. For example, physcial vapor deposition by direct current (DC) sputtering may be used to apply metallic glass materials. Also by way of example, radio frequency (RF) sputtering may be used to apply the metallic glass materials. In some embodiments, sputtering can be done from a single target with multiple elements. A film of the metallic glass materials may be amorphous (which can be detected by X-ray diffraction (XRD)) and multicomponent (which can be detected by electron energy loss spectroscopy (EELS) or energy-dispersive X-ray spectroscopy (EDX). The thickness of the metallic glass material may be on the order of about a nanometer to tens of nanometers (nm). By way of non-limiting example, the thickness of the metallic glass material may be about three (3) to fifty (50) nm.

[0017] FIG. 1 is a simplified view of an electronic device 100, according to some embodiments. The electronic device 100 includes a semiconductor substrate 1 10, an electrical component 120 formed on or in the semiconductor substrate 1 10, an electrically conductive material 130 (e.g., an electrode, a contact, etc.) on or in the electrical component 120 and configured to conduct electrical charge at least one of to or from the electrical component 120, and a barrier material 132 comprising a metallic glass material in contact with the electrically conductive material 130. The barrier material 132 serves as a barrier to ions (e.g., oxygen ions dislodged in RRAM). Accordingly, the integrity of the electrical component 120 may be

preserved, especially where the integrity of the electrical component 120 relies upon retention of such ions. Also, the barrier material 132 may prevent the electrically conductive material 130 from oxidizing, preventing degradation of the electrical component 120.

[0018] In some embodiments, the electrical component 120 includes a

component of a RRAM device. As will be apparent to those of ordinary skill in the art, RRAM data storage elements include oxide materials (e.g., oxygen vacancy filament oxide materials) in which oxygen vacancies are formed by removing oxygen from the oxide materials. By way of non-limiting example, such an oxide material may include a binary transition metal oxide (e.g., NiO, Ti0₂, Hf0₂, Ta₂0₅, etc.), a perovskite (e.g., Sr(Zr)Ti0₃, PrxCayMnOs (PCMO), etc.), other oxide materials, or combinations thereof. Oxygen ions may be mobile in these RRAM devices as a result of removing oxygen. The barrier material 132 may prevent these oxygen ions from escaping the vicinity of the data storage element, resulting in prolonged life expectancy and prevention of device degradation (due to loss of oxygen and/or oxidation of surrounding materials, such as the electrically conductive material 130) during processing and operation of RRAM.

[0019] In embodiments where the electrical component 120 includes a memory cell of an RRAM device, the electrically conductive material 130 includes an electrode of the memory cell. By way of non-limiting example, the electrically conductive material 130 may include a top electrode, and the electronic device 100 may include an electrically conductive material 160 serving as a bottom electrode. In some embodiments, the electronic device 100 may also include a barrier material 162 including a metallic glass material, which serves as a barrier of the bottom electrode. In some embodiments, only the bottom electrode will include a barrier material 162, and the electrically conductive material 130 of the top electrode may not include the barrier material 132.

[0020] In some embodiments, the electrical component 120 may include a component of some other type of memory other than RRAM (e.g., an embedded magnetic memory, a ferroelectric memory, a Flash memory, capacitive RAM, etc.). More will be discussed regarding embodiments involving various types of memory with reference to FIG. 2 below.

[0021] In some embodiments, the electrical component 120 may include a two-terminal device (e.g., a resistor, a capacitor, a diode, a memory cell, other devices, etc.). In FIG. 1 , multiple optional electrically conductive materials 140, 150, and 160 are shown with optional barrier materials 142, 152, 162 corresponding thereto. In embodiments where the electrical component 120 includes a

two-terminal device, one or both of the electrodes may include a barrier material. The two terminals may include the electrically conductive material 130, and any one of electrically conductive materials 140, 150, or 160. It should be noted that, regardless of how the electrically conductive materials 130, 140, 150, and 160 are illustrated in FIG. 1 , the terminals may be arranged in any manner suitable to the two-terminal device (e.g., opposite each other across the device, side by side, etc., in any orientation such as vertical, horizontal, or any other orientation).

[0022] In some embodiments, the electrical component 120 may include a three, four, or higher number of terminals device. In such embodiments, one or any number more than one of the electrically conductive materials 130, 140, 150, and 160 may include a barrier material 132, 142, 152, and 162. Also, the terminals may be arranged in any way suitable for the electrical component 120. By way of non-limiting example, the electrical component 120 may include a transistor (e.g., a digital switching transistor, a Flash memory data storage element, etc.). In such embodiments, electrically conductive materials 130 and 150 may serve as source/drain terminals, and the electrically conductive material 140 may serve as a gate terminal. In some such embodiments, the electrically conductive material 160 may be a body connection terminal (as a transistor may be described as a four terminal device when considering the body connection). In some embodiments, only one of the transistor terminals may include the barrier material (e.g., the gate, the body connection terminal, etc.). In some embodiments, all of the terminals may include a barrier material. In some embodiments, any one, two, three, or four terminals may include a barrier material.

[0023] In some embodiments, the electrical component 120 may include a backend device. In some embodiments, the electrical component 120 may include a frontend device. [0024] In some embodiments, the electrically conductive material 130, 140, 150, 160 includes a single-element metal (e.g., copper, gold, titanium, aluminum, tungsten, ruthenium, palladium, platinum, cobalt, nickel, etc.) or a compound (e.g., a binary compound such as, for example titanium nitride (TiN), metal alloys, metal oxides, metal carbides, etc.). In some embodiments, the electrically conductive material includes a highly doped material (e.g., polysilicon, doped semiconductor material, etc.). Some or all of these materials may benefit from barrier materials to prevent ions from passing through, and/or to prevent oxidization.

[0025] FIG. 2 is a simplified cross-sectional view of a memory cell 200, according to some embodiments. A memory device may include an array 300 (see FIG. 3 below) of memory cells similar to the memory cell 200. The memory cell 200 includes a data storage element 270, at least one barrier material 232 and/or 262 (i.e., including a metallic glass material), and a pair of electrodes (top electrode 230 and bottom electrode 260). At least one (i.e., one or both) of the electrodes 230 and/or 260 is located between the at least one barrier material 232 and/or 262 and the data storage element 270. As a result, one or both of the electrodes 230 and/or 260 is protected by a barrier material 232 and/or 262.

[0026] In some embodiments, the data storage element 270 includes a RRAM data storage element. In some embodiments, the data storage element 270 includes an embedded magnetic memory data storage element. In some embodiments, the data storage element 270 includes a ferroelectric memory element. In some embodiments, the data storage element 270 includes a transistor data storage element (e.g., a Flash memory transistor). In some embodiments, the data storage element 270 includes a capacitive data storage element (e.g., a dynamic RAM (DRAM) element). It is also contemplated that the data storage element 270 may include a conductive bridging RAM (CBRAM) element, a phase-change memory (PCM) element, or other data storage element known in the art.

[0027] Although the memory cell 200 of FIG. 2 is disclosed as having a vertical orientation (i.e., top electrode 230, bottom electrode 260, etc.), horizontal, tilted, or asymmetric orientations are contemplated herein.

[0028] FIG. 3 is a simplified plan view of an array 300 of memory cells 200, according to some embodiments. In some embodiments, the array 300 may include a two-dimensional array. In some embodiments, the array 300 may include a three-dimensional array. In some embodiments, the array 300 may be arranged in a cross-point architecture.

[0029] Inasmuch as the present disclosure includes transistors (e.g., the electrical component 120 of FIG. 1 may include a transistor or be connected to a transistor), a discussion regarding transistors follows. A plurality of transistors, such as

metal-oxide-semiconductor field-effect transistors (MOSFET or simply MOS transistors), may be fabricated on the substrate (e.g., the semiconductor substrate 1 10 of FIG. 1 ). In various implementations of the disclosure, the MOS transistors may be planar transistors, nonplanar transistors, or a combination of both.

Nonplanar transistors include FinFET transistors such as double-gate transistors and tri-gate transistors, and wrap-around or all-around gate transistors such as

nanoribbon and nanowire transistors. Although the implementations described herein may illustrate only planar transistors, it should be noted that the disclosure may also be carried out using nonplanar transistors.

[0030] Each MOS transistor includes a gate stack formed of at least two layers, a gate dielectric layer and a gate electrode layer. The gate dielectric layer may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide (SiO2) and/or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric layer to improve its quality when a high-k material is used.

[0031] The gate electrode layer is formed on the gate dielectric layer and may include at least one P-type workfunction metal or N-type workfunction metal, depending on whether the transistor is to be a PMOS or an NMOS transistor. In some implementations, the gate electrode layer may include a stack of two or more metal layers, where one or more metal layers are workfunction metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer.

[0032] For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide. A P-type metal layer will enable the formation of a PMOS gate electrode with a workfunction that is between about 4.9 eV and about 5.2 eV. For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. An N-type metal layer will enable the formation of an NMOS gate electrode with a workfunction that is between about 3.9 eV and about 4.2 eV.

[0033] In some implementations, when viewed as a cross-section of the transistor along the source-channel-drain direction, the gate electrode may include a

"U"-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially

perpendicular to the top surface of the substrate. In another implementation, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In further implementations of the disclosure, the gate electrode may include a

combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may include one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.

[0034] In some implementations of the disclosure, a pair of sidewall spacers may be formed on opposing sides of the gate stack that bracket the gate stack. The sidewall spacers may be formed from a material such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In an alternate implementation, a plurality of spacer pairs may be used, for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.

[0035] As is well known in the art, source and drain regions are formed within the substrate adjacent to the gate stack of each MOS transistor. The source and drain regions are generally formed using either an implantation/diffusion process or an etching/deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate to form the source and drain regions. An annealing process that activates the dopants and causes them to diffuse further into the substrate typically follows the ion implantation process. In the latter process, the substrate may first be etched to form recesses at the locations of the source and drain regions. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the source and drain regions. In some implementations, the source and drain regions may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some implementations the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In further embodiments, the source and drain regions may be formed using one or more alternate semiconductor materials such as germanium or a group lll-V material or alloy. And in further embodiments, one or more layers of metal and/or metal alloys may be used to form the source and drain regions.

[0036] One or more interlayer dielectrics (ILD) are deposited over the MOS transistors. The ILD layers may be formed using dielectric materials known for their applicability in integrated circuit structures, such as low-k dielectric materials.

Examples of dielectric materials that may be used include, but are not limited to, silicon dioxide (SiO2), carbon doped oxide (CDO), silicon nitride, organic polymers such as perfluorocyclobutane or polytetrafluoroethylene, fluorosilicate glass (FSG), and organosilicates such as silsesquioxane, siloxane, or organosilicate glass. The ILD layers may include pores or air gaps to further reduce their dielectric constant.

[0037] FIG. 4 illustrates an interposer 1000 that includes one or more

embodiments of the disclosure. The interposer 1000 is an intervening substrate used to bridge a first substrate 1002 to a second substrate 1004. The first substrate 1002 may be, for instance, an integrated circuit die. The second substrate 1004 may be, for instance, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of an interposer 1000 is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, an interposer 1000 may couple an integrated circuit die to a ball grid array (BGA) 1006 that can subsequently be coupled to the second substrate 1004. In some

embodiments, the first and second substrates 1002/1004 are attached to opposing sides of the interposer 1000. In other embodiments, the first and second substrates 1002/1004 are attached to the same side of the interposer 1000. And in further embodiments, three or more substrates are interconnected by way of the interposer 1000.

[0038] The interposer 1000 may be formed of an epoxy resin, a fiberglass- reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further implementations, the interposer 1000 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group lll-V and group IV materials.

[0039] The interposer 1000 may include metal interconnects 1008 and vias 1010, including but not limited to through-silicon vias (TSVs) 1012. The interposer 1000 may further include embedded devices 1014, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and

electrostatic discharge (ESD) devices. More complex devices such as radio- frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer 1000.

[0040] In accordance with embodiments of the disclosure, apparatuses or processes disclosed herein may be used in the fabrication of the interposer 1000.

[0041] FIG. 5 illustrates a computing device 1200 in accordance with one embodiment of the disclosure. The computing device 1200 may include a number of components. In one embodiment, these components are attached to one or more motherboards. In an alternate embodiment, some or all of these components are fabricated onto a single system-on-a-chip (SoC) die, such as an SoC used for mobile devices. The components in the computing device 1200 include, but are not limited to, an integrated circuit die 1202 and at least one communications logic unit 1208 (e.g., a communications ship). In some implementations the communications logic unit 1208 is fabricated within the integrated circuit die 1202 while in other

implementations the communications logic unit 1208 is fabricated in a separate integrated circuit chip that may be bonded to a substrate or motherboard that is shared with or electronically coupled to the integrated circuit die 1202. The

integrated circuit die 1202 may include a processor 1204 (e.g., a CPU) as well as on- die memory 1206, often used as cache memory, that can be provided by

technologies such as embedded DRAM (eDRAM), SRAM, or spin-transfer torque memory (STT-MRAM).

[0042] Computing device 1200 may include other components that may or may not be physically and electrically coupled to the motherboard or fabricated within an SoC die. These other components include, but are not limited to, volatile memory 1210 (e.g., DRAM), non-volatile memory 1212 (e.g., ROM or flash memory), a graphics processing unit 1214 (GPU), a digital signal processor 1216, a crypto processor 1242 (e.g., a specialized processor that executes cryptographic algorithms within hardware), a chipset 1220, at least one antenna 1222 (in some

implementations two or more antenna may be used), a display or a touchscreen display 1224, a touchscreen controller 1226, a battery 1229 or other power source, a power amplifier (not shown), a voltage regulator (not shown), a global positioning system (GPS) device 1228, a compass (not shown), a motion coprocessor or sensors 1232 (that may include an accelerometer, a gyroscope, and a compass), a microphone (not shown), a speaker 1234, a camera 1236, user input devices 1238 (such as a keyboard, mouse, stylus, and touchpad), and a mass storage device 1240 (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth). The computing device 1200 may incorporate further transmission, telecommunication, or radio functionality not already described herein. In some implementations, the computing device 1200 includes a radio that is used to communicate over a distance by modulating and radiating electromagnetic waves in air or space. In further implementations, the computing device 1200 includes a transmitter and a receiver (or a transceiver) that is used to communicate over a distance by modulating and radiating electromagnetic waves in air or space.

[0043] The communications logic unit 1208 enables wireless communications for the transfer of data to and from the computing device 1200. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communications logic unit 1208 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.1 1 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Infrared (IR), Near Field Communication (NFC), Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 1200 may include a plurality of communications logic units 1208. For instance, a first communications logic unit 1208 may be dedicated to shorter range wireless communications such as Wi-Fi, NFC, and Bluetooth and a second communications logic unit 1208 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

[0044] The processor 1204 of the computing device 1200 includes one or more electronic components (e.g., the electronic component 120 of FIG. 1 ), such as transistors, memory cells (e.g., RRAM), backend devices, frontend devices, or etc., that are formed in accordance with embodiments of the disclosure (having barrier materials including metallic glass materials on or in electrodes and/or contacts therein). The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

[0045] The communications logic unit 1208 may also include one or more devices, such as transistors, memory cells (e.g., RRAM), backend devices, frontend devices, or etc., that are formed in accordance with embodiments of the disclosure (having barrier materials including metallic glass materials on or in electrodes and/or contacts therein).

[0046] In further embodiments, another component housed within the computing device 1200 may contain one or more devices, such as transistors, memory cells (e.g., RRAM), backend devices, frontend devices, or etc., that are formed in accordance with implementations of the disclosure (having barrier materials including metallic glass materials on or in electrodes and/or contacts therein).

[0047] In various embodiments, the computing device 1200 may be a laptop computer, a netbook computer, a notebook computer, an ultrabook computer, a smartphone, a dumbphone, a tablet, a tablet/laptop hybrid, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 1200 may be any other electronic device that processes data.

Examples

[0048] The following is a non-exhaustive list of example embodiments that fall within the scope of the disclosure. In order to avoid complexity in providing the disclosure, not all of the examples listed below are separately and explicitly disclosed as having been contemplated herein as combinable with all of the others of the examples listed below and other embodiments disclosed hereinabove. Unless one of ordinary skill in the art would understand that these examples listed below, and the above disclosed embodiments, are not combinable, it is contemplated within the scope of the disclosure that such examples and embodiments are combinable.

[0049] Example 1 : An electronic device, comprising: a semiconductor substrate; an electrical component formed on or in the semiconductor substrate; an electrically conductive material on or in the electrical component and configured to conduct electrical charge at least one of to or from the electrical component; and a barrier material comprising a metallic glass material in contact with the electrically

conductive material.

[0050] Example 2: The electronic device of Example 1 , wherein the electrical component comprises a component of a resistive random access memory (RRAM) device.

[0051] Example 3: The electronic device of Example 2, wherein the component comprises a memory cell of the RRAM device, and the electrically conductive material comprises an electrode of the memory cell.

[0052] Example 4: The electronic device of Example 3, wherein the electrode is between the barrier material and an oxygen vacancy filament oxide material.

[0053] Example 5: The electronic device of Example 4, wherein the oxygen vacancy filament oxide material comprises at least one of a binary transition metal oxide or a perovskite.

[0054] Example 6: The electronic device according to any one of Examples 1 -5, wherein: the electrical component comprises a memory cell comprising: a pair of metallic glass regions; a pair of electrodes; and a data storage element between the pair of electrodes and between the pair of metallic glass regions, and the pair of electrodes between the data storage element and the pair of metallic glass regions; the electrically conductive material includes one of the pair of electrodes; and the barrier material comprises one of the metallic glass regions that is adjacent the one of the pair of electrodes.

[0055] Example 7: The electronic device according to any one of Examples 1 -6, wherein the metallic glass material comprises at least one material selected from the group consisting of AICoCrCuFeNi, AICoCrFeNi, AI_{0 5}CoCrFeNi, CoCrCuFeNi, AICoCrFeNiTio.5, AICoCrCuFeNiTi₀.₅, AICoCrFeNiMo_{0 5}, Alo.3CrFei.₅MnNi₀.5,

Alo.sCrFetsMnNio.s, AICoCrFeNiNb_{0 5}, AICoCrFeNiSi_{0 4}, AICoCrFeNi_{2 1} ,

AI0.5NbTa0.8Ti1.5V0.2Zr, NbMoTaW, VnbMoTaW,

TaNbHfZrTi, NbCrMoo_.sTao_.sTiZr, and NbTiVZr.

[0056] Example 8: The electronic device according to any one of Examples 1 -6, wherein the metallic glass material comprises a compound including silicon (Si).

[0057] Example 9: The electronic device according to any one of Examples 1 -8, wherein the electrically conductive material comprises one of a metal or a binary compound.

[0058] Example 10: The electronic device of Example 9, wherein the electrically conductive material comprises one of Ti or TiN.

[0059] Example 1 1 : The electronic device according to any one of Examples 1 and 6-10, wherein the electrical component comprises a component of a device selected from the group consisting of an embedded magnetic memory, a ferroelectric memory, or a transistor.

[0060] Example 12: A memory device, comprising: an array of memory cells, each memory cell of the array comprising: a data storage element; at least one metallic glass material; and at least one electrode between the at least one metallic glass material and the data storage element.

[0061] Example 13: The memory device of Example 12, wherein the data storage element comprises a resistive random access memory data storage element.

[0062] Example 14: The memory device of Example 12, wherein the data storage element comprises an embedded magnetic memory data storage element.

[0063] Example 15: The memory device of Example 12, wherein the data storage element comprises a ferroelectric memory element.

[0064] Example 16: The memory device of Example 12, wherein the data storage element comprises a transistor data storage element. [0065] Example 17: The memory device according to any one of Examples 12 and 16, wherein the data storage element comprises a capacitive data storage element.

[0066] Example 18: A computing device comprising: an electronic device comprising a semiconductor structure including: a component for the electronic device; an electrode or a contact comprising electrically conductive material and operably coupled to the component; and a barrier material comprising a metallic glass in contact with the electrically conductive material.

[0067] Example 19: The computing device of Example 18, wherein the electronic device comprises at least one device taken from the group consisting of: a processor mounted on a substrate; a memory unit capable of storing data; a graphics

processing unit; an antenna within the computing device; a display on the computing device; a battery within the computing device; a power amplifier within the processor; and a voltage regulator within the processor.

[0068] Example 20: The computing device of Example 18, wherein the electronic device comprises a memory unit capable of storing data.

[0069] Example 21 : The computing device of Example 20, wherein the

component for the electronic device comprises a memory cell.

[0070] Example 22: A method of manufacturing an electronic device, the method comprising: forming an electrical component on or in a semiconductor substrate; forming an electrically conductive material on or in the electrical component, the electrically conductive material configured to conduct electrical charge at least one of to or from the electrical component; and forming a barrier material comprising a metallic glass material on the electrically conductive material.

[0071] Example 23: The method of Example 22, wherein forming electrical component comprises forming a component of a resistive random access memory

(RRAM) device.

[0072] Example 24: The method of Example 23, wherein: forming a component of a RRAM device comprises forming a memory cell of the RRAM device; and forming an electrically conductive material on or in the electrical component comprises forming an electrode of the memory cell on or in the memory cell.

[0073] Example 25: The method of Example 24, wherein forming an electrode on or in the memory cell comprises forming the electrode between the barrier material and an oxygen vacancy filament oxide material. [0074] Example 26: The method of Example 25, wherein the oxygen vacancy filament oxide material comprises at least one of a binary transition metal oxide or a perovskite.

[0075] Example 27: The method according to any one of Examples 22-26, wherein: forming an electrical component comprises: forming a pair of metallic glass regions; forming a pair of electrodes; and forming a data storage element between the pair of electrodes and between the pair of metallic glass regions with the pair of electrodes between the data storage element and the pair of metallic glass regions; forming an electrically conductive material includes forming one of the pair of electrodes; and forming the barrier material comprises forming one of the metallic glass regions that is adjacent the one of the pair of electrodes.

[0076] Example 28: The method according to any one of Examples 22-26, wherein forming a barrier material including a metallic glass material comprises forming at least one material selected from the group consisting of AICoCrCuFeNi, AICoCrFeNi, AI_{0 5}CoCrFeNi, CoCrCuFeNi, AICoCrFeNiTi_{0 5}, AICoCrCuFeNiTi₀.₅, AICoCrFeNiMoo.5, Alo.sCrFeisMnNio.s, Alo.sCrFeisMnNio.s, AICoCrFeNiNb_{0 5},

AICoCrFeNiSi_{0 4}, AICoCrFeNi_{2 1}, AIMoo.sNbTao.sTiZr, AINbisTao.sT .sZro.s,

Alo.₄Hf₀.₆NbTaTiZr, Alo.₃NbTaTii.₄Zri.₃, Alo_.3NbTao.₈Tii.₄Vo_.2Zri.3,

AI0_.5NbTa0.8Ti1_.5V0_.2Zr, NbMoTaW, VnbMoTaW, TaNbHfZrTi, NbCrMoo_.5Tao_.5TiZr, and NbTiVZr.

[0077] Example 29: The method according to any one of Examples 22-26, wherein forming a barrier material including a metallic glass material comprises forming a compound including silicon (Si).

[0078] Example 30: The method according to any one of Examples 22-30, wherein forming an electrically conductive material comprises forming one of a metal or a binary compound.

[0079] Example 31 : The method of Example 30, wherein forming one of a metal or a binary compound comprises forming one of Ti or TiN.

[0080] Example 32: The method of Example 22 and 27-31 , wherein forming an electrical component comprises a forming component of a device selected from the group consisting of an embedded magnetic memory, a ferroelectric memory, or a transistor.

[0081] Example 33: A method of manufacturing an array of memory cells, the method comprising: forming a data storage element; forming at least one metallic glass material; and forming at least one electrode between the at least one metallic glass material and the data storage element.

[0082] Example 34: The method of Example 33, wherein forming a data storage element comprises forming a resistive random access memory data storage element.

[0083] Example 35: The method of Example 33, wherein forming a data storage element comprises forming an embedded magnetic memory data storage element.

[0084] Example 36: The method of Example 33, wherein forming a data storage element comprises forming a ferroelectric memory element.

[0085] Example 37: The method of Example 33, wherein forming a data storage element comprises forming a transistor data storage element.

[0086] Example 38: The method according to any one of Examples 33 and 37, wherein forming a data storage element comprises forming a capacitive data storage element.

[0087] Example 39: A method of operating a computing device, the method comprising: operating a component of an electronic device of the computing device; conducting an electrical charge at least one of to or from an electrode or a contact comprising electrically conductive material and operably coupled to the component; and protecting the component with a barrier material comprising a metallic glass in contact with the electrically conductive material.

[0088] Example 40: The method of Example 39, wherein operating a component of the electronic device comprises operating a component of at least one device taken from the group consisting of: a processor mounted on a substrate; a memory unit capable of storing data; a graphics processing unit; an antenna within the computing device; a display on the computing device; a battery within the computing device; a power amplifier within the processor; and a voltage regulator within the processor.

[0089] Example 41 : The method of Example 39, wherein operating a component of the electronic device comprises operating a component of a memory unit capable of storing data.

[0090] Example 42: The method of Example 41 , wherein operating a component of a memory unit capable of storing data comprises operating a memory cell.

[0091] Example 43: A computer-readable medium having computer-readable instructions stored thereon, the computer-readable instructions configured to instruct one or more processors to perform at least a portion of the method according to any one of Examples 22-42.

[0092] Example 44: A means for performing at least a portion the method according to any one of Examples 22-42.

Conclusion

[0093] The above description of illustrated implementations of the disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific implementations of, and examples for, the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize.

[0094] It will be apparent to those having skill in the art that many changes may be made to the details of the above-described embodiments without departing from the underlying principles of the disclosure. The scope of the disclosure should, therefore, be determined only by the following claims.

Claims

1 . An electronic device, comprising:

a semiconductor substrate;

an electrical component formed on or in the semiconductor substrate;

an electrically conductive material on or in the electrical component and configured to conduct electrical charge at least one of to or from the electrical component; and

a barrier material comprising a metallic glass material in contact with the electrically conductive material.

2. The electronic device of claim 1 , wherein the electrical component comprises a component of a resistive random access memory (RRAM) device.

3. The electronic device of claim 2, wherein the component comprises a memory cell of the RRAM device, and the electrically conductive material comprises an electrode of the memory cell.

4. The electronic device of claim 3, wherein the electrode is between the barrier material and an oxygen vacancy filament oxide material.

5. The electronic device of claim 4, wherein the oxygen vacancy filament oxide material comprises at least one of a binary transition metal oxide or a perovskite.

6. The electronic device of claim 1 , wherein:

the electrical component comprises a memory cell comprising:

a pair of metallic glass regions;

a pair of electrodes; and

a data storage element between the pair of electrodes and between the pair of metallic glass regions, and the pair of electrodes between the data storage element and the pair of metallic glass regions;

the electrically conductive material includes one of the pair of electrodes; and the barrier material comprises one of the metallic glass regions that is adjacent the one of the pair of electrodes.

7. The electronic device according to any one of claims 1 -6, wherein the metallic glass material comprises at least one material selected from the group consisting of AICoCrCuFeNi, AICoCrFeNi, AI_{0 5}CoCrFeNi, CoCrCuFeNi,

AICoCrFeNiTio.5, AICoCrCuFeNiTi₀.₅, AICoCrFeNiMo_{0 5}, Alo.sCrFeisMnNio.s,

Alo.sCrFeisMnNio.s, AICoCrFeNiNb_{0 5}, AICoCrFeNiSi_{0 4}, AICoCrFeNi_{2 1} , AIMc-o.sNbTao.sTiZr, AINbisTao.sT .sZro.s, Al₀.₄Hfo.₆NbTaTiZr, Alo.sNbTaT ^Zn.s,

AI0.5NbTa0.8Ti1.5V0.2Zr, NbMoTaW, VnbMoTaW,

TaNbHfZrTi, NbCrMoo_.sTao_.sTiZr, and NbTiVZr.

8. The electronic device according to any one of claims 1 -6, wherein the metallic glass material comprises a compound including silicon (Si).

9. The electronic device according to any one of claims 1 -6, wherein the electrically conductive material comprises one of a metal or a binary compound.

10. The electronic device of claim 9, wherein the electrically conductive material comprises one of Ti or TiN.

1 1 . The electronic device of claim 1 , wherein the electrical component comprises a component of a device selected from the group consisting of an embedded magnetic memory, a ferroelectric memory, or a transistor.

12. A memory device, comprising:

an array of memory cells, each memory cell of the array comprising:

a data storage element;

at least one metallic glass material; and

at least one electrode between the at least one metallic glass material and the data storage element.

13. The memory device of claim 12, wherein the data storage element comprises a resistive random access memory data storage element.

14. The memory device of claim 12, wherein the data storage element comprises an embedded magnetic memory data storage element.

15. The memory device of claim 12, wherein the data storage element comprises a ferroelectric memory element.

16. The memory device of claim 12, wherein the data storage element comprises a transistor data storage element.

17. The memory device of claim 12, wherein the data storage element comprises a capacitive data storage element.

18. A computing device comprising:

an electronic device comprising a semiconductor structure including:

a component for the electronic device;

an electrode or a contact comprising electrically conductive material and operably coupled to the component; and a barrier material comprising a metallic glass in contact with the electrically conductive material.

19. The computing device of claim 18, wherein the electronic device comprises at least one device taken from the group consisting of:

a processor mounted on a substrate;

a memory unit capable of storing data;

a graphics processing unit;

an antenna within the computing device;

a display on the computing device;

a battery within the computing device;

a power amplifier within the processor; and

a voltage regulator within the processor.

20. The computing device of claim 18, wherein the electronic device comprises a memory unit capable of storing data.

21 . The computing device of claim 20, wherein the component for the electronic device comprises a memory cell.